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xen/pt: correctly handle PM status bit
[qemu/ar7.git] / hw / xen / xen_pt_config_init.c
blob027ac324b36c16b4944d29588be9f1b4298fbc92
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
7 *
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
11 *
12 * This file implements direct PCI assignment to a HVM guest
13 */
14
15 #include "qemu/timer.h"
16 #include "hw/xen/xen_backend.h"
17 #include "xen_pt.h"
18
19 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
21
22 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
23
24 /* prototype */
25
26 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
27 uint32_t real_offset, uint32_t *data);
28
29
30 /* helper */
31
32 /* A return value of 1 means the capability should NOT be exposed to guest. */
33 static int xen_pt_hide_dev_cap(const XenHostPCIDevice *d, uint8_t grp_id)
34 {
35 switch (grp_id) {
36 case PCI_CAP_ID_EXP:
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
40 *
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
43 *
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
49 */
50 if (d->vendor_id == PCI_VENDOR_ID_INTEL &&
51 d->device_id == PCI_DEVICE_ID_INTEL_82599_SFP_VF) {
52 return 1;
53 }
54 break;
55 }
56 return 0;
57 }
58
59 /* find emulate register group entry */
60 XenPTRegGroup *xen_pt_find_reg_grp(XenPCIPassthroughState *s, uint32_t address)
61 {
62 XenPTRegGroup *entry = NULL;
63
64 /* find register group entry */
65 QLIST_FOREACH(entry, &s->reg_grps, entries) {
66 /* check address */
67 if ((entry->base_offset <= address)
68 && ((entry->base_offset + entry->size) > address)) {
69 return entry;
70 }
71 }
72
73 /* group entry not found */
74 return NULL;
75 }
76
77 /* find emulate register entry */
78 XenPTReg *xen_pt_find_reg(XenPTRegGroup *reg_grp, uint32_t address)
79 {
80 XenPTReg *reg_entry = NULL;
81 XenPTRegInfo *reg = NULL;
82 uint32_t real_offset = 0;
83
84 /* find register entry */
85 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) {
86 reg = reg_entry->reg;
87 real_offset = reg_grp->base_offset + reg->offset;
88 /* check address */
89 if ((real_offset <= address)
90 && ((real_offset + reg->size) > address)) {
91 return reg_entry;
92 }
93 }
94
95 return NULL;
96 }
97
98
99 /****************
100 * general register functions
101 */
102
103 /* register initialization function */
104
105 static int xen_pt_common_reg_init(XenPCIPassthroughState *s,
106 XenPTRegInfo *reg, uint32_t real_offset,
107 uint32_t *data)
108 {
109 *data = reg->init_val;
110 return 0;
111 }
112
113 /* Read register functions */
114
115 static int xen_pt_byte_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
116 uint8_t *value, uint8_t valid_mask)
117 {
118 XenPTRegInfo *reg = cfg_entry->reg;
119 uint8_t valid_emu_mask = 0;
120
121 /* emulate byte register */
122 valid_emu_mask = reg->emu_mask & valid_mask;
123 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
124
125 return 0;
126 }
127 static int xen_pt_word_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
128 uint16_t *value, uint16_t valid_mask)
129 {
130 XenPTRegInfo *reg = cfg_entry->reg;
131 uint16_t valid_emu_mask = 0;
132
133 /* emulate word register */
134 valid_emu_mask = reg->emu_mask & valid_mask;
135 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
136
137 return 0;
138 }
139 static int xen_pt_long_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
140 uint32_t *value, uint32_t valid_mask)
141 {
142 XenPTRegInfo *reg = cfg_entry->reg;
143 uint32_t valid_emu_mask = 0;
144
145 /* emulate long register */
146 valid_emu_mask = reg->emu_mask & valid_mask;
147 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
148
149 return 0;
150 }
151
152 /* Write register functions */
153
154 static int xen_pt_byte_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
155 uint8_t *val, uint8_t dev_value,
156 uint8_t valid_mask)
157 {
158 XenPTRegInfo *reg = cfg_entry->reg;
159 uint8_t writable_mask = 0;
160 uint8_t throughable_mask = 0;
161
162 /* modify emulate register */
163 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
164 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
165
166 /* create value for writing to I/O device register */
167 throughable_mask = ~reg->emu_mask & valid_mask;
168 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
169
170 return 0;
171 }
172 static int xen_pt_word_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
173 uint16_t *val, uint16_t dev_value,
174 uint16_t valid_mask)
175 {
176 XenPTRegInfo *reg = cfg_entry->reg;
177 uint16_t writable_mask = 0;
178 uint16_t throughable_mask = 0;
179
180 /* modify emulate register */
181 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
182 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
183
184 /* create value for writing to I/O device register */
185 throughable_mask = ~reg->emu_mask & valid_mask;
186 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
187
188 return 0;
189 }
190 static int xen_pt_long_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
191 uint32_t *val, uint32_t dev_value,
192 uint32_t valid_mask)
193 {
194 XenPTRegInfo *reg = cfg_entry->reg;
195 uint32_t writable_mask = 0;
196 uint32_t throughable_mask = 0;
197
198 /* modify emulate register */
199 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
200 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
201
202 /* create value for writing to I/O device register */
203 throughable_mask = ~reg->emu_mask & valid_mask;
204 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
205
206 return 0;
207 }
208
209
210 /* XenPTRegInfo declaration
211 * - only for emulated register (either a part or whole bit).
212 * - for passthrough register that need special behavior (like interacting with
213 * other component), set emu_mask to all 0 and specify r/w func properly.
214 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
215 */
216
217 /********************
218 * Header Type0
219 */
220
221 static int xen_pt_vendor_reg_init(XenPCIPassthroughState *s,
222 XenPTRegInfo *reg, uint32_t real_offset,
223 uint32_t *data)
224 {
225 *data = s->real_device.vendor_id;
226 return 0;
227 }
228 static int xen_pt_device_reg_init(XenPCIPassthroughState *s,
229 XenPTRegInfo *reg, uint32_t real_offset,
230 uint32_t *data)
231 {
232 *data = s->real_device.device_id;
233 return 0;
234 }
235 static int xen_pt_status_reg_init(XenPCIPassthroughState *s,
236 XenPTRegInfo *reg, uint32_t real_offset,
237 uint32_t *data)
238 {
239 XenPTRegGroup *reg_grp_entry = NULL;
240 XenPTReg *reg_entry = NULL;
241 uint32_t reg_field = 0;
242
243 /* find Header register group */
244 reg_grp_entry = xen_pt_find_reg_grp(s, PCI_CAPABILITY_LIST);
245 if (reg_grp_entry) {
246 /* find Capabilities Pointer register */
247 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
248 if (reg_entry) {
249 /* check Capabilities Pointer register */
250 if (reg_entry->data) {
251 reg_field |= PCI_STATUS_CAP_LIST;
252 } else {
253 reg_field &= ~PCI_STATUS_CAP_LIST;
254 }
255 } else {
256 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
257 " for Capabilities Pointer register."
258 " (%s)\n", __func__);
259 return -1;
260 }
261 } else {
262 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
263 " for Header. (%s)\n", __func__);
264 return -1;
265 }
266
267 *data = reg_field;
268 return 0;
269 }
270 static int xen_pt_header_type_reg_init(XenPCIPassthroughState *s,
271 XenPTRegInfo *reg, uint32_t real_offset,
272 uint32_t *data)
273 {
274 /* read PCI_HEADER_TYPE */
275 *data = reg->init_val | 0x80;
276 return 0;
277 }
278
279 /* initialize Interrupt Pin register */
280 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState *s,
281 XenPTRegInfo *reg, uint32_t real_offset,
282 uint32_t *data)
283 {
284 *data = xen_pt_pci_read_intx(s);
285 return 0;
286 }
287
288 /* Command register */
289 static int xen_pt_cmd_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
290 uint16_t *val, uint16_t dev_value,
291 uint16_t valid_mask)
292 {
293 XenPTRegInfo *reg = cfg_entry->reg;
294 uint16_t writable_mask = 0;
295 uint16_t throughable_mask = 0;
296
297 /* modify emulate register */
298 writable_mask = ~reg->ro_mask & valid_mask;
299 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
300
301 /* create value for writing to I/O device register */
302 throughable_mask = ~reg->emu_mask & valid_mask;
303
304 if (*val & PCI_COMMAND_INTX_DISABLE) {
305 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
306 } else {
307 if (s->machine_irq) {
308 throughable_mask |= PCI_COMMAND_INTX_DISABLE;
309 }
310 }
311
312 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
313
314 return 0;
315 }
316
317 /* BAR */
318 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
319 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
320 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
321 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
322
323 static bool is_64bit_bar(PCIIORegion *r)
324 {
325 return !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
326 }
327
328 static uint64_t xen_pt_get_bar_size(PCIIORegion *r)
329 {
330 if (is_64bit_bar(r)) {
331 uint64_t size64;
332 size64 = (r + 1)->size;
333 size64 <<= 32;
334 size64 += r->size;
335 return size64;
336 }
337 return r->size;
338 }
339
340 static XenPTBarFlag xen_pt_bar_reg_parse(XenPCIPassthroughState *s,
341 int index)
342 {
343 PCIDevice *d = &s->dev;
344 XenPTRegion *region = NULL;
345 PCIIORegion *r;
346
347 /* check 64bit BAR */
348 if ((0 < index) && (index < PCI_ROM_SLOT)) {
349 int type = s->real_device.io_regions[index - 1].type;
350
351 if ((type & XEN_HOST_PCI_REGION_TYPE_MEM)
352 && (type & XEN_HOST_PCI_REGION_TYPE_MEM_64)) {
353 region = &s->bases[index - 1];
354 if (region->bar_flag != XEN_PT_BAR_FLAG_UPPER) {
355 return XEN_PT_BAR_FLAG_UPPER;
356 }
357 }
358 }
359
360 /* check unused BAR */
361 r = &d->io_regions[index];
362 if (!xen_pt_get_bar_size(r)) {
363 return XEN_PT_BAR_FLAG_UNUSED;
364 }
365
366 /* for ExpROM BAR */
367 if (index == PCI_ROM_SLOT) {
368 return XEN_PT_BAR_FLAG_MEM;
369 }
370
371 /* check BAR I/O indicator */
372 if (s->real_device.io_regions[index].type & XEN_HOST_PCI_REGION_TYPE_IO) {
373 return XEN_PT_BAR_FLAG_IO;
374 } else {
375 return XEN_PT_BAR_FLAG_MEM;
376 }
377 }
378
379 static inline uint32_t base_address_with_flags(XenHostPCIIORegion *hr)
380 {
381 if (hr->type & XEN_HOST_PCI_REGION_TYPE_IO) {
382 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_IO_MASK);
383 } else {
384 return hr->base_addr | (hr->bus_flags & ~PCI_BASE_ADDRESS_MEM_MASK);
385 }
386 }
387
388 static int xen_pt_bar_reg_init(XenPCIPassthroughState *s, XenPTRegInfo *reg,
389 uint32_t real_offset, uint32_t *data)
390 {
391 uint32_t reg_field = 0;
392 int index;
393
394 index = xen_pt_bar_offset_to_index(reg->offset);
395 if (index < 0 || index >= PCI_NUM_REGIONS) {
396 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
397 return -1;
398 }
399
400 /* set BAR flag */
401 s->bases[index].bar_flag = xen_pt_bar_reg_parse(s, index);
402 if (s->bases[index].bar_flag == XEN_PT_BAR_FLAG_UNUSED) {
403 reg_field = XEN_PT_INVALID_REG;
404 }
405
406 *data = reg_field;
407 return 0;
408 }
409 static int xen_pt_bar_reg_read(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
410 uint32_t *value, uint32_t valid_mask)
411 {
412 XenPTRegInfo *reg = cfg_entry->reg;
413 uint32_t valid_emu_mask = 0;
414 uint32_t bar_emu_mask = 0;
415 int index;
416
417 /* get BAR index */
418 index = xen_pt_bar_offset_to_index(reg->offset);
419 if (index < 0 || index >= PCI_NUM_REGIONS - 1) {
420 XEN_PT_ERR(&s->dev, "Internal error: Invalid BAR index [%d].\n", index);
421 return -1;
422 }
423
424 /* use fixed-up value from kernel sysfs */
425 *value = base_address_with_flags(&s->real_device.io_regions[index]);
426
427 /* set emulate mask depend on BAR flag */
428 switch (s->bases[index].bar_flag) {
429 case XEN_PT_BAR_FLAG_MEM:
430 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
431 break;
432 case XEN_PT_BAR_FLAG_IO:
433 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
434 break;
435 case XEN_PT_BAR_FLAG_UPPER:
436 bar_emu_mask = XEN_PT_BAR_ALLF;
437 break;
438 default:
439 break;
440 }
441
442 /* emulate BAR */
443 valid_emu_mask = bar_emu_mask & valid_mask;
444 *value = XEN_PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
445
446 return 0;
447 }
448 static int xen_pt_bar_reg_write(XenPCIPassthroughState *s, XenPTReg *cfg_entry,
449 uint32_t *val, uint32_t dev_value,
450 uint32_t valid_mask)
451 {
452 XenPTRegInfo *reg = cfg_entry->reg;
453 XenPTRegion *base = NULL;
454 PCIDevice *d = &s->dev;
455 const PCIIORegion *r;
456 uint32_t writable_mask = 0;
457 uint32_t throughable_mask = 0;
458 uint32_t bar_emu_mask = 0;
459 uint32_t bar_ro_mask = 0;
460 uint32_t r_size = 0;
461 int index = 0;
462
463 index = xen_pt_bar_offset_to_index(reg->offset);
464 if (index < 0 || index >= PCI_NUM_REGIONS) {
465 XEN_PT_ERR(d, "Internal error: Invalid BAR index [%d].\n", index);
466 return -1;
467 }
468
469 r = &d->io_regions[index];
470 base = &s->bases[index];
471 r_size = xen_pt_get_emul_size(base->bar_flag, r->size);
472
473 /* set emulate mask and read-only mask values depend on the BAR flag */
474 switch (s->bases[index].bar_flag) {
475 case XEN_PT_BAR_FLAG_MEM:
476 bar_emu_mask = XEN_PT_BAR_MEM_EMU_MASK;
477 if (!r_size) {
478 /* low 32 bits mask for 64 bit bars */
479 bar_ro_mask = XEN_PT_BAR_ALLF;
480 } else {
481 bar_ro_mask = XEN_PT_BAR_MEM_RO_MASK | (r_size - 1);
482 }
483 break;
484 case XEN_PT_BAR_FLAG_IO:
485 bar_emu_mask = XEN_PT_BAR_IO_EMU_MASK;
486 bar_ro_mask = XEN_PT_BAR_IO_RO_MASK | (r_size - 1);
487 break;
488 case XEN_PT_BAR_FLAG_UPPER:
489 bar_emu_mask = XEN_PT_BAR_ALLF;
490 bar_ro_mask = r_size ? r_size - 1 : 0;
491 break;
492 default:
493 break;
494 }
495
496 /* modify emulate register */
497 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
498 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
499
500 /* check whether we need to update the virtual region address or not */
501 switch (s->bases[index].bar_flag) {
502 case XEN_PT_BAR_FLAG_UPPER:
503 case XEN_PT_BAR_FLAG_MEM:
504 /* nothing to do */
505 break;
506 case XEN_PT_BAR_FLAG_IO:
507 /* nothing to do */
508 break;
509 default:
510 break;
511 }
512
513 /* create value for writing to I/O device register */
514 throughable_mask = ~bar_emu_mask & valid_mask;
515 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
516
517 return 0;
518 }
519
520 /* write Exp ROM BAR */
521 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState *s,
522 XenPTReg *cfg_entry, uint32_t *val,
523 uint32_t dev_value, uint32_t valid_mask)
524 {
525 XenPTRegInfo *reg = cfg_entry->reg;
526 XenPTRegion *base = NULL;
527 PCIDevice *d = (PCIDevice *)&s->dev;
528 uint32_t writable_mask = 0;
529 uint32_t throughable_mask = 0;
530 pcibus_t r_size = 0;
531 uint32_t bar_emu_mask = 0;
532 uint32_t bar_ro_mask = 0;
533
534 r_size = d->io_regions[PCI_ROM_SLOT].size;
535 base = &s->bases[PCI_ROM_SLOT];
536 /* align memory type resource size */
537 r_size = xen_pt_get_emul_size(base->bar_flag, r_size);
538
539 /* set emulate mask and read-only mask */
540 bar_emu_mask = reg->emu_mask;
541 bar_ro_mask = (reg->ro_mask | (r_size - 1)) & ~PCI_ROM_ADDRESS_ENABLE;
542
543 /* modify emulate register */
544 writable_mask = ~bar_ro_mask & valid_mask;
545 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
546
547 /* create value for writing to I/O device register */
548 throughable_mask = ~bar_emu_mask & valid_mask;
549 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
550
551 return 0;
552 }
553
554 /* Header Type0 reg static information table */
555 static XenPTRegInfo xen_pt_emu_reg_header0[] = {
556 /* Vendor ID reg */
557 {
558 .offset = PCI_VENDOR_ID,
559 .size = 2,
560 .init_val = 0x0000,
561 .ro_mask = 0xFFFF,
562 .emu_mask = 0xFFFF,
563 .init = xen_pt_vendor_reg_init,
564 .u.w.read = xen_pt_word_reg_read,
565 .u.w.write = xen_pt_word_reg_write,
566 },
567 /* Device ID reg */
568 {
569 .offset = PCI_DEVICE_ID,
570 .size = 2,
571 .init_val = 0x0000,
572 .ro_mask = 0xFFFF,
573 .emu_mask = 0xFFFF,
574 .init = xen_pt_device_reg_init,
575 .u.w.read = xen_pt_word_reg_read,
576 .u.w.write = xen_pt_word_reg_write,
577 },
578 /* Command reg */
579 {
580 .offset = PCI_COMMAND,
581 .size = 2,
582 .init_val = 0x0000,
583 .ro_mask = 0xF880,
584 .emu_mask = 0x0743,
585 .init = xen_pt_common_reg_init,
586 .u.w.read = xen_pt_word_reg_read,
587 .u.w.write = xen_pt_cmd_reg_write,
588 },
589 /* Capabilities Pointer reg */
590 {
591 .offset = PCI_CAPABILITY_LIST,
592 .size = 1,
593 .init_val = 0x00,
594 .ro_mask = 0xFF,
595 .emu_mask = 0xFF,
596 .init = xen_pt_ptr_reg_init,
597 .u.b.read = xen_pt_byte_reg_read,
598 .u.b.write = xen_pt_byte_reg_write,
599 },
600 /* Status reg */
601 /* use emulated Cap Ptr value to initialize,
602 * so need to be declared after Cap Ptr reg
603 */
604 {
605 .offset = PCI_STATUS,
606 .size = 2,
607 .init_val = 0x0000,
608 .ro_mask = 0x06FF,
609 .emu_mask = 0x0010,
610 .init = xen_pt_status_reg_init,
611 .u.w.read = xen_pt_word_reg_read,
612 .u.w.write = xen_pt_word_reg_write,
613 },
614 /* Cache Line Size reg */
615 {
616 .offset = PCI_CACHE_LINE_SIZE,
617 .size = 1,
618 .init_val = 0x00,
619 .ro_mask = 0x00,
620 .emu_mask = 0xFF,
621 .init = xen_pt_common_reg_init,
622 .u.b.read = xen_pt_byte_reg_read,
623 .u.b.write = xen_pt_byte_reg_write,
624 },
625 /* Latency Timer reg */
626 {
627 .offset = PCI_LATENCY_TIMER,
628 .size = 1,
629 .init_val = 0x00,
630 .ro_mask = 0x00,
631 .emu_mask = 0xFF,
632 .init = xen_pt_common_reg_init,
633 .u.b.read = xen_pt_byte_reg_read,
634 .u.b.write = xen_pt_byte_reg_write,
635 },
636 /* Header Type reg */
637 {
638 .offset = PCI_HEADER_TYPE,
639 .size = 1,
640 .init_val = 0x00,
641 .ro_mask = 0xFF,
642 .emu_mask = 0x00,
643 .init = xen_pt_header_type_reg_init,
644 .u.b.read = xen_pt_byte_reg_read,
645 .u.b.write = xen_pt_byte_reg_write,
646 },
647 /* Interrupt Line reg */
648 {
649 .offset = PCI_INTERRUPT_LINE,
650 .size = 1,
651 .init_val = 0x00,
652 .ro_mask = 0x00,
653 .emu_mask = 0xFF,
654 .init = xen_pt_common_reg_init,
655 .u.b.read = xen_pt_byte_reg_read,
656 .u.b.write = xen_pt_byte_reg_write,
657 },
658 /* Interrupt Pin reg */
659 {
660 .offset = PCI_INTERRUPT_PIN,
661 .size = 1,
662 .init_val = 0x00,
663 .ro_mask = 0xFF,
664 .emu_mask = 0xFF,
665 .init = xen_pt_irqpin_reg_init,
666 .u.b.read = xen_pt_byte_reg_read,
667 .u.b.write = xen_pt_byte_reg_write,
668 },
669 /* BAR 0 reg */
670 /* mask of BAR need to be decided later, depends on IO/MEM type */
671 {
672 .offset = PCI_BASE_ADDRESS_0,
673 .size = 4,
674 .init_val = 0x00000000,
675 .init = xen_pt_bar_reg_init,
676 .u.dw.read = xen_pt_bar_reg_read,
677 .u.dw.write = xen_pt_bar_reg_write,
678 },
679 /* BAR 1 reg */
680 {
681 .offset = PCI_BASE_ADDRESS_1,
682 .size = 4,
683 .init_val = 0x00000000,
684 .init = xen_pt_bar_reg_init,
685 .u.dw.read = xen_pt_bar_reg_read,
686 .u.dw.write = xen_pt_bar_reg_write,
687 },
688 /* BAR 2 reg */
689 {
690 .offset = PCI_BASE_ADDRESS_2,
691 .size = 4,
692 .init_val = 0x00000000,
693 .init = xen_pt_bar_reg_init,
694 .u.dw.read = xen_pt_bar_reg_read,
695 .u.dw.write = xen_pt_bar_reg_write,
696 },
697 /* BAR 3 reg */
698 {
699 .offset = PCI_BASE_ADDRESS_3,
700 .size = 4,
701 .init_val = 0x00000000,
702 .init = xen_pt_bar_reg_init,
703 .u.dw.read = xen_pt_bar_reg_read,
704 .u.dw.write = xen_pt_bar_reg_write,
705 },
706 /* BAR 4 reg */
707 {
708 .offset = PCI_BASE_ADDRESS_4,
709 .size = 4,
710 .init_val = 0x00000000,
711 .init = xen_pt_bar_reg_init,
712 .u.dw.read = xen_pt_bar_reg_read,
713 .u.dw.write = xen_pt_bar_reg_write,
714 },
715 /* BAR 5 reg */
716 {
717 .offset = PCI_BASE_ADDRESS_5,
718 .size = 4,
719 .init_val = 0x00000000,
720 .init = xen_pt_bar_reg_init,
721 .u.dw.read = xen_pt_bar_reg_read,
722 .u.dw.write = xen_pt_bar_reg_write,
723 },
724 /* Expansion ROM BAR reg */
725 {
726 .offset = PCI_ROM_ADDRESS,
727 .size = 4,
728 .init_val = 0x00000000,
729 .ro_mask = 0x000007FE,
730 .emu_mask = 0xFFFFF800,
731 .init = xen_pt_bar_reg_init,
732 .u.dw.read = xen_pt_long_reg_read,
733 .u.dw.write = xen_pt_exp_rom_bar_reg_write,
734 },
735 {
736 .size = 0,
737 },
738 };
739
740
741 /*********************************
742 * Vital Product Data Capability
743 */
744
745 /* Vital Product Data Capability Structure reg static information table */
746 static XenPTRegInfo xen_pt_emu_reg_vpd[] = {
747 {
748 .offset = PCI_CAP_LIST_NEXT,
749 .size = 1,
750 .init_val = 0x00,
751 .ro_mask = 0xFF,
752 .emu_mask = 0xFF,
753 .init = xen_pt_ptr_reg_init,
754 .u.b.read = xen_pt_byte_reg_read,
755 .u.b.write = xen_pt_byte_reg_write,
756 },
757 {
758 .size = 0,
759 },
760 };
761
762
763 /**************************************
764 * Vendor Specific Capability
765 */
766
767 /* Vendor Specific Capability Structure reg static information table */
768 static XenPTRegInfo xen_pt_emu_reg_vendor[] = {
769 {
770 .offset = PCI_CAP_LIST_NEXT,
771 .size = 1,
772 .init_val = 0x00,
773 .ro_mask = 0xFF,
774 .emu_mask = 0xFF,
775 .init = xen_pt_ptr_reg_init,
776 .u.b.read = xen_pt_byte_reg_read,
777 .u.b.write = xen_pt_byte_reg_write,
778 },
779 {
780 .size = 0,
781 },
782 };
783
784
785 /*****************************
786 * PCI Express Capability
787 */
788
789 static inline uint8_t get_capability_version(XenPCIPassthroughState *s,
790 uint32_t offset)
791 {
792 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
793 return flags & PCI_EXP_FLAGS_VERS;
794 }
795
796 static inline uint8_t get_device_type(XenPCIPassthroughState *s,
797 uint32_t offset)
798 {
799 uint8_t flags = pci_get_byte(s->dev.config + offset + PCI_EXP_FLAGS);
800 return (flags & PCI_EXP_FLAGS_TYPE) >> 4;
801 }
802
803 /* initialize Link Control register */
804 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState *s,
805 XenPTRegInfo *reg, uint32_t real_offset,
806 uint32_t *data)
807 {
808 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
809 uint8_t dev_type = get_device_type(s, real_offset - reg->offset);
810
811 /* no need to initialize in case of Root Complex Integrated Endpoint
812 * with cap_ver 1.x
813 */
814 if ((dev_type == PCI_EXP_TYPE_RC_END) && (cap_ver == 1)) {
815 *data = XEN_PT_INVALID_REG;
816 }
817
818 *data = reg->init_val;
819 return 0;
820 }
821 /* initialize Device Control 2 register */
822 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState *s,
823 XenPTRegInfo *reg, uint32_t real_offset,
824 uint32_t *data)
825 {
826 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
827
828 /* no need to initialize in case of cap_ver 1.x */
829 if (cap_ver == 1) {
830 *data = XEN_PT_INVALID_REG;
831 }
832
833 *data = reg->init_val;
834 return 0;
835 }
836 /* initialize Link Control 2 register */
837 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState *s,
838 XenPTRegInfo *reg, uint32_t real_offset,
839 uint32_t *data)
840 {
841 uint8_t cap_ver = get_capability_version(s, real_offset - reg->offset);
842 uint32_t reg_field = 0;
843
844 /* no need to initialize in case of cap_ver 1.x */
845 if (cap_ver == 1) {
846 reg_field = XEN_PT_INVALID_REG;
847 } else {
848 /* set Supported Link Speed */
849 uint8_t lnkcap = pci_get_byte(s->dev.config + real_offset - reg->offset
850 + PCI_EXP_LNKCAP);
851 reg_field |= PCI_EXP_LNKCAP_SLS & lnkcap;
852 }
853
854 *data = reg_field;
855 return 0;
856 }
857
858 /* PCI Express Capability Structure reg static information table */
859 static XenPTRegInfo xen_pt_emu_reg_pcie[] = {
860 /* Next Pointer reg */
861 {
862 .offset = PCI_CAP_LIST_NEXT,
863 .size = 1,
864 .init_val = 0x00,
865 .ro_mask = 0xFF,
866 .emu_mask = 0xFF,
867 .init = xen_pt_ptr_reg_init,
868 .u.b.read = xen_pt_byte_reg_read,
869 .u.b.write = xen_pt_byte_reg_write,
870 },
871 /* Device Capabilities reg */
872 {
873 .offset = PCI_EXP_DEVCAP,
874 .size = 4,
875 .init_val = 0x00000000,
876 .ro_mask = 0x1FFCFFFF,
877 .emu_mask = 0x10000000,
878 .init = xen_pt_common_reg_init,
879 .u.dw.read = xen_pt_long_reg_read,
880 .u.dw.write = xen_pt_long_reg_write,
881 },
882 /* Device Control reg */
883 {
884 .offset = PCI_EXP_DEVCTL,
885 .size = 2,
886 .init_val = 0x2810,
887 .ro_mask = 0x8400,
888 .emu_mask = 0xFFFF,
889 .init = xen_pt_common_reg_init,
890 .u.w.read = xen_pt_word_reg_read,
891 .u.w.write = xen_pt_word_reg_write,
892 },
893 /* Link Control reg */
894 {
895 .offset = PCI_EXP_LNKCTL,
896 .size = 2,
897 .init_val = 0x0000,
898 .ro_mask = 0xFC34,
899 .emu_mask = 0xFFFF,
900 .init = xen_pt_linkctrl_reg_init,
901 .u.w.read = xen_pt_word_reg_read,
902 .u.w.write = xen_pt_word_reg_write,
903 },
904 /* Device Control 2 reg */
905 {
906 .offset = 0x28,
907 .size = 2,
908 .init_val = 0x0000,
909 .ro_mask = 0xFFE0,
910 .emu_mask = 0xFFFF,
911 .init = xen_pt_devctrl2_reg_init,
912 .u.w.read = xen_pt_word_reg_read,
913 .u.w.write = xen_pt_word_reg_write,
914 },
915 /* Link Control 2 reg */
916 {
917 .offset = 0x30,
918 .size = 2,
919 .init_val = 0x0000,
920 .ro_mask = 0xE040,
921 .emu_mask = 0xFFFF,
922 .init = xen_pt_linkctrl2_reg_init,
923 .u.w.read = xen_pt_word_reg_read,
924 .u.w.write = xen_pt_word_reg_write,
925 },
926 {
927 .size = 0,
928 },
929 };
930
931
932 /*********************************
933 * Power Management Capability
934 */
935
936 /* write Power Management Control/Status register */
937 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s,
938 XenPTReg *cfg_entry, uint16_t *val,
939 uint16_t dev_value, uint16_t valid_mask)
940 {
941 XenPTRegInfo *reg = cfg_entry->reg;
942 uint16_t writable_mask = 0;
943 uint16_t throughable_mask = 0;
944
945 /* modify emulate register */
946 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
947 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
948
949 /* create value for writing to I/O device register */
950 throughable_mask = ~reg->emu_mask & valid_mask;
951 *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS,
952 throughable_mask);
953
954 return 0;
955 }
956
957 /* Power Management Capability reg static information table */
958 static XenPTRegInfo xen_pt_emu_reg_pm[] = {
959 /* Next Pointer reg */
960 {
961 .offset = PCI_CAP_LIST_NEXT,
962 .size = 1,
963 .init_val = 0x00,
964 .ro_mask = 0xFF,
965 .emu_mask = 0xFF,
966 .init = xen_pt_ptr_reg_init,
967 .u.b.read = xen_pt_byte_reg_read,
968 .u.b.write = xen_pt_byte_reg_write,
969 },
970 /* Power Management Capabilities reg */
971 {
972 .offset = PCI_CAP_FLAGS,
973 .size = 2,
974 .init_val = 0x0000,
975 .ro_mask = 0xFFFF,
976 .emu_mask = 0xF9C8,
977 .init = xen_pt_common_reg_init,
978 .u.w.read = xen_pt_word_reg_read,
979 .u.w.write = xen_pt_word_reg_write,
980 },
981 /* PCI Power Management Control/Status reg */
982 {
983 .offset = PCI_PM_CTRL,
984 .size = 2,
985 .init_val = 0x0008,
986 .ro_mask = 0xE1FC,
987 .emu_mask = 0x810B,
988 .init = xen_pt_common_reg_init,
989 .u.w.read = xen_pt_word_reg_read,
990 .u.w.write = xen_pt_pmcsr_reg_write,
991 },
992 {
993 .size = 0,
994 },
995 };
996
997
998 /********************************
999 * MSI Capability
1000 */
1001
1002 /* Helper */
1003 #define xen_pt_msi_check_type(offset, flags, what) \
1004 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1005 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
1006
1007 /* Message Control register */
1008 static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState *s,
1009 XenPTRegInfo *reg, uint32_t real_offset,
1010 uint32_t *data)
1011 {
1012 PCIDevice *d = &s->dev;
1013 XenPTMSI *msi = s->msi;
1014 uint16_t reg_field = 0;
1015
1016 /* use I/O device register's value as initial value */
1017 reg_field = pci_get_word(d->config + real_offset);
1018
1019 if (reg_field & PCI_MSI_FLAGS_ENABLE) {
1020 XEN_PT_LOG(&s->dev, "MSI already enabled, disabling it first\n");
1021 xen_host_pci_set_word(&s->real_device, real_offset,
1022 reg_field & ~PCI_MSI_FLAGS_ENABLE);
1023 }
1024 msi->flags |= reg_field;
1025 msi->ctrl_offset = real_offset;
1026 msi->initialized = false;
1027 msi->mapped = false;
1028
1029 *data = reg->init_val;
1030 return 0;
1031 }
1032 static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState *s,
1033 XenPTReg *cfg_entry, uint16_t *val,
1034 uint16_t dev_value, uint16_t valid_mask)
1035 {
1036 XenPTRegInfo *reg = cfg_entry->reg;
1037 XenPTMSI *msi = s->msi;
1038 uint16_t writable_mask = 0;
1039 uint16_t throughable_mask = 0;
1040
1041 /* Currently no support for multi-vector */
1042 if (*val & PCI_MSI_FLAGS_QSIZE) {
1043 XEN_PT_WARN(&s->dev, "Tries to set more than 1 vector ctrl %x\n", *val);
1044 }
1045
1046 /* modify emulate register */
1047 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1048 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1049 msi->flags |= cfg_entry->data & ~PCI_MSI_FLAGS_ENABLE;
1050
1051 /* create value for writing to I/O device register */
1052 throughable_mask = ~reg->emu_mask & valid_mask;
1053 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1054
1055 /* update MSI */
1056 if (*val & PCI_MSI_FLAGS_ENABLE) {
1057 /* setup MSI pirq for the first time */
1058 if (!msi->initialized) {
1059 /* Init physical one */
1060 XEN_PT_LOG(&s->dev, "setup MSI\n");
1061 if (xen_pt_msi_setup(s)) {
1062 /* We do not broadcast the error to the framework code, so
1063 * that MSI errors are contained in MSI emulation code and
1064 * QEMU can go on running.
1065 * Guest MSI would be actually not working.
1066 */
1067 *val &= ~PCI_MSI_FLAGS_ENABLE;
1068 XEN_PT_WARN(&s->dev, "Can not map MSI.\n");
1069 return 0;
1070 }
1071 if (xen_pt_msi_update(s)) {
1072 *val &= ~PCI_MSI_FLAGS_ENABLE;
1073 XEN_PT_WARN(&s->dev, "Can not bind MSI\n");
1074 return 0;
1075 }
1076 msi->initialized = true;
1077 msi->mapped = true;
1078 }
1079 msi->flags |= PCI_MSI_FLAGS_ENABLE;
1080 } else if (msi->mapped) {
1081 xen_pt_msi_disable(s);
1082 }
1083
1084 return 0;
1085 }
1086
1087 /* initialize Message Upper Address register */
1088 static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState *s,
1089 XenPTRegInfo *reg, uint32_t real_offset,
1090 uint32_t *data)
1091 {
1092 /* no need to initialize in case of 32 bit type */
1093 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1094 *data = XEN_PT_INVALID_REG;
1095 } else {
1096 *data = reg->init_val;
1097 }
1098
1099 return 0;
1100 }
1101 /* this function will be called twice (for 32 bit and 64 bit type) */
1102 /* initialize Message Data register */
1103 static int xen_pt_msgdata_reg_init(XenPCIPassthroughState *s,
1104 XenPTRegInfo *reg, uint32_t real_offset,
1105 uint32_t *data)
1106 {
1107 uint32_t flags = s->msi->flags;
1108 uint32_t offset = reg->offset;
1109
1110 /* check the offset whether matches the type or not */
1111 if (xen_pt_msi_check_type(offset, flags, DATA)) {
1112 *data = reg->init_val;
1113 } else {
1114 *data = XEN_PT_INVALID_REG;
1115 }
1116 return 0;
1117 }
1118
1119 /* this function will be called twice (for 32 bit and 64 bit type) */
1120 /* initialize Mask register */
1121 static int xen_pt_mask_reg_init(XenPCIPassthroughState *s,
1122 XenPTRegInfo *reg, uint32_t real_offset,
1123 uint32_t *data)
1124 {
1125 uint32_t flags = s->msi->flags;
1126
1127 /* check the offset whether matches the type or not */
1128 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1129 *data = XEN_PT_INVALID_REG;
1130 } else if (xen_pt_msi_check_type(reg->offset, flags, MASK)) {
1131 *data = reg->init_val;
1132 } else {
1133 *data = XEN_PT_INVALID_REG;
1134 }
1135 return 0;
1136 }
1137
1138 /* this function will be called twice (for 32 bit and 64 bit type) */
1139 /* initialize Pending register */
1140 static int xen_pt_pending_reg_init(XenPCIPassthroughState *s,
1141 XenPTRegInfo *reg, uint32_t real_offset,
1142 uint32_t *data)
1143 {
1144 uint32_t flags = s->msi->flags;
1145
1146 /* check the offset whether matches the type or not */
1147 if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
1148 *data = XEN_PT_INVALID_REG;
1149 } else if (xen_pt_msi_check_type(reg->offset, flags, PENDING)) {
1150 *data = reg->init_val;
1151 } else {
1152 *data = XEN_PT_INVALID_REG;
1153 }
1154 return 0;
1155 }
1156
1157 /* write Message Address register */
1158 static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState *s,
1159 XenPTReg *cfg_entry, uint32_t *val,
1160 uint32_t dev_value, uint32_t valid_mask)
1161 {
1162 XenPTRegInfo *reg = cfg_entry->reg;
1163 uint32_t writable_mask = 0;
1164 uint32_t throughable_mask = 0;
1165 uint32_t old_addr = cfg_entry->data;
1166
1167 /* modify emulate register */
1168 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1169 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1170 s->msi->addr_lo = cfg_entry->data;
1171
1172 /* create value for writing to I/O device register */
1173 throughable_mask = ~reg->emu_mask & valid_mask;
1174 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1175
1176 /* update MSI */
1177 if (cfg_entry->data != old_addr) {
1178 if (s->msi->mapped) {
1179 xen_pt_msi_update(s);
1180 }
1181 }
1182
1183 return 0;
1184 }
1185 /* write Message Upper Address register */
1186 static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState *s,
1187 XenPTReg *cfg_entry, uint32_t *val,
1188 uint32_t dev_value, uint32_t valid_mask)
1189 {
1190 XenPTRegInfo *reg = cfg_entry->reg;
1191 uint32_t writable_mask = 0;
1192 uint32_t throughable_mask = 0;
1193 uint32_t old_addr = cfg_entry->data;
1194
1195 /* check whether the type is 64 bit or not */
1196 if (!(s->msi->flags & PCI_MSI_FLAGS_64BIT)) {
1197 XEN_PT_ERR(&s->dev,
1198 "Can't write to the upper address without 64 bit support\n");
1199 return -1;
1200 }
1201
1202 /* modify emulate register */
1203 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1204 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1205 /* update the msi_info too */
1206 s->msi->addr_hi = cfg_entry->data;
1207
1208 /* create value for writing to I/O device register */
1209 throughable_mask = ~reg->emu_mask & valid_mask;
1210 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1211
1212 /* update MSI */
1213 if (cfg_entry->data != old_addr) {
1214 if (s->msi->mapped) {
1215 xen_pt_msi_update(s);
1216 }
1217 }
1218
1219 return 0;
1220 }
1221
1222
1223 /* this function will be called twice (for 32 bit and 64 bit type) */
1224 /* write Message Data register */
1225 static int xen_pt_msgdata_reg_write(XenPCIPassthroughState *s,
1226 XenPTReg *cfg_entry, uint16_t *val,
1227 uint16_t dev_value, uint16_t valid_mask)
1228 {
1229 XenPTRegInfo *reg = cfg_entry->reg;
1230 XenPTMSI *msi = s->msi;
1231 uint16_t writable_mask = 0;
1232 uint16_t throughable_mask = 0;
1233 uint16_t old_data = cfg_entry->data;
1234 uint32_t offset = reg->offset;
1235
1236 /* check the offset whether matches the type or not */
1237 if (!xen_pt_msi_check_type(offset, msi->flags, DATA)) {
1238 /* exit I/O emulator */
1239 XEN_PT_ERR(&s->dev, "the offset does not match the 32/64 bit type!\n");
1240 return -1;
1241 }
1242
1243 /* modify emulate register */
1244 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1245 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1246 /* update the msi_info too */
1247 msi->data = cfg_entry->data;
1248
1249 /* create value for writing to I/O device register */
1250 throughable_mask = ~reg->emu_mask & valid_mask;
1251 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1252
1253 /* update MSI */
1254 if (cfg_entry->data != old_data) {
1255 if (msi->mapped) {
1256 xen_pt_msi_update(s);
1257 }
1258 }
1259
1260 return 0;
1261 }
1262
1263 /* MSI Capability Structure reg static information table */
1264 static XenPTRegInfo xen_pt_emu_reg_msi[] = {
1265 /* Next Pointer reg */
1266 {
1267 .offset = PCI_CAP_LIST_NEXT,
1268 .size = 1,
1269 .init_val = 0x00,
1270 .ro_mask = 0xFF,
1271 .emu_mask = 0xFF,
1272 .init = xen_pt_ptr_reg_init,
1273 .u.b.read = xen_pt_byte_reg_read,
1274 .u.b.write = xen_pt_byte_reg_write,
1275 },
1276 /* Message Control reg */
1277 {
1278 .offset = PCI_MSI_FLAGS,
1279 .size = 2,
1280 .init_val = 0x0000,
1281 .ro_mask = 0xFF8E,
1282 .emu_mask = 0x017E,
1283 .init = xen_pt_msgctrl_reg_init,
1284 .u.w.read = xen_pt_word_reg_read,
1285 .u.w.write = xen_pt_msgctrl_reg_write,
1286 },
1287 /* Message Address reg */
1288 {
1289 .offset = PCI_MSI_ADDRESS_LO,
1290 .size = 4,
1291 .init_val = 0x00000000,
1292 .ro_mask = 0x00000003,
1293 .emu_mask = 0xFFFFFFFF,
1294 .init = xen_pt_common_reg_init,
1295 .u.dw.read = xen_pt_long_reg_read,
1296 .u.dw.write = xen_pt_msgaddr32_reg_write,
1297 },
1298 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1299 {
1300 .offset = PCI_MSI_ADDRESS_HI,
1301 .size = 4,
1302 .init_val = 0x00000000,
1303 .ro_mask = 0x00000000,
1304 .emu_mask = 0xFFFFFFFF,
1305 .init = xen_pt_msgaddr64_reg_init,
1306 .u.dw.read = xen_pt_long_reg_read,
1307 .u.dw.write = xen_pt_msgaddr64_reg_write,
1308 },
1309 /* Message Data reg (16 bits of data for 32-bit devices) */
1310 {
1311 .offset = PCI_MSI_DATA_32,
1312 .size = 2,
1313 .init_val = 0x0000,
1314 .ro_mask = 0x0000,
1315 .emu_mask = 0xFFFF,
1316 .init = xen_pt_msgdata_reg_init,
1317 .u.w.read = xen_pt_word_reg_read,
1318 .u.w.write = xen_pt_msgdata_reg_write,
1319 },
1320 /* Message Data reg (16 bits of data for 64-bit devices) */
1321 {
1322 .offset = PCI_MSI_DATA_64,
1323 .size = 2,
1324 .init_val = 0x0000,
1325 .ro_mask = 0x0000,
1326 .emu_mask = 0xFFFF,
1327 .init = xen_pt_msgdata_reg_init,
1328 .u.w.read = xen_pt_word_reg_read,
1329 .u.w.write = xen_pt_msgdata_reg_write,
1330 },
1331 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1332 {
1333 .offset = PCI_MSI_MASK_32,
1334 .size = 4,
1335 .init_val = 0x00000000,
1336 .ro_mask = 0xFFFFFFFF,
1337 .emu_mask = 0xFFFFFFFF,
1338 .init = xen_pt_mask_reg_init,
1339 .u.dw.read = xen_pt_long_reg_read,
1340 .u.dw.write = xen_pt_long_reg_write,
1341 },
1342 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1343 {
1344 .offset = PCI_MSI_MASK_64,
1345 .size = 4,
1346 .init_val = 0x00000000,
1347 .ro_mask = 0xFFFFFFFF,
1348 .emu_mask = 0xFFFFFFFF,
1349 .init = xen_pt_mask_reg_init,
1350 .u.dw.read = xen_pt_long_reg_read,
1351 .u.dw.write = xen_pt_long_reg_write,
1352 },
1353 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1354 {
1355 .offset = PCI_MSI_MASK_32 + 4,
1356 .size = 4,
1357 .init_val = 0x00000000,
1358 .ro_mask = 0xFFFFFFFF,
1359 .emu_mask = 0x00000000,
1360 .init = xen_pt_pending_reg_init,
1361 .u.dw.read = xen_pt_long_reg_read,
1362 .u.dw.write = xen_pt_long_reg_write,
1363 },
1364 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1365 {
1366 .offset = PCI_MSI_MASK_64 + 4,
1367 .size = 4,
1368 .init_val = 0x00000000,
1369 .ro_mask = 0xFFFFFFFF,
1370 .emu_mask = 0x00000000,
1371 .init = xen_pt_pending_reg_init,
1372 .u.dw.read = xen_pt_long_reg_read,
1373 .u.dw.write = xen_pt_long_reg_write,
1374 },
1375 {
1376 .size = 0,
1377 },
1378 };
1379
1380
1381 /**************************************
1382 * MSI-X Capability
1383 */
1384
1385 /* Message Control register for MSI-X */
1386 static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState *s,
1387 XenPTRegInfo *reg, uint32_t real_offset,
1388 uint32_t *data)
1389 {
1390 PCIDevice *d = &s->dev;
1391 uint16_t reg_field = 0;
1392
1393 /* use I/O device register's value as initial value */
1394 reg_field = pci_get_word(d->config + real_offset);
1395
1396 if (reg_field & PCI_MSIX_FLAGS_ENABLE) {
1397 XEN_PT_LOG(d, "MSIX already enabled, disabling it first\n");
1398 xen_host_pci_set_word(&s->real_device, real_offset,
1399 reg_field & ~PCI_MSIX_FLAGS_ENABLE);
1400 }
1401
1402 s->msix->ctrl_offset = real_offset;
1403
1404 *data = reg->init_val;
1405 return 0;
1406 }
1407 static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState *s,
1408 XenPTReg *cfg_entry, uint16_t *val,
1409 uint16_t dev_value, uint16_t valid_mask)
1410 {
1411 XenPTRegInfo *reg = cfg_entry->reg;
1412 uint16_t writable_mask = 0;
1413 uint16_t throughable_mask = 0;
1414 int debug_msix_enabled_old;
1415
1416 /* modify emulate register */
1417 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
1418 cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask);
1419
1420 /* create value for writing to I/O device register */
1421 throughable_mask = ~reg->emu_mask & valid_mask;
1422 *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask);
1423
1424 /* update MSI-X */
1425 if ((*val & PCI_MSIX_FLAGS_ENABLE)
1426 && !(*val & PCI_MSIX_FLAGS_MASKALL)) {
1427 xen_pt_msix_update(s);
1428 } else if (!(*val & PCI_MSIX_FLAGS_ENABLE) && s->msix->enabled) {
1429 xen_pt_msix_disable(s);
1430 }
1431
1432 debug_msix_enabled_old = s->msix->enabled;
1433 s->msix->enabled = !!(*val & PCI_MSIX_FLAGS_ENABLE);
1434 if (s->msix->enabled != debug_msix_enabled_old) {
1435 XEN_PT_LOG(&s->dev, "%s MSI-X\n",
1436 s->msix->enabled ? "enable" : "disable");
1437 }
1438
1439 return 0;
1440 }
1441
1442 /* MSI-X Capability Structure reg static information table */
1443 static XenPTRegInfo xen_pt_emu_reg_msix[] = {
1444 /* Next Pointer reg */
1445 {
1446 .offset = PCI_CAP_LIST_NEXT,
1447 .size = 1,
1448 .init_val = 0x00,
1449 .ro_mask = 0xFF,
1450 .emu_mask = 0xFF,
1451 .init = xen_pt_ptr_reg_init,
1452 .u.b.read = xen_pt_byte_reg_read,
1453 .u.b.write = xen_pt_byte_reg_write,
1454 },
1455 /* Message Control reg */
1456 {
1457 .offset = PCI_MSI_FLAGS,
1458 .size = 2,
1459 .init_val = 0x0000,
1460 .ro_mask = 0x3FFF,
1461 .emu_mask = 0x0000,
1462 .init = xen_pt_msixctrl_reg_init,
1463 .u.w.read = xen_pt_word_reg_read,
1464 .u.w.write = xen_pt_msixctrl_reg_write,
1465 },
1466 {
1467 .size = 0,
1468 },
1469 };
1470
1471
1472 /****************************
1473 * Capabilities
1474 */
1475
1476 /* capability structure register group size functions */
1477
1478 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState *s,
1479 const XenPTRegGroupInfo *grp_reg,
1480 uint32_t base_offset, uint8_t *size)
1481 {
1482 *size = grp_reg->grp_size;
1483 return 0;
1484 }
1485 /* get Vendor Specific Capability Structure register group size */
1486 static int xen_pt_vendor_size_init(XenPCIPassthroughState *s,
1487 const XenPTRegGroupInfo *grp_reg,
1488 uint32_t base_offset, uint8_t *size)
1489 {
1490 *size = pci_get_byte(s->dev.config + base_offset + 0x02);
1491 return 0;
1492 }
1493 /* get PCI Express Capability Structure register group size */
1494 static int xen_pt_pcie_size_init(XenPCIPassthroughState *s,
1495 const XenPTRegGroupInfo *grp_reg,
1496 uint32_t base_offset, uint8_t *size)
1497 {
1498 PCIDevice *d = &s->dev;
1499 uint8_t version = get_capability_version(s, base_offset);
1500 uint8_t type = get_device_type(s, base_offset);
1501 uint8_t pcie_size = 0;
1502
1503
1504 /* calculate size depend on capability version and device/port type */
1505 /* in case of PCI Express Base Specification Rev 1.x */
1506 if (version == 1) {
1507 /* The PCI Express Capabilities, Device Capabilities, and Device
1508 * Status/Control registers are required for all PCI Express devices.
1509 * The Link Capabilities and Link Status/Control are required for all
1510 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1511 * are not required to implement registers other than those listed
1512 * above and terminate the capability structure.
1513 */
1514 switch (type) {
1515 case PCI_EXP_TYPE_ENDPOINT:
1516 case PCI_EXP_TYPE_LEG_END:
1517 pcie_size = 0x14;
1518 break;
1519 case PCI_EXP_TYPE_RC_END:
1520 /* has no link */
1521 pcie_size = 0x0C;
1522 break;
1523 /* only EndPoint passthrough is supported */
1524 case PCI_EXP_TYPE_ROOT_PORT:
1525 case PCI_EXP_TYPE_UPSTREAM:
1526 case PCI_EXP_TYPE_DOWNSTREAM:
1527 case PCI_EXP_TYPE_PCI_BRIDGE:
1528 case PCI_EXP_TYPE_PCIE_BRIDGE:
1529 case PCI_EXP_TYPE_RC_EC:
1530 default:
1531 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1532 return -1;
1533 }
1534 }
1535 /* in case of PCI Express Base Specification Rev 2.0 */
1536 else if (version == 2) {
1537 switch (type) {
1538 case PCI_EXP_TYPE_ENDPOINT:
1539 case PCI_EXP_TYPE_LEG_END:
1540 case PCI_EXP_TYPE_RC_END:
1541 /* For Functions that do not implement the registers,
1542 * these spaces must be hardwired to 0b.
1543 */
1544 pcie_size = 0x3C;
1545 break;
1546 /* only EndPoint passthrough is supported */
1547 case PCI_EXP_TYPE_ROOT_PORT:
1548 case PCI_EXP_TYPE_UPSTREAM:
1549 case PCI_EXP_TYPE_DOWNSTREAM:
1550 case PCI_EXP_TYPE_PCI_BRIDGE:
1551 case PCI_EXP_TYPE_PCIE_BRIDGE:
1552 case PCI_EXP_TYPE_RC_EC:
1553 default:
1554 XEN_PT_ERR(d, "Unsupported device/port type %#x.\n", type);
1555 return -1;
1556 }
1557 } else {
1558 XEN_PT_ERR(d, "Unsupported capability version %#x.\n", version);
1559 return -1;
1560 }
1561
1562 *size = pcie_size;
1563 return 0;
1564 }
1565 /* get MSI Capability Structure register group size */
1566 static int xen_pt_msi_size_init(XenPCIPassthroughState *s,
1567 const XenPTRegGroupInfo *grp_reg,
1568 uint32_t base_offset, uint8_t *size)
1569 {
1570 PCIDevice *d = &s->dev;
1571 uint16_t msg_ctrl = 0;
1572 uint8_t msi_size = 0xa;
1573
1574 msg_ctrl = pci_get_word(d->config + (base_offset + PCI_MSI_FLAGS));
1575
1576 /* check if 64-bit address is capable of per-vector masking */
1577 if (msg_ctrl & PCI_MSI_FLAGS_64BIT) {
1578 msi_size += 4;
1579 }
1580 if (msg_ctrl & PCI_MSI_FLAGS_MASKBIT) {
1581 msi_size += 10;
1582 }
1583
1584 s->msi = g_new0(XenPTMSI, 1);
1585 s->msi->pirq = XEN_PT_UNASSIGNED_PIRQ;
1586
1587 *size = msi_size;
1588 return 0;
1589 }
1590 /* get MSI-X Capability Structure register group size */
1591 static int xen_pt_msix_size_init(XenPCIPassthroughState *s,
1592 const XenPTRegGroupInfo *grp_reg,
1593 uint32_t base_offset, uint8_t *size)
1594 {
1595 int rc = 0;
1596
1597 rc = xen_pt_msix_init(s, base_offset);
1598
1599 if (rc < 0) {
1600 XEN_PT_ERR(&s->dev, "Internal error: Invalid xen_pt_msix_init.\n");
1601 return rc;
1602 }
1603
1604 *size = grp_reg->grp_size;
1605 return 0;
1606 }
1607
1608
1609 static const XenPTRegGroupInfo xen_pt_emu_reg_grps[] = {
1610 /* Header Type0 reg group */
1611 {
1612 .grp_id = 0xFF,
1613 .grp_type = XEN_PT_GRP_TYPE_EMU,
1614 .grp_size = 0x40,
1615 .size_init = xen_pt_reg_grp_size_init,
1616 .emu_regs = xen_pt_emu_reg_header0,
1617 },
1618 /* PCI PowerManagement Capability reg group */
1619 {
1620 .grp_id = PCI_CAP_ID_PM,
1621 .grp_type = XEN_PT_GRP_TYPE_EMU,
1622 .grp_size = PCI_PM_SIZEOF,
1623 .size_init = xen_pt_reg_grp_size_init,
1624 .emu_regs = xen_pt_emu_reg_pm,
1625 },
1626 /* AGP Capability Structure reg group */
1627 {
1628 .grp_id = PCI_CAP_ID_AGP,
1629 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1630 .grp_size = 0x30,
1631 .size_init = xen_pt_reg_grp_size_init,
1632 },
1633 /* Vital Product Data Capability Structure reg group */
1634 {
1635 .grp_id = PCI_CAP_ID_VPD,
1636 .grp_type = XEN_PT_GRP_TYPE_EMU,
1637 .grp_size = 0x08,
1638 .size_init = xen_pt_reg_grp_size_init,
1639 .emu_regs = xen_pt_emu_reg_vpd,
1640 },
1641 /* Slot Identification reg group */
1642 {
1643 .grp_id = PCI_CAP_ID_SLOTID,
1644 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1645 .grp_size = 0x04,
1646 .size_init = xen_pt_reg_grp_size_init,
1647 },
1648 /* MSI Capability Structure reg group */
1649 {
1650 .grp_id = PCI_CAP_ID_MSI,
1651 .grp_type = XEN_PT_GRP_TYPE_EMU,
1652 .grp_size = 0xFF,
1653 .size_init = xen_pt_msi_size_init,
1654 .emu_regs = xen_pt_emu_reg_msi,
1655 },
1656 /* PCI-X Capabilities List Item reg group */
1657 {
1658 .grp_id = PCI_CAP_ID_PCIX,
1659 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1660 .grp_size = 0x18,
1661 .size_init = xen_pt_reg_grp_size_init,
1662 },
1663 /* Vendor Specific Capability Structure reg group */
1664 {
1665 .grp_id = PCI_CAP_ID_VNDR,
1666 .grp_type = XEN_PT_GRP_TYPE_EMU,
1667 .grp_size = 0xFF,
1668 .size_init = xen_pt_vendor_size_init,
1669 .emu_regs = xen_pt_emu_reg_vendor,
1670 },
1671 /* SHPC Capability List Item reg group */
1672 {
1673 .grp_id = PCI_CAP_ID_SHPC,
1674 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1675 .grp_size = 0x08,
1676 .size_init = xen_pt_reg_grp_size_init,
1677 },
1678 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1679 {
1680 .grp_id = PCI_CAP_ID_SSVID,
1681 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1682 .grp_size = 0x08,
1683 .size_init = xen_pt_reg_grp_size_init,
1684 },
1685 /* AGP 8x Capability Structure reg group */
1686 {
1687 .grp_id = PCI_CAP_ID_AGP3,
1688 .grp_type = XEN_PT_GRP_TYPE_HARDWIRED,
1689 .grp_size = 0x30,
1690 .size_init = xen_pt_reg_grp_size_init,
1691 },
1692 /* PCI Express Capability Structure reg group */
1693 {
1694 .grp_id = PCI_CAP_ID_EXP,
1695 .grp_type = XEN_PT_GRP_TYPE_EMU,
1696 .grp_size = 0xFF,
1697 .size_init = xen_pt_pcie_size_init,
1698 .emu_regs = xen_pt_emu_reg_pcie,
1699 },
1700 /* MSI-X Capability Structure reg group */
1701 {
1702 .grp_id = PCI_CAP_ID_MSIX,
1703 .grp_type = XEN_PT_GRP_TYPE_EMU,
1704 .grp_size = 0x0C,
1705 .size_init = xen_pt_msix_size_init,
1706 .emu_regs = xen_pt_emu_reg_msix,
1707 },
1708 {
1709 .grp_size = 0,
1710 },
1711 };
1712
1713 /* initialize Capabilities Pointer or Next Pointer register */
1714 static int xen_pt_ptr_reg_init(XenPCIPassthroughState *s,
1715 XenPTRegInfo *reg, uint32_t real_offset,
1716 uint32_t *data)
1717 {
1718 int i;
1719 uint8_t *config = s->dev.config;
1720 uint32_t reg_field = pci_get_byte(config + real_offset);
1721 uint8_t cap_id = 0;
1722
1723 /* find capability offset */
1724 while (reg_field) {
1725 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1726 if (xen_pt_hide_dev_cap(&s->real_device,
1727 xen_pt_emu_reg_grps[i].grp_id)) {
1728 continue;
1729 }
1730
1731 cap_id = pci_get_byte(config + reg_field + PCI_CAP_LIST_ID);
1732 if (xen_pt_emu_reg_grps[i].grp_id == cap_id) {
1733 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1734 goto out;
1735 }
1736 /* ignore the 0 hardwired capability, find next one */
1737 break;
1738 }
1739 }
1740
1741 /* next capability */
1742 reg_field = pci_get_byte(config + reg_field + PCI_CAP_LIST_NEXT);
1743 }
1744
1745 out:
1746 *data = reg_field;
1747 return 0;
1748 }
1749
1750
1751 /*************
1752 * Main
1753 */
1754
1755 static uint8_t find_cap_offset(XenPCIPassthroughState *s, uint8_t cap)
1756 {
1757 uint8_t id;
1758 unsigned max_cap = PCI_CAP_MAX;
1759 uint8_t pos = PCI_CAPABILITY_LIST;
1760 uint8_t status = 0;
1761
1762 if (xen_host_pci_get_byte(&s->real_device, PCI_STATUS, &status)) {
1763 return 0;
1764 }
1765 if ((status & PCI_STATUS_CAP_LIST) == 0) {
1766 return 0;
1767 }
1768
1769 while (max_cap--) {
1770 if (xen_host_pci_get_byte(&s->real_device, pos, &pos)) {
1771 break;
1772 }
1773 if (pos < PCI_CONFIG_HEADER_SIZE) {
1774 break;
1775 }
1776
1777 pos &= ~3;
1778 if (xen_host_pci_get_byte(&s->real_device,
1779 pos + PCI_CAP_LIST_ID, &id)) {
1780 break;
1781 }
1782
1783 if (id == 0xff) {
1784 break;
1785 }
1786 if (id == cap) {
1787 return pos;
1788 }
1789
1790 pos += PCI_CAP_LIST_NEXT;
1791 }
1792 return 0;
1793 }
1794
1795 static int xen_pt_config_reg_init(XenPCIPassthroughState *s,
1796 XenPTRegGroup *reg_grp, XenPTRegInfo *reg)
1797 {
1798 XenPTReg *reg_entry;
1799 uint32_t data = 0;
1800 int rc = 0;
1801
1802 reg_entry = g_new0(XenPTReg, 1);
1803 reg_entry->reg = reg;
1804
1805 if (reg->init) {
1806 /* initialize emulate register */
1807 rc = reg->init(s, reg_entry->reg,
1808 reg_grp->base_offset + reg->offset, &data);
1809 if (rc < 0) {
1810 g_free(reg_entry);
1811 return rc;
1812 }
1813 if (data == XEN_PT_INVALID_REG) {
1814 /* free unused BAR register entry */
1815 g_free(reg_entry);
1816 return 0;
1817 }
1818 /* set register value */
1819 reg_entry->data = data;
1820 }
1821 /* list add register entry */
1822 QLIST_INSERT_HEAD(&reg_grp->reg_tbl_list, reg_entry, entries);
1823
1824 return 0;
1825 }
1826
1827 int xen_pt_config_init(XenPCIPassthroughState *s)
1828 {
1829 int i, rc;
1830
1831 QLIST_INIT(&s->reg_grps);
1832
1833 for (i = 0; xen_pt_emu_reg_grps[i].grp_size != 0; i++) {
1834 uint32_t reg_grp_offset = 0;
1835 XenPTRegGroup *reg_grp_entry = NULL;
1836
1837 if (xen_pt_emu_reg_grps[i].grp_id != 0xFF) {
1838 if (xen_pt_hide_dev_cap(&s->real_device,
1839 xen_pt_emu_reg_grps[i].grp_id)) {
1840 continue;
1841 }
1842
1843 reg_grp_offset = find_cap_offset(s, xen_pt_emu_reg_grps[i].grp_id);
1844
1845 if (!reg_grp_offset) {
1846 continue;
1847 }
1848 }
1849
1850 reg_grp_entry = g_new0(XenPTRegGroup, 1);
1851 QLIST_INIT(&reg_grp_entry->reg_tbl_list);
1852 QLIST_INSERT_HEAD(&s->reg_grps, reg_grp_entry, entries);
1853
1854 reg_grp_entry->base_offset = reg_grp_offset;
1855 reg_grp_entry->reg_grp = xen_pt_emu_reg_grps + i;
1856 if (xen_pt_emu_reg_grps[i].size_init) {
1857 /* get register group size */
1858 rc = xen_pt_emu_reg_grps[i].size_init(s, reg_grp_entry->reg_grp,
1859 reg_grp_offset,
1860 &reg_grp_entry->size);
1861 if (rc < 0) {
1862 xen_pt_config_delete(s);
1863 return rc;
1864 }
1865 }
1866
1867 if (xen_pt_emu_reg_grps[i].grp_type == XEN_PT_GRP_TYPE_EMU) {
1868 if (xen_pt_emu_reg_grps[i].emu_regs) {
1869 int j = 0;
1870 XenPTRegInfo *regs = xen_pt_emu_reg_grps[i].emu_regs;
1871 /* initialize capability register */
1872 for (j = 0; regs->size != 0; j++, regs++) {
1873 /* initialize capability register */
1874 rc = xen_pt_config_reg_init(s, reg_grp_entry, regs);
1875 if (rc < 0) {
1876 xen_pt_config_delete(s);
1877 return rc;
1878 }
1879 }
1880 }
1881 }
1882 }
1883
1884 return 0;
1885 }
1886
1887 /* delete all emulate register */
1888 void xen_pt_config_delete(XenPCIPassthroughState *s)
1889 {
1890 struct XenPTRegGroup *reg_group, *next_grp;
1891 struct XenPTReg *reg, *next_reg;
1892
1893 /* free MSI/MSI-X info table */
1894 if (s->msix) {
1895 xen_pt_msix_delete(s);
1896 }
1897 if (s->msi) {
1898 g_free(s->msi);
1899 }
1900
1901 /* free all register group entry */
1902 QLIST_FOREACH_SAFE(reg_group, &s->reg_grps, entries, next_grp) {
1903 /* free all register entry */
1904 QLIST_FOREACH_SAFE(reg, &reg_group->reg_tbl_list, entries, next_reg) {
1905 QLIST_REMOVE(reg, entries);
1906 g_free(reg);
1907 }
1908
1909 QLIST_REMOVE(reg_group, entries);
1910 g_free(reg_group);
1911 }
1912 }
AR7 emulation for QEMU