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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / target-cris / translate.c
blob51636ed6d13da23eed83faa630a05aea2090f4a3
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "qemu/osdep.h"
27 #include "cpu.h"
28 #include "disas/disas.h"
29 #include "tcg-op.h"
30 #include "exec/helper-proto.h"
31 #include "mmu.h"
32 #include "exec/cpu_ldst.h"
33 #include "crisv32-decode.h"
34
35 #include "exec/helper-gen.h"
36
37 #include "trace-tcg.h"
38 #include "exec/log.h"
39
40
41 #define DISAS_CRIS 0
42 #if DISAS_CRIS
43 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
44 #else
45 # define LOG_DIS(...) do { } while (0)
46 #endif
47
48 #define D(x)
49 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
50 #define BUG_ON(x) ({if (x) BUG();})
51
52 #define DISAS_SWI 5
53
54 /* Used by the decoder. */
55 #define EXTRACT_FIELD(src, start, end) \
56 (((src) >> start) & ((1 << (end - start + 1)) - 1))
57
58 #define CC_MASK_NZ 0xc
59 #define CC_MASK_NZV 0xe
60 #define CC_MASK_NZVC 0xf
61 #define CC_MASK_RNZV 0x10e
62
63 static TCGv_env cpu_env;
64 static TCGv cpu_R[16];
65 static TCGv cpu_PR[16];
66 static TCGv cc_x;
67 static TCGv cc_src;
68 static TCGv cc_dest;
69 static TCGv cc_result;
70 static TCGv cc_op;
71 static TCGv cc_size;
72 static TCGv cc_mask;
73
74 static TCGv env_btaken;
75 static TCGv env_btarget;
76 static TCGv env_pc;
77
78 #include "exec/gen-icount.h"
79
80 /* This is the state at translation time. */
81 typedef struct DisasContext {
82 CRISCPU *cpu;
83 target_ulong pc, ppc;
84
85 /* Decoder. */
86 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
87 uint32_t ir;
88 uint32_t opcode;
89 unsigned int op1;
90 unsigned int op2;
91 unsigned int zsize, zzsize;
92 unsigned int mode;
93 unsigned int postinc;
94
95 unsigned int size;
96 unsigned int src;
97 unsigned int dst;
98 unsigned int cond;
99
100 int update_cc;
101 int cc_op;
102 int cc_size;
103 uint32_t cc_mask;
104
105 int cc_size_uptodate; /* -1 invalid or last written value. */
106
107 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
108 int flags_uptodate; /* Whether or not $ccs is up-to-date. */
109 int flagx_known; /* Whether or not flags_x has the x flag known at
110 translation time. */
111 int flags_x;
112
113 int clear_x; /* Clear x after this insn? */
114 int clear_prefix; /* Clear prefix after this insn? */
115 int clear_locked_irq; /* Clear the irq lockout. */
116 int cpustate_changed;
117 unsigned int tb_flags; /* tb dependent flags. */
118 int is_jmp;
119
120 #define JMP_NOJMP 0
121 #define JMP_DIRECT 1
122 #define JMP_DIRECT_CC 2
123 #define JMP_INDIRECT 3
124 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
125 uint32_t jmp_pc;
126
127 int delayed_branch;
128
129 struct TranslationBlock *tb;
130 int singlestep_enabled;
131 } DisasContext;
132
133 static void QEMU_NORETURN gen_BUG(DisasContext *dc, const char *file, int line)
134 {
135 fprintf(stderr, "BUG: pc=%x %s %d\n", dc->pc, file, line);
136 if (qemu_log_separate()) {
137 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
138 }
139 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
140 }
141
142 static const char *regnames[] =
143 {
144 "$r0", "$r1", "$r2", "$r3",
145 "$r4", "$r5", "$r6", "$r7",
146 "$r8", "$r9", "$r10", "$r11",
147 "$r12", "$r13", "$sp", "$acr",
148 };
149 static const char *pregnames[] =
150 {
151 "$bz", "$vr", "$pid", "$srs",
152 "$wz", "$exs", "$eda", "$mof",
153 "$dz", "$ebp", "$erp", "$srp",
154 "$nrp", "$ccs", "$usp", "$spc",
155 };
156
157 /* We need this table to handle preg-moves with implicit width. */
158 static int preg_sizes[] = {
159 1, /* bz. */
160 1, /* vr. */
161 4, /* pid. */
162 1, /* srs. */
163 2, /* wz. */
164 4, 4, 4,
165 4, 4, 4, 4,
166 4, 4, 4, 4,
167 };
168
169 #define t_gen_mov_TN_env(tn, member) \
170 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
171 #define t_gen_mov_env_TN(member, tn) \
172 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
173
174 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
175 {
176 assert(r >= 0 && r <= 15);
177 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
178 tcg_gen_mov_tl(tn, tcg_const_tl(0));
179 } else if (r == PR_VR) {
180 tcg_gen_mov_tl(tn, tcg_const_tl(32));
181 } else {
182 tcg_gen_mov_tl(tn, cpu_PR[r]);
183 }
184 }
185 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
186 {
187 assert(r >= 0 && r <= 15);
188 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
189 return;
190 } else if (r == PR_SRS) {
191 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
192 } else {
193 if (r == PR_PID) {
194 gen_helper_tlb_flush_pid(cpu_env, tn);
195 }
196 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
197 gen_helper_spc_write(cpu_env, tn);
198 } else if (r == PR_CCS) {
199 dc->cpustate_changed = 1;
200 }
201 tcg_gen_mov_tl(cpu_PR[r], tn);
202 }
203 }
204
205 /* Sign extend at translation time. */
206 static int sign_extend(unsigned int val, unsigned int width)
207 {
208 int sval;
209
210 /* LSL. */
211 val <<= 31 - width;
212 sval = val;
213 /* ASR. */
214 sval >>= 31 - width;
215 return sval;
216 }
217
218 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
219 unsigned int size, unsigned int sign)
220 {
221 int r;
222
223 switch (size) {
224 case 4:
225 {
226 r = cpu_ldl_code(env, addr);
227 break;
228 }
229 case 2:
230 {
231 if (sign) {
232 r = cpu_ldsw_code(env, addr);
233 } else {
234 r = cpu_lduw_code(env, addr);
235 }
236 break;
237 }
238 case 1:
239 {
240 if (sign) {
241 r = cpu_ldsb_code(env, addr);
242 } else {
243 r = cpu_ldub_code(env, addr);
244 }
245 break;
246 }
247 default:
248 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
249 break;
250 }
251 return r;
252 }
253
254 static void cris_lock_irq(DisasContext *dc)
255 {
256 dc->clear_locked_irq = 0;
257 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
258 }
259
260 static inline void t_gen_raise_exception(uint32_t index)
261 {
262 TCGv_i32 tmp = tcg_const_i32(index);
263 gen_helper_raise_exception(cpu_env, tmp);
264 tcg_temp_free_i32(tmp);
265 }
266
267 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
268 {
269 TCGv t0, t_31;
270
271 t0 = tcg_temp_new();
272 t_31 = tcg_const_tl(31);
273 tcg_gen_shl_tl(d, a, b);
274
275 tcg_gen_sub_tl(t0, t_31, b);
276 tcg_gen_sar_tl(t0, t0, t_31);
277 tcg_gen_and_tl(t0, t0, d);
278 tcg_gen_xor_tl(d, d, t0);
279 tcg_temp_free(t0);
280 tcg_temp_free(t_31);
281 }
282
283 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
284 {
285 TCGv t0, t_31;
286
287 t0 = tcg_temp_new();
288 t_31 = tcg_temp_new();
289 tcg_gen_shr_tl(d, a, b);
290
291 tcg_gen_movi_tl(t_31, 31);
292 tcg_gen_sub_tl(t0, t_31, b);
293 tcg_gen_sar_tl(t0, t0, t_31);
294 tcg_gen_and_tl(t0, t0, d);
295 tcg_gen_xor_tl(d, d, t0);
296 tcg_temp_free(t0);
297 tcg_temp_free(t_31);
298 }
299
300 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
301 {
302 TCGv t0, t_31;
303
304 t0 = tcg_temp_new();
305 t_31 = tcg_temp_new();
306 tcg_gen_sar_tl(d, a, b);
307
308 tcg_gen_movi_tl(t_31, 31);
309 tcg_gen_sub_tl(t0, t_31, b);
310 tcg_gen_sar_tl(t0, t0, t_31);
311 tcg_gen_or_tl(d, d, t0);
312 tcg_temp_free(t0);
313 tcg_temp_free(t_31);
314 }
315
316 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
317 {
318 TCGv t = tcg_temp_new();
319
320 /*
321 * d <<= 1
322 * if (d >= s)
323 * d -= s;
324 */
325 tcg_gen_shli_tl(d, a, 1);
326 tcg_gen_sub_tl(t, d, b);
327 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d);
328 tcg_temp_free(t);
329 }
330
331 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
332 {
333 TCGv t;
334
335 /*
336 * d <<= 1
337 * if (n)
338 * d += s;
339 */
340 t = tcg_temp_new();
341 tcg_gen_shli_tl(d, a, 1);
342 tcg_gen_shli_tl(t, ccs, 31 - 3);
343 tcg_gen_sari_tl(t, t, 31);
344 tcg_gen_and_tl(t, t, b);
345 tcg_gen_add_tl(d, d, t);
346 tcg_temp_free(t);
347 }
348
349 /* Extended arithmetics on CRIS. */
350 static inline void t_gen_add_flag(TCGv d, int flag)
351 {
352 TCGv c;
353
354 c = tcg_temp_new();
355 t_gen_mov_TN_preg(c, PR_CCS);
356 /* Propagate carry into d. */
357 tcg_gen_andi_tl(c, c, 1 << flag);
358 if (flag) {
359 tcg_gen_shri_tl(c, c, flag);
360 }
361 tcg_gen_add_tl(d, d, c);
362 tcg_temp_free(c);
363 }
364
365 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
366 {
367 if (dc->flagx_known) {
368 if (dc->flags_x) {
369 TCGv c;
370
371 c = tcg_temp_new();
372 t_gen_mov_TN_preg(c, PR_CCS);
373 /* C flag is already at bit 0. */
374 tcg_gen_andi_tl(c, c, C_FLAG);
375 tcg_gen_add_tl(d, d, c);
376 tcg_temp_free(c);
377 }
378 } else {
379 TCGv x, c;
380
381 x = tcg_temp_new();
382 c = tcg_temp_new();
383 t_gen_mov_TN_preg(x, PR_CCS);
384 tcg_gen_mov_tl(c, x);
385
386 /* Propagate carry into d if X is set. Branch free. */
387 tcg_gen_andi_tl(c, c, C_FLAG);
388 tcg_gen_andi_tl(x, x, X_FLAG);
389 tcg_gen_shri_tl(x, x, 4);
390
391 tcg_gen_and_tl(x, x, c);
392 tcg_gen_add_tl(d, d, x);
393 tcg_temp_free(x);
394 tcg_temp_free(c);
395 }
396 }
397
398 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
399 {
400 if (dc->flagx_known) {
401 if (dc->flags_x) {
402 TCGv c;
403
404 c = tcg_temp_new();
405 t_gen_mov_TN_preg(c, PR_CCS);
406 /* C flag is already at bit 0. */
407 tcg_gen_andi_tl(c, c, C_FLAG);
408 tcg_gen_sub_tl(d, d, c);
409 tcg_temp_free(c);
410 }
411 } else {
412 TCGv x, c;
413
414 x = tcg_temp_new();
415 c = tcg_temp_new();
416 t_gen_mov_TN_preg(x, PR_CCS);
417 tcg_gen_mov_tl(c, x);
418
419 /* Propagate carry into d if X is set. Branch free. */
420 tcg_gen_andi_tl(c, c, C_FLAG);
421 tcg_gen_andi_tl(x, x, X_FLAG);
422 tcg_gen_shri_tl(x, x, 4);
423
424 tcg_gen_and_tl(x, x, c);
425 tcg_gen_sub_tl(d, d, x);
426 tcg_temp_free(x);
427 tcg_temp_free(c);
428 }
429 }
430
431 /* Swap the two bytes within each half word of the s operand.
432 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
433 static inline void t_gen_swapb(TCGv d, TCGv s)
434 {
435 TCGv t, org_s;
436
437 t = tcg_temp_new();
438 org_s = tcg_temp_new();
439
440 /* d and s may refer to the same object. */
441 tcg_gen_mov_tl(org_s, s);
442 tcg_gen_shli_tl(t, org_s, 8);
443 tcg_gen_andi_tl(d, t, 0xff00ff00);
444 tcg_gen_shri_tl(t, org_s, 8);
445 tcg_gen_andi_tl(t, t, 0x00ff00ff);
446 tcg_gen_or_tl(d, d, t);
447 tcg_temp_free(t);
448 tcg_temp_free(org_s);
449 }
450
451 /* Swap the halfwords of the s operand. */
452 static inline void t_gen_swapw(TCGv d, TCGv s)
453 {
454 TCGv t;
455 /* d and s refer the same object. */
456 t = tcg_temp_new();
457 tcg_gen_mov_tl(t, s);
458 tcg_gen_shli_tl(d, t, 16);
459 tcg_gen_shri_tl(t, t, 16);
460 tcg_gen_or_tl(d, d, t);
461 tcg_temp_free(t);
462 }
463
464 /* Reverse the within each byte.
465 T0 = (((T0 << 7) & 0x80808080) |
466 ((T0 << 5) & 0x40404040) |
467 ((T0 << 3) & 0x20202020) |
468 ((T0 << 1) & 0x10101010) |
469 ((T0 >> 1) & 0x08080808) |
470 ((T0 >> 3) & 0x04040404) |
471 ((T0 >> 5) & 0x02020202) |
472 ((T0 >> 7) & 0x01010101));
473 */
474 static inline void t_gen_swapr(TCGv d, TCGv s)
475 {
476 struct {
477 int shift; /* LSL when positive, LSR when negative. */
478 uint32_t mask;
479 } bitrev[] = {
480 {7, 0x80808080},
481 {5, 0x40404040},
482 {3, 0x20202020},
483 {1, 0x10101010},
484 {-1, 0x08080808},
485 {-3, 0x04040404},
486 {-5, 0x02020202},
487 {-7, 0x01010101}
488 };
489 int i;
490 TCGv t, org_s;
491
492 /* d and s refer the same object. */
493 t = tcg_temp_new();
494 org_s = tcg_temp_new();
495 tcg_gen_mov_tl(org_s, s);
496
497 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
498 tcg_gen_andi_tl(d, t, bitrev[0].mask);
499 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
500 if (bitrev[i].shift >= 0) {
501 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
502 } else {
503 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
504 }
505 tcg_gen_andi_tl(t, t, bitrev[i].mask);
506 tcg_gen_or_tl(d, d, t);
507 }
508 tcg_temp_free(t);
509 tcg_temp_free(org_s);
510 }
511
512 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
513 {
514 TCGLabel *l1 = gen_new_label();
515
516 /* Conditional jmp. */
517 tcg_gen_mov_tl(env_pc, pc_false);
518 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
519 tcg_gen_mov_tl(env_pc, pc_true);
520 gen_set_label(l1);
521 }
522
523 static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
524 {
525 #ifndef CONFIG_USER_ONLY
526 return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
527 (dc->ppc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
528 #else
529 return true;
530 #endif
531 }
532
533 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
534 {
535 if (use_goto_tb(dc, dest)) {
536 tcg_gen_goto_tb(n);
537 tcg_gen_movi_tl(env_pc, dest);
538 tcg_gen_exit_tb((uintptr_t)dc->tb + n);
539 } else {
540 tcg_gen_movi_tl(env_pc, dest);
541 tcg_gen_exit_tb(0);
542 }
543 }
544
545 static inline void cris_clear_x_flag(DisasContext *dc)
546 {
547 if (dc->flagx_known && dc->flags_x) {
548 dc->flags_uptodate = 0;
549 }
550
551 dc->flagx_known = 1;
552 dc->flags_x = 0;
553 }
554
555 static void cris_flush_cc_state(DisasContext *dc)
556 {
557 if (dc->cc_size_uptodate != dc->cc_size) {
558 tcg_gen_movi_tl(cc_size, dc->cc_size);
559 dc->cc_size_uptodate = dc->cc_size;
560 }
561 tcg_gen_movi_tl(cc_op, dc->cc_op);
562 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
563 }
564
565 static void cris_evaluate_flags(DisasContext *dc)
566 {
567 if (dc->flags_uptodate) {
568 return;
569 }
570
571 cris_flush_cc_state(dc);
572
573 switch (dc->cc_op) {
574 case CC_OP_MCP:
575 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
576 cpu_PR[PR_CCS], cc_src,
577 cc_dest, cc_result);
578 break;
579 case CC_OP_MULS:
580 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
581 cpu_PR[PR_CCS], cc_result,
582 cpu_PR[PR_MOF]);
583 break;
584 case CC_OP_MULU:
585 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
586 cpu_PR[PR_CCS], cc_result,
587 cpu_PR[PR_MOF]);
588 break;
589 case CC_OP_MOVE:
590 case CC_OP_AND:
591 case CC_OP_OR:
592 case CC_OP_XOR:
593 case CC_OP_ASR:
594 case CC_OP_LSR:
595 case CC_OP_LSL:
596 switch (dc->cc_size) {
597 case 4:
598 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
599 cpu_env, cpu_PR[PR_CCS], cc_result);
600 break;
601 case 2:
602 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
603 cpu_env, cpu_PR[PR_CCS], cc_result);
604 break;
605 default:
606 gen_helper_evaluate_flags(cpu_env);
607 break;
608 }
609 break;
610 case CC_OP_FLAGS:
611 /* live. */
612 break;
613 case CC_OP_SUB:
614 case CC_OP_CMP:
615 if (dc->cc_size == 4) {
616 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
617 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
618 } else {
619 gen_helper_evaluate_flags(cpu_env);
620 }
621
622 break;
623 default:
624 switch (dc->cc_size) {
625 case 4:
626 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
627 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
628 break;
629 default:
630 gen_helper_evaluate_flags(cpu_env);
631 break;
632 }
633 break;
634 }
635
636 if (dc->flagx_known) {
637 if (dc->flags_x) {
638 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
639 } else if (dc->cc_op == CC_OP_FLAGS) {
640 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
641 }
642 }
643 dc->flags_uptodate = 1;
644 }
645
646 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
647 {
648 uint32_t ovl;
649
650 if (!mask) {
651 dc->update_cc = 0;
652 return;
653 }
654
655 /* Check if we need to evaluate the condition codes due to
656 CC overlaying. */
657 ovl = (dc->cc_mask ^ mask) & ~mask;
658 if (ovl) {
659 /* TODO: optimize this case. It trigs all the time. */
660 cris_evaluate_flags(dc);
661 }
662 dc->cc_mask = mask;
663 dc->update_cc = 1;
664 }
665
666 static void cris_update_cc_op(DisasContext *dc, int op, int size)
667 {
668 dc->cc_op = op;
669 dc->cc_size = size;
670 dc->flags_uptodate = 0;
671 }
672
673 static inline void cris_update_cc_x(DisasContext *dc)
674 {
675 /* Save the x flag state at the time of the cc snapshot. */
676 if (dc->flagx_known) {
677 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
678 return;
679 }
680 tcg_gen_movi_tl(cc_x, dc->flags_x);
681 dc->cc_x_uptodate = 2 | dc->flags_x;
682 } else {
683 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
684 dc->cc_x_uptodate = 1;
685 }
686 }
687
688 /* Update cc prior to executing ALU op. Needs source operands untouched. */
689 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
690 TCGv dst, TCGv src, int size)
691 {
692 if (dc->update_cc) {
693 cris_update_cc_op(dc, op, size);
694 tcg_gen_mov_tl(cc_src, src);
695
696 if (op != CC_OP_MOVE
697 && op != CC_OP_AND
698 && op != CC_OP_OR
699 && op != CC_OP_XOR
700 && op != CC_OP_ASR
701 && op != CC_OP_LSR
702 && op != CC_OP_LSL) {
703 tcg_gen_mov_tl(cc_dest, dst);
704 }
705
706 cris_update_cc_x(dc);
707 }
708 }
709
710 /* Update cc after executing ALU op. needs the result. */
711 static inline void cris_update_result(DisasContext *dc, TCGv res)
712 {
713 if (dc->update_cc) {
714 tcg_gen_mov_tl(cc_result, res);
715 }
716 }
717
718 /* Returns one if the write back stage should execute. */
719 static void cris_alu_op_exec(DisasContext *dc, int op,
720 TCGv dst, TCGv a, TCGv b, int size)
721 {
722 /* Emit the ALU insns. */
723 switch (op) {
724 case CC_OP_ADD:
725 tcg_gen_add_tl(dst, a, b);
726 /* Extended arithmetics. */
727 t_gen_addx_carry(dc, dst);
728 break;
729 case CC_OP_ADDC:
730 tcg_gen_add_tl(dst, a, b);
731 t_gen_add_flag(dst, 0); /* C_FLAG. */
732 break;
733 case CC_OP_MCP:
734 tcg_gen_add_tl(dst, a, b);
735 t_gen_add_flag(dst, 8); /* R_FLAG. */
736 break;
737 case CC_OP_SUB:
738 tcg_gen_sub_tl(dst, a, b);
739 /* Extended arithmetics. */
740 t_gen_subx_carry(dc, dst);
741 break;
742 case CC_OP_MOVE:
743 tcg_gen_mov_tl(dst, b);
744 break;
745 case CC_OP_OR:
746 tcg_gen_or_tl(dst, a, b);
747 break;
748 case CC_OP_AND:
749 tcg_gen_and_tl(dst, a, b);
750 break;
751 case CC_OP_XOR:
752 tcg_gen_xor_tl(dst, a, b);
753 break;
754 case CC_OP_LSL:
755 t_gen_lsl(dst, a, b);
756 break;
757 case CC_OP_LSR:
758 t_gen_lsr(dst, a, b);
759 break;
760 case CC_OP_ASR:
761 t_gen_asr(dst, a, b);
762 break;
763 case CC_OP_NEG:
764 tcg_gen_neg_tl(dst, b);
765 /* Extended arithmetics. */
766 t_gen_subx_carry(dc, dst);
767 break;
768 case CC_OP_LZ:
769 gen_helper_lz(dst, b);
770 break;
771 case CC_OP_MULS:
772 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
773 break;
774 case CC_OP_MULU:
775 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
776 break;
777 case CC_OP_DSTEP:
778 t_gen_cris_dstep(dst, a, b);
779 break;
780 case CC_OP_MSTEP:
781 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
782 break;
783 case CC_OP_BOUND:
784 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b);
785 break;
786 case CC_OP_CMP:
787 tcg_gen_sub_tl(dst, a, b);
788 /* Extended arithmetics. */
789 t_gen_subx_carry(dc, dst);
790 break;
791 default:
792 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
793 BUG();
794 break;
795 }
796
797 if (size == 1) {
798 tcg_gen_andi_tl(dst, dst, 0xff);
799 } else if (size == 2) {
800 tcg_gen_andi_tl(dst, dst, 0xffff);
801 }
802 }
803
804 static void cris_alu(DisasContext *dc, int op,
805 TCGv d, TCGv op_a, TCGv op_b, int size)
806 {
807 TCGv tmp;
808 int writeback;
809
810 writeback = 1;
811
812 if (op == CC_OP_CMP) {
813 tmp = tcg_temp_new();
814 writeback = 0;
815 } else if (size == 4) {
816 tmp = d;
817 writeback = 0;
818 } else {
819 tmp = tcg_temp_new();
820 }
821
822
823 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
824 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
825 cris_update_result(dc, tmp);
826
827 /* Writeback. */
828 if (writeback) {
829 if (size == 1) {
830 tcg_gen_andi_tl(d, d, ~0xff);
831 } else {
832 tcg_gen_andi_tl(d, d, ~0xffff);
833 }
834 tcg_gen_or_tl(d, d, tmp);
835 }
836 if (!TCGV_EQUAL(tmp, d)) {
837 tcg_temp_free(tmp);
838 }
839 }
840
841 static int arith_cc(DisasContext *dc)
842 {
843 if (dc->update_cc) {
844 switch (dc->cc_op) {
845 case CC_OP_ADDC: return 1;
846 case CC_OP_ADD: return 1;
847 case CC_OP_SUB: return 1;
848 case CC_OP_DSTEP: return 1;
849 case CC_OP_LSL: return 1;
850 case CC_OP_LSR: return 1;
851 case CC_OP_ASR: return 1;
852 case CC_OP_CMP: return 1;
853 case CC_OP_NEG: return 1;
854 case CC_OP_OR: return 1;
855 case CC_OP_AND: return 1;
856 case CC_OP_XOR: return 1;
857 case CC_OP_MULU: return 1;
858 case CC_OP_MULS: return 1;
859 default:
860 return 0;
861 }
862 }
863 return 0;
864 }
865
866 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
867 {
868 int arith_opt, move_opt;
869
870 /* TODO: optimize more condition codes. */
871
872 /*
873 * If the flags are live, we've gotta look into the bits of CCS.
874 * Otherwise, if we just did an arithmetic operation we try to
875 * evaluate the condition code faster.
876 *
877 * When this function is done, T0 should be non-zero if the condition
878 * code is true.
879 */
880 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
881 move_opt = (dc->cc_op == CC_OP_MOVE);
882 switch (cond) {
883 case CC_EQ:
884 if ((arith_opt || move_opt)
885 && dc->cc_x_uptodate != (2 | X_FLAG)) {
886 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
887 cc_result, tcg_const_tl(0));
888 } else {
889 cris_evaluate_flags(dc);
890 tcg_gen_andi_tl(cc,
891 cpu_PR[PR_CCS], Z_FLAG);
892 }
893 break;
894 case CC_NE:
895 if ((arith_opt || move_opt)
896 && dc->cc_x_uptodate != (2 | X_FLAG)) {
897 tcg_gen_mov_tl(cc, cc_result);
898 } else {
899 cris_evaluate_flags(dc);
900 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
901 Z_FLAG);
902 tcg_gen_andi_tl(cc, cc, Z_FLAG);
903 }
904 break;
905 case CC_CS:
906 cris_evaluate_flags(dc);
907 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
908 break;
909 case CC_CC:
910 cris_evaluate_flags(dc);
911 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
912 tcg_gen_andi_tl(cc, cc, C_FLAG);
913 break;
914 case CC_VS:
915 cris_evaluate_flags(dc);
916 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
917 break;
918 case CC_VC:
919 cris_evaluate_flags(dc);
920 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
921 V_FLAG);
922 tcg_gen_andi_tl(cc, cc, V_FLAG);
923 break;
924 case CC_PL:
925 if (arith_opt || move_opt) {
926 int bits = 31;
927
928 if (dc->cc_size == 1) {
929 bits = 7;
930 } else if (dc->cc_size == 2) {
931 bits = 15;
932 }
933
934 tcg_gen_shri_tl(cc, cc_result, bits);
935 tcg_gen_xori_tl(cc, cc, 1);
936 } else {
937 cris_evaluate_flags(dc);
938 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
939 N_FLAG);
940 tcg_gen_andi_tl(cc, cc, N_FLAG);
941 }
942 break;
943 case CC_MI:
944 if (arith_opt || move_opt) {
945 int bits = 31;
946
947 if (dc->cc_size == 1) {
948 bits = 7;
949 } else if (dc->cc_size == 2) {
950 bits = 15;
951 }
952
953 tcg_gen_shri_tl(cc, cc_result, bits);
954 tcg_gen_andi_tl(cc, cc, 1);
955 } else {
956 cris_evaluate_flags(dc);
957 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
958 N_FLAG);
959 }
960 break;
961 case CC_LS:
962 cris_evaluate_flags(dc);
963 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
964 C_FLAG | Z_FLAG);
965 break;
966 case CC_HI:
967 cris_evaluate_flags(dc);
968 {
969 TCGv tmp;
970
971 tmp = tcg_temp_new();
972 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
973 C_FLAG | Z_FLAG);
974 /* Overlay the C flag on top of the Z. */
975 tcg_gen_shli_tl(cc, tmp, 2);
976 tcg_gen_and_tl(cc, tmp, cc);
977 tcg_gen_andi_tl(cc, cc, Z_FLAG);
978
979 tcg_temp_free(tmp);
980 }
981 break;
982 case CC_GE:
983 cris_evaluate_flags(dc);
984 /* Overlay the V flag on top of the N. */
985 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
986 tcg_gen_xor_tl(cc,
987 cpu_PR[PR_CCS], cc);
988 tcg_gen_andi_tl(cc, cc, N_FLAG);
989 tcg_gen_xori_tl(cc, cc, N_FLAG);
990 break;
991 case CC_LT:
992 cris_evaluate_flags(dc);
993 /* Overlay the V flag on top of the N. */
994 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
995 tcg_gen_xor_tl(cc,
996 cpu_PR[PR_CCS], cc);
997 tcg_gen_andi_tl(cc, cc, N_FLAG);
998 break;
999 case CC_GT:
1000 cris_evaluate_flags(dc);
1001 {
1002 TCGv n, z;
1003
1004 n = tcg_temp_new();
1005 z = tcg_temp_new();
1006
1007 /* To avoid a shift we overlay everything on
1008 the V flag. */
1009 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1010 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1011 /* invert Z. */
1012 tcg_gen_xori_tl(z, z, 2);
1013
1014 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1015 tcg_gen_xori_tl(n, n, 2);
1016 tcg_gen_and_tl(cc, z, n);
1017 tcg_gen_andi_tl(cc, cc, 2);
1018
1019 tcg_temp_free(n);
1020 tcg_temp_free(z);
1021 }
1022 break;
1023 case CC_LE:
1024 cris_evaluate_flags(dc);
1025 {
1026 TCGv n, z;
1027
1028 n = tcg_temp_new();
1029 z = tcg_temp_new();
1030
1031 /* To avoid a shift we overlay everything on
1032 the V flag. */
1033 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1034 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1035
1036 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1037 tcg_gen_or_tl(cc, z, n);
1038 tcg_gen_andi_tl(cc, cc, 2);
1039
1040 tcg_temp_free(n);
1041 tcg_temp_free(z);
1042 }
1043 break;
1044 case CC_P:
1045 cris_evaluate_flags(dc);
1046 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1047 break;
1048 case CC_A:
1049 tcg_gen_movi_tl(cc, 1);
1050 break;
1051 default:
1052 BUG();
1053 break;
1054 };
1055 }
1056
1057 static void cris_store_direct_jmp(DisasContext *dc)
1058 {
1059 /* Store the direct jmp state into the cpu-state. */
1060 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1061 if (dc->jmp == JMP_DIRECT) {
1062 tcg_gen_movi_tl(env_btaken, 1);
1063 }
1064 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1065 dc->jmp = JMP_INDIRECT;
1066 }
1067 }
1068
1069 static void cris_prepare_cc_branch (DisasContext *dc,
1070 int offset, int cond)
1071 {
1072 /* This helps us re-schedule the micro-code to insns in delay-slots
1073 before the actual jump. */
1074 dc->delayed_branch = 2;
1075 dc->jmp = JMP_DIRECT_CC;
1076 dc->jmp_pc = dc->pc + offset;
1077
1078 gen_tst_cc(dc, env_btaken, cond);
1079 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1080 }
1081
1082
1083 /* jumps, when the dest is in a live reg for example. Direct should be set
1084 when the dest addr is constant to allow tb chaining. */
1085 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1086 {
1087 /* This helps us re-schedule the micro-code to insns in delay-slots
1088 before the actual jump. */
1089 dc->delayed_branch = 2;
1090 dc->jmp = type;
1091 if (type == JMP_INDIRECT) {
1092 tcg_gen_movi_tl(env_btaken, 1);
1093 }
1094 }
1095
1096 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1097 {
1098 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1099
1100 /* If we get a fault on a delayslot we must keep the jmp state in
1101 the cpu-state to be able to re-execute the jmp. */
1102 if (dc->delayed_branch == 1) {
1103 cris_store_direct_jmp(dc);
1104 }
1105
1106 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
1107 }
1108
1109 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1110 unsigned int size, int sign)
1111 {
1112 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1113
1114 /* If we get a fault on a delayslot we must keep the jmp state in
1115 the cpu-state to be able to re-execute the jmp. */
1116 if (dc->delayed_branch == 1) {
1117 cris_store_direct_jmp(dc);
1118 }
1119
1120 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1121 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1122 }
1123
1124 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1125 unsigned int size)
1126 {
1127 int mem_index = cpu_mmu_index(&dc->cpu->env, false);
1128
1129 /* If we get a fault on a delayslot we must keep the jmp state in
1130 the cpu-state to be able to re-execute the jmp. */
1131 if (dc->delayed_branch == 1) {
1132 cris_store_direct_jmp(dc);
1133 }
1134
1135
1136 /* Conditional writes. We only support the kind were X and P are known
1137 at translation time. */
1138 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1139 dc->postinc = 0;
1140 cris_evaluate_flags(dc);
1141 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1142 return;
1143 }
1144
1145 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
1146
1147 if (dc->flagx_known && dc->flags_x) {
1148 cris_evaluate_flags(dc);
1149 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1150 }
1151 }
1152
1153 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1154 {
1155 if (size == 1) {
1156 tcg_gen_ext8s_i32(d, s);
1157 } else if (size == 2) {
1158 tcg_gen_ext16s_i32(d, s);
1159 } else if (!TCGV_EQUAL(d, s)) {
1160 tcg_gen_mov_tl(d, s);
1161 }
1162 }
1163
1164 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1165 {
1166 if (size == 1) {
1167 tcg_gen_ext8u_i32(d, s);
1168 } else if (size == 2) {
1169 tcg_gen_ext16u_i32(d, s);
1170 } else if (!TCGV_EQUAL(d, s)) {
1171 tcg_gen_mov_tl(d, s);
1172 }
1173 }
1174
1175 #if DISAS_CRIS
1176 static char memsize_char(int size)
1177 {
1178 switch (size) {
1179 case 1: return 'b'; break;
1180 case 2: return 'w'; break;
1181 case 4: return 'd'; break;
1182 default:
1183 return 'x';
1184 break;
1185 }
1186 }
1187 #endif
1188
1189 static inline unsigned int memsize_z(DisasContext *dc)
1190 {
1191 return dc->zsize + 1;
1192 }
1193
1194 static inline unsigned int memsize_zz(DisasContext *dc)
1195 {
1196 switch (dc->zzsize) {
1197 case 0: return 1;
1198 case 1: return 2;
1199 default:
1200 return 4;
1201 }
1202 }
1203
1204 static inline void do_postinc (DisasContext *dc, int size)
1205 {
1206 if (dc->postinc) {
1207 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1208 }
1209 }
1210
1211 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1212 int size, int s_ext, TCGv dst)
1213 {
1214 if (s_ext) {
1215 t_gen_sext(dst, cpu_R[rs], size);
1216 } else {
1217 t_gen_zext(dst, cpu_R[rs], size);
1218 }
1219 }
1220
1221 /* Prepare T0 and T1 for a register alu operation.
1222 s_ext decides if the operand1 should be sign-extended or zero-extended when
1223 needed. */
1224 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1225 int size, int s_ext, TCGv dst, TCGv src)
1226 {
1227 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1228
1229 if (s_ext) {
1230 t_gen_sext(dst, cpu_R[rd], size);
1231 } else {
1232 t_gen_zext(dst, cpu_R[rd], size);
1233 }
1234 }
1235
1236 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1237 int s_ext, int memsize, TCGv dst)
1238 {
1239 unsigned int rs;
1240 uint32_t imm;
1241 int is_imm;
1242 int insn_len = 2;
1243
1244 rs = dc->op1;
1245 is_imm = rs == 15 && dc->postinc;
1246
1247 /* Load [$rs] onto T1. */
1248 if (is_imm) {
1249 insn_len = 2 + memsize;
1250 if (memsize == 1) {
1251 insn_len++;
1252 }
1253
1254 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1255 tcg_gen_movi_tl(dst, imm);
1256 dc->postinc = 0;
1257 } else {
1258 cris_flush_cc_state(dc);
1259 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1260 if (s_ext) {
1261 t_gen_sext(dst, dst, memsize);
1262 } else {
1263 t_gen_zext(dst, dst, memsize);
1264 }
1265 }
1266 return insn_len;
1267 }
1268
1269 /* Prepare T0 and T1 for a memory + alu operation.
1270 s_ext decides if the operand1 should be sign-extended or zero-extended when
1271 needed. */
1272 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1273 int s_ext, int memsize, TCGv dst, TCGv src)
1274 {
1275 int insn_len;
1276
1277 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1278 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1279 return insn_len;
1280 }
1281
1282 #if DISAS_CRIS
1283 static const char *cc_name(int cc)
1284 {
1285 static const char *cc_names[16] = {
1286 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1287 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1288 };
1289 assert(cc < 16);
1290 return cc_names[cc];
1291 }
1292 #endif
1293
1294 /* Start of insn decoders. */
1295
1296 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1297 {
1298 int32_t offset;
1299 int sign;
1300 uint32_t cond = dc->op2;
1301
1302 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1303 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1304
1305 offset *= 2;
1306 offset |= sign << 8;
1307 offset = sign_extend(offset, 8);
1308
1309 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1310
1311 /* op2 holds the condition-code. */
1312 cris_cc_mask(dc, 0);
1313 cris_prepare_cc_branch(dc, offset, cond);
1314 return 2;
1315 }
1316 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1317 {
1318 int32_t imm;
1319
1320 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1321 imm = sign_extend(dc->op1, 7);
1322
1323 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1324 cris_cc_mask(dc, 0);
1325 /* Fetch register operand, */
1326 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1327
1328 return 2;
1329 }
1330 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1331 {
1332 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1333
1334 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1335
1336 cris_cc_mask(dc, CC_MASK_NZVC);
1337
1338 cris_alu(dc, CC_OP_ADD,
1339 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1340 return 2;
1341 }
1342 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1343 {
1344 uint32_t imm;
1345
1346 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1347 imm = sign_extend(dc->op1, 5);
1348 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1349
1350 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1351 return 2;
1352 }
1353 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1354 {
1355 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1356
1357 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1358
1359 cris_cc_mask(dc, CC_MASK_NZVC);
1360 cris_alu(dc, CC_OP_SUB,
1361 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1362 return 2;
1363 }
1364 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1365 {
1366 uint32_t imm;
1367 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1368 imm = sign_extend(dc->op1, 5);
1369
1370 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1371 cris_cc_mask(dc, CC_MASK_NZVC);
1372
1373 cris_alu(dc, CC_OP_CMP,
1374 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1375 return 2;
1376 }
1377 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1378 {
1379 uint32_t imm;
1380 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1381 imm = sign_extend(dc->op1, 5);
1382
1383 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1384 cris_cc_mask(dc, CC_MASK_NZ);
1385
1386 cris_alu(dc, CC_OP_AND,
1387 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1388 return 2;
1389 }
1390 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1391 {
1392 uint32_t imm;
1393 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1394 imm = sign_extend(dc->op1, 5);
1395 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1396 cris_cc_mask(dc, CC_MASK_NZ);
1397
1398 cris_alu(dc, CC_OP_OR,
1399 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1400 return 2;
1401 }
1402 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1403 {
1404 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1405 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1406
1407 cris_cc_mask(dc, CC_MASK_NZ);
1408 cris_evaluate_flags(dc);
1409 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1410 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1411 cris_alu(dc, CC_OP_MOVE,
1412 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1413 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1414 dc->flags_uptodate = 1;
1415 return 2;
1416 }
1417 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1418 {
1419 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1420 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1421 cris_cc_mask(dc, CC_MASK_NZ);
1422
1423 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1424 cris_alu(dc, CC_OP_MOVE,
1425 cpu_R[dc->op2],
1426 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1427 return 2;
1428 }
1429 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1430 {
1431 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1432 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1433
1434 cris_cc_mask(dc, CC_MASK_NZ);
1435
1436 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1437
1438 cris_alu(dc, CC_OP_MOVE,
1439 cpu_R[dc->op2],
1440 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1441 return 2;
1442 }
1443 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1444 {
1445 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1446 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1447
1448 cris_cc_mask(dc, CC_MASK_NZ);
1449
1450 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1451 cris_alu(dc, CC_OP_MOVE,
1452 cpu_R[dc->op2],
1453 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1454 return 2;
1455 }
1456
1457 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1458 {
1459 int size = memsize_zz(dc);
1460
1461 LOG_DIS("move.%c $r%u, $r%u\n",
1462 memsize_char(size), dc->op1, dc->op2);
1463
1464 cris_cc_mask(dc, CC_MASK_NZ);
1465 if (size == 4) {
1466 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1467 cris_cc_mask(dc, CC_MASK_NZ);
1468 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1469 cris_update_cc_x(dc);
1470 cris_update_result(dc, cpu_R[dc->op2]);
1471 } else {
1472 TCGv t0;
1473
1474 t0 = tcg_temp_new();
1475 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1476 cris_alu(dc, CC_OP_MOVE,
1477 cpu_R[dc->op2],
1478 cpu_R[dc->op2], t0, size);
1479 tcg_temp_free(t0);
1480 }
1481 return 2;
1482 }
1483
1484 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1485 {
1486 int cond = dc->op2;
1487
1488 LOG_DIS("s%s $r%u\n",
1489 cc_name(cond), dc->op1);
1490
1491 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1492 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0);
1493
1494 cris_cc_mask(dc, 0);
1495 return 2;
1496 }
1497
1498 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1499 {
1500 if (size == 4) {
1501 t[0] = cpu_R[dc->op2];
1502 t[1] = cpu_R[dc->op1];
1503 } else {
1504 t[0] = tcg_temp_new();
1505 t[1] = tcg_temp_new();
1506 }
1507 }
1508
1509 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1510 {
1511 if (size != 4) {
1512 tcg_temp_free(t[0]);
1513 tcg_temp_free(t[1]);
1514 }
1515 }
1516
1517 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1518 {
1519 TCGv t[2];
1520 int size = memsize_zz(dc);
1521
1522 LOG_DIS("and.%c $r%u, $r%u\n",
1523 memsize_char(size), dc->op1, dc->op2);
1524
1525 cris_cc_mask(dc, CC_MASK_NZ);
1526
1527 cris_alu_alloc_temps(dc, size, t);
1528 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1529 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1530 cris_alu_free_temps(dc, size, t);
1531 return 2;
1532 }
1533
1534 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1535 {
1536 TCGv t0;
1537 LOG_DIS("lz $r%u, $r%u\n",
1538 dc->op1, dc->op2);
1539 cris_cc_mask(dc, CC_MASK_NZ);
1540 t0 = tcg_temp_new();
1541 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1542 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1543 tcg_temp_free(t0);
1544 return 2;
1545 }
1546
1547 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1548 {
1549 TCGv t[2];
1550 int size = memsize_zz(dc);
1551
1552 LOG_DIS("lsl.%c $r%u, $r%u\n",
1553 memsize_char(size), dc->op1, dc->op2);
1554
1555 cris_cc_mask(dc, CC_MASK_NZ);
1556 cris_alu_alloc_temps(dc, size, t);
1557 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1558 tcg_gen_andi_tl(t[1], t[1], 63);
1559 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1560 cris_alu_alloc_temps(dc, size, t);
1561 return 2;
1562 }
1563
1564 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1565 {
1566 TCGv t[2];
1567 int size = memsize_zz(dc);
1568
1569 LOG_DIS("lsr.%c $r%u, $r%u\n",
1570 memsize_char(size), dc->op1, dc->op2);
1571
1572 cris_cc_mask(dc, CC_MASK_NZ);
1573 cris_alu_alloc_temps(dc, size, t);
1574 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1575 tcg_gen_andi_tl(t[1], t[1], 63);
1576 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1577 cris_alu_free_temps(dc, size, t);
1578 return 2;
1579 }
1580
1581 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1582 {
1583 TCGv t[2];
1584 int size = memsize_zz(dc);
1585
1586 LOG_DIS("asr.%c $r%u, $r%u\n",
1587 memsize_char(size), dc->op1, dc->op2);
1588
1589 cris_cc_mask(dc, CC_MASK_NZ);
1590 cris_alu_alloc_temps(dc, size, t);
1591 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1592 tcg_gen_andi_tl(t[1], t[1], 63);
1593 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1594 cris_alu_free_temps(dc, size, t);
1595 return 2;
1596 }
1597
1598 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1599 {
1600 TCGv t[2];
1601 int size = memsize_zz(dc);
1602
1603 LOG_DIS("muls.%c $r%u, $r%u\n",
1604 memsize_char(size), dc->op1, dc->op2);
1605 cris_cc_mask(dc, CC_MASK_NZV);
1606 cris_alu_alloc_temps(dc, size, t);
1607 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1608
1609 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1610 cris_alu_free_temps(dc, size, t);
1611 return 2;
1612 }
1613
1614 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1615 {
1616 TCGv t[2];
1617 int size = memsize_zz(dc);
1618
1619 LOG_DIS("mulu.%c $r%u, $r%u\n",
1620 memsize_char(size), dc->op1, dc->op2);
1621 cris_cc_mask(dc, CC_MASK_NZV);
1622 cris_alu_alloc_temps(dc, size, t);
1623 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1624
1625 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1626 cris_alu_alloc_temps(dc, size, t);
1627 return 2;
1628 }
1629
1630
1631 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1632 {
1633 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1634 cris_cc_mask(dc, CC_MASK_NZ);
1635 cris_alu(dc, CC_OP_DSTEP,
1636 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1637 return 2;
1638 }
1639
1640 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1641 {
1642 TCGv t[2];
1643 int size = memsize_zz(dc);
1644 LOG_DIS("xor.%c $r%u, $r%u\n",
1645 memsize_char(size), dc->op1, dc->op2);
1646 BUG_ON(size != 4); /* xor is dword. */
1647 cris_cc_mask(dc, CC_MASK_NZ);
1648 cris_alu_alloc_temps(dc, size, t);
1649 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1650
1651 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1652 cris_alu_free_temps(dc, size, t);
1653 return 2;
1654 }
1655
1656 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1657 {
1658 TCGv l0;
1659 int size = memsize_zz(dc);
1660 LOG_DIS("bound.%c $r%u, $r%u\n",
1661 memsize_char(size), dc->op1, dc->op2);
1662 cris_cc_mask(dc, CC_MASK_NZ);
1663 l0 = tcg_temp_local_new();
1664 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1665 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1666 tcg_temp_free(l0);
1667 return 2;
1668 }
1669
1670 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1671 {
1672 TCGv t[2];
1673 int size = memsize_zz(dc);
1674 LOG_DIS("cmp.%c $r%u, $r%u\n",
1675 memsize_char(size), dc->op1, dc->op2);
1676 cris_cc_mask(dc, CC_MASK_NZVC);
1677 cris_alu_alloc_temps(dc, size, t);
1678 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1679
1680 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1681 cris_alu_free_temps(dc, size, t);
1682 return 2;
1683 }
1684
1685 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1686 {
1687 TCGv t0;
1688
1689 LOG_DIS("abs $r%u, $r%u\n",
1690 dc->op1, dc->op2);
1691 cris_cc_mask(dc, CC_MASK_NZ);
1692
1693 t0 = tcg_temp_new();
1694 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1695 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1696 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1697 tcg_temp_free(t0);
1698
1699 cris_alu(dc, CC_OP_MOVE,
1700 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1701 return 2;
1702 }
1703
1704 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1705 {
1706 TCGv t[2];
1707 int size = memsize_zz(dc);
1708 LOG_DIS("add.%c $r%u, $r%u\n",
1709 memsize_char(size), dc->op1, dc->op2);
1710 cris_cc_mask(dc, CC_MASK_NZVC);
1711 cris_alu_alloc_temps(dc, size, t);
1712 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1713
1714 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1715 cris_alu_free_temps(dc, size, t);
1716 return 2;
1717 }
1718
1719 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1720 {
1721 LOG_DIS("addc $r%u, $r%u\n",
1722 dc->op1, dc->op2);
1723 cris_evaluate_flags(dc);
1724 /* Set for this insn. */
1725 dc->flagx_known = 1;
1726 dc->flags_x = X_FLAG;
1727
1728 cris_cc_mask(dc, CC_MASK_NZVC);
1729 cris_alu(dc, CC_OP_ADDC,
1730 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1731 return 2;
1732 }
1733
1734 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1735 {
1736 LOG_DIS("mcp $p%u, $r%u\n",
1737 dc->op2, dc->op1);
1738 cris_evaluate_flags(dc);
1739 cris_cc_mask(dc, CC_MASK_RNZV);
1740 cris_alu(dc, CC_OP_MCP,
1741 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1742 return 2;
1743 }
1744
1745 #if DISAS_CRIS
1746 static char * swapmode_name(int mode, char *modename) {
1747 int i = 0;
1748 if (mode & 8) {
1749 modename[i++] = 'n';
1750 }
1751 if (mode & 4) {
1752 modename[i++] = 'w';
1753 }
1754 if (mode & 2) {
1755 modename[i++] = 'b';
1756 }
1757 if (mode & 1) {
1758 modename[i++] = 'r';
1759 }
1760 modename[i++] = 0;
1761 return modename;
1762 }
1763 #endif
1764
1765 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1766 {
1767 TCGv t0;
1768 #if DISAS_CRIS
1769 char modename[4];
1770 #endif
1771 LOG_DIS("swap%s $r%u\n",
1772 swapmode_name(dc->op2, modename), dc->op1);
1773
1774 cris_cc_mask(dc, CC_MASK_NZ);
1775 t0 = tcg_temp_new();
1776 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
1777 if (dc->op2 & 8) {
1778 tcg_gen_not_tl(t0, t0);
1779 }
1780 if (dc->op2 & 4) {
1781 t_gen_swapw(t0, t0);
1782 }
1783 if (dc->op2 & 2) {
1784 t_gen_swapb(t0, t0);
1785 }
1786 if (dc->op2 & 1) {
1787 t_gen_swapr(t0, t0);
1788 }
1789 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1790 tcg_temp_free(t0);
1791 return 2;
1792 }
1793
1794 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1795 {
1796 TCGv t[2];
1797 int size = memsize_zz(dc);
1798 LOG_DIS("or.%c $r%u, $r%u\n",
1799 memsize_char(size), dc->op1, dc->op2);
1800 cris_cc_mask(dc, CC_MASK_NZ);
1801 cris_alu_alloc_temps(dc, size, t);
1802 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1803 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1804 cris_alu_free_temps(dc, size, t);
1805 return 2;
1806 }
1807
1808 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1809 {
1810 TCGv t0;
1811 LOG_DIS("addi.%c $r%u, $r%u\n",
1812 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1813 cris_cc_mask(dc, 0);
1814 t0 = tcg_temp_new();
1815 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1816 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1817 tcg_temp_free(t0);
1818 return 2;
1819 }
1820
1821 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1822 {
1823 TCGv t0;
1824 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1825 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1826 cris_cc_mask(dc, 0);
1827 t0 = tcg_temp_new();
1828 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1829 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1830 tcg_temp_free(t0);
1831 return 2;
1832 }
1833
1834 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1835 {
1836 TCGv t[2];
1837 int size = memsize_zz(dc);
1838 LOG_DIS("neg.%c $r%u, $r%u\n",
1839 memsize_char(size), dc->op1, dc->op2);
1840 cris_cc_mask(dc, CC_MASK_NZVC);
1841 cris_alu_alloc_temps(dc, size, t);
1842 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1843
1844 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1845 cris_alu_free_temps(dc, size, t);
1846 return 2;
1847 }
1848
1849 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1850 {
1851 LOG_DIS("btst $r%u, $r%u\n",
1852 dc->op1, dc->op2);
1853 cris_cc_mask(dc, CC_MASK_NZ);
1854 cris_evaluate_flags(dc);
1855 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1856 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1857 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1858 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1859 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1860 dc->flags_uptodate = 1;
1861 return 2;
1862 }
1863
1864 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1865 {
1866 TCGv t[2];
1867 int size = memsize_zz(dc);
1868 LOG_DIS("sub.%c $r%u, $r%u\n",
1869 memsize_char(size), dc->op1, dc->op2);
1870 cris_cc_mask(dc, CC_MASK_NZVC);
1871 cris_alu_alloc_temps(dc, size, t);
1872 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1873 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1874 cris_alu_free_temps(dc, size, t);
1875 return 2;
1876 }
1877
1878 /* Zero extension. From size to dword. */
1879 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1880 {
1881 TCGv t0;
1882 int size = memsize_z(dc);
1883 LOG_DIS("movu.%c $r%u, $r%u\n",
1884 memsize_char(size),
1885 dc->op1, dc->op2);
1886
1887 cris_cc_mask(dc, CC_MASK_NZ);
1888 t0 = tcg_temp_new();
1889 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1890 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1891 tcg_temp_free(t0);
1892 return 2;
1893 }
1894
1895 /* Sign extension. From size to dword. */
1896 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1897 {
1898 TCGv t0;
1899 int size = memsize_z(dc);
1900 LOG_DIS("movs.%c $r%u, $r%u\n",
1901 memsize_char(size),
1902 dc->op1, dc->op2);
1903
1904 cris_cc_mask(dc, CC_MASK_NZ);
1905 t0 = tcg_temp_new();
1906 /* Size can only be qi or hi. */
1907 t_gen_sext(t0, cpu_R[dc->op1], size);
1908 cris_alu(dc, CC_OP_MOVE,
1909 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1910 tcg_temp_free(t0);
1911 return 2;
1912 }
1913
1914 /* zero extension. From size to dword. */
1915 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1916 {
1917 TCGv t0;
1918 int size = memsize_z(dc);
1919 LOG_DIS("addu.%c $r%u, $r%u\n",
1920 memsize_char(size),
1921 dc->op1, dc->op2);
1922
1923 cris_cc_mask(dc, CC_MASK_NZVC);
1924 t0 = tcg_temp_new();
1925 /* Size can only be qi or hi. */
1926 t_gen_zext(t0, cpu_R[dc->op1], size);
1927 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1928 tcg_temp_free(t0);
1929 return 2;
1930 }
1931
1932 /* Sign extension. From size to dword. */
1933 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1934 {
1935 TCGv t0;
1936 int size = memsize_z(dc);
1937 LOG_DIS("adds.%c $r%u, $r%u\n",
1938 memsize_char(size),
1939 dc->op1, dc->op2);
1940
1941 cris_cc_mask(dc, CC_MASK_NZVC);
1942 t0 = tcg_temp_new();
1943 /* Size can only be qi or hi. */
1944 t_gen_sext(t0, cpu_R[dc->op1], size);
1945 cris_alu(dc, CC_OP_ADD,
1946 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1947 tcg_temp_free(t0);
1948 return 2;
1949 }
1950
1951 /* Zero extension. From size to dword. */
1952 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1953 {
1954 TCGv t0;
1955 int size = memsize_z(dc);
1956 LOG_DIS("subu.%c $r%u, $r%u\n",
1957 memsize_char(size),
1958 dc->op1, dc->op2);
1959
1960 cris_cc_mask(dc, CC_MASK_NZVC);
1961 t0 = tcg_temp_new();
1962 /* Size can only be qi or hi. */
1963 t_gen_zext(t0, cpu_R[dc->op1], size);
1964 cris_alu(dc, CC_OP_SUB,
1965 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1966 tcg_temp_free(t0);
1967 return 2;
1968 }
1969
1970 /* Sign extension. From size to dword. */
1971 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
1972 {
1973 TCGv t0;
1974 int size = memsize_z(dc);
1975 LOG_DIS("subs.%c $r%u, $r%u\n",
1976 memsize_char(size),
1977 dc->op1, dc->op2);
1978
1979 cris_cc_mask(dc, CC_MASK_NZVC);
1980 t0 = tcg_temp_new();
1981 /* Size can only be qi or hi. */
1982 t_gen_sext(t0, cpu_R[dc->op1], size);
1983 cris_alu(dc, CC_OP_SUB,
1984 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1985 tcg_temp_free(t0);
1986 return 2;
1987 }
1988
1989 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
1990 {
1991 uint32_t flags;
1992 int set = (~dc->opcode >> 2) & 1;
1993
1994
1995 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1996 | EXTRACT_FIELD(dc->ir, 0, 3);
1997 if (set && flags == 0) {
1998 LOG_DIS("nop\n");
1999 return 2;
2000 } else if (!set && (flags & 0x20)) {
2001 LOG_DIS("di\n");
2002 } else {
2003 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
2004 }
2005
2006 /* User space is not allowed to touch these. Silently ignore. */
2007 if (dc->tb_flags & U_FLAG) {
2008 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2009 }
2010
2011 if (flags & X_FLAG) {
2012 dc->flagx_known = 1;
2013 if (set) {
2014 dc->flags_x = X_FLAG;
2015 } else {
2016 dc->flags_x = 0;
2017 }
2018 }
2019
2020 /* Break the TB if any of the SPI flag changes. */
2021 if (flags & (P_FLAG | S_FLAG)) {
2022 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2023 dc->is_jmp = DISAS_UPDATE;
2024 dc->cpustate_changed = 1;
2025 }
2026
2027 /* For the I flag, only act on posedge. */
2028 if ((flags & I_FLAG)) {
2029 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2030 dc->is_jmp = DISAS_UPDATE;
2031 dc->cpustate_changed = 1;
2032 }
2033
2034
2035 /* Simply decode the flags. */
2036 cris_evaluate_flags(dc);
2037 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2038 cris_update_cc_x(dc);
2039 tcg_gen_movi_tl(cc_op, dc->cc_op);
2040
2041 if (set) {
2042 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2043 /* Enter user mode. */
2044 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2045 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2046 dc->cpustate_changed = 1;
2047 }
2048 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2049 } else {
2050 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2051 }
2052
2053 dc->flags_uptodate = 1;
2054 dc->clear_x = 0;
2055 return 2;
2056 }
2057
2058 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2059 {
2060 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2061 cris_cc_mask(dc, 0);
2062 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2063 tcg_const_tl(dc->op1));
2064 return 2;
2065 }
2066 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2067 {
2068 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2069 cris_cc_mask(dc, 0);
2070 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2071 tcg_const_tl(dc->op2));
2072 return 2;
2073 }
2074
2075 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2076 {
2077 TCGv t[2];
2078 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2079 cris_cc_mask(dc, 0);
2080
2081 t[0] = tcg_temp_new();
2082 if (dc->op2 == PR_CCS) {
2083 cris_evaluate_flags(dc);
2084 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2085 if (dc->tb_flags & U_FLAG) {
2086 t[1] = tcg_temp_new();
2087 /* User space is not allowed to touch all flags. */
2088 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2089 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2090 tcg_gen_or_tl(t[0], t[1], t[0]);
2091 tcg_temp_free(t[1]);
2092 }
2093 } else {
2094 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2095 }
2096
2097 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2098 if (dc->op2 == PR_CCS) {
2099 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2100 dc->flags_uptodate = 1;
2101 }
2102 tcg_temp_free(t[0]);
2103 return 2;
2104 }
2105 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2106 {
2107 TCGv t0;
2108 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2109 cris_cc_mask(dc, 0);
2110
2111 if (dc->op2 == PR_CCS) {
2112 cris_evaluate_flags(dc);
2113 }
2114
2115 if (dc->op2 == PR_DZ) {
2116 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2117 } else {
2118 t0 = tcg_temp_new();
2119 t_gen_mov_TN_preg(t0, dc->op2);
2120 cris_alu(dc, CC_OP_MOVE,
2121 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2122 preg_sizes[dc->op2]);
2123 tcg_temp_free(t0);
2124 }
2125 return 2;
2126 }
2127
2128 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2129 {
2130 int memsize = memsize_zz(dc);
2131 int insn_len;
2132 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2133 memsize_char(memsize),
2134 dc->op1, dc->postinc ? "+]" : "]",
2135 dc->op2);
2136
2137 if (memsize == 4) {
2138 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2139 cris_cc_mask(dc, CC_MASK_NZ);
2140 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2141 cris_update_cc_x(dc);
2142 cris_update_result(dc, cpu_R[dc->op2]);
2143 } else {
2144 TCGv t0;
2145
2146 t0 = tcg_temp_new();
2147 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2148 cris_cc_mask(dc, CC_MASK_NZ);
2149 cris_alu(dc, CC_OP_MOVE,
2150 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2151 tcg_temp_free(t0);
2152 }
2153 do_postinc(dc, memsize);
2154 return insn_len;
2155 }
2156
2157 static inline void cris_alu_m_alloc_temps(TCGv *t)
2158 {
2159 t[0] = tcg_temp_new();
2160 t[1] = tcg_temp_new();
2161 }
2162
2163 static inline void cris_alu_m_free_temps(TCGv *t)
2164 {
2165 tcg_temp_free(t[0]);
2166 tcg_temp_free(t[1]);
2167 }
2168
2169 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2170 {
2171 TCGv t[2];
2172 int memsize = memsize_z(dc);
2173 int insn_len;
2174 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2175 memsize_char(memsize),
2176 dc->op1, dc->postinc ? "+]" : "]",
2177 dc->op2);
2178
2179 cris_alu_m_alloc_temps(t);
2180 /* sign extend. */
2181 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2182 cris_cc_mask(dc, CC_MASK_NZ);
2183 cris_alu(dc, CC_OP_MOVE,
2184 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2185 do_postinc(dc, memsize);
2186 cris_alu_m_free_temps(t);
2187 return insn_len;
2188 }
2189
2190 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2191 {
2192 TCGv t[2];
2193 int memsize = memsize_z(dc);
2194 int insn_len;
2195 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2196 memsize_char(memsize),
2197 dc->op1, dc->postinc ? "+]" : "]",
2198 dc->op2);
2199
2200 cris_alu_m_alloc_temps(t);
2201 /* sign extend. */
2202 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2203 cris_cc_mask(dc, CC_MASK_NZVC);
2204 cris_alu(dc, CC_OP_ADD,
2205 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2206 do_postinc(dc, memsize);
2207 cris_alu_m_free_temps(t);
2208 return insn_len;
2209 }
2210
2211 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2212 {
2213 TCGv t[2];
2214 int memsize = memsize_z(dc);
2215 int insn_len;
2216 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2217 memsize_char(memsize),
2218 dc->op1, dc->postinc ? "+]" : "]",
2219 dc->op2);
2220
2221 cris_alu_m_alloc_temps(t);
2222 /* sign extend. */
2223 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2224 cris_cc_mask(dc, CC_MASK_NZVC);
2225 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2226 do_postinc(dc, memsize);
2227 cris_alu_m_free_temps(t);
2228 return insn_len;
2229 }
2230
2231 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2232 {
2233 TCGv t[2];
2234 int memsize = memsize_z(dc);
2235 int insn_len;
2236 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2237 memsize_char(memsize),
2238 dc->op1, dc->postinc ? "+]" : "]",
2239 dc->op2);
2240
2241 cris_alu_m_alloc_temps(t);
2242 /* sign extend. */
2243 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2244 cris_cc_mask(dc, CC_MASK_NZVC);
2245 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2246 do_postinc(dc, memsize);
2247 cris_alu_m_free_temps(t);
2248 return insn_len;
2249 }
2250
2251 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2252 {
2253 TCGv t[2];
2254 int memsize = memsize_z(dc);
2255 int insn_len;
2256 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2257 memsize_char(memsize),
2258 dc->op1, dc->postinc ? "+]" : "]",
2259 dc->op2);
2260
2261 cris_alu_m_alloc_temps(t);
2262 /* sign extend. */
2263 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2264 cris_cc_mask(dc, CC_MASK_NZVC);
2265 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2266 do_postinc(dc, memsize);
2267 cris_alu_m_free_temps(t);
2268 return insn_len;
2269 }
2270
2271 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2272 {
2273 TCGv t[2];
2274 int memsize = memsize_z(dc);
2275 int insn_len;
2276
2277 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2278 memsize_char(memsize),
2279 dc->op1, dc->postinc ? "+]" : "]",
2280 dc->op2);
2281
2282 cris_alu_m_alloc_temps(t);
2283 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2284 cris_cc_mask(dc, CC_MASK_NZ);
2285 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2286 do_postinc(dc, memsize);
2287 cris_alu_m_free_temps(t);
2288 return insn_len;
2289 }
2290
2291 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2292 {
2293 TCGv t[2];
2294 int memsize = memsize_z(dc);
2295 int insn_len;
2296 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2297 memsize_char(memsize),
2298 dc->op1, dc->postinc ? "+]" : "]",
2299 dc->op2);
2300
2301 cris_alu_m_alloc_temps(t);
2302 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2303 cris_cc_mask(dc, CC_MASK_NZVC);
2304 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2305 do_postinc(dc, memsize);
2306 cris_alu_m_free_temps(t);
2307 return insn_len;
2308 }
2309
2310 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2311 {
2312 TCGv t[2];
2313 int memsize = memsize_z(dc);
2314 int insn_len;
2315 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2316 memsize_char(memsize),
2317 dc->op1, dc->postinc ? "+]" : "]",
2318 dc->op2);
2319
2320 cris_alu_m_alloc_temps(t);
2321 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2322 cris_cc_mask(dc, CC_MASK_NZVC);
2323 cris_alu(dc, CC_OP_CMP,
2324 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2325 memsize_zz(dc));
2326 do_postinc(dc, memsize);
2327 cris_alu_m_free_temps(t);
2328 return insn_len;
2329 }
2330
2331 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2332 {
2333 TCGv t[2];
2334 int memsize = memsize_zz(dc);
2335 int insn_len;
2336 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2337 memsize_char(memsize),
2338 dc->op1, dc->postinc ? "+]" : "]",
2339 dc->op2);
2340
2341 cris_alu_m_alloc_temps(t);
2342 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2343 cris_cc_mask(dc, CC_MASK_NZVC);
2344 cris_alu(dc, CC_OP_CMP,
2345 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2346 memsize_zz(dc));
2347 do_postinc(dc, memsize);
2348 cris_alu_m_free_temps(t);
2349 return insn_len;
2350 }
2351
2352 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2353 {
2354 TCGv t[2];
2355 int memsize = memsize_zz(dc);
2356 int insn_len;
2357 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2358 memsize_char(memsize),
2359 dc->op1, dc->postinc ? "+]" : "]",
2360 dc->op2);
2361
2362 cris_evaluate_flags(dc);
2363
2364 cris_alu_m_alloc_temps(t);
2365 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2366 cris_cc_mask(dc, CC_MASK_NZ);
2367 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2368
2369 cris_alu(dc, CC_OP_CMP,
2370 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2371 do_postinc(dc, memsize);
2372 cris_alu_m_free_temps(t);
2373 return insn_len;
2374 }
2375
2376 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2377 {
2378 TCGv t[2];
2379 int memsize = memsize_zz(dc);
2380 int insn_len;
2381 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2382 memsize_char(memsize),
2383 dc->op1, dc->postinc ? "+]" : "]",
2384 dc->op2);
2385
2386 cris_alu_m_alloc_temps(t);
2387 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2388 cris_cc_mask(dc, CC_MASK_NZ);
2389 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2390 do_postinc(dc, memsize);
2391 cris_alu_m_free_temps(t);
2392 return insn_len;
2393 }
2394
2395 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2396 {
2397 TCGv t[2];
2398 int memsize = memsize_zz(dc);
2399 int insn_len;
2400 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2401 memsize_char(memsize),
2402 dc->op1, dc->postinc ? "+]" : "]",
2403 dc->op2);
2404
2405 cris_alu_m_alloc_temps(t);
2406 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2407 cris_cc_mask(dc, CC_MASK_NZVC);
2408 cris_alu(dc, CC_OP_ADD,
2409 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2410 do_postinc(dc, memsize);
2411 cris_alu_m_free_temps(t);
2412 return insn_len;
2413 }
2414
2415 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2416 {
2417 TCGv t[2];
2418 int memsize = memsize_zz(dc);
2419 int insn_len;
2420 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2421 memsize_char(memsize),
2422 dc->op1, dc->postinc ? "+]" : "]",
2423 dc->op2);
2424
2425 cris_alu_m_alloc_temps(t);
2426 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2427 cris_cc_mask(dc, 0);
2428 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2429 do_postinc(dc, memsize);
2430 cris_alu_m_free_temps(t);
2431 return insn_len;
2432 }
2433
2434 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2435 {
2436 TCGv l[2];
2437 int memsize = memsize_zz(dc);
2438 int insn_len;
2439 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2440 memsize_char(memsize),
2441 dc->op1, dc->postinc ? "+]" : "]",
2442 dc->op2);
2443
2444 l[0] = tcg_temp_local_new();
2445 l[1] = tcg_temp_local_new();
2446 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2447 cris_cc_mask(dc, CC_MASK_NZ);
2448 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2449 do_postinc(dc, memsize);
2450 tcg_temp_free(l[0]);
2451 tcg_temp_free(l[1]);
2452 return insn_len;
2453 }
2454
2455 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2456 {
2457 TCGv t[2];
2458 int insn_len = 2;
2459 LOG_DIS("addc [$r%u%s, $r%u\n",
2460 dc->op1, dc->postinc ? "+]" : "]",
2461 dc->op2);
2462
2463 cris_evaluate_flags(dc);
2464
2465 /* Set for this insn. */
2466 dc->flagx_known = 1;
2467 dc->flags_x = X_FLAG;
2468
2469 cris_alu_m_alloc_temps(t);
2470 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2471 cris_cc_mask(dc, CC_MASK_NZVC);
2472 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2473 do_postinc(dc, 4);
2474 cris_alu_m_free_temps(t);
2475 return insn_len;
2476 }
2477
2478 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2479 {
2480 TCGv t[2];
2481 int memsize = memsize_zz(dc);
2482 int insn_len;
2483 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2484 memsize_char(memsize),
2485 dc->op1, dc->postinc ? "+]" : "]",
2486 dc->op2, dc->ir, dc->zzsize);
2487
2488 cris_alu_m_alloc_temps(t);
2489 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2490 cris_cc_mask(dc, CC_MASK_NZVC);
2491 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2492 do_postinc(dc, memsize);
2493 cris_alu_m_free_temps(t);
2494 return insn_len;
2495 }
2496
2497 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2498 {
2499 TCGv t[2];
2500 int memsize = memsize_zz(dc);
2501 int insn_len;
2502 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2503 memsize_char(memsize),
2504 dc->op1, dc->postinc ? "+]" : "]",
2505 dc->op2, dc->pc);
2506
2507 cris_alu_m_alloc_temps(t);
2508 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2509 cris_cc_mask(dc, CC_MASK_NZ);
2510 cris_alu(dc, CC_OP_OR,
2511 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2512 do_postinc(dc, memsize);
2513 cris_alu_m_free_temps(t);
2514 return insn_len;
2515 }
2516
2517 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2518 {
2519 TCGv t[2];
2520 int memsize = memsize_zz(dc);
2521 int insn_len = 2;
2522
2523 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2524 memsize_char(memsize),
2525 dc->op1,
2526 dc->postinc ? "+]" : "]",
2527 dc->op2);
2528
2529 cris_alu_m_alloc_temps(t);
2530 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2531 cris_cc_mask(dc, 0);
2532 if (dc->op2 == PR_CCS) {
2533 cris_evaluate_flags(dc);
2534 if (dc->tb_flags & U_FLAG) {
2535 /* User space is not allowed to touch all flags. */
2536 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2537 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2538 tcg_gen_or_tl(t[1], t[0], t[1]);
2539 }
2540 }
2541
2542 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2543
2544 do_postinc(dc, memsize);
2545 cris_alu_m_free_temps(t);
2546 return insn_len;
2547 }
2548
2549 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2550 {
2551 TCGv t0;
2552 int memsize;
2553
2554 memsize = preg_sizes[dc->op2];
2555
2556 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2557 memsize_char(memsize),
2558 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2559
2560 /* prepare store. Address in T0, value in T1. */
2561 if (dc->op2 == PR_CCS) {
2562 cris_evaluate_flags(dc);
2563 }
2564 t0 = tcg_temp_new();
2565 t_gen_mov_TN_preg(t0, dc->op2);
2566 cris_flush_cc_state(dc);
2567 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2568 tcg_temp_free(t0);
2569
2570 cris_cc_mask(dc, 0);
2571 if (dc->postinc) {
2572 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2573 }
2574 return 2;
2575 }
2576
2577 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2578 {
2579 TCGv_i64 tmp[16];
2580 TCGv tmp32;
2581 TCGv addr;
2582 int i;
2583 int nr = dc->op2 + 1;
2584
2585 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2586 dc->postinc ? "+]" : "]", dc->op2);
2587
2588 addr = tcg_temp_new();
2589 /* There are probably better ways of doing this. */
2590 cris_flush_cc_state(dc);
2591 for (i = 0; i < (nr >> 1); i++) {
2592 tmp[i] = tcg_temp_new_i64();
2593 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2594 gen_load64(dc, tmp[i], addr);
2595 }
2596 if (nr & 1) {
2597 tmp32 = tcg_temp_new_i32();
2598 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2599 gen_load(dc, tmp32, addr, 4, 0);
2600 } else {
2601 TCGV_UNUSED(tmp32);
2602 }
2603 tcg_temp_free(addr);
2604
2605 for (i = 0; i < (nr >> 1); i++) {
2606 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]);
2607 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2608 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2609 tcg_temp_free_i64(tmp[i]);
2610 }
2611 if (nr & 1) {
2612 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2613 tcg_temp_free(tmp32);
2614 }
2615
2616 /* writeback the updated pointer value. */
2617 if (dc->postinc) {
2618 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2619 }
2620
2621 /* gen_load might want to evaluate the previous insns flags. */
2622 cris_cc_mask(dc, 0);
2623 return 2;
2624 }
2625
2626 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2627 {
2628 TCGv tmp;
2629 TCGv addr;
2630 int i;
2631
2632 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2633 dc->postinc ? "+]" : "]");
2634
2635 cris_flush_cc_state(dc);
2636
2637 tmp = tcg_temp_new();
2638 addr = tcg_temp_new();
2639 tcg_gen_movi_tl(tmp, 4);
2640 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2641 for (i = 0; i <= dc->op2; i++) {
2642 /* Displace addr. */
2643 /* Perform the store. */
2644 gen_store(dc, addr, cpu_R[i], 4);
2645 tcg_gen_add_tl(addr, addr, tmp);
2646 }
2647 if (dc->postinc) {
2648 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2649 }
2650 cris_cc_mask(dc, 0);
2651 tcg_temp_free(tmp);
2652 tcg_temp_free(addr);
2653 return 2;
2654 }
2655
2656 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2657 {
2658 int memsize;
2659
2660 memsize = memsize_zz(dc);
2661
2662 LOG_DIS("move.%c $r%u, [$r%u]\n",
2663 memsize_char(memsize), dc->op2, dc->op1);
2664
2665 /* prepare store. */
2666 cris_flush_cc_state(dc);
2667 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2668
2669 if (dc->postinc) {
2670 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2671 }
2672 cris_cc_mask(dc, 0);
2673 return 2;
2674 }
2675
2676 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2677 {
2678 LOG_DIS("lapcq %x, $r%u\n",
2679 dc->pc + dc->op1*2, dc->op2);
2680 cris_cc_mask(dc, 0);
2681 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2682 return 2;
2683 }
2684
2685 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2686 {
2687 unsigned int rd;
2688 int32_t imm;
2689 int32_t pc;
2690
2691 rd = dc->op2;
2692
2693 cris_cc_mask(dc, 0);
2694 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2695 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2696
2697 pc = dc->pc;
2698 pc += imm;
2699 tcg_gen_movi_tl(cpu_R[rd], pc);
2700 return 6;
2701 }
2702
2703 /* Jump to special reg. */
2704 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2705 {
2706 LOG_DIS("jump $p%u\n", dc->op2);
2707
2708 if (dc->op2 == PR_CCS) {
2709 cris_evaluate_flags(dc);
2710 }
2711 t_gen_mov_TN_preg(env_btarget, dc->op2);
2712 /* rete will often have low bit set to indicate delayslot. */
2713 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2714 cris_cc_mask(dc, 0);
2715 cris_prepare_jmp(dc, JMP_INDIRECT);
2716 return 2;
2717 }
2718
2719 /* Jump and save. */
2720 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2721 {
2722 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2723 cris_cc_mask(dc, 0);
2724 /* Store the return address in Pd. */
2725 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2726 if (dc->op2 > 15) {
2727 abort();
2728 }
2729 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2730
2731 cris_prepare_jmp(dc, JMP_INDIRECT);
2732 return 2;
2733 }
2734
2735 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2736 {
2737 uint32_t imm;
2738
2739 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2740
2741 LOG_DIS("jas 0x%x\n", imm);
2742 cris_cc_mask(dc, 0);
2743 /* Store the return address in Pd. */
2744 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2745
2746 dc->jmp_pc = imm;
2747 cris_prepare_jmp(dc, JMP_DIRECT);
2748 return 6;
2749 }
2750
2751 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2752 {
2753 uint32_t imm;
2754
2755 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2756
2757 LOG_DIS("jasc 0x%x\n", imm);
2758 cris_cc_mask(dc, 0);
2759 /* Store the return address in Pd. */
2760 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2761
2762 dc->jmp_pc = imm;
2763 cris_prepare_jmp(dc, JMP_DIRECT);
2764 return 6;
2765 }
2766
2767 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2768 {
2769 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2770 cris_cc_mask(dc, 0);
2771 /* Store the return address in Pd. */
2772 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2773 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2774 cris_prepare_jmp(dc, JMP_INDIRECT);
2775 return 2;
2776 }
2777
2778 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2779 {
2780 int32_t offset;
2781 uint32_t cond = dc->op2;
2782
2783 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2784
2785 LOG_DIS("b%s %d pc=%x dst=%x\n",
2786 cc_name(cond), offset,
2787 dc->pc, dc->pc + offset);
2788
2789 cris_cc_mask(dc, 0);
2790 /* op2 holds the condition-code. */
2791 cris_prepare_cc_branch(dc, offset, cond);
2792 return 4;
2793 }
2794
2795 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2796 {
2797 int32_t simm;
2798
2799 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2800
2801 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2802 cris_cc_mask(dc, 0);
2803 /* Store the return address in Pd. */
2804 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2805
2806 dc->jmp_pc = dc->pc + simm;
2807 cris_prepare_jmp(dc, JMP_DIRECT);
2808 return 6;
2809 }
2810
2811 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2812 {
2813 int32_t simm;
2814 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2815
2816 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2817 cris_cc_mask(dc, 0);
2818 /* Store the return address in Pd. */
2819 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2820
2821 dc->jmp_pc = dc->pc + simm;
2822 cris_prepare_jmp(dc, JMP_DIRECT);
2823 return 6;
2824 }
2825
2826 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2827 {
2828 cris_cc_mask(dc, 0);
2829
2830 if (dc->op2 == 15) {
2831 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2832 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2833 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2834 t_gen_raise_exception(EXCP_HLT);
2835 return 2;
2836 }
2837
2838 switch (dc->op2 & 7) {
2839 case 2:
2840 /* rfe. */
2841 LOG_DIS("rfe\n");
2842 cris_evaluate_flags(dc);
2843 gen_helper_rfe(cpu_env);
2844 dc->is_jmp = DISAS_UPDATE;
2845 break;
2846 case 5:
2847 /* rfn. */
2848 LOG_DIS("rfn\n");
2849 cris_evaluate_flags(dc);
2850 gen_helper_rfn(cpu_env);
2851 dc->is_jmp = DISAS_UPDATE;
2852 break;
2853 case 6:
2854 LOG_DIS("break %d\n", dc->op1);
2855 cris_evaluate_flags(dc);
2856 /* break. */
2857 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2858
2859 /* Breaks start at 16 in the exception vector. */
2860 t_gen_mov_env_TN(trap_vector,
2861 tcg_const_tl(dc->op1 + 16));
2862 t_gen_raise_exception(EXCP_BREAK);
2863 dc->is_jmp = DISAS_UPDATE;
2864 break;
2865 default:
2866 printf("op2=%x\n", dc->op2);
2867 BUG();
2868 break;
2869
2870 }
2871 return 2;
2872 }
2873
2874 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2875 {
2876 return 2;
2877 }
2878
2879 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2880 {
2881 return 2;
2882 }
2883
2884 static int QEMU_NORETURN dec_null(CPUCRISState *env, DisasContext *dc)
2885 {
2886 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2887 dc->pc, dc->opcode, dc->op1, dc->op2);
2888 fflush(NULL);
2889 BUG();
2890 }
2891
2892 static struct decoder_info {
2893 struct {
2894 uint32_t bits;
2895 uint32_t mask;
2896 };
2897 int (*dec)(CPUCRISState *env, DisasContext *dc);
2898 } decinfo[] = {
2899 /* Order matters here. */
2900 {DEC_MOVEQ, dec_moveq},
2901 {DEC_BTSTQ, dec_btstq},
2902 {DEC_CMPQ, dec_cmpq},
2903 {DEC_ADDOQ, dec_addoq},
2904 {DEC_ADDQ, dec_addq},
2905 {DEC_SUBQ, dec_subq},
2906 {DEC_ANDQ, dec_andq},
2907 {DEC_ORQ, dec_orq},
2908 {DEC_ASRQ, dec_asrq},
2909 {DEC_LSLQ, dec_lslq},
2910 {DEC_LSRQ, dec_lsrq},
2911 {DEC_BCCQ, dec_bccq},
2912
2913 {DEC_BCC_IM, dec_bcc_im},
2914 {DEC_JAS_IM, dec_jas_im},
2915 {DEC_JAS_R, dec_jas_r},
2916 {DEC_JASC_IM, dec_jasc_im},
2917 {DEC_JASC_R, dec_jasc_r},
2918 {DEC_BAS_IM, dec_bas_im},
2919 {DEC_BASC_IM, dec_basc_im},
2920 {DEC_JUMP_P, dec_jump_p},
2921 {DEC_LAPC_IM, dec_lapc_im},
2922 {DEC_LAPCQ, dec_lapcq},
2923
2924 {DEC_RFE_ETC, dec_rfe_etc},
2925 {DEC_ADDC_MR, dec_addc_mr},
2926
2927 {DEC_MOVE_MP, dec_move_mp},
2928 {DEC_MOVE_PM, dec_move_pm},
2929 {DEC_MOVEM_MR, dec_movem_mr},
2930 {DEC_MOVEM_RM, dec_movem_rm},
2931 {DEC_MOVE_PR, dec_move_pr},
2932 {DEC_SCC_R, dec_scc_r},
2933 {DEC_SETF, dec_setclrf},
2934 {DEC_CLEARF, dec_setclrf},
2935
2936 {DEC_MOVE_SR, dec_move_sr},
2937 {DEC_MOVE_RP, dec_move_rp},
2938 {DEC_SWAP_R, dec_swap_r},
2939 {DEC_ABS_R, dec_abs_r},
2940 {DEC_LZ_R, dec_lz_r},
2941 {DEC_MOVE_RS, dec_move_rs},
2942 {DEC_BTST_R, dec_btst_r},
2943 {DEC_ADDC_R, dec_addc_r},
2944
2945 {DEC_DSTEP_R, dec_dstep_r},
2946 {DEC_XOR_R, dec_xor_r},
2947 {DEC_MCP_R, dec_mcp_r},
2948 {DEC_CMP_R, dec_cmp_r},
2949
2950 {DEC_ADDI_R, dec_addi_r},
2951 {DEC_ADDI_ACR, dec_addi_acr},
2952
2953 {DEC_ADD_R, dec_add_r},
2954 {DEC_SUB_R, dec_sub_r},
2955
2956 {DEC_ADDU_R, dec_addu_r},
2957 {DEC_ADDS_R, dec_adds_r},
2958 {DEC_SUBU_R, dec_subu_r},
2959 {DEC_SUBS_R, dec_subs_r},
2960 {DEC_LSL_R, dec_lsl_r},
2961
2962 {DEC_AND_R, dec_and_r},
2963 {DEC_OR_R, dec_or_r},
2964 {DEC_BOUND_R, dec_bound_r},
2965 {DEC_ASR_R, dec_asr_r},
2966 {DEC_LSR_R, dec_lsr_r},
2967
2968 {DEC_MOVU_R, dec_movu_r},
2969 {DEC_MOVS_R, dec_movs_r},
2970 {DEC_NEG_R, dec_neg_r},
2971 {DEC_MOVE_R, dec_move_r},
2972
2973 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2974 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2975
2976 {DEC_MULS_R, dec_muls_r},
2977 {DEC_MULU_R, dec_mulu_r},
2978
2979 {DEC_ADDU_M, dec_addu_m},
2980 {DEC_ADDS_M, dec_adds_m},
2981 {DEC_SUBU_M, dec_subu_m},
2982 {DEC_SUBS_M, dec_subs_m},
2983
2984 {DEC_CMPU_M, dec_cmpu_m},
2985 {DEC_CMPS_M, dec_cmps_m},
2986 {DEC_MOVU_M, dec_movu_m},
2987 {DEC_MOVS_M, dec_movs_m},
2988
2989 {DEC_CMP_M, dec_cmp_m},
2990 {DEC_ADDO_M, dec_addo_m},
2991 {DEC_BOUND_M, dec_bound_m},
2992 {DEC_ADD_M, dec_add_m},
2993 {DEC_SUB_M, dec_sub_m},
2994 {DEC_AND_M, dec_and_m},
2995 {DEC_OR_M, dec_or_m},
2996 {DEC_MOVE_RM, dec_move_rm},
2997 {DEC_TEST_M, dec_test_m},
2998 {DEC_MOVE_MR, dec_move_mr},
2999
3000 {{0, 0}, dec_null}
3001 };
3002
3003 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
3004 {
3005 int insn_len = 2;
3006 int i;
3007
3008 /* Load a halfword onto the instruction register. */
3009 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3010
3011 /* Now decode it. */
3012 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3013 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3014 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3015 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3016 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3017 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3018
3019 /* Large switch for all insns. */
3020 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3021 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3022 insn_len = decinfo[i].dec(env, dc);
3023 break;
3024 }
3025 }
3026
3027 #if !defined(CONFIG_USER_ONLY)
3028 /* Single-stepping ? */
3029 if (dc->tb_flags & S_FLAG) {
3030 TCGLabel *l1 = gen_new_label();
3031 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3032 /* We treat SPC as a break with an odd trap vector. */
3033 cris_evaluate_flags(dc);
3034 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3035 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3036 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3037 t_gen_raise_exception(EXCP_BREAK);
3038 gen_set_label(l1);
3039 }
3040 #endif
3041 return insn_len;
3042 }
3043
3044 #include "translate_v10.c"
3045
3046 /*
3047 * Delay slots on QEMU/CRIS.
3048 *
3049 * If an exception hits on a delayslot, the core will let ERP (the Exception
3050 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3051 * to give SW a hint that the exception actually hit on the dslot.
3052 *
3053 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3054 * the core and any jmp to an odd addresses will mask off that lsb. It is
3055 * simply there to let sw know there was an exception on a dslot.
3056 *
3057 * When the software returns from an exception, the branch will re-execute.
3058 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3059 * and the branch and delayslot don't share pages.
3060 *
3061 * The TB contaning the branch insn will set up env->btarget and evaluate
3062 * env->btaken. When the translation loop exits we will note that the branch
3063 * sequence is broken and let env->dslot be the size of the branch insn (those
3064 * vary in length).
3065 *
3066 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3067 * set). It will also expect to have env->dslot setup with the size of the
3068 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3069 * will execute the dslot and take the branch, either to btarget or just one
3070 * insn ahead.
3071 *
3072 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3073 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3074 * branch and set lsb). Then env->dslot gets cleared so that the exception
3075 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3076 * masked off and we will reexecute the branch insn.
3077 *
3078 */
3079
3080 /* generate intermediate code for basic block 'tb'. */
3081 void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
3082 {
3083 CRISCPU *cpu = cris_env_get_cpu(env);
3084 CPUState *cs = CPU(cpu);
3085 uint32_t pc_start;
3086 unsigned int insn_len;
3087 struct DisasContext ctx;
3088 struct DisasContext *dc = &ctx;
3089 uint32_t next_page_start;
3090 target_ulong npc;
3091 int num_insns;
3092 int max_insns;
3093
3094 if (env->pregs[PR_VR] == 32) {
3095 dc->decoder = crisv32_decoder;
3096 dc->clear_locked_irq = 0;
3097 } else {
3098 dc->decoder = crisv10_decoder;
3099 dc->clear_locked_irq = 1;
3100 }
3101
3102 /* Odd PC indicates that branch is rexecuting due to exception in the
3103 * delayslot, like in real hw.
3104 */
3105 pc_start = tb->pc & ~1;
3106 dc->cpu = cpu;
3107 dc->tb = tb;
3108
3109 dc->is_jmp = DISAS_NEXT;
3110 dc->ppc = pc_start;
3111 dc->pc = pc_start;
3112 dc->singlestep_enabled = cs->singlestep_enabled;
3113 dc->flags_uptodate = 1;
3114 dc->flagx_known = 1;
3115 dc->flags_x = tb->flags & X_FLAG;
3116 dc->cc_x_uptodate = 0;
3117 dc->cc_mask = 0;
3118 dc->update_cc = 0;
3119 dc->clear_prefix = 0;
3120
3121 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3122 dc->cc_size_uptodate = -1;
3123
3124 /* Decode TB flags. */
3125 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3126 | X_FLAG | PFIX_FLAG);
3127 dc->delayed_branch = !!(tb->flags & 7);
3128 if (dc->delayed_branch) {
3129 dc->jmp = JMP_INDIRECT;
3130 } else {
3131 dc->jmp = JMP_NOJMP;
3132 }
3133
3134 dc->cpustate_changed = 0;
3135
3136 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3137 qemu_log(
3138 "pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3139 "pid=%x usp=%x\n"
3140 "%x.%x.%x.%x\n"
3141 "%x.%x.%x.%x\n"
3142 "%x.%x.%x.%x\n"
3143 "%x.%x.%x.%x\n",
3144 dc->pc, dc->ppc,
3145 (uint64_t)tb->flags,
3146 env->btarget, (unsigned)tb->flags & 7,
3147 env->pregs[PR_CCS],
3148 env->pregs[PR_PID], env->pregs[PR_USP],
3149 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3150 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3151 env->regs[8], env->regs[9],
3152 env->regs[10], env->regs[11],
3153 env->regs[12], env->regs[13],
3154 env->regs[14], env->regs[15]);
3155 qemu_log("--------------\n");
3156 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3157 }
3158
3159 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3160 num_insns = 0;
3161 max_insns = tb->cflags & CF_COUNT_MASK;
3162 if (max_insns == 0) {
3163 max_insns = CF_COUNT_MASK;
3164 }
3165 if (max_insns > TCG_MAX_INSNS) {
3166 max_insns = TCG_MAX_INSNS;
3167 }
3168
3169 gen_tb_start(tb);
3170 do {
3171 tcg_gen_insn_start(dc->delayed_branch == 1
3172 ? dc->ppc | 1 : dc->pc);
3173 num_insns++;
3174
3175 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3176 cris_evaluate_flags(dc);
3177 tcg_gen_movi_tl(env_pc, dc->pc);
3178 t_gen_raise_exception(EXCP_DEBUG);
3179 dc->is_jmp = DISAS_UPDATE;
3180 /* The address covered by the breakpoint must be included in
3181 [tb->pc, tb->pc + tb->size) in order to for it to be
3182 properly cleared -- thus we increment the PC here so that
3183 the logic setting tb->size below does the right thing. */
3184 dc->pc += 2;
3185 break;
3186 }
3187
3188 /* Pretty disas. */
3189 LOG_DIS("%8.8x:\t", dc->pc);
3190
3191 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3192 gen_io_start();
3193 }
3194 dc->clear_x = 1;
3195
3196 insn_len = dc->decoder(env, dc);
3197 dc->ppc = dc->pc;
3198 dc->pc += insn_len;
3199 if (dc->clear_x) {
3200 cris_clear_x_flag(dc);
3201 }
3202
3203 /* Check for delayed branches here. If we do it before
3204 actually generating any host code, the simulator will just
3205 loop doing nothing for on this program location. */
3206 if (dc->delayed_branch) {
3207 dc->delayed_branch--;
3208 if (dc->delayed_branch == 0) {
3209 if (tb->flags & 7) {
3210 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3211 }
3212 if (dc->cpustate_changed || !dc->flagx_known
3213 || (dc->flags_x != (tb->flags & X_FLAG))) {
3214 cris_store_direct_jmp(dc);
3215 }
3216
3217 if (dc->clear_locked_irq) {
3218 dc->clear_locked_irq = 0;
3219 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3220 }
3221
3222 if (dc->jmp == JMP_DIRECT_CC) {
3223 TCGLabel *l1 = gen_new_label();
3224 cris_evaluate_flags(dc);
3225
3226 /* Conditional jmp. */
3227 tcg_gen_brcondi_tl(TCG_COND_EQ,
3228 env_btaken, 0, l1);
3229 gen_goto_tb(dc, 1, dc->jmp_pc);
3230 gen_set_label(l1);
3231 gen_goto_tb(dc, 0, dc->pc);
3232 dc->is_jmp = DISAS_TB_JUMP;
3233 dc->jmp = JMP_NOJMP;
3234 } else if (dc->jmp == JMP_DIRECT) {
3235 cris_evaluate_flags(dc);
3236 gen_goto_tb(dc, 0, dc->jmp_pc);
3237 dc->is_jmp = DISAS_TB_JUMP;
3238 dc->jmp = JMP_NOJMP;
3239 } else {
3240 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3241 dc->is_jmp = DISAS_JUMP;
3242 }
3243 break;
3244 }
3245 }
3246
3247 /* If we are rexecuting a branch due to exceptions on
3248 delay slots don't break. */
3249 if (!(tb->pc & 1) && cs->singlestep_enabled) {
3250 break;
3251 }
3252 } while (!dc->is_jmp && !dc->cpustate_changed
3253 && !tcg_op_buf_full()
3254 && !singlestep
3255 && (dc->pc < next_page_start)
3256 && num_insns < max_insns);
3257
3258 if (dc->clear_locked_irq) {
3259 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3260 }
3261
3262 npc = dc->pc;
3263
3264 if (tb->cflags & CF_LAST_IO)
3265 gen_io_end();
3266 /* Force an update if the per-tb cpu state has changed. */
3267 if (dc->is_jmp == DISAS_NEXT
3268 && (dc->cpustate_changed || !dc->flagx_known
3269 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3270 dc->is_jmp = DISAS_UPDATE;
3271 tcg_gen_movi_tl(env_pc, npc);
3272 }
3273 /* Broken branch+delayslot sequence. */
3274 if (dc->delayed_branch == 1) {
3275 /* Set env->dslot to the size of the branch insn. */
3276 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3277 cris_store_direct_jmp(dc);
3278 }
3279
3280 cris_evaluate_flags(dc);
3281
3282 if (unlikely(cs->singlestep_enabled)) {
3283 if (dc->is_jmp == DISAS_NEXT) {
3284 tcg_gen_movi_tl(env_pc, npc);
3285 }
3286 t_gen_raise_exception(EXCP_DEBUG);
3287 } else {
3288 switch (dc->is_jmp) {
3289 case DISAS_NEXT:
3290 gen_goto_tb(dc, 1, npc);
3291 break;
3292 default:
3293 case DISAS_JUMP:
3294 case DISAS_UPDATE:
3295 /* indicate that the hash table must be used
3296 to find the next TB */
3297 tcg_gen_exit_tb(0);
3298 break;
3299 case DISAS_SWI:
3300 case DISAS_TB_JUMP:
3301 /* nothing more to generate */
3302 break;
3303 }
3304 }
3305 gen_tb_end(tb, num_insns);
3306
3307 tb->size = dc->pc - pc_start;
3308 tb->icount = num_insns;
3309
3310 #ifdef DEBUG_DISAS
3311 #if !DISAS_CRIS
3312 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3313 log_target_disas(cs, pc_start, dc->pc - pc_start,
3314 env->pregs[PR_VR]);
3315 qemu_log("\nisize=%d osize=%d\n",
3316 dc->pc - pc_start, tcg_op_buf_count());
3317 }
3318 #endif
3319 #endif
3320 }
3321
3322 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3323 int flags)
3324 {
3325 CRISCPU *cpu = CRIS_CPU(cs);
3326 CPUCRISState *env = &cpu->env;
3327 int i;
3328 uint32_t srs;
3329
3330 if (!env || !f) {
3331 return;
3332 }
3333
3334 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3335 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3336 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3337 env->cc_op,
3338 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3339
3340
3341 for (i = 0; i < 16; i++) {
3342 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3343 if ((i + 1) % 4 == 0) {
3344 cpu_fprintf(f, "\n");
3345 }
3346 }
3347 cpu_fprintf(f, "\nspecial regs:\n");
3348 for (i = 0; i < 16; i++) {
3349 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3350 if ((i + 1) % 4 == 0) {
3351 cpu_fprintf(f, "\n");
3352 }
3353 }
3354 srs = env->pregs[PR_SRS];
3355 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3356 if (srs < ARRAY_SIZE(env->sregs)) {
3357 for (i = 0; i < 16; i++) {
3358 cpu_fprintf(f, "s%2.2d=%8.8x ",
3359 i, env->sregs[srs][i]);
3360 if ((i + 1) % 4 == 0) {
3361 cpu_fprintf(f, "\n");
3362 }
3363 }
3364 }
3365 cpu_fprintf(f, "\n\n");
3366
3367 }
3368
3369 void cris_initialize_tcg(void)
3370 {
3371 int i;
3372
3373 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3374 cc_x = tcg_global_mem_new(cpu_env,
3375 offsetof(CPUCRISState, cc_x), "cc_x");
3376 cc_src = tcg_global_mem_new(cpu_env,
3377 offsetof(CPUCRISState, cc_src), "cc_src");
3378 cc_dest = tcg_global_mem_new(cpu_env,
3379 offsetof(CPUCRISState, cc_dest),
3380 "cc_dest");
3381 cc_result = tcg_global_mem_new(cpu_env,
3382 offsetof(CPUCRISState, cc_result),
3383 "cc_result");
3384 cc_op = tcg_global_mem_new(cpu_env,
3385 offsetof(CPUCRISState, cc_op), "cc_op");
3386 cc_size = tcg_global_mem_new(cpu_env,
3387 offsetof(CPUCRISState, cc_size),
3388 "cc_size");
3389 cc_mask = tcg_global_mem_new(cpu_env,
3390 offsetof(CPUCRISState, cc_mask),
3391 "cc_mask");
3392
3393 env_pc = tcg_global_mem_new(cpu_env,
3394 offsetof(CPUCRISState, pc),
3395 "pc");
3396 env_btarget = tcg_global_mem_new(cpu_env,
3397 offsetof(CPUCRISState, btarget),
3398 "btarget");
3399 env_btaken = tcg_global_mem_new(cpu_env,
3400 offsetof(CPUCRISState, btaken),
3401 "btaken");
3402 for (i = 0; i < 16; i++) {
3403 cpu_R[i] = tcg_global_mem_new(cpu_env,
3404 offsetof(CPUCRISState, regs[i]),
3405 regnames[i]);
3406 }
3407 for (i = 0; i < 16; i++) {
3408 cpu_PR[i] = tcg_global_mem_new(cpu_env,
3409 offsetof(CPUCRISState, pregs[i]),
3410 pregnames[i]);
3411 }
3412 }
3413
3414 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb,
3415 target_ulong *data)
3416 {
3417 env->pc = data[0];
3418 }
AR7 emulation for QEMU