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Merge remote-tracking branch 'qemu-project/master'
[qemu/ar7.git] / target / cris / translate.c
blobebb3bcbb704bc82b882b45bbe7b36e8571e22981
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "qemu/osdep.h"
27 #include "cpu.h"
28 #include "disas/disas.h"
29 #include "exec/exec-all.h"
30 #include "tcg/tcg-op.h"
31 #include "exec/helper-proto.h"
32 #include "mmu.h"
33 #include "exec/cpu_ldst.h"
34 #include "exec/translator.h"
35 #include "crisv32-decode.h"
36 #include "qemu/qemu-print.h"
37 #include "exec/helper-gen.h"
38 #include "exec/log.h"
39
40 #define HELPER_H "helper.h"
41 #include "exec/helper-info.c.inc"
42 #undef HELPER_H
43
44
45 #define DISAS_CRIS 0
46 #if DISAS_CRIS
47 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
48 #else
49 # define LOG_DIS(...) do { } while (0)
50 #endif
51
52 #define D(x)
53 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
54 #define BUG_ON(x) ({if (x) BUG();})
55
56 /*
57 * Target-specific is_jmp field values
58 */
59 /* Only pc was modified dynamically */
60 #define DISAS_JUMP DISAS_TARGET_0
61 /* Cpu state was modified dynamically, including pc */
62 #define DISAS_UPDATE DISAS_TARGET_1
63 /* Cpu state was modified dynamically, excluding pc -- use npc */
64 #define DISAS_UPDATE_NEXT DISAS_TARGET_2
65 /* PC update for delayed branch, see cpustate_changed otherwise */
66 #define DISAS_DBRANCH DISAS_TARGET_3
67
68 /* Used by the decoder. */
69 #define EXTRACT_FIELD(src, start, end) \
70 (((src) >> start) & ((1 << (end - start + 1)) - 1))
71
72 #define CC_MASK_NZ 0xc
73 #define CC_MASK_NZV 0xe
74 #define CC_MASK_NZVC 0xf
75 #define CC_MASK_RNZV 0x10e
76
77 static TCGv cpu_R[16];
78 static TCGv cpu_PR[16];
79 static TCGv cc_x;
80 static TCGv cc_src;
81 static TCGv cc_dest;
82 static TCGv cc_result;
83 static TCGv cc_op;
84 static TCGv cc_size;
85 static TCGv cc_mask;
86
87 static TCGv env_btaken;
88 static TCGv env_btarget;
89 static TCGv env_pc;
90
91 /* This is the state at translation time. */
92 typedef struct DisasContext {
93 DisasContextBase base;
94
95 CRISCPU *cpu;
96 target_ulong pc, ppc;
97 int mem_index;
98
99 /* Decoder. */
100 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
101 uint32_t ir;
102 uint32_t opcode;
103 unsigned int op1;
104 unsigned int op2;
105 unsigned int zsize, zzsize;
106 unsigned int mode;
107 unsigned int postinc;
108
109 unsigned int size;
110 unsigned int src;
111 unsigned int dst;
112 unsigned int cond;
113
114 int update_cc;
115 int cc_op;
116 int cc_size;
117 uint32_t cc_mask;
118
119 int cc_size_uptodate; /* -1 invalid or last written value. */
120
121 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not up-to-date. */
122 int flags_uptodate; /* Whether or not $ccs is up-to-date. */
123 int flags_x;
124
125 int clear_x; /* Clear x after this insn? */
126 int clear_prefix; /* Clear prefix after this insn? */
127 int clear_locked_irq; /* Clear the irq lockout. */
128 int cpustate_changed;
129 unsigned int tb_flags; /* tb dependent flags. */
130
131 #define JMP_NOJMP 0
132 #define JMP_DIRECT 1
133 #define JMP_DIRECT_CC 2
134 #define JMP_INDIRECT 3
135 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
136 uint32_t jmp_pc;
137
138 int delayed_branch;
139 } DisasContext;
140
141 static void G_NORETURN gen_BUG(DisasContext *dc, const char *file, int line)
142 {
143 cpu_abort(CPU(dc->cpu), "%s:%d pc=%x\n", file, line, dc->pc);
144 }
145
146 static const char * const regnames_v32[] =
147 {
148 "$r0", "$r1", "$r2", "$r3",
149 "$r4", "$r5", "$r6", "$r7",
150 "$r8", "$r9", "$r10", "$r11",
151 "$r12", "$r13", "$sp", "$acr",
152 };
153
154 static const char * const pregnames_v32[] =
155 {
156 "$bz", "$vr", "$pid", "$srs",
157 "$wz", "$exs", "$eda", "$mof",
158 "$dz", "$ebp", "$erp", "$srp",
159 "$nrp", "$ccs", "$usp", "$spc",
160 };
161
162 /* We need this table to handle preg-moves with implicit width. */
163 static const int preg_sizes[] = {
164 1, /* bz. */
165 1, /* vr. */
166 4, /* pid. */
167 1, /* srs. */
168 2, /* wz. */
169 4, 4, 4,
170 4, 4, 4, 4,
171 4, 4, 4, 4,
172 };
173
174 #define t_gen_mov_TN_env(tn, member) \
175 tcg_gen_ld_tl(tn, tcg_env, offsetof(CPUCRISState, member))
176 #define t_gen_mov_env_TN(member, tn) \
177 tcg_gen_st_tl(tn, tcg_env, offsetof(CPUCRISState, member))
178 #define t_gen_movi_env_TN(member, c) \
179 t_gen_mov_env_TN(member, tcg_constant_tl(c))
180
181 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
182 {
183 assert(r >= 0 && r <= 15);
184 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
185 tcg_gen_movi_tl(tn, 0);
186 } else if (r == PR_VR) {
187 tcg_gen_movi_tl(tn, 32);
188 } else {
189 tcg_gen_mov_tl(tn, cpu_PR[r]);
190 }
191 }
192 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
193 {
194 assert(r >= 0 && r <= 15);
195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
196 return;
197 } else if (r == PR_SRS) {
198 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
199 } else {
200 if (r == PR_PID) {
201 gen_helper_tlb_flush_pid(tcg_env, tn);
202 }
203 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
204 gen_helper_spc_write(tcg_env, tn);
205 } else if (r == PR_CCS) {
206 dc->cpustate_changed = 1;
207 }
208 tcg_gen_mov_tl(cpu_PR[r], tn);
209 }
210 }
211
212 /* Sign extend at translation time. */
213 static int sign_extend(unsigned int val, unsigned int width)
214 {
215 int sval;
216
217 /* LSL. */
218 val <<= 31 - width;
219 sval = val;
220 /* ASR. */
221 sval >>= 31 - width;
222 return sval;
223 }
224
225 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
226 unsigned int size, unsigned int sign)
227 {
228 int r;
229
230 switch (size) {
231 case 4:
232 {
233 r = cpu_ldl_code(env, addr);
234 break;
235 }
236 case 2:
237 {
238 if (sign) {
239 r = cpu_ldsw_code(env, addr);
240 } else {
241 r = cpu_lduw_code(env, addr);
242 }
243 break;
244 }
245 case 1:
246 {
247 if (sign) {
248 r = cpu_ldsb_code(env, addr);
249 } else {
250 r = cpu_ldub_code(env, addr);
251 }
252 break;
253 }
254 default:
255 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
256 break;
257 }
258 return r;
259 }
260
261 static void cris_lock_irq(DisasContext *dc)
262 {
263 dc->clear_locked_irq = 0;
264 t_gen_movi_env_TN(locked_irq, 1);
265 }
266
267 static inline void t_gen_raise_exception(uint32_t index)
268 {
269 gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
270 }
271
272 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
273 {
274 TCGv t0, t_31;
275
276 t0 = tcg_temp_new();
277 t_31 = tcg_constant_tl(31);
278 tcg_gen_shl_tl(d, a, b);
279
280 tcg_gen_sub_tl(t0, t_31, b);
281 tcg_gen_sar_tl(t0, t0, t_31);
282 tcg_gen_and_tl(t0, t0, d);
283 tcg_gen_xor_tl(d, d, t0);
284 }
285
286 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
287 {
288 TCGv t0, t_31;
289
290 t0 = tcg_temp_new();
291 t_31 = tcg_temp_new();
292 tcg_gen_shr_tl(d, a, b);
293
294 tcg_gen_movi_tl(t_31, 31);
295 tcg_gen_sub_tl(t0, t_31, b);
296 tcg_gen_sar_tl(t0, t0, t_31);
297 tcg_gen_and_tl(t0, t0, d);
298 tcg_gen_xor_tl(d, d, t0);
299 }
300
301 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
302 {
303 TCGv t0, t_31;
304
305 t0 = tcg_temp_new();
306 t_31 = tcg_temp_new();
307 tcg_gen_sar_tl(d, a, b);
308
309 tcg_gen_movi_tl(t_31, 31);
310 tcg_gen_sub_tl(t0, t_31, b);
311 tcg_gen_sar_tl(t0, t0, t_31);
312 tcg_gen_or_tl(d, d, t0);
313 }
314
315 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
316 {
317 TCGv t = tcg_temp_new();
318
319 /*
320 * d <<= 1
321 * if (d >= s)
322 * d -= s;
323 */
324 tcg_gen_shli_tl(d, a, 1);
325 tcg_gen_sub_tl(t, d, b);
326 tcg_gen_movcond_tl(TCG_COND_GEU, d, d, b, t, d);
327 }
328
329 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
330 {
331 TCGv t;
332
333 /*
334 * d <<= 1
335 * if (n)
336 * d += s;
337 */
338 t = tcg_temp_new();
339 tcg_gen_shli_tl(d, a, 1);
340 tcg_gen_shli_tl(t, ccs, 31 - 3);
341 tcg_gen_sari_tl(t, t, 31);
342 tcg_gen_and_tl(t, t, b);
343 tcg_gen_add_tl(d, d, t);
344 }
345
346 /* Extended arithmetic on CRIS. */
347 static inline void t_gen_add_flag(TCGv d, int flag)
348 {
349 TCGv c;
350
351 c = tcg_temp_new();
352 t_gen_mov_TN_preg(c, PR_CCS);
353 /* Propagate carry into d. */
354 tcg_gen_andi_tl(c, c, 1 << flag);
355 if (flag) {
356 tcg_gen_shri_tl(c, c, flag);
357 }
358 tcg_gen_add_tl(d, d, c);
359 }
360
361 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
362 {
363 if (dc->flags_x) {
364 TCGv c = tcg_temp_new();
365
366 t_gen_mov_TN_preg(c, PR_CCS);
367 /* C flag is already at bit 0. */
368 tcg_gen_andi_tl(c, c, C_FLAG);
369 tcg_gen_add_tl(d, d, c);
370 }
371 }
372
373 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
374 {
375 if (dc->flags_x) {
376 TCGv c = tcg_temp_new();
377
378 t_gen_mov_TN_preg(c, PR_CCS);
379 /* C flag is already at bit 0. */
380 tcg_gen_andi_tl(c, c, C_FLAG);
381 tcg_gen_sub_tl(d, d, c);
382 }
383 }
384
385 /* Swap the two bytes within each half word of the s operand.
386 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
387 static inline void t_gen_swapb(TCGv d, TCGv s)
388 {
389 TCGv t, org_s;
390
391 t = tcg_temp_new();
392 org_s = tcg_temp_new();
393
394 /* d and s may refer to the same object. */
395 tcg_gen_mov_tl(org_s, s);
396 tcg_gen_shli_tl(t, org_s, 8);
397 tcg_gen_andi_tl(d, t, 0xff00ff00);
398 tcg_gen_shri_tl(t, org_s, 8);
399 tcg_gen_andi_tl(t, t, 0x00ff00ff);
400 tcg_gen_or_tl(d, d, t);
401 }
402
403 /* Swap the halfwords of the s operand. */
404 static inline void t_gen_swapw(TCGv d, TCGv s)
405 {
406 TCGv t;
407 /* d and s refer the same object. */
408 t = tcg_temp_new();
409 tcg_gen_mov_tl(t, s);
410 tcg_gen_shli_tl(d, t, 16);
411 tcg_gen_shri_tl(t, t, 16);
412 tcg_gen_or_tl(d, d, t);
413 }
414
415 /*
416 * Reverse the bits within each byte.
417 *
418 * T0 = ((T0 << 7) & 0x80808080)
419 * | ((T0 << 5) & 0x40404040)
420 * | ((T0 << 3) & 0x20202020)
421 * | ((T0 << 1) & 0x10101010)
422 * | ((T0 >> 1) & 0x08080808)
423 * | ((T0 >> 3) & 0x04040404)
424 * | ((T0 >> 5) & 0x02020202)
425 * | ((T0 >> 7) & 0x01010101);
426 */
427 static void t_gen_swapr(TCGv d, TCGv s)
428 {
429 static const struct {
430 int shift; /* LSL when positive, LSR when negative. */
431 uint32_t mask;
432 } bitrev[] = {
433 {7, 0x80808080},
434 {5, 0x40404040},
435 {3, 0x20202020},
436 {1, 0x10101010},
437 {-1, 0x08080808},
438 {-3, 0x04040404},
439 {-5, 0x02020202},
440 {-7, 0x01010101}
441 };
442 int i;
443 TCGv t, org_s;
444
445 /* d and s refer the same object. */
446 t = tcg_temp_new();
447 org_s = tcg_temp_new();
448 tcg_gen_mov_tl(org_s, s);
449
450 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
451 tcg_gen_andi_tl(d, t, bitrev[0].mask);
452 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
453 if (bitrev[i].shift >= 0) {
454 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
455 } else {
456 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
457 }
458 tcg_gen_andi_tl(t, t, bitrev[i].mask);
459 tcg_gen_or_tl(d, d, t);
460 }
461 }
462
463 static bool use_goto_tb(DisasContext *dc, target_ulong dest)
464 {
465 return translator_use_goto_tb(&dc->base, dest);
466 }
467
468 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
469 {
470 if (use_goto_tb(dc, dest)) {
471 tcg_gen_goto_tb(n);
472 tcg_gen_movi_tl(env_pc, dest);
473 tcg_gen_exit_tb(dc->base.tb, n);
474 } else {
475 tcg_gen_movi_tl(env_pc, dest);
476 tcg_gen_lookup_and_goto_ptr();
477 }
478 }
479
480 static inline void cris_clear_x_flag(DisasContext *dc)
481 {
482 if (dc->flags_x) {
483 dc->flags_uptodate = 0;
484 }
485 dc->flags_x = 0;
486 }
487
488 static void cris_flush_cc_state(DisasContext *dc)
489 {
490 if (dc->cc_size_uptodate != dc->cc_size) {
491 tcg_gen_movi_tl(cc_size, dc->cc_size);
492 dc->cc_size_uptodate = dc->cc_size;
493 }
494 tcg_gen_movi_tl(cc_op, dc->cc_op);
495 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
496 }
497
498 static void cris_evaluate_flags(DisasContext *dc)
499 {
500 if (dc->flags_uptodate) {
501 return;
502 }
503
504 cris_flush_cc_state(dc);
505
506 switch (dc->cc_op) {
507 case CC_OP_MCP:
508 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], tcg_env,
509 cpu_PR[PR_CCS], cc_src,
510 cc_dest, cc_result);
511 break;
512 case CC_OP_MULS:
513 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], tcg_env,
514 cpu_PR[PR_CCS], cc_result,
515 cpu_PR[PR_MOF]);
516 break;
517 case CC_OP_MULU:
518 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], tcg_env,
519 cpu_PR[PR_CCS], cc_result,
520 cpu_PR[PR_MOF]);
521 break;
522 case CC_OP_MOVE:
523 case CC_OP_AND:
524 case CC_OP_OR:
525 case CC_OP_XOR:
526 case CC_OP_ASR:
527 case CC_OP_LSR:
528 case CC_OP_LSL:
529 switch (dc->cc_size) {
530 case 4:
531 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
532 tcg_env, cpu_PR[PR_CCS], cc_result);
533 break;
534 case 2:
535 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
536 tcg_env, cpu_PR[PR_CCS], cc_result);
537 break;
538 default:
539 gen_helper_evaluate_flags(tcg_env);
540 break;
541 }
542 break;
543 case CC_OP_FLAGS:
544 /* live. */
545 break;
546 case CC_OP_SUB:
547 case CC_OP_CMP:
548 if (dc->cc_size == 4) {
549 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], tcg_env,
550 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
551 } else {
552 gen_helper_evaluate_flags(tcg_env);
553 }
554
555 break;
556 default:
557 switch (dc->cc_size) {
558 case 4:
559 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], tcg_env,
560 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
561 break;
562 default:
563 gen_helper_evaluate_flags(tcg_env);
564 break;
565 }
566 break;
567 }
568
569 if (dc->flags_x) {
570 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
571 } else if (dc->cc_op == CC_OP_FLAGS) {
572 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
573 }
574 dc->flags_uptodate = 1;
575 }
576
577 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
578 {
579 uint32_t ovl;
580
581 if (!mask) {
582 dc->update_cc = 0;
583 return;
584 }
585
586 /* Check if we need to evaluate the condition codes due to
587 CC overlaying. */
588 ovl = (dc->cc_mask ^ mask) & ~mask;
589 if (ovl) {
590 /* TODO: optimize this case. It trigs all the time. */
591 cris_evaluate_flags(dc);
592 }
593 dc->cc_mask = mask;
594 dc->update_cc = 1;
595 }
596
597 static void cris_update_cc_op(DisasContext *dc, int op, int size)
598 {
599 dc->cc_op = op;
600 dc->cc_size = size;
601 dc->flags_uptodate = 0;
602 }
603
604 static inline void cris_update_cc_x(DisasContext *dc)
605 {
606 /* Save the x flag state at the time of the cc snapshot. */
607 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
608 return;
609 }
610 tcg_gen_movi_tl(cc_x, dc->flags_x);
611 dc->cc_x_uptodate = 2 | dc->flags_x;
612 }
613
614 /* Update cc prior to executing ALU op. Needs source operands untouched. */
615 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
616 TCGv dst, TCGv src, int size)
617 {
618 if (dc->update_cc) {
619 cris_update_cc_op(dc, op, size);
620 tcg_gen_mov_tl(cc_src, src);
621
622 if (op != CC_OP_MOVE
623 && op != CC_OP_AND
624 && op != CC_OP_OR
625 && op != CC_OP_XOR
626 && op != CC_OP_ASR
627 && op != CC_OP_LSR
628 && op != CC_OP_LSL) {
629 tcg_gen_mov_tl(cc_dest, dst);
630 }
631
632 cris_update_cc_x(dc);
633 }
634 }
635
636 /* Update cc after executing ALU op. needs the result. */
637 static inline void cris_update_result(DisasContext *dc, TCGv res)
638 {
639 if (dc->update_cc) {
640 tcg_gen_mov_tl(cc_result, res);
641 }
642 }
643
644 /* Returns one if the write back stage should execute. */
645 static void cris_alu_op_exec(DisasContext *dc, int op,
646 TCGv dst, TCGv a, TCGv b, int size)
647 {
648 /* Emit the ALU insns. */
649 switch (op) {
650 case CC_OP_ADD:
651 tcg_gen_add_tl(dst, a, b);
652 /* Extended arithmetic. */
653 t_gen_addx_carry(dc, dst);
654 break;
655 case CC_OP_ADDC:
656 tcg_gen_add_tl(dst, a, b);
657 t_gen_add_flag(dst, 0); /* C_FLAG. */
658 break;
659 case CC_OP_MCP:
660 tcg_gen_add_tl(dst, a, b);
661 t_gen_add_flag(dst, 8); /* R_FLAG. */
662 break;
663 case CC_OP_SUB:
664 tcg_gen_sub_tl(dst, a, b);
665 /* Extended arithmetic. */
666 t_gen_subx_carry(dc, dst);
667 break;
668 case CC_OP_MOVE:
669 tcg_gen_mov_tl(dst, b);
670 break;
671 case CC_OP_OR:
672 tcg_gen_or_tl(dst, a, b);
673 break;
674 case CC_OP_AND:
675 tcg_gen_and_tl(dst, a, b);
676 break;
677 case CC_OP_XOR:
678 tcg_gen_xor_tl(dst, a, b);
679 break;
680 case CC_OP_LSL:
681 t_gen_lsl(dst, a, b);
682 break;
683 case CC_OP_LSR:
684 t_gen_lsr(dst, a, b);
685 break;
686 case CC_OP_ASR:
687 t_gen_asr(dst, a, b);
688 break;
689 case CC_OP_NEG:
690 tcg_gen_neg_tl(dst, b);
691 /* Extended arithmetic. */
692 t_gen_subx_carry(dc, dst);
693 break;
694 case CC_OP_LZ:
695 tcg_gen_clzi_tl(dst, b, TARGET_LONG_BITS);
696 break;
697 case CC_OP_MULS:
698 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
699 break;
700 case CC_OP_MULU:
701 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
702 break;
703 case CC_OP_DSTEP:
704 t_gen_cris_dstep(dst, a, b);
705 break;
706 case CC_OP_MSTEP:
707 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
708 break;
709 case CC_OP_BOUND:
710 tcg_gen_movcond_tl(TCG_COND_LEU, dst, a, b, a, b);
711 break;
712 case CC_OP_CMP:
713 tcg_gen_sub_tl(dst, a, b);
714 /* Extended arithmetic. */
715 t_gen_subx_carry(dc, dst);
716 break;
717 default:
718 qemu_log_mask(LOG_GUEST_ERROR, "illegal ALU op.\n");
719 BUG();
720 break;
721 }
722
723 if (size == 1) {
724 tcg_gen_andi_tl(dst, dst, 0xff);
725 } else if (size == 2) {
726 tcg_gen_andi_tl(dst, dst, 0xffff);
727 }
728 }
729
730 static void cris_alu(DisasContext *dc, int op,
731 TCGv d, TCGv op_a, TCGv op_b, int size)
732 {
733 TCGv tmp;
734 int writeback;
735
736 writeback = 1;
737
738 if (op == CC_OP_CMP) {
739 tmp = tcg_temp_new();
740 writeback = 0;
741 } else if (size == 4) {
742 tmp = d;
743 writeback = 0;
744 } else {
745 tmp = tcg_temp_new();
746 }
747
748
749 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
750 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
751 cris_update_result(dc, tmp);
752
753 /* Writeback. */
754 if (writeback) {
755 if (size == 1) {
756 tcg_gen_andi_tl(d, d, ~0xff);
757 } else {
758 tcg_gen_andi_tl(d, d, ~0xffff);
759 }
760 tcg_gen_or_tl(d, d, tmp);
761 }
762 }
763
764 static int arith_cc(DisasContext *dc)
765 {
766 if (dc->update_cc) {
767 switch (dc->cc_op) {
768 case CC_OP_ADDC: return 1;
769 case CC_OP_ADD: return 1;
770 case CC_OP_SUB: return 1;
771 case CC_OP_DSTEP: return 1;
772 case CC_OP_LSL: return 1;
773 case CC_OP_LSR: return 1;
774 case CC_OP_ASR: return 1;
775 case CC_OP_CMP: return 1;
776 case CC_OP_NEG: return 1;
777 case CC_OP_OR: return 1;
778 case CC_OP_AND: return 1;
779 case CC_OP_XOR: return 1;
780 case CC_OP_MULU: return 1;
781 case CC_OP_MULS: return 1;
782 default:
783 return 0;
784 }
785 }
786 return 0;
787 }
788
789 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
790 {
791 int arith_opt, move_opt;
792
793 /* TODO: optimize more condition codes. */
794
795 /*
796 * If the flags are live, we've gotta look into the bits of CCS.
797 * Otherwise, if we just did an arithmetic operation we try to
798 * evaluate the condition code faster.
799 *
800 * When this function is done, T0 should be non-zero if the condition
801 * code is true.
802 */
803 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
804 move_opt = (dc->cc_op == CC_OP_MOVE);
805 switch (cond) {
806 case CC_EQ:
807 if ((arith_opt || move_opt)
808 && dc->cc_x_uptodate != (2 | X_FLAG)) {
809 tcg_gen_setcondi_tl(TCG_COND_EQ, cc, cc_result, 0);
810 } else {
811 cris_evaluate_flags(dc);
812 tcg_gen_andi_tl(cc,
813 cpu_PR[PR_CCS], Z_FLAG);
814 }
815 break;
816 case CC_NE:
817 if ((arith_opt || move_opt)
818 && dc->cc_x_uptodate != (2 | X_FLAG)) {
819 tcg_gen_mov_tl(cc, cc_result);
820 } else {
821 cris_evaluate_flags(dc);
822 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
823 Z_FLAG);
824 tcg_gen_andi_tl(cc, cc, Z_FLAG);
825 }
826 break;
827 case CC_CS:
828 cris_evaluate_flags(dc);
829 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
830 break;
831 case CC_CC:
832 cris_evaluate_flags(dc);
833 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
834 tcg_gen_andi_tl(cc, cc, C_FLAG);
835 break;
836 case CC_VS:
837 cris_evaluate_flags(dc);
838 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
839 break;
840 case CC_VC:
841 cris_evaluate_flags(dc);
842 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
843 V_FLAG);
844 tcg_gen_andi_tl(cc, cc, V_FLAG);
845 break;
846 case CC_PL:
847 if (arith_opt || move_opt) {
848 int bits = 31;
849
850 if (dc->cc_size == 1) {
851 bits = 7;
852 } else if (dc->cc_size == 2) {
853 bits = 15;
854 }
855
856 tcg_gen_shri_tl(cc, cc_result, bits);
857 tcg_gen_xori_tl(cc, cc, 1);
858 } else {
859 cris_evaluate_flags(dc);
860 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
861 N_FLAG);
862 tcg_gen_andi_tl(cc, cc, N_FLAG);
863 }
864 break;
865 case CC_MI:
866 if (arith_opt || move_opt) {
867 int bits = 31;
868
869 if (dc->cc_size == 1) {
870 bits = 7;
871 } else if (dc->cc_size == 2) {
872 bits = 15;
873 }
874
875 tcg_gen_shri_tl(cc, cc_result, bits);
876 tcg_gen_andi_tl(cc, cc, 1);
877 } else {
878 cris_evaluate_flags(dc);
879 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
880 N_FLAG);
881 }
882 break;
883 case CC_LS:
884 cris_evaluate_flags(dc);
885 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
886 C_FLAG | Z_FLAG);
887 break;
888 case CC_HI:
889 cris_evaluate_flags(dc);
890 {
891 TCGv tmp;
892
893 tmp = tcg_temp_new();
894 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
895 C_FLAG | Z_FLAG);
896 /* Overlay the C flag on top of the Z. */
897 tcg_gen_shli_tl(cc, tmp, 2);
898 tcg_gen_and_tl(cc, tmp, cc);
899 tcg_gen_andi_tl(cc, cc, Z_FLAG);
900 }
901 break;
902 case CC_GE:
903 cris_evaluate_flags(dc);
904 /* Overlay the V flag on top of the N. */
905 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
906 tcg_gen_xor_tl(cc,
907 cpu_PR[PR_CCS], cc);
908 tcg_gen_andi_tl(cc, cc, N_FLAG);
909 tcg_gen_xori_tl(cc, cc, N_FLAG);
910 break;
911 case CC_LT:
912 cris_evaluate_flags(dc);
913 /* Overlay the V flag on top of the N. */
914 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
915 tcg_gen_xor_tl(cc,
916 cpu_PR[PR_CCS], cc);
917 tcg_gen_andi_tl(cc, cc, N_FLAG);
918 break;
919 case CC_GT:
920 cris_evaluate_flags(dc);
921 {
922 TCGv n, z;
923
924 n = tcg_temp_new();
925 z = tcg_temp_new();
926
927 /* To avoid a shift we overlay everything on
928 the V flag. */
929 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
930 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
931 /* invert Z. */
932 tcg_gen_xori_tl(z, z, 2);
933
934 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
935 tcg_gen_xori_tl(n, n, 2);
936 tcg_gen_and_tl(cc, z, n);
937 tcg_gen_andi_tl(cc, cc, 2);
938 }
939 break;
940 case CC_LE:
941 cris_evaluate_flags(dc);
942 {
943 TCGv n, z;
944
945 n = tcg_temp_new();
946 z = tcg_temp_new();
947
948 /* To avoid a shift we overlay everything on
949 the V flag. */
950 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
951 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
952
953 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
954 tcg_gen_or_tl(cc, z, n);
955 tcg_gen_andi_tl(cc, cc, 2);
956 }
957 break;
958 case CC_P:
959 cris_evaluate_flags(dc);
960 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
961 break;
962 case CC_A:
963 tcg_gen_movi_tl(cc, 1);
964 break;
965 default:
966 BUG();
967 break;
968 };
969 }
970
971 static void cris_store_direct_jmp(DisasContext *dc)
972 {
973 /* Store the direct jmp state into the cpu-state. */
974 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
975 if (dc->jmp == JMP_DIRECT) {
976 tcg_gen_movi_tl(env_btaken, 1);
977 }
978 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
979 dc->jmp = JMP_INDIRECT;
980 }
981 }
982
983 static void cris_prepare_cc_branch (DisasContext *dc,
984 int offset, int cond)
985 {
986 /* This helps us re-schedule the micro-code to insns in delay-slots
987 before the actual jump. */
988 dc->delayed_branch = 2;
989 dc->jmp = JMP_DIRECT_CC;
990 dc->jmp_pc = dc->pc + offset;
991
992 gen_tst_cc(dc, env_btaken, cond);
993 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
994 }
995
996
997 /* jumps, when the dest is in a live reg for example. Direct should be set
998 when the dest addr is constant to allow tb chaining. */
999 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1000 {
1001 /* This helps us re-schedule the micro-code to insns in delay-slots
1002 before the actual jump. */
1003 dc->delayed_branch = 2;
1004 dc->jmp = type;
1005 if (type == JMP_INDIRECT) {
1006 tcg_gen_movi_tl(env_btaken, 1);
1007 }
1008 }
1009
1010 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1011 {
1012 /* If we get a fault on a delayslot we must keep the jmp state in
1013 the cpu-state to be able to re-execute the jmp. */
1014 if (dc->delayed_branch == 1) {
1015 cris_store_direct_jmp(dc);
1016 }
1017
1018 tcg_gen_qemu_ld_i64(dst, addr, dc->mem_index, MO_TEUQ);
1019 }
1020
1021 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1022 unsigned int size, int sign)
1023 {
1024 /* If we get a fault on a delayslot we must keep the jmp state in
1025 the cpu-state to be able to re-execute the jmp. */
1026 if (dc->delayed_branch == 1) {
1027 cris_store_direct_jmp(dc);
1028 }
1029
1030 tcg_gen_qemu_ld_tl(dst, addr, dc->mem_index,
1031 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1032 }
1033
1034 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1035 unsigned int size)
1036 {
1037 /* If we get a fault on a delayslot we must keep the jmp state in
1038 the cpu-state to be able to re-execute the jmp. */
1039 if (dc->delayed_branch == 1) {
1040 cris_store_direct_jmp(dc);
1041 }
1042
1043
1044 /* Conditional writes. We only support the kind were X and P are known
1045 at translation time. */
1046 if (dc->flags_x && (dc->tb_flags & P_FLAG)) {
1047 dc->postinc = 0;
1048 cris_evaluate_flags(dc);
1049 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1050 return;
1051 }
1052
1053 tcg_gen_qemu_st_tl(val, addr, dc->mem_index, MO_TE + ctz32(size));
1054
1055 if (dc->flags_x) {
1056 cris_evaluate_flags(dc);
1057 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1058 }
1059 }
1060
1061 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1062 {
1063 if (size == 1) {
1064 tcg_gen_ext8s_i32(d, s);
1065 } else if (size == 2) {
1066 tcg_gen_ext16s_i32(d, s);
1067 } else {
1068 tcg_gen_mov_tl(d, s);
1069 }
1070 }
1071
1072 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1073 {
1074 if (size == 1) {
1075 tcg_gen_ext8u_i32(d, s);
1076 } else if (size == 2) {
1077 tcg_gen_ext16u_i32(d, s);
1078 } else {
1079 tcg_gen_mov_tl(d, s);
1080 }
1081 }
1082
1083 #if DISAS_CRIS
1084 static char memsize_char(int size)
1085 {
1086 switch (size) {
1087 case 1: return 'b';
1088 case 2: return 'w';
1089 case 4: return 'd';
1090 default:
1091 return 'x';
1092 }
1093 }
1094 #endif
1095
1096 static inline unsigned int memsize_z(DisasContext *dc)
1097 {
1098 return dc->zsize + 1;
1099 }
1100
1101 static inline unsigned int memsize_zz(DisasContext *dc)
1102 {
1103 switch (dc->zzsize) {
1104 case 0: return 1;
1105 case 1: return 2;
1106 default:
1107 return 4;
1108 }
1109 }
1110
1111 static inline void do_postinc (DisasContext *dc, int size)
1112 {
1113 if (dc->postinc) {
1114 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1115 }
1116 }
1117
1118 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1119 int size, int s_ext, TCGv dst)
1120 {
1121 if (s_ext) {
1122 t_gen_sext(dst, cpu_R[rs], size);
1123 } else {
1124 t_gen_zext(dst, cpu_R[rs], size);
1125 }
1126 }
1127
1128 /* Prepare T0 and T1 for a register alu operation.
1129 s_ext decides if the operand1 should be sign-extended or zero-extended when
1130 needed. */
1131 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1132 int size, int s_ext, TCGv dst, TCGv src)
1133 {
1134 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1135
1136 if (s_ext) {
1137 t_gen_sext(dst, cpu_R[rd], size);
1138 } else {
1139 t_gen_zext(dst, cpu_R[rd], size);
1140 }
1141 }
1142
1143 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1144 int s_ext, int memsize, TCGv dst)
1145 {
1146 unsigned int rs;
1147 uint32_t imm;
1148 int is_imm;
1149 int insn_len = 2;
1150
1151 rs = dc->op1;
1152 is_imm = rs == 15 && dc->postinc;
1153
1154 /* Load [$rs] onto T1. */
1155 if (is_imm) {
1156 insn_len = 2 + memsize;
1157 if (memsize == 1) {
1158 insn_len++;
1159 }
1160
1161 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1162 tcg_gen_movi_tl(dst, imm);
1163 dc->postinc = 0;
1164 } else {
1165 cris_flush_cc_state(dc);
1166 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1167 if (s_ext) {
1168 t_gen_sext(dst, dst, memsize);
1169 } else {
1170 t_gen_zext(dst, dst, memsize);
1171 }
1172 }
1173 return insn_len;
1174 }
1175
1176 /* Prepare T0 and T1 for a memory + alu operation.
1177 s_ext decides if the operand1 should be sign-extended or zero-extended when
1178 needed. */
1179 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1180 int s_ext, int memsize, TCGv dst, TCGv src)
1181 {
1182 int insn_len;
1183
1184 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1185 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1186 return insn_len;
1187 }
1188
1189 #if DISAS_CRIS
1190 static const char *cc_name(int cc)
1191 {
1192 static const char * const cc_names[16] = {
1193 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1194 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1195 };
1196 assert(cc < 16);
1197 return cc_names[cc];
1198 }
1199 #endif
1200
1201 /* Start of insn decoders. */
1202
1203 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1204 {
1205 int32_t offset;
1206 int sign;
1207 uint32_t cond = dc->op2;
1208
1209 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1210 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1211
1212 offset *= 2;
1213 offset |= sign << 8;
1214 offset = sign_extend(offset, 8);
1215
1216 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1217
1218 /* op2 holds the condition-code. */
1219 cris_cc_mask(dc, 0);
1220 cris_prepare_cc_branch(dc, offset, cond);
1221 return 2;
1222 }
1223 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1224 {
1225 int32_t imm;
1226
1227 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1228 imm = sign_extend(dc->op1, 7);
1229
1230 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1231 cris_cc_mask(dc, 0);
1232 /* Fetch register operand, */
1233 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1234
1235 return 2;
1236 }
1237 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1238 {
1239 TCGv c;
1240 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1241
1242 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1243
1244 cris_cc_mask(dc, CC_MASK_NZVC);
1245
1246 c = tcg_constant_tl(dc->op1);
1247 cris_alu(dc, CC_OP_ADD,
1248 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1249 return 2;
1250 }
1251 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1252 {
1253 uint32_t imm;
1254
1255 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1256 imm = sign_extend(dc->op1, 5);
1257 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1258
1259 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1260 return 2;
1261 }
1262 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1263 {
1264 TCGv c;
1265 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1266
1267 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1268
1269 cris_cc_mask(dc, CC_MASK_NZVC);
1270 c = tcg_constant_tl(dc->op1);
1271 cris_alu(dc, CC_OP_SUB,
1272 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1273 return 2;
1274 }
1275 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1276 {
1277 uint32_t imm;
1278 TCGv c;
1279 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1280 imm = sign_extend(dc->op1, 5);
1281
1282 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1283 cris_cc_mask(dc, CC_MASK_NZVC);
1284
1285 c = tcg_constant_tl(imm);
1286 cris_alu(dc, CC_OP_CMP,
1287 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1288 return 2;
1289 }
1290 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1291 {
1292 uint32_t imm;
1293 TCGv c;
1294 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1295 imm = sign_extend(dc->op1, 5);
1296
1297 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1298 cris_cc_mask(dc, CC_MASK_NZ);
1299
1300 c = tcg_constant_tl(imm);
1301 cris_alu(dc, CC_OP_AND,
1302 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1303 return 2;
1304 }
1305 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1306 {
1307 uint32_t imm;
1308 TCGv c;
1309 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1310 imm = sign_extend(dc->op1, 5);
1311 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1312 cris_cc_mask(dc, CC_MASK_NZ);
1313
1314 c = tcg_constant_tl(imm);
1315 cris_alu(dc, CC_OP_OR,
1316 cpu_R[dc->op2], cpu_R[dc->op2], c, 4);
1317 return 2;
1318 }
1319 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1320 {
1321 TCGv c;
1322 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1323 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1324
1325 cris_cc_mask(dc, CC_MASK_NZ);
1326 c = tcg_constant_tl(dc->op1);
1327 cris_evaluate_flags(dc);
1328 gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2],
1329 c, cpu_PR[PR_CCS]);
1330 cris_alu(dc, CC_OP_MOVE,
1331 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1332 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1333 dc->flags_uptodate = 1;
1334 return 2;
1335 }
1336 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1337 {
1338 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1339 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1340 cris_cc_mask(dc, CC_MASK_NZ);
1341
1342 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1343 cris_alu(dc, CC_OP_MOVE,
1344 cpu_R[dc->op2],
1345 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1346 return 2;
1347 }
1348 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1349 {
1350 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1351 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1352
1353 cris_cc_mask(dc, CC_MASK_NZ);
1354
1355 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1356
1357 cris_alu(dc, CC_OP_MOVE,
1358 cpu_R[dc->op2],
1359 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1360 return 2;
1361 }
1362 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1363 {
1364 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1365 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1366
1367 cris_cc_mask(dc, CC_MASK_NZ);
1368
1369 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1370 cris_alu(dc, CC_OP_MOVE,
1371 cpu_R[dc->op2],
1372 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1373 return 2;
1374 }
1375
1376 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1377 {
1378 int size = memsize_zz(dc);
1379
1380 LOG_DIS("move.%c $r%u, $r%u\n",
1381 memsize_char(size), dc->op1, dc->op2);
1382
1383 cris_cc_mask(dc, CC_MASK_NZ);
1384 if (size == 4) {
1385 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1386 cris_cc_mask(dc, CC_MASK_NZ);
1387 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1388 cris_update_cc_x(dc);
1389 cris_update_result(dc, cpu_R[dc->op2]);
1390 } else {
1391 TCGv t0;
1392
1393 t0 = tcg_temp_new();
1394 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1395 cris_alu(dc, CC_OP_MOVE,
1396 cpu_R[dc->op2],
1397 cpu_R[dc->op2], t0, size);
1398 }
1399 return 2;
1400 }
1401
1402 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1403 {
1404 int cond = dc->op2;
1405
1406 LOG_DIS("s%s $r%u\n",
1407 cc_name(cond), dc->op1);
1408
1409 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1410 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_R[dc->op1], cpu_R[dc->op1], 0);
1411
1412 cris_cc_mask(dc, 0);
1413 return 2;
1414 }
1415
1416 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1417 {
1418 if (size == 4) {
1419 t[0] = cpu_R[dc->op2];
1420 t[1] = cpu_R[dc->op1];
1421 } else {
1422 t[0] = tcg_temp_new();
1423 t[1] = tcg_temp_new();
1424 }
1425 }
1426
1427 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1428 {
1429 TCGv t[2];
1430 int size = memsize_zz(dc);
1431
1432 LOG_DIS("and.%c $r%u, $r%u\n",
1433 memsize_char(size), dc->op1, dc->op2);
1434
1435 cris_cc_mask(dc, CC_MASK_NZ);
1436
1437 cris_alu_alloc_temps(dc, size, t);
1438 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1439 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1440 return 2;
1441 }
1442
1443 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1444 {
1445 TCGv t0;
1446 LOG_DIS("lz $r%u, $r%u\n",
1447 dc->op1, dc->op2);
1448 cris_cc_mask(dc, CC_MASK_NZ);
1449 t0 = tcg_temp_new();
1450 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1451 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1452 return 2;
1453 }
1454
1455 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1456 {
1457 TCGv t[2];
1458 int size = memsize_zz(dc);
1459
1460 LOG_DIS("lsl.%c $r%u, $r%u\n",
1461 memsize_char(size), dc->op1, dc->op2);
1462
1463 cris_cc_mask(dc, CC_MASK_NZ);
1464 cris_alu_alloc_temps(dc, size, t);
1465 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1466 tcg_gen_andi_tl(t[1], t[1], 63);
1467 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1468 return 2;
1469 }
1470
1471 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1472 {
1473 TCGv t[2];
1474 int size = memsize_zz(dc);
1475
1476 LOG_DIS("lsr.%c $r%u, $r%u\n",
1477 memsize_char(size), dc->op1, dc->op2);
1478
1479 cris_cc_mask(dc, CC_MASK_NZ);
1480 cris_alu_alloc_temps(dc, size, t);
1481 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1482 tcg_gen_andi_tl(t[1], t[1], 63);
1483 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1484 return 2;
1485 }
1486
1487 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1488 {
1489 TCGv t[2];
1490 int size = memsize_zz(dc);
1491
1492 LOG_DIS("asr.%c $r%u, $r%u\n",
1493 memsize_char(size), dc->op1, dc->op2);
1494
1495 cris_cc_mask(dc, CC_MASK_NZ);
1496 cris_alu_alloc_temps(dc, size, t);
1497 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1498 tcg_gen_andi_tl(t[1], t[1], 63);
1499 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1500 return 2;
1501 }
1502
1503 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1504 {
1505 TCGv t[2];
1506 int size = memsize_zz(dc);
1507
1508 LOG_DIS("muls.%c $r%u, $r%u\n",
1509 memsize_char(size), dc->op1, dc->op2);
1510 cris_cc_mask(dc, CC_MASK_NZV);
1511 cris_alu_alloc_temps(dc, size, t);
1512 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1513
1514 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1515 return 2;
1516 }
1517
1518 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1519 {
1520 TCGv t[2];
1521 int size = memsize_zz(dc);
1522
1523 LOG_DIS("mulu.%c $r%u, $r%u\n",
1524 memsize_char(size), dc->op1, dc->op2);
1525 cris_cc_mask(dc, CC_MASK_NZV);
1526 cris_alu_alloc_temps(dc, size, t);
1527 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1528
1529 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1530 return 2;
1531 }
1532
1533
1534 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1535 {
1536 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1537 cris_cc_mask(dc, CC_MASK_NZ);
1538 cris_alu(dc, CC_OP_DSTEP,
1539 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1540 return 2;
1541 }
1542
1543 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1544 {
1545 TCGv t[2];
1546 int size = memsize_zz(dc);
1547 LOG_DIS("xor.%c $r%u, $r%u\n",
1548 memsize_char(size), dc->op1, dc->op2);
1549 BUG_ON(size != 4); /* xor is dword. */
1550 cris_cc_mask(dc, CC_MASK_NZ);
1551 cris_alu_alloc_temps(dc, size, t);
1552 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1553
1554 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1555 return 2;
1556 }
1557
1558 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1559 {
1560 TCGv l0;
1561 int size = memsize_zz(dc);
1562 LOG_DIS("bound.%c $r%u, $r%u\n",
1563 memsize_char(size), dc->op1, dc->op2);
1564 cris_cc_mask(dc, CC_MASK_NZ);
1565 l0 = tcg_temp_new();
1566 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1567 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1568 return 2;
1569 }
1570
1571 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1572 {
1573 TCGv t[2];
1574 int size = memsize_zz(dc);
1575 LOG_DIS("cmp.%c $r%u, $r%u\n",
1576 memsize_char(size), dc->op1, dc->op2);
1577 cris_cc_mask(dc, CC_MASK_NZVC);
1578 cris_alu_alloc_temps(dc, size, t);
1579 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1580
1581 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1582 return 2;
1583 }
1584
1585 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1586 {
1587 LOG_DIS("abs $r%u, $r%u\n",
1588 dc->op1, dc->op2);
1589 cris_cc_mask(dc, CC_MASK_NZ);
1590
1591 tcg_gen_abs_tl(cpu_R[dc->op2], cpu_R[dc->op1]);
1592 cris_alu(dc, CC_OP_MOVE,
1593 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1594 return 2;
1595 }
1596
1597 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1598 {
1599 TCGv t[2];
1600 int size = memsize_zz(dc);
1601 LOG_DIS("add.%c $r%u, $r%u\n",
1602 memsize_char(size), dc->op1, dc->op2);
1603 cris_cc_mask(dc, CC_MASK_NZVC);
1604 cris_alu_alloc_temps(dc, size, t);
1605 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1606
1607 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1608 return 2;
1609 }
1610
1611 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1612 {
1613 LOG_DIS("addc $r%u, $r%u\n",
1614 dc->op1, dc->op2);
1615 cris_evaluate_flags(dc);
1616
1617 /* Set for this insn. */
1618 dc->flags_x = X_FLAG;
1619
1620 cris_cc_mask(dc, CC_MASK_NZVC);
1621 cris_alu(dc, CC_OP_ADDC,
1622 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1623 return 2;
1624 }
1625
1626 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1627 {
1628 LOG_DIS("mcp $p%u, $r%u\n",
1629 dc->op2, dc->op1);
1630 cris_evaluate_flags(dc);
1631 cris_cc_mask(dc, CC_MASK_RNZV);
1632 cris_alu(dc, CC_OP_MCP,
1633 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1634 return 2;
1635 }
1636
1637 #if DISAS_CRIS
1638 static char * swapmode_name(int mode, char *modename) {
1639 int i = 0;
1640 if (mode & 8) {
1641 modename[i++] = 'n';
1642 }
1643 if (mode & 4) {
1644 modename[i++] = 'w';
1645 }
1646 if (mode & 2) {
1647 modename[i++] = 'b';
1648 }
1649 if (mode & 1) {
1650 modename[i++] = 'r';
1651 }
1652 modename[i++] = 0;
1653 return modename;
1654 }
1655 #endif
1656
1657 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1658 {
1659 TCGv t0;
1660 #if DISAS_CRIS
1661 char modename[4];
1662 #endif
1663 LOG_DIS("swap%s $r%u\n",
1664 swapmode_name(dc->op2, modename), dc->op1);
1665
1666 cris_cc_mask(dc, CC_MASK_NZ);
1667 t0 = tcg_temp_new();
1668 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
1669 if (dc->op2 & 8) {
1670 tcg_gen_not_tl(t0, t0);
1671 }
1672 if (dc->op2 & 4) {
1673 t_gen_swapw(t0, t0);
1674 }
1675 if (dc->op2 & 2) {
1676 t_gen_swapb(t0, t0);
1677 }
1678 if (dc->op2 & 1) {
1679 t_gen_swapr(t0, t0);
1680 }
1681 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1682 return 2;
1683 }
1684
1685 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1686 {
1687 TCGv t[2];
1688 int size = memsize_zz(dc);
1689 LOG_DIS("or.%c $r%u, $r%u\n",
1690 memsize_char(size), dc->op1, dc->op2);
1691 cris_cc_mask(dc, CC_MASK_NZ);
1692 cris_alu_alloc_temps(dc, size, t);
1693 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1694 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1695 return 2;
1696 }
1697
1698 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1699 {
1700 TCGv t0;
1701 LOG_DIS("addi.%c $r%u, $r%u\n",
1702 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1703 cris_cc_mask(dc, 0);
1704 t0 = tcg_temp_new();
1705 tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize);
1706 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1707 return 2;
1708 }
1709
1710 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1711 {
1712 TCGv t0;
1713 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1714 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1715 cris_cc_mask(dc, 0);
1716 t0 = tcg_temp_new();
1717 tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize);
1718 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1719 return 2;
1720 }
1721
1722 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1723 {
1724 TCGv t[2];
1725 int size = memsize_zz(dc);
1726 LOG_DIS("neg.%c $r%u, $r%u\n",
1727 memsize_char(size), dc->op1, dc->op2);
1728 cris_cc_mask(dc, CC_MASK_NZVC);
1729 cris_alu_alloc_temps(dc, size, t);
1730 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1731
1732 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1733 return 2;
1734 }
1735
1736 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1737 {
1738 LOG_DIS("btst $r%u, $r%u\n",
1739 dc->op1, dc->op2);
1740 cris_cc_mask(dc, CC_MASK_NZ);
1741 cris_evaluate_flags(dc);
1742 gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2],
1743 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1744 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1745 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1746 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1747 dc->flags_uptodate = 1;
1748 return 2;
1749 }
1750
1751 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1752 {
1753 TCGv t[2];
1754 int size = memsize_zz(dc);
1755 LOG_DIS("sub.%c $r%u, $r%u\n",
1756 memsize_char(size), dc->op1, dc->op2);
1757 cris_cc_mask(dc, CC_MASK_NZVC);
1758 cris_alu_alloc_temps(dc, size, t);
1759 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1760 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1761 return 2;
1762 }
1763
1764 /* Zero extension. From size to dword. */
1765 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1766 {
1767 TCGv t0;
1768 int size = memsize_z(dc);
1769 LOG_DIS("movu.%c $r%u, $r%u\n",
1770 memsize_char(size),
1771 dc->op1, dc->op2);
1772
1773 cris_cc_mask(dc, CC_MASK_NZ);
1774 t0 = tcg_temp_new();
1775 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1776 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1777 return 2;
1778 }
1779
1780 /* Sign extension. From size to dword. */
1781 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1782 {
1783 TCGv t0;
1784 int size = memsize_z(dc);
1785 LOG_DIS("movs.%c $r%u, $r%u\n",
1786 memsize_char(size),
1787 dc->op1, dc->op2);
1788
1789 cris_cc_mask(dc, CC_MASK_NZ);
1790 t0 = tcg_temp_new();
1791 /* Size can only be qi or hi. */
1792 t_gen_sext(t0, cpu_R[dc->op1], size);
1793 cris_alu(dc, CC_OP_MOVE,
1794 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1795 return 2;
1796 }
1797
1798 /* zero extension. From size to dword. */
1799 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1800 {
1801 TCGv t0;
1802 int size = memsize_z(dc);
1803 LOG_DIS("addu.%c $r%u, $r%u\n",
1804 memsize_char(size),
1805 dc->op1, dc->op2);
1806
1807 cris_cc_mask(dc, CC_MASK_NZVC);
1808 t0 = tcg_temp_new();
1809 /* Size can only be qi or hi. */
1810 t_gen_zext(t0, cpu_R[dc->op1], size);
1811 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1812 return 2;
1813 }
1814
1815 /* Sign extension. From size to dword. */
1816 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1817 {
1818 TCGv t0;
1819 int size = memsize_z(dc);
1820 LOG_DIS("adds.%c $r%u, $r%u\n",
1821 memsize_char(size),
1822 dc->op1, dc->op2);
1823
1824 cris_cc_mask(dc, CC_MASK_NZVC);
1825 t0 = tcg_temp_new();
1826 /* Size can only be qi or hi. */
1827 t_gen_sext(t0, cpu_R[dc->op1], size);
1828 cris_alu(dc, CC_OP_ADD,
1829 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1830 return 2;
1831 }
1832
1833 /* Zero extension. From size to dword. */
1834 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1835 {
1836 TCGv t0;
1837 int size = memsize_z(dc);
1838 LOG_DIS("subu.%c $r%u, $r%u\n",
1839 memsize_char(size),
1840 dc->op1, dc->op2);
1841
1842 cris_cc_mask(dc, CC_MASK_NZVC);
1843 t0 = tcg_temp_new();
1844 /* Size can only be qi or hi. */
1845 t_gen_zext(t0, cpu_R[dc->op1], size);
1846 cris_alu(dc, CC_OP_SUB,
1847 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1848 return 2;
1849 }
1850
1851 /* Sign extension. From size to dword. */
1852 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
1853 {
1854 TCGv t0;
1855 int size = memsize_z(dc);
1856 LOG_DIS("subs.%c $r%u, $r%u\n",
1857 memsize_char(size),
1858 dc->op1, dc->op2);
1859
1860 cris_cc_mask(dc, CC_MASK_NZVC);
1861 t0 = tcg_temp_new();
1862 /* Size can only be qi or hi. */
1863 t_gen_sext(t0, cpu_R[dc->op1], size);
1864 cris_alu(dc, CC_OP_SUB,
1865 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1866 return 2;
1867 }
1868
1869 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
1870 {
1871 uint32_t flags;
1872 int set = (~dc->opcode >> 2) & 1;
1873
1874
1875 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1876 | EXTRACT_FIELD(dc->ir, 0, 3);
1877 if (set && flags == 0) {
1878 LOG_DIS("nop\n");
1879 return 2;
1880 } else if (!set && (flags & 0x20)) {
1881 LOG_DIS("di\n");
1882 } else {
1883 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
1884 }
1885
1886 /* User space is not allowed to touch these. Silently ignore. */
1887 if (dc->tb_flags & U_FLAG) {
1888 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
1889 }
1890
1891 if (flags & X_FLAG) {
1892 if (set) {
1893 dc->flags_x = X_FLAG;
1894 } else {
1895 dc->flags_x = 0;
1896 }
1897 }
1898
1899 /* Break the TB if any of the SPI flag changes. */
1900 if (flags & (P_FLAG | S_FLAG)) {
1901 tcg_gen_movi_tl(env_pc, dc->pc + 2);
1902 dc->base.is_jmp = DISAS_UPDATE;
1903 dc->cpustate_changed = 1;
1904 }
1905
1906 /* For the I flag, only act on posedge. */
1907 if ((flags & I_FLAG)) {
1908 tcg_gen_movi_tl(env_pc, dc->pc + 2);
1909 dc->base.is_jmp = DISAS_UPDATE;
1910 dc->cpustate_changed = 1;
1911 }
1912
1913
1914 /* Simply decode the flags. */
1915 cris_evaluate_flags(dc);
1916 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1917 cris_update_cc_x(dc);
1918 tcg_gen_movi_tl(cc_op, dc->cc_op);
1919
1920 if (set) {
1921 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
1922 /* Enter user mode. */
1923 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
1924 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
1925 dc->cpustate_changed = 1;
1926 }
1927 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
1928 } else {
1929 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
1930 }
1931
1932 dc->flags_uptodate = 1;
1933 dc->clear_x = 0;
1934 return 2;
1935 }
1936
1937 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
1938 {
1939 TCGv c2, c1;
1940 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
1941 c1 = tcg_constant_tl(dc->op1);
1942 c2 = tcg_constant_tl(dc->op2);
1943 cris_cc_mask(dc, 0);
1944 gen_helper_movl_sreg_reg(tcg_env, c2, c1);
1945 return 2;
1946 }
1947 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
1948 {
1949 TCGv c2, c1;
1950 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
1951 c1 = tcg_constant_tl(dc->op1);
1952 c2 = tcg_constant_tl(dc->op2);
1953 cris_cc_mask(dc, 0);
1954 gen_helper_movl_reg_sreg(tcg_env, c1, c2);
1955 return 2;
1956 }
1957
1958 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
1959 {
1960 TCGv t[2];
1961 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
1962 cris_cc_mask(dc, 0);
1963
1964 t[0] = tcg_temp_new();
1965 if (dc->op2 == PR_CCS) {
1966 cris_evaluate_flags(dc);
1967 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
1968 if (dc->tb_flags & U_FLAG) {
1969 t[1] = tcg_temp_new();
1970 /* User space is not allowed to touch all flags. */
1971 tcg_gen_andi_tl(t[0], t[0], 0x39f);
1972 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
1973 tcg_gen_or_tl(t[0], t[1], t[0]);
1974 }
1975 } else {
1976 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
1977 }
1978
1979 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
1980 if (dc->op2 == PR_CCS) {
1981 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1982 dc->flags_uptodate = 1;
1983 }
1984 return 2;
1985 }
1986 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
1987 {
1988 TCGv t0;
1989 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
1990 cris_cc_mask(dc, 0);
1991
1992 if (dc->op2 == PR_CCS) {
1993 cris_evaluate_flags(dc);
1994 }
1995
1996 if (dc->op2 == PR_DZ) {
1997 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
1998 } else {
1999 t0 = tcg_temp_new();
2000 t_gen_mov_TN_preg(t0, dc->op2);
2001 cris_alu(dc, CC_OP_MOVE,
2002 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2003 preg_sizes[dc->op2]);
2004 }
2005 return 2;
2006 }
2007
2008 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2009 {
2010 int memsize = memsize_zz(dc);
2011 int insn_len;
2012 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2013 memsize_char(memsize),
2014 dc->op1, dc->postinc ? "+]" : "]",
2015 dc->op2);
2016
2017 if (memsize == 4) {
2018 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2019 cris_cc_mask(dc, CC_MASK_NZ);
2020 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2021 cris_update_cc_x(dc);
2022 cris_update_result(dc, cpu_R[dc->op2]);
2023 } else {
2024 TCGv t0;
2025
2026 t0 = tcg_temp_new();
2027 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2028 cris_cc_mask(dc, CC_MASK_NZ);
2029 cris_alu(dc, CC_OP_MOVE,
2030 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2031 }
2032 do_postinc(dc, memsize);
2033 return insn_len;
2034 }
2035
2036 static inline void cris_alu_m_alloc_temps(TCGv *t)
2037 {
2038 t[0] = tcg_temp_new();
2039 t[1] = tcg_temp_new();
2040 }
2041
2042 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2043 {
2044 TCGv t[2];
2045 int memsize = memsize_z(dc);
2046 int insn_len;
2047 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2048 memsize_char(memsize),
2049 dc->op1, dc->postinc ? "+]" : "]",
2050 dc->op2);
2051
2052 cris_alu_m_alloc_temps(t);
2053 /* sign extend. */
2054 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2055 cris_cc_mask(dc, CC_MASK_NZ);
2056 cris_alu(dc, CC_OP_MOVE,
2057 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2058 do_postinc(dc, memsize);
2059 return insn_len;
2060 }
2061
2062 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2063 {
2064 TCGv t[2];
2065 int memsize = memsize_z(dc);
2066 int insn_len;
2067 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2068 memsize_char(memsize),
2069 dc->op1, dc->postinc ? "+]" : "]",
2070 dc->op2);
2071
2072 cris_alu_m_alloc_temps(t);
2073 /* sign extend. */
2074 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2075 cris_cc_mask(dc, CC_MASK_NZVC);
2076 cris_alu(dc, CC_OP_ADD,
2077 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2078 do_postinc(dc, memsize);
2079 return insn_len;
2080 }
2081
2082 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2083 {
2084 TCGv t[2];
2085 int memsize = memsize_z(dc);
2086 int insn_len;
2087 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2088 memsize_char(memsize),
2089 dc->op1, dc->postinc ? "+]" : "]",
2090 dc->op2);
2091
2092 cris_alu_m_alloc_temps(t);
2093 /* sign extend. */
2094 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2095 cris_cc_mask(dc, CC_MASK_NZVC);
2096 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2097 do_postinc(dc, memsize);
2098 return insn_len;
2099 }
2100
2101 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2102 {
2103 TCGv t[2];
2104 int memsize = memsize_z(dc);
2105 int insn_len;
2106 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2107 memsize_char(memsize),
2108 dc->op1, dc->postinc ? "+]" : "]",
2109 dc->op2);
2110
2111 cris_alu_m_alloc_temps(t);
2112 /* sign extend. */
2113 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2114 cris_cc_mask(dc, CC_MASK_NZVC);
2115 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2116 do_postinc(dc, memsize);
2117 return insn_len;
2118 }
2119
2120 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2121 {
2122 TCGv t[2];
2123 int memsize = memsize_z(dc);
2124 int insn_len;
2125 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2126 memsize_char(memsize),
2127 dc->op1, dc->postinc ? "+]" : "]",
2128 dc->op2);
2129
2130 cris_alu_m_alloc_temps(t);
2131 /* sign extend. */
2132 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2133 cris_cc_mask(dc, CC_MASK_NZVC);
2134 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2135 do_postinc(dc, memsize);
2136 return insn_len;
2137 }
2138
2139 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2140 {
2141 TCGv t[2];
2142 int memsize = memsize_z(dc);
2143 int insn_len;
2144
2145 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2146 memsize_char(memsize),
2147 dc->op1, dc->postinc ? "+]" : "]",
2148 dc->op2);
2149
2150 cris_alu_m_alloc_temps(t);
2151 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2152 cris_cc_mask(dc, CC_MASK_NZ);
2153 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2154 do_postinc(dc, memsize);
2155 return insn_len;
2156 }
2157
2158 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2159 {
2160 TCGv t[2];
2161 int memsize = memsize_z(dc);
2162 int insn_len;
2163 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2164 memsize_char(memsize),
2165 dc->op1, dc->postinc ? "+]" : "]",
2166 dc->op2);
2167
2168 cris_alu_m_alloc_temps(t);
2169 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2170 cris_cc_mask(dc, CC_MASK_NZVC);
2171 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2172 do_postinc(dc, memsize);
2173 return insn_len;
2174 }
2175
2176 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2177 {
2178 TCGv t[2];
2179 int memsize = memsize_z(dc);
2180 int insn_len;
2181 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2182 memsize_char(memsize),
2183 dc->op1, dc->postinc ? "+]" : "]",
2184 dc->op2);
2185
2186 cris_alu_m_alloc_temps(t);
2187 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2188 cris_cc_mask(dc, CC_MASK_NZVC);
2189 cris_alu(dc, CC_OP_CMP,
2190 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2191 memsize_zz(dc));
2192 do_postinc(dc, memsize);
2193 return insn_len;
2194 }
2195
2196 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2197 {
2198 TCGv t[2];
2199 int memsize = memsize_zz(dc);
2200 int insn_len;
2201 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2202 memsize_char(memsize),
2203 dc->op1, dc->postinc ? "+]" : "]",
2204 dc->op2);
2205
2206 cris_alu_m_alloc_temps(t);
2207 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2208 cris_cc_mask(dc, CC_MASK_NZVC);
2209 cris_alu(dc, CC_OP_CMP,
2210 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2211 memsize_zz(dc));
2212 do_postinc(dc, memsize);
2213 return insn_len;
2214 }
2215
2216 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2217 {
2218 TCGv t[2], c;
2219 int memsize = memsize_zz(dc);
2220 int insn_len;
2221 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2222 memsize_char(memsize),
2223 dc->op1, dc->postinc ? "+]" : "]",
2224 dc->op2);
2225
2226 cris_evaluate_flags(dc);
2227
2228 cris_alu_m_alloc_temps(t);
2229 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2230 cris_cc_mask(dc, CC_MASK_NZ);
2231 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2232
2233 c = tcg_constant_tl(0);
2234 cris_alu(dc, CC_OP_CMP,
2235 cpu_R[dc->op2], t[1], c, memsize_zz(dc));
2236 do_postinc(dc, memsize);
2237 return insn_len;
2238 }
2239
2240 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2241 {
2242 TCGv t[2];
2243 int memsize = memsize_zz(dc);
2244 int insn_len;
2245 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2246 memsize_char(memsize),
2247 dc->op1, dc->postinc ? "+]" : "]",
2248 dc->op2);
2249
2250 cris_alu_m_alloc_temps(t);
2251 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2252 cris_cc_mask(dc, CC_MASK_NZ);
2253 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2254 do_postinc(dc, memsize);
2255 return insn_len;
2256 }
2257
2258 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2259 {
2260 TCGv t[2];
2261 int memsize = memsize_zz(dc);
2262 int insn_len;
2263 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2264 memsize_char(memsize),
2265 dc->op1, dc->postinc ? "+]" : "]",
2266 dc->op2);
2267
2268 cris_alu_m_alloc_temps(t);
2269 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2270 cris_cc_mask(dc, CC_MASK_NZVC);
2271 cris_alu(dc, CC_OP_ADD,
2272 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2273 do_postinc(dc, memsize);
2274 return insn_len;
2275 }
2276
2277 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2278 {
2279 TCGv t[2];
2280 int memsize = memsize_zz(dc);
2281 int insn_len;
2282 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2283 memsize_char(memsize),
2284 dc->op1, dc->postinc ? "+]" : "]",
2285 dc->op2);
2286
2287 cris_alu_m_alloc_temps(t);
2288 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2289 cris_cc_mask(dc, 0);
2290 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2291 do_postinc(dc, memsize);
2292 return insn_len;
2293 }
2294
2295 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2296 {
2297 TCGv l[2];
2298 int memsize = memsize_zz(dc);
2299 int insn_len;
2300 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2301 memsize_char(memsize),
2302 dc->op1, dc->postinc ? "+]" : "]",
2303 dc->op2);
2304
2305 l[0] = tcg_temp_new();
2306 l[1] = tcg_temp_new();
2307 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2308 cris_cc_mask(dc, CC_MASK_NZ);
2309 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2310 do_postinc(dc, memsize);
2311 return insn_len;
2312 }
2313
2314 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2315 {
2316 TCGv t[2];
2317 int insn_len = 2;
2318 LOG_DIS("addc [$r%u%s, $r%u\n",
2319 dc->op1, dc->postinc ? "+]" : "]",
2320 dc->op2);
2321
2322 cris_evaluate_flags(dc);
2323
2324 /* Set for this insn. */
2325 dc->flags_x = X_FLAG;
2326
2327 cris_alu_m_alloc_temps(t);
2328 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2329 cris_cc_mask(dc, CC_MASK_NZVC);
2330 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2331 do_postinc(dc, 4);
2332 return insn_len;
2333 }
2334
2335 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2336 {
2337 TCGv t[2];
2338 int memsize = memsize_zz(dc);
2339 int insn_len;
2340 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2341 memsize_char(memsize),
2342 dc->op1, dc->postinc ? "+]" : "]",
2343 dc->op2, dc->ir, dc->zzsize);
2344
2345 cris_alu_m_alloc_temps(t);
2346 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2347 cris_cc_mask(dc, CC_MASK_NZVC);
2348 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2349 do_postinc(dc, memsize);
2350 return insn_len;
2351 }
2352
2353 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2354 {
2355 TCGv t[2];
2356 int memsize = memsize_zz(dc);
2357 int insn_len;
2358 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2359 memsize_char(memsize),
2360 dc->op1, dc->postinc ? "+]" : "]",
2361 dc->op2, dc->pc);
2362
2363 cris_alu_m_alloc_temps(t);
2364 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2365 cris_cc_mask(dc, CC_MASK_NZ);
2366 cris_alu(dc, CC_OP_OR,
2367 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2368 do_postinc(dc, memsize);
2369 return insn_len;
2370 }
2371
2372 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2373 {
2374 TCGv t[2];
2375 int memsize = memsize_zz(dc);
2376 int insn_len = 2;
2377
2378 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2379 memsize_char(memsize),
2380 dc->op1,
2381 dc->postinc ? "+]" : "]",
2382 dc->op2);
2383
2384 cris_alu_m_alloc_temps(t);
2385 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2386 cris_cc_mask(dc, 0);
2387 if (dc->op2 == PR_CCS) {
2388 cris_evaluate_flags(dc);
2389 if (dc->tb_flags & U_FLAG) {
2390 /* User space is not allowed to touch all flags. */
2391 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2392 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2393 tcg_gen_or_tl(t[1], t[0], t[1]);
2394 }
2395 }
2396
2397 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2398
2399 do_postinc(dc, memsize);
2400 return insn_len;
2401 }
2402
2403 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2404 {
2405 TCGv t0;
2406 int memsize;
2407
2408 memsize = preg_sizes[dc->op2];
2409
2410 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2411 memsize_char(memsize),
2412 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2413
2414 /* prepare store. Address in T0, value in T1. */
2415 if (dc->op2 == PR_CCS) {
2416 cris_evaluate_flags(dc);
2417 }
2418 t0 = tcg_temp_new();
2419 t_gen_mov_TN_preg(t0, dc->op2);
2420 cris_flush_cc_state(dc);
2421 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2422
2423 cris_cc_mask(dc, 0);
2424 if (dc->postinc) {
2425 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2426 }
2427 return 2;
2428 }
2429
2430 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2431 {
2432 TCGv_i64 tmp[16];
2433 TCGv tmp32;
2434 TCGv addr;
2435 int i;
2436 int nr = dc->op2 + 1;
2437
2438 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2439 dc->postinc ? "+]" : "]", dc->op2);
2440
2441 addr = tcg_temp_new();
2442 /* There are probably better ways of doing this. */
2443 cris_flush_cc_state(dc);
2444 for (i = 0; i < (nr >> 1); i++) {
2445 tmp[i] = tcg_temp_new_i64();
2446 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2447 gen_load64(dc, tmp[i], addr);
2448 }
2449 if (nr & 1) {
2450 tmp32 = tcg_temp_new_i32();
2451 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2452 gen_load(dc, tmp32, addr, 4, 0);
2453 } else {
2454 tmp32 = NULL;
2455 }
2456
2457 for (i = 0; i < (nr >> 1); i++) {
2458 tcg_gen_extrl_i64_i32(cpu_R[i * 2], tmp[i]);
2459 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2460 tcg_gen_extrl_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2461 }
2462 if (nr & 1) {
2463 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2464 }
2465
2466 /* writeback the updated pointer value. */
2467 if (dc->postinc) {
2468 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2469 }
2470
2471 /* gen_load might want to evaluate the previous insns flags. */
2472 cris_cc_mask(dc, 0);
2473 return 2;
2474 }
2475
2476 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2477 {
2478 TCGv tmp;
2479 TCGv addr;
2480 int i;
2481
2482 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2483 dc->postinc ? "+]" : "]");
2484
2485 cris_flush_cc_state(dc);
2486
2487 tmp = tcg_temp_new();
2488 addr = tcg_temp_new();
2489 tcg_gen_movi_tl(tmp, 4);
2490 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2491 for (i = 0; i <= dc->op2; i++) {
2492 /* Displace addr. */
2493 /* Perform the store. */
2494 gen_store(dc, addr, cpu_R[i], 4);
2495 tcg_gen_add_tl(addr, addr, tmp);
2496 }
2497 if (dc->postinc) {
2498 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2499 }
2500 cris_cc_mask(dc, 0);
2501 return 2;
2502 }
2503
2504 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2505 {
2506 int memsize;
2507
2508 memsize = memsize_zz(dc);
2509
2510 LOG_DIS("move.%c $r%u, [$r%u]\n",
2511 memsize_char(memsize), dc->op2, dc->op1);
2512
2513 /* prepare store. */
2514 cris_flush_cc_state(dc);
2515 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2516
2517 if (dc->postinc) {
2518 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2519 }
2520 cris_cc_mask(dc, 0);
2521 return 2;
2522 }
2523
2524 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2525 {
2526 LOG_DIS("lapcq %x, $r%u\n",
2527 dc->pc + dc->op1*2, dc->op2);
2528 cris_cc_mask(dc, 0);
2529 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2530 return 2;
2531 }
2532
2533 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2534 {
2535 unsigned int rd;
2536 int32_t imm;
2537 int32_t pc;
2538
2539 rd = dc->op2;
2540
2541 cris_cc_mask(dc, 0);
2542 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2543 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2544
2545 pc = dc->pc;
2546 pc += imm;
2547 tcg_gen_movi_tl(cpu_R[rd], pc);
2548 return 6;
2549 }
2550
2551 /* Jump to special reg. */
2552 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2553 {
2554 LOG_DIS("jump $p%u\n", dc->op2);
2555
2556 if (dc->op2 == PR_CCS) {
2557 cris_evaluate_flags(dc);
2558 }
2559 t_gen_mov_TN_preg(env_btarget, dc->op2);
2560 /* rete will often have low bit set to indicate delayslot. */
2561 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2562 cris_cc_mask(dc, 0);
2563 cris_prepare_jmp(dc, JMP_INDIRECT);
2564 return 2;
2565 }
2566
2567 /* Jump and save. */
2568 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2569 {
2570 TCGv c;
2571 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2572 cris_cc_mask(dc, 0);
2573 /* Store the return address in Pd. */
2574 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2575 if (dc->op2 > 15) {
2576 abort();
2577 }
2578 c = tcg_constant_tl(dc->pc + 4);
2579 t_gen_mov_preg_TN(dc, dc->op2, c);
2580
2581 cris_prepare_jmp(dc, JMP_INDIRECT);
2582 return 2;
2583 }
2584
2585 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2586 {
2587 uint32_t imm;
2588 TCGv c;
2589
2590 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2591
2592 LOG_DIS("jas 0x%x\n", imm);
2593 cris_cc_mask(dc, 0);
2594 c = tcg_constant_tl(dc->pc + 8);
2595 /* Store the return address in Pd. */
2596 t_gen_mov_preg_TN(dc, dc->op2, c);
2597
2598 dc->jmp_pc = imm;
2599 cris_prepare_jmp(dc, JMP_DIRECT);
2600 return 6;
2601 }
2602
2603 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2604 {
2605 uint32_t imm;
2606 TCGv c;
2607
2608 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2609
2610 LOG_DIS("jasc 0x%x\n", imm);
2611 cris_cc_mask(dc, 0);
2612 c = tcg_constant_tl(dc->pc + 8 + 4);
2613 /* Store the return address in Pd. */
2614 t_gen_mov_preg_TN(dc, dc->op2, c);
2615
2616 dc->jmp_pc = imm;
2617 cris_prepare_jmp(dc, JMP_DIRECT);
2618 return 6;
2619 }
2620
2621 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2622 {
2623 TCGv c;
2624 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2625 cris_cc_mask(dc, 0);
2626 /* Store the return address in Pd. */
2627 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2628 c = tcg_constant_tl(dc->pc + 4 + 4);
2629 t_gen_mov_preg_TN(dc, dc->op2, c);
2630 cris_prepare_jmp(dc, JMP_INDIRECT);
2631 return 2;
2632 }
2633
2634 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2635 {
2636 int32_t offset;
2637 uint32_t cond = dc->op2;
2638
2639 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2640
2641 LOG_DIS("b%s %d pc=%x dst=%x\n",
2642 cc_name(cond), offset,
2643 dc->pc, dc->pc + offset);
2644
2645 cris_cc_mask(dc, 0);
2646 /* op2 holds the condition-code. */
2647 cris_prepare_cc_branch(dc, offset, cond);
2648 return 4;
2649 }
2650
2651 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2652 {
2653 int32_t simm;
2654 TCGv c;
2655
2656 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2657
2658 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2659 cris_cc_mask(dc, 0);
2660 c = tcg_constant_tl(dc->pc + 8);
2661 /* Store the return address in Pd. */
2662 t_gen_mov_preg_TN(dc, dc->op2, c);
2663
2664 dc->jmp_pc = dc->pc + simm;
2665 cris_prepare_jmp(dc, JMP_DIRECT);
2666 return 6;
2667 }
2668
2669 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2670 {
2671 int32_t simm;
2672 TCGv c;
2673 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2674
2675 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2676 cris_cc_mask(dc, 0);
2677 c = tcg_constant_tl(dc->pc + 12);
2678 /* Store the return address in Pd. */
2679 t_gen_mov_preg_TN(dc, dc->op2, c);
2680
2681 dc->jmp_pc = dc->pc + simm;
2682 cris_prepare_jmp(dc, JMP_DIRECT);
2683 return 6;
2684 }
2685
2686 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2687 {
2688 cris_cc_mask(dc, 0);
2689
2690 if (dc->op2 == 15) {
2691 tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
2692 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2693 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2694 t_gen_raise_exception(EXCP_HLT);
2695 dc->base.is_jmp = DISAS_NORETURN;
2696 return 2;
2697 }
2698
2699 switch (dc->op2 & 7) {
2700 case 2:
2701 /* rfe. */
2702 LOG_DIS("rfe\n");
2703 cris_evaluate_flags(dc);
2704 gen_helper_rfe(tcg_env);
2705 dc->base.is_jmp = DISAS_UPDATE;
2706 dc->cpustate_changed = true;
2707 break;
2708 case 5:
2709 /* rfn. */
2710 LOG_DIS("rfn\n");
2711 cris_evaluate_flags(dc);
2712 gen_helper_rfn(tcg_env);
2713 dc->base.is_jmp = DISAS_UPDATE;
2714 dc->cpustate_changed = true;
2715 break;
2716 case 6:
2717 LOG_DIS("break %d\n", dc->op1);
2718 cris_evaluate_flags(dc);
2719 /* break. */
2720 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2721
2722 /* Breaks start at 16 in the exception vector. */
2723 t_gen_movi_env_TN(trap_vector, dc->op1 + 16);
2724 t_gen_raise_exception(EXCP_BREAK);
2725 dc->base.is_jmp = DISAS_NORETURN;
2726 break;
2727 default:
2728 printf("op2=%x\n", dc->op2);
2729 BUG();
2730 break;
2731
2732 }
2733 return 2;
2734 }
2735
2736 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2737 {
2738 return 2;
2739 }
2740
2741 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2742 {
2743 return 2;
2744 }
2745
2746 static int G_NORETURN dec_null(CPUCRISState *env, DisasContext *dc)
2747 {
2748 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2749 dc->pc, dc->opcode, dc->op1, dc->op2);
2750 fflush(NULL);
2751 BUG();
2752 }
2753
2754 static const struct decoder_info {
2755 struct {
2756 uint32_t bits;
2757 uint32_t mask;
2758 };
2759 int (*dec)(CPUCRISState *env, DisasContext *dc);
2760 } decinfo[] = {
2761 /* Order matters here. */
2762 {DEC_MOVEQ, dec_moveq},
2763 {DEC_BTSTQ, dec_btstq},
2764 {DEC_CMPQ, dec_cmpq},
2765 {DEC_ADDOQ, dec_addoq},
2766 {DEC_ADDQ, dec_addq},
2767 {DEC_SUBQ, dec_subq},
2768 {DEC_ANDQ, dec_andq},
2769 {DEC_ORQ, dec_orq},
2770 {DEC_ASRQ, dec_asrq},
2771 {DEC_LSLQ, dec_lslq},
2772 {DEC_LSRQ, dec_lsrq},
2773 {DEC_BCCQ, dec_bccq},
2774
2775 {DEC_BCC_IM, dec_bcc_im},
2776 {DEC_JAS_IM, dec_jas_im},
2777 {DEC_JAS_R, dec_jas_r},
2778 {DEC_JASC_IM, dec_jasc_im},
2779 {DEC_JASC_R, dec_jasc_r},
2780 {DEC_BAS_IM, dec_bas_im},
2781 {DEC_BASC_IM, dec_basc_im},
2782 {DEC_JUMP_P, dec_jump_p},
2783 {DEC_LAPC_IM, dec_lapc_im},
2784 {DEC_LAPCQ, dec_lapcq},
2785
2786 {DEC_RFE_ETC, dec_rfe_etc},
2787 {DEC_ADDC_MR, dec_addc_mr},
2788
2789 {DEC_MOVE_MP, dec_move_mp},
2790 {DEC_MOVE_PM, dec_move_pm},
2791 {DEC_MOVEM_MR, dec_movem_mr},
2792 {DEC_MOVEM_RM, dec_movem_rm},
2793 {DEC_MOVE_PR, dec_move_pr},
2794 {DEC_SCC_R, dec_scc_r},
2795 {DEC_SETF, dec_setclrf},
2796 {DEC_CLEARF, dec_setclrf},
2797
2798 {DEC_MOVE_SR, dec_move_sr},
2799 {DEC_MOVE_RP, dec_move_rp},
2800 {DEC_SWAP_R, dec_swap_r},
2801 {DEC_ABS_R, dec_abs_r},
2802 {DEC_LZ_R, dec_lz_r},
2803 {DEC_MOVE_RS, dec_move_rs},
2804 {DEC_BTST_R, dec_btst_r},
2805 {DEC_ADDC_R, dec_addc_r},
2806
2807 {DEC_DSTEP_R, dec_dstep_r},
2808 {DEC_XOR_R, dec_xor_r},
2809 {DEC_MCP_R, dec_mcp_r},
2810 {DEC_CMP_R, dec_cmp_r},
2811
2812 {DEC_ADDI_R, dec_addi_r},
2813 {DEC_ADDI_ACR, dec_addi_acr},
2814
2815 {DEC_ADD_R, dec_add_r},
2816 {DEC_SUB_R, dec_sub_r},
2817
2818 {DEC_ADDU_R, dec_addu_r},
2819 {DEC_ADDS_R, dec_adds_r},
2820 {DEC_SUBU_R, dec_subu_r},
2821 {DEC_SUBS_R, dec_subs_r},
2822 {DEC_LSL_R, dec_lsl_r},
2823
2824 {DEC_AND_R, dec_and_r},
2825 {DEC_OR_R, dec_or_r},
2826 {DEC_BOUND_R, dec_bound_r},
2827 {DEC_ASR_R, dec_asr_r},
2828 {DEC_LSR_R, dec_lsr_r},
2829
2830 {DEC_MOVU_R, dec_movu_r},
2831 {DEC_MOVS_R, dec_movs_r},
2832 {DEC_NEG_R, dec_neg_r},
2833 {DEC_MOVE_R, dec_move_r},
2834
2835 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2836 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2837
2838 {DEC_MULS_R, dec_muls_r},
2839 {DEC_MULU_R, dec_mulu_r},
2840
2841 {DEC_ADDU_M, dec_addu_m},
2842 {DEC_ADDS_M, dec_adds_m},
2843 {DEC_SUBU_M, dec_subu_m},
2844 {DEC_SUBS_M, dec_subs_m},
2845
2846 {DEC_CMPU_M, dec_cmpu_m},
2847 {DEC_CMPS_M, dec_cmps_m},
2848 {DEC_MOVU_M, dec_movu_m},
2849 {DEC_MOVS_M, dec_movs_m},
2850
2851 {DEC_CMP_M, dec_cmp_m},
2852 {DEC_ADDO_M, dec_addo_m},
2853 {DEC_BOUND_M, dec_bound_m},
2854 {DEC_ADD_M, dec_add_m},
2855 {DEC_SUB_M, dec_sub_m},
2856 {DEC_AND_M, dec_and_m},
2857 {DEC_OR_M, dec_or_m},
2858 {DEC_MOVE_RM, dec_move_rm},
2859 {DEC_TEST_M, dec_test_m},
2860 {DEC_MOVE_MR, dec_move_mr},
2861
2862 {{0, 0}, dec_null}
2863 };
2864
2865 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
2866 {
2867 int insn_len = 2;
2868 int i;
2869
2870 /* Load a halfword onto the instruction register. */
2871 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
2872
2873 /* Now decode it. */
2874 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2875 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2876 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2877 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2878 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2879 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2880
2881 /* Large switch for all insns. */
2882 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
2883 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
2884 insn_len = decinfo[i].dec(env, dc);
2885 break;
2886 }
2887 }
2888
2889 #if !defined(CONFIG_USER_ONLY)
2890 /* Single-stepping ? */
2891 if (dc->tb_flags & S_FLAG) {
2892 TCGLabel *l1 = gen_new_label();
2893 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
2894 /* We treat SPC as a break with an odd trap vector. */
2895 cris_evaluate_flags(dc);
2896 t_gen_movi_env_TN(trap_vector, 3);
2897 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
2898 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
2899 t_gen_raise_exception(EXCP_BREAK);
2900 gen_set_label(l1);
2901 }
2902 #endif
2903 return insn_len;
2904 }
2905
2906 #include "translate_v10.c.inc"
2907
2908 /*
2909 * Delay slots on QEMU/CRIS.
2910 *
2911 * If an exception hits on a delayslot, the core will let ERP (the Exception
2912 * Return Pointer) point to the branch (the previous) insn and set the lsb to
2913 * to give SW a hint that the exception actually hit on the dslot.
2914 *
2915 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
2916 * the core and any jmp to an odd addresses will mask off that lsb. It is
2917 * simply there to let sw know there was an exception on a dslot.
2918 *
2919 * When the software returns from an exception, the branch will re-execute.
2920 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
2921 * and the branch and delayslot don't share pages.
2922 *
2923 * The TB containing the branch insn will set up env->btarget and evaluate
2924 * env->btaken. When the translation loop exits we will note that the branch
2925 * sequence is broken and let env->dslot be the size of the branch insn (those
2926 * vary in length).
2927 *
2928 * The TB containing the delayslot will have the PC of its real insn (i.e no lsb
2929 * set). It will also expect to have env->dslot setup with the size of the
2930 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
2931 * will execute the dslot and take the branch, either to btarget or just one
2932 * insn ahead.
2933 *
2934 * When exceptions occur, we check for env->dslot in do_interrupt to detect
2935 * broken branch sequences and setup $erp accordingly (i.e let it point to the
2936 * branch and set lsb). Then env->dslot gets cleared so that the exception
2937 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
2938 * masked off and we will reexecute the branch insn.
2939 *
2940 */
2941
2942 static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
2943 {
2944 DisasContext *dc = container_of(dcbase, DisasContext, base);
2945 CPUCRISState *env = cpu_env(cs);
2946 uint32_t tb_flags = dc->base.tb->flags;
2947 uint32_t pc_start;
2948
2949 if (env->pregs[PR_VR] == 32) {
2950 dc->decoder = crisv32_decoder;
2951 dc->clear_locked_irq = 0;
2952 } else {
2953 dc->decoder = crisv10_decoder;
2954 dc->clear_locked_irq = 1;
2955 }
2956
2957 /*
2958 * Odd PC indicates that branch is rexecuting due to exception in the
2959 * delayslot, like in real hw.
2960 */
2961 pc_start = dc->base.pc_first & ~1;
2962 dc->base.pc_first = pc_start;
2963 dc->base.pc_next = pc_start;
2964
2965 dc->cpu = env_archcpu(env);
2966 dc->ppc = pc_start;
2967 dc->pc = pc_start;
2968 dc->mem_index = cpu_mmu_index(cs, false);
2969 dc->flags_uptodate = 1;
2970 dc->flags_x = tb_flags & X_FLAG;
2971 dc->cc_x_uptodate = 0;
2972 dc->cc_mask = 0;
2973 dc->update_cc = 0;
2974 dc->clear_prefix = 0;
2975 dc->cpustate_changed = 0;
2976
2977 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2978 dc->cc_size_uptodate = -1;
2979
2980 /* Decode TB flags. */
2981 dc->tb_flags = tb_flags & (S_FLAG | P_FLAG | U_FLAG | X_FLAG | PFIX_FLAG);
2982 dc->delayed_branch = !!(tb_flags & 7);
2983 if (dc->delayed_branch) {
2984 dc->jmp = JMP_INDIRECT;
2985 } else {
2986 dc->jmp = JMP_NOJMP;
2987 }
2988 }
2989
2990 static void cris_tr_tb_start(DisasContextBase *db, CPUState *cpu)
2991 {
2992 }
2993
2994 static void cris_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
2995 {
2996 DisasContext *dc = container_of(dcbase, DisasContext, base);
2997
2998 tcg_gen_insn_start(dc->delayed_branch == 1 ? dc->ppc | 1 : dc->pc);
2999 }
3000
3001 static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
3002 {
3003 DisasContext *dc = container_of(dcbase, DisasContext, base);
3004 CPUCRISState *env = cpu_env(cs);
3005 unsigned int insn_len;
3006
3007 /* Pretty disas. */
3008 LOG_DIS("%8.8x:\t", dc->pc);
3009
3010 dc->clear_x = 1;
3011
3012 insn_len = dc->decoder(env, dc);
3013 dc->ppc = dc->pc;
3014 dc->pc += insn_len;
3015 dc->base.pc_next += insn_len;
3016
3017 if (dc->base.is_jmp == DISAS_NORETURN) {
3018 return;
3019 }
3020
3021 if (dc->clear_x) {
3022 cris_clear_x_flag(dc);
3023 }
3024
3025 /*
3026 * All branches are delayed branches, handled immediately below.
3027 * We don't expect to see odd combinations of exit conditions.
3028 */
3029 assert(dc->base.is_jmp == DISAS_NEXT || dc->cpustate_changed);
3030
3031 if (dc->delayed_branch && --dc->delayed_branch == 0) {
3032 dc->base.is_jmp = DISAS_DBRANCH;
3033 return;
3034 }
3035
3036 if (dc->base.is_jmp != DISAS_NEXT) {
3037 return;
3038 }
3039
3040 /* Force an update if the per-tb cpu state has changed. */
3041 if (dc->cpustate_changed) {
3042 dc->base.is_jmp = DISAS_UPDATE_NEXT;
3043 return;
3044 }
3045
3046 /*
3047 * FIXME: Only the first insn in the TB should cross a page boundary.
3048 * If we can detect the length of the next insn easily, we should.
3049 * In the meantime, simply stop when we do cross.
3050 */
3051 if ((dc->pc ^ dc->base.pc_first) & TARGET_PAGE_MASK) {
3052 dc->base.is_jmp = DISAS_TOO_MANY;
3053 }
3054 }
3055
3056 static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
3057 {
3058 DisasContext *dc = container_of(dcbase, DisasContext, base);
3059 DisasJumpType is_jmp = dc->base.is_jmp;
3060 target_ulong npc = dc->pc;
3061
3062 if (is_jmp == DISAS_NORETURN) {
3063 /* If we have a broken branch+delayslot sequence, it's too late. */
3064 assert(dc->delayed_branch != 1);
3065 return;
3066 }
3067
3068 if (dc->clear_locked_irq) {
3069 t_gen_movi_env_TN(locked_irq, 0);
3070 }
3071
3072 /* Broken branch+delayslot sequence. */
3073 if (dc->delayed_branch == 1) {
3074 /* Set env->dslot to the size of the branch insn. */
3075 t_gen_movi_env_TN(dslot, dc->pc - dc->ppc);
3076 cris_store_direct_jmp(dc);
3077 }
3078
3079 cris_evaluate_flags(dc);
3080
3081 /* Evaluate delayed branch destination and fold to another is_jmp case. */
3082 if (is_jmp == DISAS_DBRANCH) {
3083 if (dc->base.tb->flags & 7) {
3084 t_gen_movi_env_TN(dslot, 0);
3085 }
3086
3087 switch (dc->jmp) {
3088 case JMP_DIRECT:
3089 npc = dc->jmp_pc;
3090 is_jmp = dc->cpustate_changed ? DISAS_UPDATE_NEXT : DISAS_TOO_MANY;
3091 break;
3092
3093 case JMP_DIRECT_CC:
3094 /*
3095 * Use a conditional branch if either taken or not-taken path
3096 * can use goto_tb. If neither can, then treat it as indirect.
3097 */
3098 if (likely(!dc->cpustate_changed)
3099 && (use_goto_tb(dc, dc->jmp_pc) || use_goto_tb(dc, npc))) {
3100 TCGLabel *not_taken = gen_new_label();
3101
3102 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, not_taken);
3103 gen_goto_tb(dc, 1, dc->jmp_pc);
3104 gen_set_label(not_taken);
3105
3106 /* not-taken case handled below. */
3107 is_jmp = DISAS_TOO_MANY;
3108 break;
3109 }
3110 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
3111 /* fall through */
3112
3113 case JMP_INDIRECT:
3114 tcg_gen_movcond_tl(TCG_COND_NE, env_pc,
3115 env_btaken, tcg_constant_tl(0),
3116 env_btarget, tcg_constant_tl(npc));
3117 is_jmp = dc->cpustate_changed ? DISAS_UPDATE : DISAS_JUMP;
3118
3119 /*
3120 * We have now consumed btaken and btarget. Hint to the
3121 * tcg compiler that the writeback to env may be dropped.
3122 */
3123 tcg_gen_discard_tl(env_btaken);
3124 tcg_gen_discard_tl(env_btarget);
3125 break;
3126
3127 default:
3128 g_assert_not_reached();
3129 }
3130 }
3131
3132 switch (is_jmp) {
3133 case DISAS_TOO_MANY:
3134 gen_goto_tb(dc, 0, npc);
3135 break;
3136 case DISAS_UPDATE_NEXT:
3137 tcg_gen_movi_tl(env_pc, npc);
3138 /* fall through */
3139 case DISAS_JUMP:
3140 tcg_gen_lookup_and_goto_ptr();
3141 break;
3142 case DISAS_UPDATE:
3143 /* Indicate that interrupts must be re-evaluated before the next TB. */
3144 tcg_gen_exit_tb(NULL, 0);
3145 break;
3146 default:
3147 g_assert_not_reached();
3148 }
3149 }
3150
3151 static void cris_tr_disas_log(const DisasContextBase *dcbase,
3152 CPUState *cpu, FILE *logfile)
3153 {
3154 if (!DISAS_CRIS) {
3155 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
3156 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
3157 }
3158 }
3159
3160 static const TranslatorOps cris_tr_ops = {
3161 .init_disas_context = cris_tr_init_disas_context,
3162 .tb_start = cris_tr_tb_start,
3163 .insn_start = cris_tr_insn_start,
3164 .translate_insn = cris_tr_translate_insn,
3165 .tb_stop = cris_tr_tb_stop,
3166 .disas_log = cris_tr_disas_log,
3167 };
3168
3169 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
3170 vaddr pc, void *host_pc)
3171 {
3172 DisasContext dc;
3173 translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base);
3174 }
3175
3176 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags)
3177 {
3178 CRISCPU *cpu = CRIS_CPU(cs);
3179 CPUCRISState *env = &cpu->env;
3180 const char * const *regnames;
3181 const char * const *pregnames;
3182 int i;
3183
3184 if (!env) {
3185 return;
3186 }
3187 if (env->pregs[PR_VR] < 32) {
3188 pregnames = pregnames_v10;
3189 regnames = regnames_v10;
3190 } else {
3191 pregnames = pregnames_v32;
3192 regnames = regnames_v32;
3193 }
3194
3195 qemu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3196 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3197 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3198 env->cc_op,
3199 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3200
3201
3202 for (i = 0; i < 16; i++) {
3203 qemu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3204 if ((i + 1) % 4 == 0) {
3205 qemu_fprintf(f, "\n");
3206 }
3207 }
3208 qemu_fprintf(f, "\nspecial regs:\n");
3209 for (i = 0; i < 16; i++) {
3210 qemu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3211 if ((i + 1) % 4 == 0) {
3212 qemu_fprintf(f, "\n");
3213 }
3214 }
3215 if (env->pregs[PR_VR] >= 32) {
3216 uint32_t srs = env->pregs[PR_SRS];
3217 qemu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3218 if (srs < ARRAY_SIZE(env->sregs)) {
3219 for (i = 0; i < 16; i++) {
3220 qemu_fprintf(f, "s%2.2d=%8.8x ",
3221 i, env->sregs[srs][i]);
3222 if ((i + 1) % 4 == 0) {
3223 qemu_fprintf(f, "\n");
3224 }
3225 }
3226 }
3227 }
3228 qemu_fprintf(f, "\n\n");
3229
3230 }
3231
3232 void cris_initialize_tcg(void)
3233 {
3234 int i;
3235
3236 cc_x = tcg_global_mem_new(tcg_env,
3237 offsetof(CPUCRISState, cc_x), "cc_x");
3238 cc_src = tcg_global_mem_new(tcg_env,
3239 offsetof(CPUCRISState, cc_src), "cc_src");
3240 cc_dest = tcg_global_mem_new(tcg_env,
3241 offsetof(CPUCRISState, cc_dest),
3242 "cc_dest");
3243 cc_result = tcg_global_mem_new(tcg_env,
3244 offsetof(CPUCRISState, cc_result),
3245 "cc_result");
3246 cc_op = tcg_global_mem_new(tcg_env,
3247 offsetof(CPUCRISState, cc_op), "cc_op");
3248 cc_size = tcg_global_mem_new(tcg_env,
3249 offsetof(CPUCRISState, cc_size),
3250 "cc_size");
3251 cc_mask = tcg_global_mem_new(tcg_env,
3252 offsetof(CPUCRISState, cc_mask),
3253 "cc_mask");
3254
3255 env_pc = tcg_global_mem_new(tcg_env,
3256 offsetof(CPUCRISState, pc),
3257 "pc");
3258 env_btarget = tcg_global_mem_new(tcg_env,
3259 offsetof(CPUCRISState, btarget),
3260 "btarget");
3261 env_btaken = tcg_global_mem_new(tcg_env,
3262 offsetof(CPUCRISState, btaken),
3263 "btaken");
3264 for (i = 0; i < 16; i++) {
3265 cpu_R[i] = tcg_global_mem_new(tcg_env,
3266 offsetof(CPUCRISState, regs[i]),
3267 regnames_v32[i]);
3268 }
3269 for (i = 0; i < 16; i++) {
3270 cpu_PR[i] = tcg_global_mem_new(tcg_env,
3271 offsetof(CPUCRISState, pregs[i]),
3272 pregnames_v32[i]);
3273 }
3274 }
AR7 emulation for QEMU