?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
megasas: change msi/msix property type
[qemu/ar7.git] / hw / scsi / megasas.c
blob636ea73adbae676634168c10d719c0f01cb85957
1 /*
2 * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3 * Based on the linux driver code at drivers/scsi/megaraid
4 *
5 * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "hw/hw.h"
23 #include "hw/pci/pci.h"
24 #include "sysemu/dma.h"
25 #include "sysemu/block-backend.h"
26 #include "hw/pci/msi.h"
27 #include "hw/pci/msix.h"
28 #include "qemu/iov.h"
29 #include "hw/scsi/scsi.h"
30 #include "block/scsi.h"
31 #include "trace.h"
32
33 #include "mfi.h"
34
35 #define MEGASAS_VERSION_GEN1 "1.70"
36 #define MEGASAS_VERSION_GEN2 "1.80"
37 #define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
38 #define MEGASAS_DEFAULT_FRAMES 1000 /* Windows requires this */
39 #define MEGASAS_GEN2_DEFAULT_FRAMES 1008 /* Windows requires this */
40 #define MEGASAS_MAX_SGE 128 /* Firmware limit */
41 #define MEGASAS_DEFAULT_SGE 80
42 #define MEGASAS_MAX_SECTORS 0xFFFF /* No real limit */
43 #define MEGASAS_MAX_ARRAYS 128
44
45 #define MEGASAS_HBA_SERIAL "QEMU123456"
46 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
47 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
48
49 #define MEGASAS_FLAG_USE_JBOD 0
50 #define MEGASAS_MASK_USE_JBOD (1 << MEGASAS_FLAG_USE_JBOD)
51 #define MEGASAS_FLAG_USE_QUEUE64 1
52 #define MEGASAS_MASK_USE_QUEUE64 (1 << MEGASAS_FLAG_USE_QUEUE64)
53
54 static const char *mfi_frame_desc[] = {
55 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
56 "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"};
57
58 typedef struct MegasasCmd {
59 uint32_t index;
60 uint16_t flags;
61 uint16_t count;
62 uint64_t context;
63
64 hwaddr pa;
65 hwaddr pa_size;
66 union mfi_frame *frame;
67 SCSIRequest *req;
68 QEMUSGList qsg;
69 void *iov_buf;
70 size_t iov_size;
71 size_t iov_offset;
72 struct MegasasState *state;
73 } MegasasCmd;
74
75 typedef struct MegasasState {
76 /*< private >*/
77 PCIDevice parent_obj;
78 /*< public >*/
79
80 MemoryRegion mmio_io;
81 MemoryRegion port_io;
82 MemoryRegion queue_io;
83 uint32_t frame_hi;
84
85 int fw_state;
86 uint32_t fw_sge;
87 uint32_t fw_cmds;
88 uint32_t flags;
89 int fw_luns;
90 int intr_mask;
91 int doorbell;
92 int busy;
93 int diag;
94 int adp_reset;
95 OnOffAuto msi;
96 OnOffAuto msix;
97
98 MegasasCmd *event_cmd;
99 int event_locale;
100 int event_class;
101 int event_count;
102 int shutdown_event;
103 int boot_event;
104
105 uint64_t sas_addr;
106 char *hba_serial;
107
108 uint64_t reply_queue_pa;
109 void *reply_queue;
110 int reply_queue_len;
111 int reply_queue_head;
112 int reply_queue_tail;
113 uint64_t consumer_pa;
114 uint64_t producer_pa;
115
116 MegasasCmd frames[MEGASAS_MAX_FRAMES];
117 DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
118 SCSIBus bus;
119 } MegasasState;
120
121 typedef struct MegasasBaseClass {
122 PCIDeviceClass parent_class;
123 const char *product_name;
124 const char *product_version;
125 int mmio_bar;
126 int ioport_bar;
127 int osts;
128 } MegasasBaseClass;
129
130 #define TYPE_MEGASAS_BASE "megasas-base"
131 #define TYPE_MEGASAS_GEN1 "megasas"
132 #define TYPE_MEGASAS_GEN2 "megasas-gen2"
133
134 #define MEGASAS(obj) \
135 OBJECT_CHECK(MegasasState, (obj), TYPE_MEGASAS_BASE)
136
137 #define MEGASAS_DEVICE_CLASS(oc) \
138 OBJECT_CLASS_CHECK(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
139 #define MEGASAS_DEVICE_GET_CLASS(oc) \
140 OBJECT_GET_CLASS(MegasasBaseClass, (oc), TYPE_MEGASAS_BASE)
141
142 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
143
144 static bool megasas_intr_enabled(MegasasState *s)
145 {
146 if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
147 MEGASAS_INTR_DISABLED_MASK) {
148 return true;
149 }
150 return false;
151 }
152
153 static bool megasas_use_queue64(MegasasState *s)
154 {
155 return s->flags & MEGASAS_MASK_USE_QUEUE64;
156 }
157
158 static bool megasas_use_msi(MegasasState *s)
159 {
160 return s->msi != ON_OFF_AUTO_OFF;
161 }
162
163 static bool megasas_use_msix(MegasasState *s)
164 {
165 return s->msix != ON_OFF_AUTO_OFF;
166 }
167
168 static bool megasas_is_jbod(MegasasState *s)
169 {
170 return s->flags & MEGASAS_MASK_USE_JBOD;
171 }
172
173 static void megasas_frame_set_cmd_status(MegasasState *s,
174 unsigned long frame, uint8_t v)
175 {
176 PCIDevice *pci = &s->parent_obj;
177 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status), v);
178 }
179
180 static void megasas_frame_set_scsi_status(MegasasState *s,
181 unsigned long frame, uint8_t v)
182 {
183 PCIDevice *pci = &s->parent_obj;
184 stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status), v);
185 }
186
187 /*
188 * Context is considered opaque, but the HBA firmware is running
189 * in little endian mode. So convert it to little endian, too.
190 */
191 static uint64_t megasas_frame_get_context(MegasasState *s,
192 unsigned long frame)
193 {
194 PCIDevice *pci = &s->parent_obj;
195 return ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context));
196 }
197
198 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
199 {
200 return cmd->flags & MFI_FRAME_IEEE_SGL;
201 }
202
203 static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
204 {
205 return cmd->flags & MFI_FRAME_SGL64;
206 }
207
208 static bool megasas_frame_is_sense64(MegasasCmd *cmd)
209 {
210 return cmd->flags & MFI_FRAME_SENSE64;
211 }
212
213 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
214 union mfi_sgl *sgl)
215 {
216 uint64_t addr;
217
218 if (megasas_frame_is_ieee_sgl(cmd)) {
219 addr = le64_to_cpu(sgl->sg_skinny->addr);
220 } else if (megasas_frame_is_sgl64(cmd)) {
221 addr = le64_to_cpu(sgl->sg64->addr);
222 } else {
223 addr = le32_to_cpu(sgl->sg32->addr);
224 }
225 return addr;
226 }
227
228 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
229 union mfi_sgl *sgl)
230 {
231 uint32_t len;
232
233 if (megasas_frame_is_ieee_sgl(cmd)) {
234 len = le32_to_cpu(sgl->sg_skinny->len);
235 } else if (megasas_frame_is_sgl64(cmd)) {
236 len = le32_to_cpu(sgl->sg64->len);
237 } else {
238 len = le32_to_cpu(sgl->sg32->len);
239 }
240 return len;
241 }
242
243 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
244 union mfi_sgl *sgl)
245 {
246 uint8_t *next = (uint8_t *)sgl;
247
248 if (megasas_frame_is_ieee_sgl(cmd)) {
249 next += sizeof(struct mfi_sg_skinny);
250 } else if (megasas_frame_is_sgl64(cmd)) {
251 next += sizeof(struct mfi_sg64);
252 } else {
253 next += sizeof(struct mfi_sg32);
254 }
255
256 if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
257 return NULL;
258 }
259 return (union mfi_sgl *)next;
260 }
261
262 static void megasas_soft_reset(MegasasState *s);
263
264 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
265 {
266 int i;
267 int iov_count = 0;
268 size_t iov_size = 0;
269
270 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
271 iov_count = cmd->frame->header.sge_count;
272 if (iov_count > MEGASAS_MAX_SGE) {
273 trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
274 MEGASAS_MAX_SGE);
275 return iov_count;
276 }
277 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
278 for (i = 0; i < iov_count; i++) {
279 dma_addr_t iov_pa, iov_size_p;
280
281 if (!sgl) {
282 trace_megasas_iovec_sgl_underflow(cmd->index, i);
283 goto unmap;
284 }
285 iov_pa = megasas_sgl_get_addr(cmd, sgl);
286 iov_size_p = megasas_sgl_get_len(cmd, sgl);
287 if (!iov_pa || !iov_size_p) {
288 trace_megasas_iovec_sgl_invalid(cmd->index, i,
289 iov_pa, iov_size_p);
290 goto unmap;
291 }
292 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
293 sgl = megasas_sgl_next(cmd, sgl);
294 iov_size += (size_t)iov_size_p;
295 }
296 if (cmd->iov_size > iov_size) {
297 trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
298 } else if (cmd->iov_size < iov_size) {
299 trace_megasas_iovec_underflow(cmd->iov_size, iov_size, cmd->iov_size);
300 }
301 cmd->iov_offset = 0;
302 return 0;
303 unmap:
304 qemu_sglist_destroy(&cmd->qsg);
305 return iov_count - i;
306 }
307
308 static void megasas_unmap_sgl(MegasasCmd *cmd)
309 {
310 qemu_sglist_destroy(&cmd->qsg);
311 cmd->iov_offset = 0;
312 }
313
314 /*
315 * passthrough sense and io sense are at the same offset
316 */
317 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
318 uint8_t sense_len)
319 {
320 PCIDevice *pcid = PCI_DEVICE(cmd->state);
321 uint32_t pa_hi = 0, pa_lo;
322 hwaddr pa;
323
324 if (sense_len > cmd->frame->header.sense_len) {
325 sense_len = cmd->frame->header.sense_len;
326 }
327 if (sense_len) {
328 pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
329 if (megasas_frame_is_sense64(cmd)) {
330 pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
331 }
332 pa = ((uint64_t) pa_hi << 32) | pa_lo;
333 pci_dma_write(pcid, pa, sense_ptr, sense_len);
334 cmd->frame->header.sense_len = sense_len;
335 }
336 return sense_len;
337 }
338
339 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
340 {
341 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
342 uint8_t sense_len = 18;
343
344 memset(sense_buf, 0, sense_len);
345 sense_buf[0] = 0xf0;
346 sense_buf[2] = sense.key;
347 sense_buf[7] = 10;
348 sense_buf[12] = sense.asc;
349 sense_buf[13] = sense.ascq;
350 megasas_build_sense(cmd, sense_buf, sense_len);
351 }
352
353 static void megasas_copy_sense(MegasasCmd *cmd)
354 {
355 uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
356 uint8_t sense_len;
357
358 sense_len = scsi_req_get_sense(cmd->req, sense_buf,
359 SCSI_SENSE_BUF_SIZE);
360 megasas_build_sense(cmd, sense_buf, sense_len);
361 }
362
363 /*
364 * Format an INQUIRY CDB
365 */
366 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
367 {
368 memset(cdb, 0, 6);
369 cdb[0] = INQUIRY;
370 if (pg > 0) {
371 cdb[1] = 0x1;
372 cdb[2] = pg;
373 }
374 cdb[3] = (len >> 8) & 0xff;
375 cdb[4] = (len & 0xff);
376 return len;
377 }
378
379 /*
380 * Encode lba and len into a READ_16/WRITE_16 CDB
381 */
382 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
383 uint32_t len, bool is_write)
384 {
385 memset(cdb, 0x0, 16);
386 if (is_write) {
387 cdb[0] = WRITE_16;
388 } else {
389 cdb[0] = READ_16;
390 }
391 cdb[2] = (lba >> 56) & 0xff;
392 cdb[3] = (lba >> 48) & 0xff;
393 cdb[4] = (lba >> 40) & 0xff;
394 cdb[5] = (lba >> 32) & 0xff;
395 cdb[6] = (lba >> 24) & 0xff;
396 cdb[7] = (lba >> 16) & 0xff;
397 cdb[8] = (lba >> 8) & 0xff;
398 cdb[9] = (lba) & 0xff;
399 cdb[10] = (len >> 24) & 0xff;
400 cdb[11] = (len >> 16) & 0xff;
401 cdb[12] = (len >> 8) & 0xff;
402 cdb[13] = (len) & 0xff;
403 }
404
405 /*
406 * Utility functions
407 */
408 static uint64_t megasas_fw_time(void)
409 {
410 struct tm curtime;
411
412 qemu_get_timedate(&curtime, 0);
413 return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
414 ((uint64_t)curtime.tm_min & 0xff) << 40 |
415 ((uint64_t)curtime.tm_hour & 0xff) << 32 |
416 ((uint64_t)curtime.tm_mday & 0xff) << 24 |
417 ((uint64_t)curtime.tm_mon & 0xff) << 16 |
418 ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
419 }
420
421 /*
422 * Default disk sata address
423 * 0x1221 is the magic number as
424 * present in real hardware,
425 * so use it here, too.
426 */
427 static uint64_t megasas_get_sata_addr(uint16_t id)
428 {
429 uint64_t addr = (0x1221ULL << 48);
430 return addr | ((uint64_t)id << 24);
431 }
432
433 /*
434 * Frame handling
435 */
436 static int megasas_next_index(MegasasState *s, int index, int limit)
437 {
438 index++;
439 if (index == limit) {
440 index = 0;
441 }
442 return index;
443 }
444
445 static MegasasCmd *megasas_lookup_frame(MegasasState *s,
446 hwaddr frame)
447 {
448 MegasasCmd *cmd = NULL;
449 int num = 0, index;
450
451 index = s->reply_queue_head;
452
453 while (num < s->fw_cmds) {
454 if (s->frames[index].pa && s->frames[index].pa == frame) {
455 cmd = &s->frames[index];
456 break;
457 }
458 index = megasas_next_index(s, index, s->fw_cmds);
459 num++;
460 }
461
462 return cmd;
463 }
464
465 static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
466 {
467 PCIDevice *p = PCI_DEVICE(s);
468
469 pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
470 cmd->frame = NULL;
471 cmd->pa = 0;
472 clear_bit(cmd->index, s->frame_map);
473 }
474
475 /*
476 * This absolutely needs to be locked if
477 * qemu ever goes multithreaded.
478 */
479 static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
480 hwaddr frame, uint64_t context, int count)
481 {
482 PCIDevice *pcid = PCI_DEVICE(s);
483 MegasasCmd *cmd = NULL;
484 int frame_size = MFI_FRAME_SIZE * 16;
485 hwaddr frame_size_p = frame_size;
486 unsigned long index;
487
488 index = 0;
489 while (index < s->fw_cmds) {
490 index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
491 if (!s->frames[index].pa)
492 break;
493 /* Busy frame found */
494 trace_megasas_qf_mapped(index);
495 }
496 if (index >= s->fw_cmds) {
497 /* All frames busy */
498 trace_megasas_qf_busy(frame);
499 return NULL;
500 }
501 cmd = &s->frames[index];
502 set_bit(index, s->frame_map);
503 trace_megasas_qf_new(index, frame);
504
505 cmd->pa = frame;
506 /* Map all possible frames */
507 cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
508 if (frame_size_p != frame_size) {
509 trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
510 if (cmd->frame) {
511 megasas_unmap_frame(s, cmd);
512 }
513 s->event_count++;
514 return NULL;
515 }
516 cmd->pa_size = frame_size_p;
517 cmd->context = context;
518 if (!megasas_use_queue64(s)) {
519 cmd->context &= (uint64_t)0xFFFFFFFF;
520 }
521 cmd->count = count;
522 s->busy++;
523
524 if (s->consumer_pa) {
525 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
526 }
527 trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
528 s->reply_queue_head, s->reply_queue_tail, s->busy);
529
530 return cmd;
531 }
532
533 static void megasas_complete_frame(MegasasState *s, uint64_t context)
534 {
535 PCIDevice *pci_dev = PCI_DEVICE(s);
536 int tail, queue_offset;
537
538 /* Decrement busy count */
539 s->busy--;
540 if (s->reply_queue_pa) {
541 /*
542 * Put command on the reply queue.
543 * Context is opaque, but emulation is running in
544 * little endian. So convert it.
545 */
546 if (megasas_use_queue64(s)) {
547 queue_offset = s->reply_queue_head * sizeof(uint64_t);
548 stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
549 } else {
550 queue_offset = s->reply_queue_head * sizeof(uint32_t);
551 stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset, context);
552 }
553 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
554 trace_megasas_qf_complete(context, s->reply_queue_head,
555 s->reply_queue_tail, s->busy);
556 }
557
558 if (megasas_intr_enabled(s)) {
559 /* Update reply queue pointer */
560 s->reply_queue_tail = ldl_le_pci_dma(pci_dev, s->consumer_pa);
561 tail = s->reply_queue_head;
562 s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
563 trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
564 s->busy);
565 stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head);
566 /* Notify HBA */
567 if (msix_enabled(pci_dev)) {
568 trace_megasas_msix_raise(0);
569 msix_notify(pci_dev, 0);
570 } else if (msi_enabled(pci_dev)) {
571 trace_megasas_msi_raise(0);
572 msi_notify(pci_dev, 0);
573 } else {
574 s->doorbell++;
575 if (s->doorbell == 1) {
576 trace_megasas_irq_raise();
577 pci_irq_assert(pci_dev);
578 }
579 }
580 } else {
581 trace_megasas_qf_complete_noirq(context);
582 }
583 }
584
585 static void megasas_reset_frames(MegasasState *s)
586 {
587 int i;
588 MegasasCmd *cmd;
589
590 for (i = 0; i < s->fw_cmds; i++) {
591 cmd = &s->frames[i];
592 if (cmd->pa) {
593 megasas_unmap_frame(s, cmd);
594 }
595 }
596 bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
597 }
598
599 static void megasas_abort_command(MegasasCmd *cmd)
600 {
601 if (cmd->req) {
602 scsi_req_cancel(cmd->req);
603 cmd->req = NULL;
604 }
605 }
606
607 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
608 {
609 PCIDevice *pcid = PCI_DEVICE(s);
610 uint32_t pa_hi, pa_lo;
611 hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
612 struct mfi_init_qinfo *initq = NULL;
613 uint32_t flags;
614 int ret = MFI_STAT_OK;
615
616 if (s->reply_queue_pa) {
617 trace_megasas_initq_mapped(s->reply_queue_pa);
618 goto out;
619 }
620 pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
621 pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
622 iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
623 trace_megasas_init_firmware((uint64_t)iq_pa);
624 initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
625 if (!initq || initq_size != sizeof(*initq)) {
626 trace_megasas_initq_map_failed(cmd->index);
627 s->event_count++;
628 ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
629 goto out;
630 }
631 s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
632 if (s->reply_queue_len > s->fw_cmds) {
633 trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
634 s->event_count++;
635 ret = MFI_STAT_INVALID_PARAMETER;
636 goto out;
637 }
638 pa_lo = le32_to_cpu(initq->rq_addr_lo);
639 pa_hi = le32_to_cpu(initq->rq_addr_hi);
640 s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
641 pa_lo = le32_to_cpu(initq->ci_addr_lo);
642 pa_hi = le32_to_cpu(initq->ci_addr_hi);
643 s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
644 pa_lo = le32_to_cpu(initq->pi_addr_lo);
645 pa_hi = le32_to_cpu(initq->pi_addr_hi);
646 s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
647 s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa);
648 s->reply_queue_head %= MEGASAS_MAX_FRAMES;
649 s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa);
650 s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
651 flags = le32_to_cpu(initq->flags);
652 if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
653 s->flags |= MEGASAS_MASK_USE_QUEUE64;
654 }
655 trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
656 s->reply_queue_len, s->reply_queue_head,
657 s->reply_queue_tail, flags);
658 megasas_reset_frames(s);
659 s->fw_state = MFI_FWSTATE_OPERATIONAL;
660 out:
661 if (initq) {
662 pci_dma_unmap(pcid, initq, initq_size, 0, 0);
663 }
664 return ret;
665 }
666
667 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
668 {
669 dma_addr_t iov_pa, iov_size;
670
671 cmd->flags = le16_to_cpu(cmd->frame->header.flags);
672 if (!cmd->frame->header.sge_count) {
673 trace_megasas_dcmd_zero_sge(cmd->index);
674 cmd->iov_size = 0;
675 return 0;
676 } else if (cmd->frame->header.sge_count > 1) {
677 trace_megasas_dcmd_invalid_sge(cmd->index,
678 cmd->frame->header.sge_count);
679 cmd->iov_size = 0;
680 return -1;
681 }
682 iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
683 iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
684 pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
685 qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
686 cmd->iov_size = iov_size;
687 return cmd->iov_size;
688 }
689
690 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
691 {
692 trace_megasas_finish_dcmd(cmd->index, iov_size);
693
694 if (cmd->frame->header.sge_count) {
695 qemu_sglist_destroy(&cmd->qsg);
696 }
697 if (iov_size > cmd->iov_size) {
698 if (megasas_frame_is_ieee_sgl(cmd)) {
699 cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
700 } else if (megasas_frame_is_sgl64(cmd)) {
701 cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
702 } else {
703 cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
704 }
705 }
706 cmd->iov_size = 0;
707 }
708
709 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
710 {
711 PCIDevice *pci_dev = PCI_DEVICE(s);
712 PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
713 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
714 struct mfi_ctrl_info info;
715 size_t dcmd_size = sizeof(info);
716 BusChild *kid;
717 int num_pd_disks = 0;
718
719 memset(&info, 0x0, dcmd_size);
720 if (cmd->iov_size < dcmd_size) {
721 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
722 dcmd_size);
723 return MFI_STAT_INVALID_PARAMETER;
724 }
725
726 info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
727 info.pci.device = cpu_to_le16(pci_class->device_id);
728 info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
729 info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
730
731 /*
732 * For some reason the firmware supports
733 * only up to 8 device ports.
734 * Despite supporting a far larger number
735 * of devices for the physical devices.
736 * So just display the first 8 devices
737 * in the device port list, independent
738 * of how many logical devices are actually
739 * present.
740 */
741 info.host.type = MFI_INFO_HOST_PCIE;
742 info.device.type = MFI_INFO_DEV_SAS3G;
743 info.device.port_count = 8;
744 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
745 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
746 uint16_t pd_id;
747
748 if (num_pd_disks < 8) {
749 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
750 info.device.port_addr[num_pd_disks] =
751 cpu_to_le64(megasas_get_sata_addr(pd_id));
752 }
753 num_pd_disks++;
754 }
755
756 memcpy(info.product_name, base_class->product_name, 24);
757 snprintf(info.serial_number, 32, "%s", s->hba_serial);
758 snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
759 memcpy(info.image_component[0].name, "APP", 3);
760 snprintf(info.image_component[0].version, 10, "%s-QEMU",
761 base_class->product_version);
762 memcpy(info.image_component[0].build_date, "Apr 1 2014", 11);
763 memcpy(info.image_component[0].build_time, "12:34:56", 8);
764 info.image_component_count = 1;
765 if (pci_dev->has_rom) {
766 uint8_t biosver[32];
767 uint8_t *ptr;
768
769 ptr = memory_region_get_ram_ptr(&pci_dev->rom);
770 memcpy(biosver, ptr + 0x41, 31);
771 biosver[31] = 0;
772 memcpy(info.image_component[1].name, "BIOS", 4);
773 memcpy(info.image_component[1].version, biosver,
774 strlen((const char *)biosver));
775 info.image_component_count++;
776 }
777 info.current_fw_time = cpu_to_le32(megasas_fw_time());
778 info.max_arms = 32;
779 info.max_spans = 8;
780 info.max_arrays = MEGASAS_MAX_ARRAYS;
781 info.max_lds = MFI_MAX_LD;
782 info.max_cmds = cpu_to_le16(s->fw_cmds);
783 info.max_sg_elements = cpu_to_le16(s->fw_sge);
784 info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
785 if (!megasas_is_jbod(s))
786 info.lds_present = cpu_to_le16(num_pd_disks);
787 info.pd_present = cpu_to_le16(num_pd_disks);
788 info.pd_disks_present = cpu_to_le16(num_pd_disks);
789 info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
790 MFI_INFO_HW_MEM |
791 MFI_INFO_HW_FLASH);
792 info.memory_size = cpu_to_le16(512);
793 info.nvram_size = cpu_to_le16(32);
794 info.flash_size = cpu_to_le16(16);
795 info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
796 info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
797 MFI_INFO_AOPS_SELF_DIAGNOSTIC |
798 MFI_INFO_AOPS_MIXED_ARRAY);
799 info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
800 MFI_INFO_LDOPS_ACCESS_POLICY |
801 MFI_INFO_LDOPS_IO_POLICY |
802 MFI_INFO_LDOPS_WRITE_POLICY |
803 MFI_INFO_LDOPS_READ_POLICY);
804 info.max_strips_per_io = cpu_to_le16(s->fw_sge);
805 info.stripe_sz_ops.min = 3;
806 info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
807 info.properties.pred_fail_poll_interval = cpu_to_le16(300);
808 info.properties.intr_throttle_cnt = cpu_to_le16(16);
809 info.properties.intr_throttle_timeout = cpu_to_le16(50);
810 info.properties.rebuild_rate = 30;
811 info.properties.patrol_read_rate = 30;
812 info.properties.bgi_rate = 30;
813 info.properties.cc_rate = 30;
814 info.properties.recon_rate = 30;
815 info.properties.cache_flush_interval = 4;
816 info.properties.spinup_drv_cnt = 2;
817 info.properties.spinup_delay = 6;
818 info.properties.ecc_bucket_size = 15;
819 info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
820 info.properties.expose_encl_devices = 1;
821 info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
822 info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
823 MFI_INFO_PDOPS_FORCE_OFFLINE);
824 info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
825 MFI_INFO_PDMIX_SATA |
826 MFI_INFO_PDMIX_LD);
827
828 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
829 return MFI_STAT_OK;
830 }
831
832 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
833 {
834 struct mfi_defaults info;
835 size_t dcmd_size = sizeof(struct mfi_defaults);
836
837 memset(&info, 0x0, dcmd_size);
838 if (cmd->iov_size < dcmd_size) {
839 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
840 dcmd_size);
841 return MFI_STAT_INVALID_PARAMETER;
842 }
843
844 info.sas_addr = cpu_to_le64(s->sas_addr);
845 info.stripe_size = 3;
846 info.flush_time = 4;
847 info.background_rate = 30;
848 info.allow_mix_in_enclosure = 1;
849 info.allow_mix_in_ld = 1;
850 info.direct_pd_mapping = 1;
851 /* Enable for BIOS support */
852 info.bios_enumerate_lds = 1;
853 info.disable_ctrl_r = 1;
854 info.expose_enclosure_devices = 1;
855 info.disable_preboot_cli = 1;
856 info.cluster_disable = 1;
857
858 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
859 return MFI_STAT_OK;
860 }
861
862 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
863 {
864 struct mfi_bios_data info;
865 size_t dcmd_size = sizeof(info);
866
867 memset(&info, 0x0, dcmd_size);
868 if (cmd->iov_size < dcmd_size) {
869 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
870 dcmd_size);
871 return MFI_STAT_INVALID_PARAMETER;
872 }
873 info.continue_on_error = 1;
874 info.verbose = 1;
875 if (megasas_is_jbod(s)) {
876 info.expose_all_drives = 1;
877 }
878
879 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
880 return MFI_STAT_OK;
881 }
882
883 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
884 {
885 uint64_t fw_time;
886 size_t dcmd_size = sizeof(fw_time);
887
888 fw_time = cpu_to_le64(megasas_fw_time());
889
890 cmd->iov_size -= dma_buf_read((uint8_t *)&fw_time, dcmd_size, &cmd->qsg);
891 return MFI_STAT_OK;
892 }
893
894 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
895 {
896 uint64_t fw_time;
897
898 /* This is a dummy; setting of firmware time is not allowed */
899 memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
900
901 trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
902 fw_time = cpu_to_le64(megasas_fw_time());
903 return MFI_STAT_OK;
904 }
905
906 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
907 {
908 struct mfi_evt_log_state info;
909 size_t dcmd_size = sizeof(info);
910
911 memset(&info, 0, dcmd_size);
912
913 info.newest_seq_num = cpu_to_le32(s->event_count);
914 info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
915 info.boot_seq_num = cpu_to_le32(s->boot_event);
916
917 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
918 return MFI_STAT_OK;
919 }
920
921 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
922 {
923 union mfi_evt event;
924
925 if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
926 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
927 sizeof(struct mfi_evt_detail));
928 return MFI_STAT_INVALID_PARAMETER;
929 }
930 s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
931 event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
932 s->event_locale = event.members.locale;
933 s->event_class = event.members.class;
934 s->event_cmd = cmd;
935 /* Decrease busy count; event frame doesn't count here */
936 s->busy--;
937 cmd->iov_size = sizeof(struct mfi_evt_detail);
938 return MFI_STAT_INVALID_STATUS;
939 }
940
941 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
942 {
943 struct mfi_pd_list info;
944 size_t dcmd_size = sizeof(info);
945 BusChild *kid;
946 uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
947
948 memset(&info, 0, dcmd_size);
949 offset = 8;
950 dcmd_limit = offset + sizeof(struct mfi_pd_address);
951 if (cmd->iov_size < dcmd_limit) {
952 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
953 dcmd_limit);
954 return MFI_STAT_INVALID_PARAMETER;
955 }
956
957 max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
958 if (max_pd_disks > MFI_MAX_SYS_PDS) {
959 max_pd_disks = MFI_MAX_SYS_PDS;
960 }
961 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
962 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
963 uint16_t pd_id;
964
965 if (num_pd_disks >= max_pd_disks)
966 break;
967
968 pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
969 info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
970 info.addr[num_pd_disks].encl_device_id = 0xFFFF;
971 info.addr[num_pd_disks].encl_index = 0;
972 info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
973 info.addr[num_pd_disks].scsi_dev_type = sdev->type;
974 info.addr[num_pd_disks].connect_port_bitmap = 0x1;
975 info.addr[num_pd_disks].sas_addr[0] =
976 cpu_to_le64(megasas_get_sata_addr(pd_id));
977 num_pd_disks++;
978 offset += sizeof(struct mfi_pd_address);
979 }
980 trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
981 max_pd_disks, offset);
982
983 info.size = cpu_to_le32(offset);
984 info.count = cpu_to_le32(num_pd_disks);
985
986 cmd->iov_size -= dma_buf_read((uint8_t *)&info, offset, &cmd->qsg);
987 return MFI_STAT_OK;
988 }
989
990 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
991 {
992 uint16_t flags;
993
994 /* mbox0 contains flags */
995 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
996 trace_megasas_dcmd_pd_list_query(cmd->index, flags);
997 if (flags == MR_PD_QUERY_TYPE_ALL ||
998 megasas_is_jbod(s)) {
999 return megasas_dcmd_pd_get_list(s, cmd);
1000 }
1001
1002 return MFI_STAT_OK;
1003 }
1004
1005 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1006 MegasasCmd *cmd)
1007 {
1008 struct mfi_pd_info *info = cmd->iov_buf;
1009 size_t dcmd_size = sizeof(struct mfi_pd_info);
1010 uint64_t pd_size;
1011 uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1012 uint8_t cmdbuf[6];
1013 SCSIRequest *req;
1014 size_t len, resid;
1015
1016 if (!cmd->iov_buf) {
1017 cmd->iov_buf = g_malloc0(dcmd_size);
1018 info = cmd->iov_buf;
1019 info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1020 info->vpd_page83[0] = 0x7f;
1021 megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1022 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1023 if (!req) {
1024 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1025 "PD get info std inquiry");
1026 g_free(cmd->iov_buf);
1027 cmd->iov_buf = NULL;
1028 return MFI_STAT_FLASH_ALLOC_FAIL;
1029 }
1030 trace_megasas_dcmd_internal_submit(cmd->index,
1031 "PD get info std inquiry", lun);
1032 len = scsi_req_enqueue(req);
1033 if (len > 0) {
1034 cmd->iov_size = len;
1035 scsi_req_continue(req);
1036 }
1037 return MFI_STAT_INVALID_STATUS;
1038 } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1039 megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1040 req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, cmd);
1041 if (!req) {
1042 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1043 "PD get info vpd inquiry");
1044 return MFI_STAT_FLASH_ALLOC_FAIL;
1045 }
1046 trace_megasas_dcmd_internal_submit(cmd->index,
1047 "PD get info vpd inquiry", lun);
1048 len = scsi_req_enqueue(req);
1049 if (len > 0) {
1050 cmd->iov_size = len;
1051 scsi_req_continue(req);
1052 }
1053 return MFI_STAT_INVALID_STATUS;
1054 }
1055 /* Finished, set FW state */
1056 if ((info->inquiry_data[0] >> 5) == 0) {
1057 if (megasas_is_jbod(cmd->state)) {
1058 info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1059 } else {
1060 info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1061 }
1062 } else {
1063 info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1064 }
1065
1066 info->ref.v.device_id = cpu_to_le16(pd_id);
1067 info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1068 MFI_PD_DDF_TYPE_INTF_SAS);
1069 blk_get_geometry(sdev->conf.blk, &pd_size);
1070 info->raw_size = cpu_to_le64(pd_size);
1071 info->non_coerced_size = cpu_to_le64(pd_size);
1072 info->coerced_size = cpu_to_le64(pd_size);
1073 info->encl_device_id = 0xFFFF;
1074 info->slot_number = (sdev->id & 0xFF);
1075 info->path_info.count = 1;
1076 info->path_info.sas_addr[0] =
1077 cpu_to_le64(megasas_get_sata_addr(pd_id));
1078 info->connected_port_bitmap = 0x1;
1079 info->device_speed = 1;
1080 info->link_speed = 1;
1081 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1082 g_free(cmd->iov_buf);
1083 cmd->iov_size = dcmd_size - resid;
1084 cmd->iov_buf = NULL;
1085 return MFI_STAT_OK;
1086 }
1087
1088 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1089 {
1090 size_t dcmd_size = sizeof(struct mfi_pd_info);
1091 uint16_t pd_id;
1092 uint8_t target_id, lun_id;
1093 SCSIDevice *sdev = NULL;
1094 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1095
1096 if (cmd->iov_size < dcmd_size) {
1097 return MFI_STAT_INVALID_PARAMETER;
1098 }
1099
1100 /* mbox0 has the ID */
1101 pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1102 target_id = (pd_id >> 8) & 0xFF;
1103 lun_id = pd_id & 0xFF;
1104 sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1105 trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1106
1107 if (sdev) {
1108 /* Submit inquiry */
1109 retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1110 }
1111
1112 return retval;
1113 }
1114
1115 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1116 {
1117 struct mfi_ld_list info;
1118 size_t dcmd_size = sizeof(info), resid;
1119 uint32_t num_ld_disks = 0, max_ld_disks;
1120 uint64_t ld_size;
1121 BusChild *kid;
1122
1123 memset(&info, 0, dcmd_size);
1124 if (cmd->iov_size > dcmd_size) {
1125 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1126 dcmd_size);
1127 return MFI_STAT_INVALID_PARAMETER;
1128 }
1129
1130 max_ld_disks = (cmd->iov_size - 8) / 16;
1131 if (megasas_is_jbod(s)) {
1132 max_ld_disks = 0;
1133 }
1134 if (max_ld_disks > MFI_MAX_LD) {
1135 max_ld_disks = MFI_MAX_LD;
1136 }
1137 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1138 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1139
1140 if (num_ld_disks >= max_ld_disks) {
1141 break;
1142 }
1143 /* Logical device size is in blocks */
1144 blk_get_geometry(sdev->conf.blk, &ld_size);
1145 info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1146 info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1147 info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1148 num_ld_disks++;
1149 }
1150 info.ld_count = cpu_to_le32(num_ld_disks);
1151 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1152
1153 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1154 cmd->iov_size = dcmd_size - resid;
1155 return MFI_STAT_OK;
1156 }
1157
1158 static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1159 {
1160 uint16_t flags;
1161 struct mfi_ld_targetid_list info;
1162 size_t dcmd_size = sizeof(info), resid;
1163 uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1164 BusChild *kid;
1165
1166 /* mbox0 contains flags */
1167 flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1168 trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1169 if (flags != MR_LD_QUERY_TYPE_ALL &&
1170 flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1171 max_ld_disks = 0;
1172 }
1173
1174 memset(&info, 0, dcmd_size);
1175 if (cmd->iov_size < 12) {
1176 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1177 dcmd_size);
1178 return MFI_STAT_INVALID_PARAMETER;
1179 }
1180 dcmd_size = sizeof(uint32_t) * 2 + 3;
1181 max_ld_disks = cmd->iov_size - dcmd_size;
1182 if (megasas_is_jbod(s)) {
1183 max_ld_disks = 0;
1184 }
1185 if (max_ld_disks > MFI_MAX_LD) {
1186 max_ld_disks = MFI_MAX_LD;
1187 }
1188 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1189 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1190
1191 if (num_ld_disks >= max_ld_disks) {
1192 break;
1193 }
1194 info.targetid[num_ld_disks] = sdev->lun;
1195 num_ld_disks++;
1196 dcmd_size++;
1197 }
1198 info.ld_count = cpu_to_le32(num_ld_disks);
1199 info.size = dcmd_size;
1200 trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1201
1202 resid = dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1203 cmd->iov_size = dcmd_size - resid;
1204 return MFI_STAT_OK;
1205 }
1206
1207 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1208 MegasasCmd *cmd)
1209 {
1210 struct mfi_ld_info *info = cmd->iov_buf;
1211 size_t dcmd_size = sizeof(struct mfi_ld_info);
1212 uint8_t cdb[6];
1213 SCSIRequest *req;
1214 ssize_t len, resid;
1215 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1216 uint64_t ld_size;
1217
1218 if (!cmd->iov_buf) {
1219 cmd->iov_buf = g_malloc0(dcmd_size);
1220 info = cmd->iov_buf;
1221 megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1222 req = scsi_req_new(sdev, cmd->index, lun, cdb, cmd);
1223 if (!req) {
1224 trace_megasas_dcmd_req_alloc_failed(cmd->index,
1225 "LD get info vpd inquiry");
1226 g_free(cmd->iov_buf);
1227 cmd->iov_buf = NULL;
1228 return MFI_STAT_FLASH_ALLOC_FAIL;
1229 }
1230 trace_megasas_dcmd_internal_submit(cmd->index,
1231 "LD get info vpd inquiry", lun);
1232 len = scsi_req_enqueue(req);
1233 if (len > 0) {
1234 cmd->iov_size = len;
1235 scsi_req_continue(req);
1236 }
1237 return MFI_STAT_INVALID_STATUS;
1238 }
1239
1240 info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1241 info->ld_config.properties.ld.v.target_id = lun;
1242 info->ld_config.params.stripe_size = 3;
1243 info->ld_config.params.num_drives = 1;
1244 info->ld_config.params.is_consistent = 1;
1245 /* Logical device size is in blocks */
1246 blk_get_geometry(sdev->conf.blk, &ld_size);
1247 info->size = cpu_to_le64(ld_size);
1248 memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1249 info->ld_config.span[0].start_block = 0;
1250 info->ld_config.span[0].num_blocks = info->size;
1251 info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1252
1253 resid = dma_buf_read(cmd->iov_buf, dcmd_size, &cmd->qsg);
1254 g_free(cmd->iov_buf);
1255 cmd->iov_size = dcmd_size - resid;
1256 cmd->iov_buf = NULL;
1257 return MFI_STAT_OK;
1258 }
1259
1260 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1261 {
1262 struct mfi_ld_info info;
1263 size_t dcmd_size = sizeof(info);
1264 uint16_t ld_id;
1265 uint32_t max_ld_disks = s->fw_luns;
1266 SCSIDevice *sdev = NULL;
1267 int retval = MFI_STAT_DEVICE_NOT_FOUND;
1268
1269 if (cmd->iov_size < dcmd_size) {
1270 return MFI_STAT_INVALID_PARAMETER;
1271 }
1272
1273 /* mbox0 has the ID */
1274 ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1275 trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1276
1277 if (megasas_is_jbod(s)) {
1278 return MFI_STAT_DEVICE_NOT_FOUND;
1279 }
1280
1281 if (ld_id < max_ld_disks) {
1282 sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1283 }
1284
1285 if (sdev) {
1286 retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1287 }
1288
1289 return retval;
1290 }
1291
1292 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1293 {
1294 uint8_t data[4096] = { 0 };
1295 struct mfi_config_data *info;
1296 int num_pd_disks = 0, array_offset, ld_offset;
1297 BusChild *kid;
1298
1299 if (cmd->iov_size > 4096) {
1300 return MFI_STAT_INVALID_PARAMETER;
1301 }
1302
1303 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1304 num_pd_disks++;
1305 }
1306 info = (struct mfi_config_data *)&data;
1307 /*
1308 * Array mapping:
1309 * - One array per SCSI device
1310 * - One logical drive per SCSI device
1311 * spanning the entire device
1312 */
1313 info->array_count = num_pd_disks;
1314 info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1315 info->log_drv_count = num_pd_disks;
1316 info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1317 info->spares_count = 0;
1318 info->spares_size = sizeof(struct mfi_spare);
1319 info->size = sizeof(struct mfi_config_data) + info->array_size +
1320 info->log_drv_size;
1321 if (info->size > 4096) {
1322 return MFI_STAT_INVALID_PARAMETER;
1323 }
1324
1325 array_offset = sizeof(struct mfi_config_data);
1326 ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1327
1328 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1329 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1330 uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1331 struct mfi_array *array;
1332 struct mfi_ld_config *ld;
1333 uint64_t pd_size;
1334 int i;
1335
1336 array = (struct mfi_array *)(data + array_offset);
1337 blk_get_geometry(sdev->conf.blk, &pd_size);
1338 array->size = cpu_to_le64(pd_size);
1339 array->num_drives = 1;
1340 array->array_ref = cpu_to_le16(sdev_id);
1341 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1342 array->pd[0].ref.v.seq_num = 0;
1343 array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1344 array->pd[0].encl.pd = 0xFF;
1345 array->pd[0].encl.slot = (sdev->id & 0xFF);
1346 for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1347 array->pd[i].ref.v.device_id = 0xFFFF;
1348 array->pd[i].ref.v.seq_num = 0;
1349 array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1350 array->pd[i].encl.pd = 0xFF;
1351 array->pd[i].encl.slot = 0xFF;
1352 }
1353 array_offset += sizeof(struct mfi_array);
1354 ld = (struct mfi_ld_config *)(data + ld_offset);
1355 memset(ld, 0, sizeof(struct mfi_ld_config));
1356 ld->properties.ld.v.target_id = sdev->id;
1357 ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1358 MR_LD_CACHE_READ_ADAPTIVE;
1359 ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1360 MR_LD_CACHE_READ_ADAPTIVE;
1361 ld->params.state = MFI_LD_STATE_OPTIMAL;
1362 ld->params.stripe_size = 3;
1363 ld->params.num_drives = 1;
1364 ld->params.span_depth = 1;
1365 ld->params.is_consistent = 1;
1366 ld->span[0].start_block = 0;
1367 ld->span[0].num_blocks = cpu_to_le64(pd_size);
1368 ld->span[0].array_ref = cpu_to_le16(sdev_id);
1369 ld_offset += sizeof(struct mfi_ld_config);
1370 }
1371
1372 cmd->iov_size -= dma_buf_read((uint8_t *)data, info->size, &cmd->qsg);
1373 return MFI_STAT_OK;
1374 }
1375
1376 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1377 {
1378 struct mfi_ctrl_props info;
1379 size_t dcmd_size = sizeof(info);
1380
1381 memset(&info, 0x0, dcmd_size);
1382 if (cmd->iov_size < dcmd_size) {
1383 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1384 dcmd_size);
1385 return MFI_STAT_INVALID_PARAMETER;
1386 }
1387 info.pred_fail_poll_interval = cpu_to_le16(300);
1388 info.intr_throttle_cnt = cpu_to_le16(16);
1389 info.intr_throttle_timeout = cpu_to_le16(50);
1390 info.rebuild_rate = 30;
1391 info.patrol_read_rate = 30;
1392 info.bgi_rate = 30;
1393 info.cc_rate = 30;
1394 info.recon_rate = 30;
1395 info.cache_flush_interval = 4;
1396 info.spinup_drv_cnt = 2;
1397 info.spinup_delay = 6;
1398 info.ecc_bucket_size = 15;
1399 info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1400 info.expose_encl_devices = 1;
1401
1402 cmd->iov_size -= dma_buf_read((uint8_t *)&info, dcmd_size, &cmd->qsg);
1403 return MFI_STAT_OK;
1404 }
1405
1406 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1407 {
1408 blk_drain_all();
1409 return MFI_STAT_OK;
1410 }
1411
1412 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1413 {
1414 s->fw_state = MFI_FWSTATE_READY;
1415 return MFI_STAT_OK;
1416 }
1417
1418 /* Some implementations use CLUSTER RESET LD to simulate a device reset */
1419 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1420 {
1421 uint16_t target_id;
1422 int i;
1423
1424 /* mbox0 contains the device index */
1425 target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1426 trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1427 for (i = 0; i < s->fw_cmds; i++) {
1428 MegasasCmd *tmp_cmd = &s->frames[i];
1429 if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1430 SCSIDevice *d = tmp_cmd->req->dev;
1431 qdev_reset_all(&d->qdev);
1432 }
1433 }
1434 return MFI_STAT_OK;
1435 }
1436
1437 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1438 {
1439 struct mfi_ctrl_props info;
1440 size_t dcmd_size = sizeof(info);
1441
1442 if (cmd->iov_size < dcmd_size) {
1443 trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1444 dcmd_size);
1445 return MFI_STAT_INVALID_PARAMETER;
1446 }
1447 dma_buf_write((uint8_t *)&info, dcmd_size, &cmd->qsg);
1448 trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1449 return MFI_STAT_OK;
1450 }
1451
1452 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1453 {
1454 trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1455 return MFI_STAT_OK;
1456 }
1457
1458 static const struct dcmd_cmd_tbl_t {
1459 int opcode;
1460 const char *desc;
1461 int (*func)(MegasasState *s, MegasasCmd *cmd);
1462 } dcmd_cmd_tbl[] = {
1463 { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1464 megasas_dcmd_dummy },
1465 { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1466 megasas_ctrl_get_info },
1467 { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1468 megasas_dcmd_get_properties },
1469 { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1470 megasas_dcmd_set_properties },
1471 { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1472 megasas_dcmd_dummy },
1473 { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1474 megasas_dcmd_dummy },
1475 { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1476 megasas_dcmd_dummy },
1477 { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1478 megasas_dcmd_dummy },
1479 { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1480 megasas_dcmd_dummy },
1481 { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1482 megasas_event_info },
1483 { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1484 megasas_dcmd_dummy },
1485 { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1486 megasas_event_wait },
1487 { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1488 megasas_ctrl_shutdown },
1489 { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1490 megasas_dcmd_dummy },
1491 { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1492 megasas_dcmd_get_fw_time },
1493 { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1494 megasas_dcmd_set_fw_time },
1495 { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1496 megasas_dcmd_get_bios_info },
1497 { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1498 megasas_dcmd_dummy },
1499 { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1500 megasas_mfc_get_defaults },
1501 { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1502 megasas_dcmd_dummy },
1503 { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1504 megasas_cache_flush },
1505 { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1506 megasas_dcmd_pd_get_list },
1507 { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1508 megasas_dcmd_pd_list_query },
1509 { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1510 megasas_dcmd_pd_get_info },
1511 { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1512 megasas_dcmd_dummy },
1513 { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1514 megasas_dcmd_dummy },
1515 { MFI_DCMD_PD_BLINK, "PD_BLINK",
1516 megasas_dcmd_dummy },
1517 { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1518 megasas_dcmd_dummy },
1519 { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1520 megasas_dcmd_ld_get_list},
1521 { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1522 megasas_dcmd_ld_list_query },
1523 { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1524 megasas_dcmd_ld_get_info },
1525 { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1526 megasas_dcmd_dummy },
1527 { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1528 megasas_dcmd_dummy },
1529 { MFI_DCMD_LD_DELETE, "LD_DELETE",
1530 megasas_dcmd_dummy },
1531 { MFI_DCMD_CFG_READ, "CFG_READ",
1532 megasas_dcmd_cfg_read },
1533 { MFI_DCMD_CFG_ADD, "CFG_ADD",
1534 megasas_dcmd_dummy },
1535 { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1536 megasas_dcmd_dummy },
1537 { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1538 megasas_dcmd_dummy },
1539 { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1540 megasas_dcmd_dummy },
1541 { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1542 megasas_dcmd_dummy },
1543 { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1544 megasas_dcmd_dummy },
1545 { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1546 megasas_dcmd_dummy },
1547 { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1548 megasas_dcmd_dummy },
1549 { MFI_DCMD_CLUSTER, "CLUSTER",
1550 megasas_dcmd_dummy },
1551 { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1552 megasas_dcmd_dummy },
1553 { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1554 megasas_cluster_reset_ld },
1555 { -1, NULL, NULL }
1556 };
1557
1558 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1559 {
1560 int opcode, len;
1561 int retval = 0;
1562 const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1563
1564 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1565 trace_megasas_handle_dcmd(cmd->index, opcode);
1566 len = megasas_map_dcmd(s, cmd);
1567 if (len < 0) {
1568 return MFI_STAT_MEMORY_NOT_AVAILABLE;
1569 }
1570 while (cmdptr->opcode != -1 && cmdptr->opcode != opcode) {
1571 cmdptr++;
1572 }
1573 if (cmdptr->opcode == -1) {
1574 trace_megasas_dcmd_unhandled(cmd->index, opcode, len);
1575 retval = megasas_dcmd_dummy(s, cmd);
1576 } else {
1577 trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1578 retval = cmdptr->func(s, cmd);
1579 }
1580 if (retval != MFI_STAT_INVALID_STATUS) {
1581 megasas_finish_dcmd(cmd, len);
1582 }
1583 return retval;
1584 }
1585
1586 static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1587 SCSIRequest *req)
1588 {
1589 int opcode;
1590 int retval = MFI_STAT_OK;
1591 int lun = req->lun;
1592
1593 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1594 scsi_req_unref(req);
1595 trace_megasas_dcmd_internal_finish(cmd->index, opcode, lun);
1596 switch (opcode) {
1597 case MFI_DCMD_PD_GET_INFO:
1598 retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1599 break;
1600 case MFI_DCMD_LD_GET_INFO:
1601 retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1602 break;
1603 default:
1604 trace_megasas_dcmd_internal_invalid(cmd->index, opcode);
1605 retval = MFI_STAT_INVALID_DCMD;
1606 break;
1607 }
1608 if (retval != MFI_STAT_INVALID_STATUS) {
1609 megasas_finish_dcmd(cmd, cmd->iov_size);
1610 }
1611 return retval;
1612 }
1613
1614 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1615 {
1616 int len;
1617
1618 len = scsi_req_enqueue(cmd->req);
1619 if (len < 0) {
1620 len = -len;
1621 }
1622 if (len > 0) {
1623 if (len > cmd->iov_size) {
1624 if (is_write) {
1625 trace_megasas_iov_write_overflow(cmd->index, len,
1626 cmd->iov_size);
1627 } else {
1628 trace_megasas_iov_read_overflow(cmd->index, len,
1629 cmd->iov_size);
1630 }
1631 }
1632 if (len < cmd->iov_size) {
1633 if (is_write) {
1634 trace_megasas_iov_write_underflow(cmd->index, len,
1635 cmd->iov_size);
1636 } else {
1637 trace_megasas_iov_read_underflow(cmd->index, len,
1638 cmd->iov_size);
1639 }
1640 cmd->iov_size = len;
1641 }
1642 scsi_req_continue(cmd->req);
1643 }
1644 return len;
1645 }
1646
1647 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1648 bool is_logical)
1649 {
1650 uint8_t *cdb;
1651 bool is_write;
1652 struct SCSIDevice *sdev = NULL;
1653
1654 cdb = cmd->frame->pass.cdb;
1655
1656 if (is_logical) {
1657 if (cmd->frame->header.target_id >= MFI_MAX_LD ||
1658 cmd->frame->header.lun_id != 0) {
1659 trace_megasas_scsi_target_not_present(
1660 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1661 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1662 return MFI_STAT_DEVICE_NOT_FOUND;
1663 }
1664 }
1665 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1666 cmd->frame->header.lun_id);
1667
1668 cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1669 trace_megasas_handle_scsi(mfi_frame_desc[cmd->frame->header.frame_cmd],
1670 is_logical, cmd->frame->header.target_id,
1671 cmd->frame->header.lun_id, sdev, cmd->iov_size);
1672
1673 if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1674 trace_megasas_scsi_target_not_present(
1675 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1676 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1677 return MFI_STAT_DEVICE_NOT_FOUND;
1678 }
1679
1680 if (cmd->frame->header.cdb_len > 16) {
1681 trace_megasas_scsi_invalid_cdb_len(
1682 mfi_frame_desc[cmd->frame->header.frame_cmd], is_logical,
1683 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1684 cmd->frame->header.cdb_len);
1685 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1686 cmd->frame->header.scsi_status = CHECK_CONDITION;
1687 s->event_count++;
1688 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1689 }
1690
1691 if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1692 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1693 cmd->frame->header.scsi_status = CHECK_CONDITION;
1694 s->event_count++;
1695 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1696 }
1697
1698 cmd->req = scsi_req_new(sdev, cmd->index,
1699 cmd->frame->header.lun_id, cdb, cmd);
1700 if (!cmd->req) {
1701 trace_megasas_scsi_req_alloc_failed(
1702 mfi_frame_desc[cmd->frame->header.frame_cmd],
1703 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1704 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1705 cmd->frame->header.scsi_status = BUSY;
1706 s->event_count++;
1707 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1708 }
1709
1710 is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1711 if (cmd->iov_size) {
1712 if (is_write) {
1713 trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1714 } else {
1715 trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1716 }
1717 } else {
1718 trace_megasas_scsi_nodata(cmd->index);
1719 }
1720 megasas_enqueue_req(cmd, is_write);
1721 return MFI_STAT_INVALID_STATUS;
1722 }
1723
1724 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd)
1725 {
1726 uint32_t lba_count, lba_start_hi, lba_start_lo;
1727 uint64_t lba_start;
1728 bool is_write = (cmd->frame->header.frame_cmd == MFI_CMD_LD_WRITE);
1729 uint8_t cdb[16];
1730 int len;
1731 struct SCSIDevice *sdev = NULL;
1732
1733 lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1734 lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1735 lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1736 lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1737
1738 if (cmd->frame->header.target_id < MFI_MAX_LD &&
1739 cmd->frame->header.lun_id == 0) {
1740 sdev = scsi_device_find(&s->bus, 0, cmd->frame->header.target_id,
1741 cmd->frame->header.lun_id);
1742 }
1743
1744 trace_megasas_handle_io(cmd->index,
1745 mfi_frame_desc[cmd->frame->header.frame_cmd],
1746 cmd->frame->header.target_id,
1747 cmd->frame->header.lun_id,
1748 (unsigned long)lba_start, (unsigned long)lba_count);
1749 if (!sdev) {
1750 trace_megasas_io_target_not_present(cmd->index,
1751 mfi_frame_desc[cmd->frame->header.frame_cmd],
1752 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1753 return MFI_STAT_DEVICE_NOT_FOUND;
1754 }
1755
1756 if (cmd->frame->header.cdb_len > 16) {
1757 trace_megasas_scsi_invalid_cdb_len(
1758 mfi_frame_desc[cmd->frame->header.frame_cmd], 1,
1759 cmd->frame->header.target_id, cmd->frame->header.lun_id,
1760 cmd->frame->header.cdb_len);
1761 megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1762 cmd->frame->header.scsi_status = CHECK_CONDITION;
1763 s->event_count++;
1764 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1765 }
1766
1767 cmd->iov_size = lba_count * sdev->blocksize;
1768 if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1769 megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1770 cmd->frame->header.scsi_status = CHECK_CONDITION;
1771 s->event_count++;
1772 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1773 }
1774
1775 megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1776 cmd->req = scsi_req_new(sdev, cmd->index,
1777 cmd->frame->header.lun_id, cdb, cmd);
1778 if (!cmd->req) {
1779 trace_megasas_scsi_req_alloc_failed(
1780 mfi_frame_desc[cmd->frame->header.frame_cmd],
1781 cmd->frame->header.target_id, cmd->frame->header.lun_id);
1782 megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1783 cmd->frame->header.scsi_status = BUSY;
1784 s->event_count++;
1785 return MFI_STAT_SCSI_DONE_WITH_ERROR;
1786 }
1787 len = megasas_enqueue_req(cmd, is_write);
1788 if (len > 0) {
1789 if (is_write) {
1790 trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1791 } else {
1792 trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1793 }
1794 }
1795 return MFI_STAT_INVALID_STATUS;
1796 }
1797
1798 static int megasas_finish_internal_command(MegasasCmd *cmd,
1799 SCSIRequest *req, size_t resid)
1800 {
1801 int retval = MFI_STAT_INVALID_CMD;
1802
1803 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1804 cmd->iov_size -= resid;
1805 retval = megasas_finish_internal_dcmd(cmd, req);
1806 }
1807 return retval;
1808 }
1809
1810 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1811 {
1812 MegasasCmd *cmd = req->hba_private;
1813
1814 if (cmd->frame->header.frame_cmd == MFI_CMD_DCMD) {
1815 return NULL;
1816 } else {
1817 return &cmd->qsg;
1818 }
1819 }
1820
1821 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1822 {
1823 MegasasCmd *cmd = req->hba_private;
1824 uint8_t *buf;
1825 uint32_t opcode;
1826
1827 trace_megasas_io_complete(cmd->index, len);
1828
1829 if (cmd->frame->header.frame_cmd != MFI_CMD_DCMD) {
1830 scsi_req_continue(req);
1831 return;
1832 }
1833
1834 buf = scsi_req_get_buf(req);
1835 opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1836 if (opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1837 struct mfi_pd_info *info = cmd->iov_buf;
1838
1839 if (info->inquiry_data[0] == 0x7f) {
1840 memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1841 memcpy(info->inquiry_data, buf, len);
1842 } else if (info->vpd_page83[0] == 0x7f) {
1843 memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1844 memcpy(info->vpd_page83, buf, len);
1845 }
1846 scsi_req_continue(req);
1847 } else if (opcode == MFI_DCMD_LD_GET_INFO) {
1848 struct mfi_ld_info *info = cmd->iov_buf;
1849
1850 if (cmd->iov_buf) {
1851 memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1852 scsi_req_continue(req);
1853 }
1854 }
1855 }
1856
1857 static void megasas_command_complete(SCSIRequest *req, uint32_t status,
1858 size_t resid)
1859 {
1860 MegasasCmd *cmd = req->hba_private;
1861 uint8_t cmd_status = MFI_STAT_OK;
1862
1863 trace_megasas_command_complete(cmd->index, status, resid);
1864
1865 if (cmd->req != req) {
1866 /*
1867 * Internal command complete
1868 */
1869 cmd_status = megasas_finish_internal_command(cmd, req, resid);
1870 if (cmd_status == MFI_STAT_INVALID_STATUS) {
1871 return;
1872 }
1873 } else {
1874 req->status = status;
1875 trace_megasas_scsi_complete(cmd->index, req->status,
1876 cmd->iov_size, req->cmd.xfer);
1877 if (req->status != GOOD) {
1878 cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1879 }
1880 if (req->status == CHECK_CONDITION) {
1881 megasas_copy_sense(cmd);
1882 }
1883
1884 megasas_unmap_sgl(cmd);
1885 cmd->frame->header.scsi_status = req->status;
1886 scsi_req_unref(cmd->req);
1887 cmd->req = NULL;
1888 }
1889 cmd->frame->header.cmd_status = cmd_status;
1890 megasas_unmap_frame(cmd->state, cmd);
1891 megasas_complete_frame(cmd->state, cmd->context);
1892 }
1893
1894 static void megasas_command_cancel(SCSIRequest *req)
1895 {
1896 MegasasCmd *cmd = req->hba_private;
1897
1898 if (cmd) {
1899 megasas_abort_command(cmd);
1900 } else {
1901 scsi_req_unref(req);
1902 }
1903 }
1904
1905 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1906 {
1907 uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1908 hwaddr abort_addr, addr_hi, addr_lo;
1909 MegasasCmd *abort_cmd;
1910
1911 addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1912 addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1913 abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1914
1915 abort_cmd = megasas_lookup_frame(s, abort_addr);
1916 if (!abort_cmd) {
1917 trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1918 s->event_count++;
1919 return MFI_STAT_OK;
1920 }
1921 if (!megasas_use_queue64(s)) {
1922 abort_ctx &= (uint64_t)0xFFFFFFFF;
1923 }
1924 if (abort_cmd->context != abort_ctx) {
1925 trace_megasas_abort_invalid_context(cmd->index, abort_cmd->index,
1926 abort_cmd->context);
1927 s->event_count++;
1928 return MFI_STAT_ABORT_NOT_POSSIBLE;
1929 }
1930 trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1931 megasas_abort_command(abort_cmd);
1932 if (!s->event_cmd || abort_cmd != s->event_cmd) {
1933 s->event_cmd = NULL;
1934 }
1935 s->event_count++;
1936 return MFI_STAT_OK;
1937 }
1938
1939 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1940 uint32_t frame_count)
1941 {
1942 uint8_t frame_status = MFI_STAT_INVALID_CMD;
1943 uint64_t frame_context;
1944 MegasasCmd *cmd;
1945
1946 /*
1947 * Always read 64bit context, top bits will be
1948 * masked out if required in megasas_enqueue_frame()
1949 */
1950 frame_context = megasas_frame_get_context(s, frame_addr);
1951
1952 cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1953 if (!cmd) {
1954 /* reply queue full */
1955 trace_megasas_frame_busy(frame_addr);
1956 megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1957 megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1958 megasas_complete_frame(s, frame_context);
1959 s->event_count++;
1960 return;
1961 }
1962 switch (cmd->frame->header.frame_cmd) {
1963 case MFI_CMD_INIT:
1964 frame_status = megasas_init_firmware(s, cmd);
1965 break;
1966 case MFI_CMD_DCMD:
1967 frame_status = megasas_handle_dcmd(s, cmd);
1968 break;
1969 case MFI_CMD_ABORT:
1970 frame_status = megasas_handle_abort(s, cmd);
1971 break;
1972 case MFI_CMD_PD_SCSI_IO:
1973 frame_status = megasas_handle_scsi(s, cmd, 0);
1974 break;
1975 case MFI_CMD_LD_SCSI_IO:
1976 frame_status = megasas_handle_scsi(s, cmd, 1);
1977 break;
1978 case MFI_CMD_LD_READ:
1979 case MFI_CMD_LD_WRITE:
1980 frame_status = megasas_handle_io(s, cmd);
1981 break;
1982 default:
1983 trace_megasas_unhandled_frame_cmd(cmd->index,
1984 cmd->frame->header.frame_cmd);
1985 s->event_count++;
1986 break;
1987 }
1988 if (frame_status != MFI_STAT_INVALID_STATUS) {
1989 if (cmd->frame) {
1990 cmd->frame->header.cmd_status = frame_status;
1991 } else {
1992 megasas_frame_set_cmd_status(s, frame_addr, frame_status);
1993 }
1994 megasas_unmap_frame(s, cmd);
1995 megasas_complete_frame(s, cmd->context);
1996 }
1997 }
1998
1999 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
2000 unsigned size)
2001 {
2002 MegasasState *s = opaque;
2003 PCIDevice *pci_dev = PCI_DEVICE(s);
2004 MegasasBaseClass *base_class = MEGASAS_DEVICE_GET_CLASS(s);
2005 uint32_t retval = 0;
2006
2007 switch (addr) {
2008 case MFI_IDB:
2009 retval = 0;
2010 trace_megasas_mmio_readl("MFI_IDB", retval);
2011 break;
2012 case MFI_OMSG0:
2013 case MFI_OSP0:
2014 retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
2015 (s->fw_state & MFI_FWSTATE_MASK) |
2016 ((s->fw_sge & 0xff) << 16) |
2017 (s->fw_cmds & 0xFFFF);
2018 trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2019 retval);
2020 break;
2021 case MFI_OSTS:
2022 if (megasas_intr_enabled(s) && s->doorbell) {
2023 retval = base_class->osts;
2024 }
2025 trace_megasas_mmio_readl("MFI_OSTS", retval);
2026 break;
2027 case MFI_OMSK:
2028 retval = s->intr_mask;
2029 trace_megasas_mmio_readl("MFI_OMSK", retval);
2030 break;
2031 case MFI_ODCR0:
2032 retval = s->doorbell ? 1 : 0;
2033 trace_megasas_mmio_readl("MFI_ODCR0", retval);
2034 break;
2035 case MFI_DIAG:
2036 retval = s->diag;
2037 trace_megasas_mmio_readl("MFI_DIAG", retval);
2038 break;
2039 case MFI_OSP1:
2040 retval = 15;
2041 trace_megasas_mmio_readl("MFI_OSP1", retval);
2042 break;
2043 default:
2044 trace_megasas_mmio_invalid_readl(addr);
2045 break;
2046 }
2047 return retval;
2048 }
2049
2050 static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2051
2052 static void megasas_mmio_write(void *opaque, hwaddr addr,
2053 uint64_t val, unsigned size)
2054 {
2055 MegasasState *s = opaque;
2056 PCIDevice *pci_dev = PCI_DEVICE(s);
2057 uint64_t frame_addr;
2058 uint32_t frame_count;
2059 int i;
2060
2061 switch (addr) {
2062 case MFI_IDB:
2063 trace_megasas_mmio_writel("MFI_IDB", val);
2064 if (val & MFI_FWINIT_ABORT) {
2065 /* Abort all pending cmds */
2066 for (i = 0; i < s->fw_cmds; i++) {
2067 megasas_abort_command(&s->frames[i]);
2068 }
2069 }
2070 if (val & MFI_FWINIT_READY) {
2071 /* move to FW READY */
2072 megasas_soft_reset(s);
2073 }
2074 if (val & MFI_FWINIT_MFIMODE) {
2075 /* discard MFIs */
2076 }
2077 if (val & MFI_FWINIT_STOP_ADP) {
2078 /* Terminal error, stop processing */
2079 s->fw_state = MFI_FWSTATE_FAULT;
2080 }
2081 break;
2082 case MFI_OMSK:
2083 trace_megasas_mmio_writel("MFI_OMSK", val);
2084 s->intr_mask = val;
2085 if (!megasas_intr_enabled(s) &&
2086 !msi_enabled(pci_dev) &&
2087 !msix_enabled(pci_dev)) {
2088 trace_megasas_irq_lower();
2089 pci_irq_deassert(pci_dev);
2090 }
2091 if (megasas_intr_enabled(s)) {
2092 if (msix_enabled(pci_dev)) {
2093 trace_megasas_msix_enabled(0);
2094 } else if (msi_enabled(pci_dev)) {
2095 trace_megasas_msi_enabled(0);
2096 } else {
2097 trace_megasas_intr_enabled();
2098 }
2099 } else {
2100 trace_megasas_intr_disabled();
2101 megasas_soft_reset(s);
2102 }
2103 break;
2104 case MFI_ODCR0:
2105 trace_megasas_mmio_writel("MFI_ODCR0", val);
2106 s->doorbell = 0;
2107 if (megasas_intr_enabled(s)) {
2108 if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2109 trace_megasas_irq_lower();
2110 pci_irq_deassert(pci_dev);
2111 }
2112 }
2113 break;
2114 case MFI_IQPH:
2115 trace_megasas_mmio_writel("MFI_IQPH", val);
2116 /* Received high 32 bits of a 64 bit MFI frame address */
2117 s->frame_hi = val;
2118 break;
2119 case MFI_IQPL:
2120 trace_megasas_mmio_writel("MFI_IQPL", val);
2121 /* Received low 32 bits of a 64 bit MFI frame address */
2122 /* Fallthrough */
2123 case MFI_IQP:
2124 if (addr == MFI_IQP) {
2125 trace_megasas_mmio_writel("MFI_IQP", val);
2126 /* Received 64 bit MFI frame address */
2127 s->frame_hi = 0;
2128 }
2129 frame_addr = (val & ~0x1F);
2130 /* Add possible 64 bit offset */
2131 frame_addr |= ((uint64_t)s->frame_hi << 32);
2132 s->frame_hi = 0;
2133 frame_count = (val >> 1) & 0xF;
2134 megasas_handle_frame(s, frame_addr, frame_count);
2135 break;
2136 case MFI_SEQ:
2137 trace_megasas_mmio_writel("MFI_SEQ", val);
2138 /* Magic sequence to start ADP reset */
2139 if (adp_reset_seq[s->adp_reset] == val) {
2140 s->adp_reset++;
2141 } else {
2142 s->adp_reset = 0;
2143 s->diag = 0;
2144 }
2145 if (s->adp_reset == 6) {
2146 s->diag = MFI_DIAG_WRITE_ENABLE;
2147 }
2148 break;
2149 case MFI_DIAG:
2150 trace_megasas_mmio_writel("MFI_DIAG", val);
2151 /* ADP reset */
2152 if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2153 (val & MFI_DIAG_RESET_ADP)) {
2154 s->diag |= MFI_DIAG_RESET_ADP;
2155 megasas_soft_reset(s);
2156 s->adp_reset = 0;
2157 s->diag = 0;
2158 }
2159 break;
2160 default:
2161 trace_megasas_mmio_invalid_writel(addr, val);
2162 break;
2163 }
2164 }
2165
2166 static const MemoryRegionOps megasas_mmio_ops = {
2167 .read = megasas_mmio_read,
2168 .write = megasas_mmio_write,
2169 .endianness = DEVICE_LITTLE_ENDIAN,
2170 .impl = {
2171 .min_access_size = 8,
2172 .max_access_size = 8,
2173 }
2174 };
2175
2176 static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2177 unsigned size)
2178 {
2179 return megasas_mmio_read(opaque, addr & 0xff, size);
2180 }
2181
2182 static void megasas_port_write(void *opaque, hwaddr addr,
2183 uint64_t val, unsigned size)
2184 {
2185 megasas_mmio_write(opaque, addr & 0xff, val, size);
2186 }
2187
2188 static const MemoryRegionOps megasas_port_ops = {
2189 .read = megasas_port_read,
2190 .write = megasas_port_write,
2191 .endianness = DEVICE_LITTLE_ENDIAN,
2192 .impl = {
2193 .min_access_size = 4,
2194 .max_access_size = 4,
2195 }
2196 };
2197
2198 static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2199 unsigned size)
2200 {
2201 return 0;
2202 }
2203
2204 static void megasas_queue_write(void *opaque, hwaddr addr,
2205 uint64_t val, unsigned size)
2206 {
2207 return;
2208 }
2209
2210 static const MemoryRegionOps megasas_queue_ops = {
2211 .read = megasas_queue_read,
2212 .write = megasas_queue_write,
2213 .endianness = DEVICE_LITTLE_ENDIAN,
2214 .impl = {
2215 .min_access_size = 8,
2216 .max_access_size = 8,
2217 }
2218 };
2219
2220 static void megasas_soft_reset(MegasasState *s)
2221 {
2222 int i;
2223 MegasasCmd *cmd;
2224
2225 trace_megasas_reset(s->fw_state);
2226 for (i = 0; i < s->fw_cmds; i++) {
2227 cmd = &s->frames[i];
2228 megasas_abort_command(cmd);
2229 }
2230 if (s->fw_state == MFI_FWSTATE_READY) {
2231 BusChild *kid;
2232
2233 /*
2234 * The EFI firmware doesn't handle UA,
2235 * so we need to clear the Power On/Reset UA
2236 * after the initial reset.
2237 */
2238 QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2239 SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2240
2241 sdev->unit_attention = SENSE_CODE(NO_SENSE);
2242 scsi_device_unit_attention_reported(sdev);
2243 }
2244 }
2245 megasas_reset_frames(s);
2246 s->reply_queue_len = s->fw_cmds;
2247 s->reply_queue_pa = 0;
2248 s->consumer_pa = 0;
2249 s->producer_pa = 0;
2250 s->fw_state = MFI_FWSTATE_READY;
2251 s->doorbell = 0;
2252 s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2253 s->frame_hi = 0;
2254 s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2255 s->event_count++;
2256 s->boot_event = s->event_count;
2257 }
2258
2259 static void megasas_scsi_reset(DeviceState *dev)
2260 {
2261 MegasasState *s = MEGASAS(dev);
2262
2263 megasas_soft_reset(s);
2264 }
2265
2266 static const VMStateDescription vmstate_megasas_gen1 = {
2267 .name = "megasas",
2268 .version_id = 0,
2269 .minimum_version_id = 0,
2270 .fields = (VMStateField[]) {
2271 VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2272 VMSTATE_MSIX(parent_obj, MegasasState),
2273
2274 VMSTATE_INT32(fw_state, MegasasState),
2275 VMSTATE_INT32(intr_mask, MegasasState),
2276 VMSTATE_INT32(doorbell, MegasasState),
2277 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2278 VMSTATE_UINT64(consumer_pa, MegasasState),
2279 VMSTATE_UINT64(producer_pa, MegasasState),
2280 VMSTATE_END_OF_LIST()
2281 }
2282 };
2283
2284 static const VMStateDescription vmstate_megasas_gen2 = {
2285 .name = "megasas-gen2",
2286 .version_id = 0,
2287 .minimum_version_id = 0,
2288 .minimum_version_id_old = 0,
2289 .fields = (VMStateField[]) {
2290 VMSTATE_PCIE_DEVICE(parent_obj, MegasasState),
2291 VMSTATE_MSIX(parent_obj, MegasasState),
2292
2293 VMSTATE_INT32(fw_state, MegasasState),
2294 VMSTATE_INT32(intr_mask, MegasasState),
2295 VMSTATE_INT32(doorbell, MegasasState),
2296 VMSTATE_UINT64(reply_queue_pa, MegasasState),
2297 VMSTATE_UINT64(consumer_pa, MegasasState),
2298 VMSTATE_UINT64(producer_pa, MegasasState),
2299 VMSTATE_END_OF_LIST()
2300 }
2301 };
2302
2303 static void megasas_scsi_uninit(PCIDevice *d)
2304 {
2305 MegasasState *s = MEGASAS(d);
2306
2307 if (megasas_use_msix(s)) {
2308 msix_uninit(d, &s->mmio_io, &s->mmio_io);
2309 }
2310 if (megasas_use_msi(s)) {
2311 msi_uninit(d);
2312 }
2313 }
2314
2315 static const struct SCSIBusInfo megasas_scsi_info = {
2316 .tcq = true,
2317 .max_target = MFI_MAX_LD,
2318 .max_lun = 255,
2319
2320 .transfer_data = megasas_xfer_complete,
2321 .get_sg_list = megasas_get_sg_list,
2322 .complete = megasas_command_complete,
2323 .cancel = megasas_command_cancel,
2324 };
2325
2326 static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2327 {
2328 DeviceState *d = DEVICE(dev);
2329 MegasasState *s = MEGASAS(dev);
2330 MegasasBaseClass *b = MEGASAS_DEVICE_GET_CLASS(s);
2331 uint8_t *pci_conf;
2332 int i, bar_type;
2333
2334 pci_conf = dev->config;
2335
2336 /* PCI latency timer = 0 */
2337 pci_conf[PCI_LATENCY_TIMER] = 0;
2338 /* Interrupt pin 1 */
2339 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2340
2341 memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2342 "megasas-mmio", 0x4000);
2343 memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2344 "megasas-io", 256);
2345 memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2346 "megasas-queue", 0x40000);
2347
2348 if (megasas_use_msi(s) &&
2349 msi_init(dev, 0x50, 1, true, false)) {
2350 s->msi = ON_OFF_AUTO_OFF;
2351 }
2352 if (megasas_use_msix(s) &&
2353 msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2354 &s->mmio_io, b->mmio_bar, 0x3800, 0x68)) {
2355 s->msix = ON_OFF_AUTO_OFF;
2356 }
2357 if (pci_is_express(dev)) {
2358 pcie_endpoint_cap_init(dev, 0xa0);
2359 }
2360
2361 bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2362 pci_register_bar(dev, b->ioport_bar,
2363 PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2364 pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2365 pci_register_bar(dev, 3, bar_type, &s->queue_io);
2366
2367 if (megasas_use_msix(s)) {
2368 msix_vector_use(dev, 0);
2369 }
2370
2371 s->fw_state = MFI_FWSTATE_READY;
2372 if (!s->sas_addr) {
2373 s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2374 IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2375 s->sas_addr |= (pci_bus_num(dev->bus) << 16);
2376 s->sas_addr |= (PCI_SLOT(dev->devfn) << 8);
2377 s->sas_addr |= PCI_FUNC(dev->devfn);
2378 }
2379 if (!s->hba_serial) {
2380 s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2381 }
2382 if (s->fw_sge >= MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE) {
2383 s->fw_sge = MEGASAS_MAX_SGE - MFI_PASS_FRAME_SIZE;
2384 } else if (s->fw_sge >= 128 - MFI_PASS_FRAME_SIZE) {
2385 s->fw_sge = 128 - MFI_PASS_FRAME_SIZE;
2386 } else {
2387 s->fw_sge = 64 - MFI_PASS_FRAME_SIZE;
2388 }
2389 if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2390 s->fw_cmds = MEGASAS_MAX_FRAMES;
2391 }
2392 trace_megasas_init(s->fw_sge, s->fw_cmds,
2393 megasas_is_jbod(s) ? "jbod" : "raid");
2394
2395 if (megasas_is_jbod(s)) {
2396 s->fw_luns = MFI_MAX_SYS_PDS;
2397 } else {
2398 s->fw_luns = MFI_MAX_LD;
2399 }
2400 s->producer_pa = 0;
2401 s->consumer_pa = 0;
2402 for (i = 0; i < s->fw_cmds; i++) {
2403 s->frames[i].index = i;
2404 s->frames[i].context = -1;
2405 s->frames[i].pa = 0;
2406 s->frames[i].state = s;
2407 }
2408
2409 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(dev),
2410 &megasas_scsi_info, NULL);
2411 if (!d->hotplugged) {
2412 scsi_bus_legacy_handle_cmdline(&s->bus, errp);
2413 }
2414 }
2415
2416 static Property megasas_properties_gen1[] = {
2417 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2418 MEGASAS_DEFAULT_SGE),
2419 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2420 MEGASAS_DEFAULT_FRAMES),
2421 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2422 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2423 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2424 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2425 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2426 MEGASAS_FLAG_USE_JBOD, false),
2427 DEFINE_PROP_END_OF_LIST(),
2428 };
2429
2430 static Property megasas_properties_gen2[] = {
2431 DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2432 MEGASAS_DEFAULT_SGE),
2433 DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2434 MEGASAS_GEN2_DEFAULT_FRAMES),
2435 DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2436 DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2437 DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2438 DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2439 DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2440 MEGASAS_FLAG_USE_JBOD, false),
2441 DEFINE_PROP_END_OF_LIST(),
2442 };
2443
2444 typedef struct MegasasInfo {
2445 const char *name;
2446 const char *desc;
2447 const char *product_name;
2448 const char *product_version;
2449 uint16_t device_id;
2450 uint16_t subsystem_id;
2451 int ioport_bar;
2452 int mmio_bar;
2453 bool is_express;
2454 int osts;
2455 const VMStateDescription *vmsd;
2456 Property *props;
2457 } MegasasInfo;
2458
2459 static struct MegasasInfo megasas_devices[] = {
2460 {
2461 .name = TYPE_MEGASAS_GEN1,
2462 .desc = "LSI MegaRAID SAS 1078",
2463 .product_name = "LSI MegaRAID SAS 8708EM2",
2464 .product_version = MEGASAS_VERSION_GEN1,
2465 .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2466 .subsystem_id = 0x1013,
2467 .ioport_bar = 2,
2468 .mmio_bar = 0,
2469 .osts = MFI_1078_RM | 1,
2470 .is_express = false,
2471 .vmsd = &vmstate_megasas_gen1,
2472 .props = megasas_properties_gen1,
2473 },{
2474 .name = TYPE_MEGASAS_GEN2,
2475 .desc = "LSI MegaRAID SAS 2108",
2476 .product_name = "LSI MegaRAID SAS 9260-8i",
2477 .product_version = MEGASAS_VERSION_GEN2,
2478 .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2479 .subsystem_id = 0x9261,
2480 .ioport_bar = 0,
2481 .mmio_bar = 1,
2482 .osts = MFI_GEN2_RM,
2483 .is_express = true,
2484 .vmsd = &vmstate_megasas_gen2,
2485 .props = megasas_properties_gen2,
2486 }
2487 };
2488
2489 static void megasas_class_init(ObjectClass *oc, void *data)
2490 {
2491 DeviceClass *dc = DEVICE_CLASS(oc);
2492 PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2493 MegasasBaseClass *e = MEGASAS_DEVICE_CLASS(oc);
2494 const MegasasInfo *info = data;
2495
2496 pc->realize = megasas_scsi_realize;
2497 pc->exit = megasas_scsi_uninit;
2498 pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2499 pc->device_id = info->device_id;
2500 pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2501 pc->subsystem_id = info->subsystem_id;
2502 pc->class_id = PCI_CLASS_STORAGE_RAID;
2503 pc->is_express = info->is_express;
2504 e->mmio_bar = info->mmio_bar;
2505 e->ioport_bar = info->ioport_bar;
2506 e->osts = info->osts;
2507 e->product_name = info->product_name;
2508 e->product_version = info->product_version;
2509 dc->props = info->props;
2510 dc->reset = megasas_scsi_reset;
2511 dc->vmsd = info->vmsd;
2512 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2513 dc->desc = info->desc;
2514 }
2515
2516 static const TypeInfo megasas_info = {
2517 .name = TYPE_MEGASAS_BASE,
2518 .parent = TYPE_PCI_DEVICE,
2519 .instance_size = sizeof(MegasasState),
2520 .class_size = sizeof(MegasasBaseClass),
2521 .abstract = true,
2522 };
2523
2524 static void megasas_register_types(void)
2525 {
2526 int i;
2527
2528 type_register_static(&megasas_info);
2529 for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2530 const MegasasInfo *info = &megasas_devices[i];
2531 TypeInfo type_info = {};
2532
2533 type_info.name = info->name;
2534 type_info.parent = TYPE_MEGASAS_BASE;
2535 type_info.class_data = (void *)info;
2536 type_info.class_init = megasas_class_init;
2537
2538 type_register(&type_info);
2539 }
2540 }
2541
2542 type_init(megasas_register_types)
AR7 emulation for QEMU