user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "exec/exec-all.h"
  23 #include "tcg.h"
  24 #include "qemu/bitops.h"
  25 #include "exec/cpu_ldst.h"
  26 #include "translate-all.h"
  27
  28 #undef EAX
  29 #undef ECX
  30 #undef EDX
  31 #undef EBX
  32 #undef ESP
  33 #undef EBP
  34 #undef ESI
  35 #undef EDI
  36 #undef EIP
  37 #ifdef __linux__
  38 #include <sys/ucontext.h>
  39 #endif
  40
  41 //#define DEBUG_SIGNAL
  42
  43 /* exit the current TB from a signal handler. The host registers are
  44    restored in a state compatible with the CPU emulator
  45  */
  46 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
  47 {
  48     /* XXX: use siglongjmp ? */
  49     sigprocmask(SIG_SETMASK, old_set, NULL);
  50     cpu_loop_exit_noexc(cpu);
  51 }
  52
  53 /* 'pc' is the host PC at which the exception was raised. 'address' is
  54    the effective address of the memory exception. 'is_write' is 1 if a
  55    write caused the exception and otherwise 0'. 'old_set' is the
  56    signal set which should be restored */
  57 static inline int handle_cpu_signal(uintptr_t pc, void *ptr,
  58                                     int is_write, sigset_t *old_set)
  59 {
  60     uintptr_t address = (uintptr_t)ptr;
  61     CPUState *cpu;
  62     CPUClass *cc;
  63     int ret;
  64
  65 #if defined(DEBUG_SIGNAL)
  66     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
  67            pc, address, is_write, *(unsigned long *)old_set);
  68 #endif
  69     /* XXX: locking issue */
  70     if (is_write && h2g_valid(address)) {
  71         switch (page_unprotect(h2g(address), pc)) {
  72         case 0:
  73             /* Fault not caused by a page marked unwritable to protect
  74              * cached translations, must be the guest binary's problem
  75              */
  76             break;
  77         case 1:
  78             /* Fault caused by protection of cached translation; TBs
  79              * invalidated, so resume execution
  80              */
  81             return 1;
  82         case 2:
  83             /* Fault caused by protection of cached translation, and the
  84              * currently executing TB was modified and must be exited
  85              * immediately.
  86              */
  87             cpu_exit_tb_from_sighandler(current_cpu, old_set);
  88             g_assert_not_reached();
  89         default:
  90             g_assert_not_reached();
  91         }
  92     }
  93
  94     /* Convert forcefully to guest address space, invalid addresses
  95        are still valid segv ones */
  96     address = h2g_nocheck(address);
  97
  98     cpu = current_cpu;
  99     cc = CPU_GET_CLASS(cpu);
 100     /* see if it is an MMU fault */
 101     g_assert(cc->handle_mmu_fault);
 102     ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
 103     if (ret < 0) {
 104         return 0; /* not an MMU fault */
 105     }
 106     if (ret == 0) {
 107         return 1; /* the MMU fault was handled without causing real CPU fault */
 108     }
 109
 110     /* Now we have a real cpu fault.  Since this is the exact location of
 111      * the exception, we must undo the adjustment done by cpu_restore_state
 112      * for handling call return addresses.  */
 113     cpu_restore_state(cpu, pc + GETPC_ADJ);
 114
 115     sigprocmask(SIG_SETMASK, old_set, NULL);
 116     cpu_loop_exit(cpu);
 117
 118     /* never comes here */
 119     return 1;
 120 }
 121
 122 #if defined(__i386__)
 123
 124 #if defined(__NetBSD__)
 125 #include <ucontext.h>
 126
 127 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 128 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 129 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 130 #define MASK_sig(context)    ((context)->uc_sigmask)
 131 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 132 #include <ucontext.h>
 133
 134 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 135 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 136 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 137 #define MASK_sig(context)    ((context)->uc_sigmask)
 138 #elif defined(__OpenBSD__)
 139 #define EIP_sig(context)     ((context)->sc_eip)
 140 #define TRAP_sig(context)    ((context)->sc_trapno)
 141 #define ERROR_sig(context)   ((context)->sc_err)
 142 #define MASK_sig(context)    ((context)->sc_mask)
 143 #else
 144 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 145 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 146 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 147 #define MASK_sig(context)    ((context)->uc_sigmask)
 148 #endif
 149
 150 int cpu_signal_handler(int host_signum, void *pinfo,
 151                        void *puc)
 152 {
 153     siginfo_t *info = pinfo;
 154 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 155     ucontext_t *uc = puc;
 156 #elif defined(__OpenBSD__)
 157     struct sigcontext *uc = puc;
 158 #else
 159     struct ucontext *uc = puc;
 160 #endif
 161     uintptr_t pc;
 162     int trapno;
 163
 164 #ifndef REG_EIP
 165 /* for glibc 2.1 */
 166 #define REG_EIP    EIP
 167 #define REG_ERR    ERR
 168 #define REG_TRAPNO TRAPNO
 169 #endif
 170     pc = EIP_sig(uc);
 171     trapno = TRAP_sig(uc);
 172     return handle_cpu_signal(pc, info->si_addr,
 173                              trapno == 0xe ?
 174                              (ERROR_sig(uc) >> 1) & 1 : 0,
 175                              &MASK_sig(uc));
 176 }
 177
 178 #elif defined(__x86_64__)
 179
 180 #ifdef __NetBSD__
 181 #define PC_sig(context)       _UC_MACHINE_PC(context)
 182 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 183 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 184 #define MASK_sig(context)     ((context)->uc_sigmask)
 185 #elif defined(__OpenBSD__)
 186 #define PC_sig(context)       ((context)->sc_rip)
 187 #define TRAP_sig(context)     ((context)->sc_trapno)
 188 #define ERROR_sig(context)    ((context)->sc_err)
 189 #define MASK_sig(context)     ((context)->sc_mask)
 190 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 191 #include <ucontext.h>
 192
 193 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 194 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 195 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 196 #define MASK_sig(context)     ((context)->uc_sigmask)
 197 #else
 198 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 199 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 200 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 201 #define MASK_sig(context)     ((context)->uc_sigmask)
 202 #endif
 203
 204 int cpu_signal_handler(int host_signum, void *pinfo,
 205                        void *puc)
 206 {
 207     siginfo_t *info = pinfo;
 208     uintptr_t pc;
 209 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 210     ucontext_t *uc = puc;
 211 #elif defined(__OpenBSD__)
 212     struct sigcontext *uc = puc;
 213 #else
 214     struct ucontext *uc = puc;
 215 #endif
 216
 217     pc = PC_sig(uc);
 218     return handle_cpu_signal(pc, info->si_addr,
 219                              TRAP_sig(uc) == 0xe ?
 220                              (ERROR_sig(uc) >> 1) & 1 : 0,
 221                              &MASK_sig(uc));
 222 }
 223
 224 #elif defined(_ARCH_PPC)
 225
 226 /***********************************************************************
 227  * signal context platform-specific definitions
 228  * From Wine
 229  */
 230 #ifdef linux
 231 /* All Registers access - only for local access */
 232 #define REG_sig(reg_name, context)              \
 233     ((context)->uc_mcontext.regs->reg_name)
 234 /* Gpr Registers access  */
 235 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 236 /* Program counter */
 237 #define IAR_sig(context)                       REG_sig(nip, context)
 238 /* Machine State Register (Supervisor) */
 239 #define MSR_sig(context)                       REG_sig(msr, context)
 240 /* Count register */
 241 #define CTR_sig(context)                       REG_sig(ctr, context)
 242 /* User's integer exception register */
 243 #define XER_sig(context)                       REG_sig(xer, context)
 244 /* Link register */
 245 #define LR_sig(context)                        REG_sig(link, context)
 246 /* Condition register */
 247 #define CR_sig(context)                        REG_sig(ccr, context)
 248
 249 /* Float Registers access  */
 250 #define FLOAT_sig(reg_num, context)                                     \
 251     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 252 #define FPSCR_sig(context) \
 253     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 254 /* Exception Registers access */
 255 #define DAR_sig(context)                       REG_sig(dar, context)
 256 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 257 #define TRAP_sig(context)                      REG_sig(trap, context)
 258 #endif /* linux */
 259
 260 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 261 #include <ucontext.h>
 262 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 263 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 264 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 265 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 266 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 267 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 268 /* Exception Registers access */
 269 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 270 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 271 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 272 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 273
 274 int cpu_signal_handler(int host_signum, void *pinfo,
 275                        void *puc)
 276 {
 277     siginfo_t *info = pinfo;
 278 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 279     ucontext_t *uc = puc;
 280 #else
 281     struct ucontext *uc = puc;
 282 #endif
 283     uintptr_t pc;
 284     int is_write;
 285
 286     pc = IAR_sig(uc);
 287     is_write = 0;
 288 #if 0
 289     /* ppc 4xx case */
 290     if (DSISR_sig(uc) & 0x00800000) {
 291         is_write = 1;
 292     }
 293 #else
 294     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 295         is_write = 1;
 296     }
 297 #endif
 298     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask);
 299 }
 300
 301 #elif defined(__alpha__)
 302
 303 int cpu_signal_handler(int host_signum, void *pinfo,
 304                            void *puc)
 305 {
 306     siginfo_t *info = pinfo;
 307     struct ucontext *uc = puc;
 308     uint32_t *pc = uc->uc_mcontext.sc_pc;
 309     uint32_t insn = *pc;
 310     int is_write = 0;
 311
 312     /* XXX: need kernel patch to get write flag faster */
 313     switch (insn >> 26) {
 314     case 0x0d: /* stw */
 315     case 0x0e: /* stb */
 316     case 0x0f: /* stq_u */
 317     case 0x24: /* stf */
 318     case 0x25: /* stg */
 319     case 0x26: /* sts */
 320     case 0x27: /* stt */
 321     case 0x2c: /* stl */
 322     case 0x2d: /* stq */
 323     case 0x2e: /* stl_c */
 324     case 0x2f: /* stq_c */
 325         is_write = 1;
 326     }
 327
 328     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask);
 329 }
 330 #elif defined(__sparc__)
 331
 332 int cpu_signal_handler(int host_signum, void *pinfo,
 333                        void *puc)
 334 {
 335     siginfo_t *info = pinfo;
 336     int is_write;
 337     uint32_t insn;
 338 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 339     uint32_t *regs = (uint32_t *)(info + 1);
 340     void *sigmask = (regs + 20);
 341     /* XXX: is there a standard glibc define ? */
 342     uintptr_t pc = regs[1];
 343 #else
 344 #ifdef __linux__
 345     struct sigcontext *sc = puc;
 346     uintptr_t pc = sc->sigc_regs.tpc;
 347     void *sigmask = (void *)sc->sigc_mask;
 348 #elif defined(__OpenBSD__)
 349     struct sigcontext *uc = puc;
 350     uintptr_t pc = uc->sc_pc;
 351     void *sigmask = (void *)(long)uc->sc_mask;
 352 #elif defined(__NetBSD__)
 353     ucontext_t *uc = puc;
 354     unsigned long pc = _UC_MACHINE_PC(uc);
 355     void *sigmask = (void *)&uc->uc_sigmask;
 356 #endif
 357 #endif
 358
 359     /* XXX: need kernel patch to get write flag faster */
 360     is_write = 0;
 361     insn = *(uint32_t *)pc;
 362     if ((insn >> 30) == 3) {
 363         switch ((insn >> 19) & 0x3f) {
 364         case 0x05: /* stb */
 365         case 0x15: /* stba */
 366         case 0x06: /* sth */
 367         case 0x16: /* stha */
 368         case 0x04: /* st */
 369         case 0x14: /* sta */
 370         case 0x07: /* std */
 371         case 0x17: /* stda */
 372         case 0x0e: /* stx */
 373         case 0x1e: /* stxa */
 374         case 0x24: /* stf */
 375         case 0x34: /* stfa */
 376         case 0x27: /* stdf */
 377         case 0x37: /* stdfa */
 378         case 0x26: /* stqf */
 379         case 0x36: /* stqfa */
 380         case 0x25: /* stfsr */
 381         case 0x3c: /* casa */
 382         case 0x3e: /* casxa */
 383             is_write = 1;
 384             break;
 385         }
 386     }
 387     return handle_cpu_signal(pc, info->si_addr, is_write, sigmask);
 388 }
 389
 390 #elif defined(__arm__)
 391
 392 #if defined(__NetBSD__)
 393 #include <ucontext.h>
 394 #endif
 395
 396 int cpu_signal_handler(int host_signum, void *pinfo,
 397                        void *puc)
 398 {
 399     siginfo_t *info = pinfo;
 400 #if defined(__NetBSD__)
 401     ucontext_t *uc = puc;
 402 #else
 403     struct ucontext *uc = puc;
 404 #endif
 405     uintptr_t pc;
 406     int is_write;
 407
 408 #if defined(__NetBSD__)
 409     pc = uc->uc_mcontext.__gregs[_REG_R15];
 410 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 411     pc = uc->uc_mcontext.gregs[R15];
 412 #else
 413     pc = uc->uc_mcontext.arm_pc;
 414 #endif
 415
 416     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 417      * later processor; on v5 we will always report this as a read).
 418      */
 419     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 420     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask);
 421 }
 422
 423 #elif defined(__aarch64__)
 424
 425 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 426 {
 427     siginfo_t *info = pinfo;
 428     struct ucontext *uc = puc;
 429     uintptr_t pc = uc->uc_mcontext.pc;
 430     uint32_t insn = *(uint32_t *)pc;
 431     bool is_write;
 432
 433     /* XXX: need kernel patch to get write flag faster.  */
 434     is_write = (   (insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */
 435                 || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */
 436                 || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */
 437                 || (insn & 0xbfc00000) == 0x0d800000   /* C3.3.4 */
 438                 || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */
 439                 || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */
 440                 || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */
 441                 /* Ingore bits 10, 11 & 21, controlling indexing.  */
 442                 || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */
 443                 || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */
 444                 /* Ignore bits 23 & 24, controlling indexing.  */
 445                 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
 446
 447     return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
 448                              is_write, &uc->uc_sigmask);
 449 }
 450
 451 #elif defined(__mc68000)
 452
 453 int cpu_signal_handler(int host_signum, void *pinfo,
 454                        void *puc)
 455 {
 456     siginfo_t *info = pinfo;
 457     struct ucontext *uc = puc;
 458     uintptr_t pc;
 459     int is_write;
 460
 461     pc = uc->uc_mcontext.gregs[16];
 462     /* XXX: compute is_write */
 463     is_write = 0;
 464     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask);
 465 }
 466
 467 #elif defined(__ia64)
 468
 469 #ifndef __ISR_VALID
 470   /* This ought to be in <bits/siginfo.h>... */
 471 # define __ISR_VALID    1
 472 #endif
 473
 474 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 475 {
 476     siginfo_t *info = pinfo;
 477     struct ucontext *uc = puc;
 478     unsigned long ip;
 479     int is_write = 0;
 480
 481     ip = uc->uc_mcontext.sc_ip;
 482     switch (host_signum) {
 483     case SIGILL:
 484     case SIGFPE:
 485     case SIGSEGV:
 486     case SIGBUS:
 487     case SIGTRAP:
 488         if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
 489             /* ISR.W (write-access) is bit 33:  */
 490             is_write = (info->si_isr >> 33) & 1;
 491         }
 492         break;
 493
 494     default:
 495         break;
 496     }
 497     return handle_cpu_signal(ip, info->si_addr, is_write,
 498                              (sigset_t *)&uc->uc_sigmask);
 499 }
 500
 501 #elif defined(__s390__)
 502
 503 int cpu_signal_handler(int host_signum, void *pinfo,
 504                        void *puc)
 505 {
 506     siginfo_t *info = pinfo;
 507     struct ucontext *uc = puc;
 508     uintptr_t pc;
 509     uint16_t *pinsn;
 510     int is_write = 0;
 511
 512     pc = uc->uc_mcontext.psw.addr;
 513
 514     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 515        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 516        from the hardware which does in fact contain the is_write value.
 517        The rt signal handler, as far as I can tell, does not give this value
 518        at all.  Not that we could get to it from here even if it were.  */
 519     /* ??? This is not even close to complete, since it ignores all
 520        of the read-modify-write instructions.  */
 521     pinsn = (uint16_t *)pc;
 522     switch (pinsn[0] >> 8) {
 523     case 0x50: /* ST */
 524     case 0x42: /* STC */
 525     case 0x40: /* STH */
 526         is_write = 1;
 527         break;
 528     case 0xc4: /* RIL format insns */
 529         switch (pinsn[0] & 0xf) {
 530         case 0xf: /* STRL */
 531         case 0xb: /* STGRL */
 532         case 0x7: /* STHRL */
 533             is_write = 1;
 534         }
 535         break;
 536     case 0xe3: /* RXY format insns */
 537         switch (pinsn[2] & 0xff) {
 538         case 0x50: /* STY */
 539         case 0x24: /* STG */
 540         case 0x72: /* STCY */
 541         case 0x70: /* STHY */
 542         case 0x8e: /* STPQ */
 543         case 0x3f: /* STRVH */
 544         case 0x3e: /* STRV */
 545         case 0x2f: /* STRVG */
 546             is_write = 1;
 547         }
 548         break;
 549     }
 550     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask);
 551 }
 552
 553 #elif defined(__mips__)
 554
 555 int cpu_signal_handler(int host_signum, void *pinfo,
 556                        void *puc)
 557 {
 558     siginfo_t *info = pinfo;
 559     struct ucontext *uc = puc;
 560     greg_t pc = uc->uc_mcontext.pc;
 561     int is_write;
 562
 563     /* XXX: compute is_write */
 564     is_write = 0;
 565     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask);
 566 }
 567
 568 #elif defined(__hppa__)
 569
 570 int cpu_signal_handler(int host_signum, void *pinfo,
 571                        void *puc)
 572 {
 573     siginfo_t *info = pinfo;
 574     struct ucontext *uc = puc;
 575     uintptr_t pc = uc->uc_mcontext.sc_iaoq[0];
 576     uint32_t insn = *(uint32_t *)pc;
 577     int is_write = 0;
 578
 579     /* XXX: need kernel patch to get write flag faster.  */
 580     switch (insn >> 26) {
 581     case 0x1a: /* STW */
 582     case 0x19: /* STH */
 583     case 0x18: /* STB */
 584     case 0x1b: /* STWM */
 585         is_write = 1;
 586         break;
 587
 588     case 0x09: /* CSTWX, FSTWX, FSTWS */
 589     case 0x0b: /* CSTDX, FSTDX, FSTDS */
 590         /* Distinguish from coprocessor load ... */
 591         is_write = (insn >> 9) & 1;
 592         break;
 593
 594     case 0x03:
 595         switch ((insn >> 6) & 15) {
 596         case 0xa: /* STWS */
 597         case 0x9: /* STHS */
 598         case 0x8: /* STBS */
 599         case 0xe: /* STWAS */
 600         case 0xc: /* STBYS */
 601             is_write = 1;
 602         }
 603         break;
 604     }
 605
 606     return handle_cpu_signal(pc, info->si_addr, is_write, &uc->uc_sigmask);
 607 }
 608
 609 #else
 610
 611 #error host CPU specific signal handler needed
 612
 613 #endif