hw/openrisc/openrisc_sim.c

   1 /*
   2  * OpenRISC simulator for use as an IIS.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Feng Gao <gf91597@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/error-report.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "hw/irq.h"
  26 #include "hw/boards.h"
  27 #include "hw/char/serial.h"
  28 #include "net/net.h"
  29 #include "hw/openrisc/boot.h"
  30 #include "hw/qdev-properties.h"
  31 #include "exec/address-spaces.h"
  32 #include "sysemu/device_tree.h"
  33 #include "sysemu/sysemu.h"
  34 #include "hw/sysbus.h"
  35 #include "sysemu/qtest.h"
  36 #include "sysemu/reset.h"
  37 #include "hw/core/split-irq.h"
  38
  39 #include <libfdt.h>
  40
  41 #define KERNEL_LOAD_ADDR 0x100
  42
  43 #define OR1KSIM_CPUS_MAX 4
  44 #define OR1KSIM_CLK_MHZ 20000000
  45
  46 #define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
  47 #define OR1KSIM_MACHINE(obj) \
  48     OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
  49
  50 typedef struct Or1ksimState {
  51     /*< private >*/
  52     MachineState parent_obj;
  53
  54     /*< public >*/
  55     void *fdt;
  56     int fdt_size;
  57
  58 } Or1ksimState;
  59
  60 enum {
  61     OR1KSIM_DRAM,
  62     OR1KSIM_UART,
  63     OR1KSIM_ETHOC,
  64     OR1KSIM_OMPIC,
  65 };
  66
  67 enum {
  68     OR1KSIM_OMPIC_IRQ = 1,
  69     OR1KSIM_UART_IRQ = 2,
  70     OR1KSIM_ETHOC_IRQ = 4,
  71 };
  72
  73 enum {
  74     OR1KSIM_UART_COUNT = 4
  75 };
  76
  77 static const struct MemmapEntry {
  78     hwaddr base;
  79     hwaddr size;
  80 } or1ksim_memmap[] = {
  81     [OR1KSIM_DRAM] =      { 0x00000000,          0 },
  82     [OR1KSIM_UART] =      { 0x90000000,      0x100 },
  83     [OR1KSIM_ETHOC] =     { 0x92000000,      0x800 },
  84     [OR1KSIM_OMPIC] =     { 0x98000000, OR1KSIM_CPUS_MAX * 8 },
  85 };
  86
  87 static struct openrisc_boot_info {
  88     uint32_t bootstrap_pc;
  89     uint32_t fdt_addr;
  90 } boot_info;
  91
  92 static void main_cpu_reset(void *opaque)
  93 {
  94     OpenRISCCPU *cpu = opaque;
  95     CPUState *cs = CPU(cpu);
  96
  97     cpu_reset(CPU(cpu));
  98
  99     cpu_set_pc(cs, boot_info.bootstrap_pc);
 100     cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
 101 }
 102
 103 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
 104 {
 105     return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
 106 }
 107
 108 static void openrisc_create_fdt(Or1ksimState *state,
 109                                 const struct MemmapEntry *memmap,
 110                                 int num_cpus, uint64_t mem_size,
 111                                 const char *cmdline)
 112 {
 113     void *fdt;
 114     int cpu;
 115     char *nodename;
 116     int pic_ph;
 117
 118     fdt = state->fdt = create_device_tree(&state->fdt_size);
 119     if (!fdt) {
 120         error_report("create_device_tree() failed");
 121         exit(1);
 122     }
 123
 124     qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
 125     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
 126     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
 127
 128     nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
 129                                memmap[OR1KSIM_DRAM].base);
 130     qemu_fdt_add_subnode(fdt, nodename);
 131     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 132                            memmap[OR1KSIM_DRAM].base, mem_size);
 133     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 134     g_free(nodename);
 135
 136     qemu_fdt_add_subnode(fdt, "/cpus");
 137     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 138     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 139
 140     for (cpu = 0; cpu < num_cpus; cpu++) {
 141         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 142         qemu_fdt_add_subnode(fdt, nodename);
 143         qemu_fdt_setprop_string(fdt, nodename, "compatible",
 144                                 "opencores,or1200-rtlsvn481");
 145         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 146         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 147                               OR1KSIM_CLK_MHZ);
 148         g_free(nodename);
 149     }
 150
 151     nodename = (char *)"/pic";
 152     qemu_fdt_add_subnode(fdt, nodename);
 153     pic_ph = qemu_fdt_alloc_phandle(fdt);
 154     qemu_fdt_setprop_string(fdt, nodename, "compatible",
 155                             "opencores,or1k-pic-level");
 156     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 157     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 158     qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph);
 159
 160     qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph);
 161
 162     qemu_fdt_add_subnode(fdt, "/chosen");
 163     if (cmdline) {
 164         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 165     }
 166
 167     /* Create aliases node for use by devices. */
 168     qemu_fdt_add_subnode(fdt, "/aliases");
 169 }
 170
 171 static void openrisc_sim_net_init(Or1ksimState *state, hwaddr base, hwaddr size,
 172                                   int num_cpus, OpenRISCCPU *cpus[],
 173                                   int irq_pin)
 174 {
 175     void *fdt = state->fdt;
 176     DeviceState *dev;
 177     SysBusDevice *s;
 178     char *nodename;
 179     int i;
 180
 181     dev = qemu_create_nic_device("open_eth", true, NULL);
 182     if (!dev) {
 183         return;
 184     }
 185
 186     s = SYS_BUS_DEVICE(dev);
 187     sysbus_realize_and_unref(s, &error_fatal);
 188     if (num_cpus > 1) {
 189         DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
 190         qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
 191         qdev_realize_and_unref(splitter, NULL, &error_fatal);
 192         for (i = 0; i < num_cpus; i++) {
 193             qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
 194         }
 195         sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0));
 196     } else {
 197         sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin));
 198     }
 199     sysbus_mmio_map(s, 0, base);
 200     sysbus_mmio_map(s, 1, base + 0x400);
 201
 202     /* Init device tree node for ethoc. */
 203     nodename = g_strdup_printf("/ethoc@%" HWADDR_PRIx, base);
 204     qemu_fdt_add_subnode(fdt, nodename);
 205     qemu_fdt_setprop_string(fdt, nodename, "compatible", "opencores,ethoc");
 206     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
 207     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
 208     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
 209
 210     qemu_fdt_setprop_string(fdt, "/aliases", "enet0", nodename);
 211     g_free(nodename);
 212 }
 213
 214 static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base,
 215                                     hwaddr size, int num_cpus,
 216                                     OpenRISCCPU *cpus[], int irq_pin)
 217 {
 218     void *fdt = state->fdt;
 219     DeviceState *dev;
 220     SysBusDevice *s;
 221     char *nodename;
 222     int i;
 223
 224     dev = qdev_new("or1k-ompic");
 225     qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
 226
 227     s = SYS_BUS_DEVICE(dev);
 228     sysbus_realize_and_unref(s, &error_fatal);
 229     for (i = 0; i < num_cpus; i++) {
 230         sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
 231     }
 232     sysbus_mmio_map(s, 0, base);
 233
 234     /* Add device tree node for ompic. */
 235     nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
 236     qemu_fdt_add_subnode(fdt, nodename);
 237     qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
 238     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
 239     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 240     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
 241     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
 242     g_free(nodename);
 243 }
 244
 245 static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
 246                                      hwaddr size, int num_cpus,
 247                                      OpenRISCCPU *cpus[], int irq_pin,
 248                                      int uart_idx)
 249 {
 250     void *fdt = state->fdt;
 251     char *nodename;
 252     qemu_irq serial_irq;
 253     char alias[sizeof("uart0")];
 254     int i;
 255
 256     if (num_cpus > 1) {
 257         DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
 258         qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
 259         qdev_realize_and_unref(splitter, NULL, &error_fatal);
 260         for (i = 0; i < num_cpus; i++) {
 261             qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
 262         }
 263         serial_irq = qdev_get_gpio_in(splitter, 0);
 264     } else {
 265         serial_irq = get_cpu_irq(cpus, 0, irq_pin);
 266     }
 267     serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
 268                    serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
 269                    DEVICE_NATIVE_ENDIAN);
 270
 271     /* Add device tree node for serial. */
 272     nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
 273     qemu_fdt_add_subnode(fdt, nodename);
 274     qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
 275     qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
 276     qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
 277     qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ);
 278     qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
 279
 280     /* The /chosen node is created during fdt creation. */
 281     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 282     snprintf(alias, sizeof(alias), "uart%d", uart_idx);
 283     qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
 284     g_free(nodename);
 285 }
 286
 287 static void openrisc_sim_init(MachineState *machine)
 288 {
 289     ram_addr_t ram_size = machine->ram_size;
 290     const char *kernel_filename = machine->kernel_filename;
 291     OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {};
 292     Or1ksimState *state = OR1KSIM_MACHINE(machine);
 293     MemoryRegion *ram;
 294     hwaddr load_addr;
 295     int n;
 296     unsigned int smp_cpus = machine->smp.cpus;
 297
 298     assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX);
 299     for (n = 0; n < smp_cpus; n++) {
 300         cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
 301         if (cpus[n] == NULL) {
 302             fprintf(stderr, "Unable to find CPU definition!\n");
 303             exit(1);
 304         }
 305
 306         cpu_openrisc_clock_init(cpus[n]);
 307
 308         qemu_register_reset(main_cpu_reset, cpus[n]);
 309     }
 310
 311     ram = g_malloc(sizeof(*ram));
 312     memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
 313     memory_region_add_subregion(get_system_memory(), 0, ram);
 314
 315     openrisc_create_fdt(state, or1ksim_memmap, smp_cpus, machine->ram_size,
 316                         machine->kernel_cmdline);
 317
 318     openrisc_sim_net_init(state, or1ksim_memmap[OR1KSIM_ETHOC].base,
 319                           or1ksim_memmap[OR1KSIM_ETHOC].size,
 320                           smp_cpus, cpus,
 321                           OR1KSIM_ETHOC_IRQ);
 322
 323     if (smp_cpus > 1) {
 324         openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
 325                                 or1ksim_memmap[OR1KSIM_OMPIC].size,
 326                                 smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
 327     }
 328
 329     for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
 330         openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
 331                                         or1ksim_memmap[OR1KSIM_UART].size * n,
 332                                  or1ksim_memmap[OR1KSIM_UART].size,
 333                                  smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
 334
 335     load_addr = openrisc_load_kernel(ram_size, kernel_filename,
 336                                      &boot_info.bootstrap_pc);
 337     if (load_addr > 0) {
 338         if (machine->initrd_filename) {
 339             load_addr = openrisc_load_initrd(state->fdt,
 340                                              machine->initrd_filename,
 341                                              load_addr, machine->ram_size);
 342         }
 343         boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
 344                                                machine->ram_size);
 345     }
 346 }
 347
 348 static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
 349 {
 350     MachineClass *mc = MACHINE_CLASS(oc);
 351
 352     mc->desc = "or1k simulation";
 353     mc->init = openrisc_sim_init;
 354     mc->max_cpus = OR1KSIM_CPUS_MAX;
 355     mc->is_default = true;
 356     mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
 357 }
 358
 359 static const TypeInfo or1ksim_machine_typeinfo = {
 360     .name       = TYPE_OR1KSIM_MACHINE,
 361     .parent     = TYPE_MACHINE,
 362     .class_init = openrisc_sim_machine_init,
 363     .instance_size = sizeof(Or1ksimState),
 364 };
 365
 366 static void or1ksim_machine_init_register_types(void)
 367 {
 368     type_register_static(&or1ksim_machine_typeinfo);
 369 }
 370
 371 type_init(or1ksim_machine_init_register_types)