target-i386/bpt_helper.c

   1 /*
   2  *  i386 breakpoint helpers
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22
  23
  24 #ifndef CONFIG_USER_ONLY
  25 static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
  26 {
  27     return (dr7 >> (index * 2)) & 1;
  28 }
  29
  30 static inline bool hw_global_breakpoint_enabled(unsigned long dr7, int index)
  31 {
  32     return (dr7 >> (index * 2)) & 2;
  33
  34 }
  35 static inline bool hw_breakpoint_enabled(unsigned long dr7, int index)
  36 {
  37     return hw_global_breakpoint_enabled(dr7, index) ||
  38            hw_local_breakpoint_enabled(dr7, index);
  39 }
  40
  41 static inline int hw_breakpoint_type(unsigned long dr7, int index)
  42 {
  43     return (dr7 >> (DR7_TYPE_SHIFT + (index * 4))) & 3;
  44 }
  45
  46 static inline int hw_breakpoint_len(unsigned long dr7, int index)
  47 {
  48     int len = ((dr7 >> (DR7_LEN_SHIFT + (index * 4))) & 3);
  49     return (len == 2) ? 8 : len + 1;
  50 }
  51
  52 static int hw_breakpoint_insert(CPUX86State *env, int index)
  53 {
  54     CPUState *cs = CPU(x86_env_get_cpu(env));
  55     target_ulong dr7 = env->dr[7];
  56     target_ulong drN = env->dr[index];
  57     int err = 0;
  58
  59     switch (hw_breakpoint_type(dr7, index)) {
  60     case DR7_TYPE_BP_INST:
  61         if (hw_breakpoint_enabled(dr7, index)) {
  62             err = cpu_breakpoint_insert(cs, drN, BP_CPU,
  63                                         &env->cpu_breakpoint[index]);
  64         }
  65         break;
  66
  67     case DR7_TYPE_IO_RW:
  68         /* Notice when we should enable calls to bpt_io.  */
  69         return hw_breakpoint_enabled(env->dr[7], index)
  70                ? HF_IOBPT_MASK : 0;
  71
  72     case DR7_TYPE_DATA_WR:
  73         if (hw_breakpoint_enabled(dr7, index)) {
  74             err = cpu_watchpoint_insert(cs, drN,
  75                                         hw_breakpoint_len(dr7, index),
  76                                         BP_CPU | BP_MEM_WRITE,
  77                                         &env->cpu_watchpoint[index]);
  78         }
  79         break;
  80
  81     case DR7_TYPE_DATA_RW:
  82         if (hw_breakpoint_enabled(dr7, index)) {
  83             err = cpu_watchpoint_insert(cs, drN,
  84                                         hw_breakpoint_len(dr7, index),
  85                                         BP_CPU | BP_MEM_ACCESS,
  86                                         &env->cpu_watchpoint[index]);
  87         }
  88         break;
  89     }
  90     if (err) {
  91         env->cpu_breakpoint[index] = NULL;
  92     }
  93     return 0;
  94 }
  95
  96 static void hw_breakpoint_remove(CPUX86State *env, int index)
  97 {
  98     CPUState *cs = CPU(x86_env_get_cpu(env));
  99
 100     switch (hw_breakpoint_type(env->dr[7], index)) {
 101     case DR7_TYPE_BP_INST:
 102         if (env->cpu_breakpoint[index]) {
 103             cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
 104             env->cpu_breakpoint[index] = NULL;
 105         }
 106         break;
 107
 108     case DR7_TYPE_DATA_WR:
 109     case DR7_TYPE_DATA_RW:
 110         if (env->cpu_breakpoint[index]) {
 111             cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
 112             env->cpu_breakpoint[index] = NULL;
 113         }
 114         break;
 115
 116     case DR7_TYPE_IO_RW:
 117         /* HF_IOBPT_MASK cleared elsewhere.  */
 118         break;
 119     }
 120 }
 121
 122 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7)
 123 {
 124     target_ulong old_dr7 = env->dr[7];
 125     int iobpt = 0;
 126     int i;
 127
 128     new_dr7 |= DR7_FIXED_1;
 129
 130     /* If nothing is changing except the global/local enable bits,
 131        then we can make the change more efficient.  */
 132     if (((old_dr7 ^ new_dr7) & ~0xff) == 0) {
 133         /* Fold the global and local enable bits together into the
 134            global fields, then xor to show which registers have
 135            changed collective enable state.  */
 136         int mod = ((old_dr7 | old_dr7 * 2) ^ (new_dr7 | new_dr7 * 2)) & 0xff;
 137
 138         for (i = 0; i < DR7_MAX_BP; i++) {
 139             if ((mod & (2 << i * 2)) && !hw_breakpoint_enabled(new_dr7, i)) {
 140                 hw_breakpoint_remove(env, i);
 141             }
 142         }
 143         env->dr[7] = new_dr7;
 144         for (i = 0; i < DR7_MAX_BP; i++) {
 145             if (mod & (2 << i * 2) && hw_breakpoint_enabled(new_dr7, i)) {
 146                 iobpt |= hw_breakpoint_insert(env, i);
 147             } else if (hw_breakpoint_type(new_dr7, i) == DR7_TYPE_IO_RW
 148                        && hw_breakpoint_enabled(new_dr7, i)) {
 149                 iobpt |= HF_IOBPT_MASK;
 150             }
 151         }
 152     } else {
 153         for (i = 0; i < DR7_MAX_BP; i++) {
 154             hw_breakpoint_remove(env, i);
 155         }
 156         env->dr[7] = new_dr7;
 157         for (i = 0; i < DR7_MAX_BP; i++) {
 158             iobpt |= hw_breakpoint_insert(env, i);
 159         }
 160     }
 161
 162     env->hflags = (env->hflags & ~HF_IOBPT_MASK) | iobpt;
 163 }
 164
 165 static bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
 166 {
 167     target_ulong dr6;
 168     int reg;
 169     bool hit_enabled = false;
 170
 171     dr6 = env->dr[6] & ~0xf;
 172     for (reg = 0; reg < DR7_MAX_BP; reg++) {
 173         bool bp_match = false;
 174         bool wp_match = false;
 175
 176         switch (hw_breakpoint_type(env->dr[7], reg)) {
 177         case DR7_TYPE_BP_INST:
 178             if (env->dr[reg] == env->eip) {
 179                 bp_match = true;
 180             }
 181             break;
 182         case DR7_TYPE_DATA_WR:
 183         case DR7_TYPE_DATA_RW:
 184             if (env->cpu_watchpoint[reg] &&
 185                 env->cpu_watchpoint[reg]->flags & BP_WATCHPOINT_HIT) {
 186                 wp_match = true;
 187             }
 188             break;
 189         case DR7_TYPE_IO_RW:
 190             break;
 191         }
 192         if (bp_match || wp_match) {
 193             dr6 |= 1 << reg;
 194             if (hw_breakpoint_enabled(env->dr[7], reg)) {
 195                 hit_enabled = true;
 196             }
 197         }
 198     }
 199
 200     if (hit_enabled || force_dr6_update) {
 201         env->dr[6] = dr6;
 202     }
 203
 204     return hit_enabled;
 205 }
 206
 207 void breakpoint_handler(CPUState *cs)
 208 {
 209     X86CPU *cpu = X86_CPU(cs);
 210     CPUX86State *env = &cpu->env;
 211     CPUBreakpoint *bp;
 212
 213     if (cs->watchpoint_hit) {
 214         if (cs->watchpoint_hit->flags & BP_CPU) {
 215             cs->watchpoint_hit = NULL;
 216             if (check_hw_breakpoints(env, false)) {
 217                 raise_exception(env, EXCP01_DB);
 218             } else {
 219                 cpu_resume_from_signal(cs, NULL);
 220             }
 221         }
 222     } else {
 223         QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
 224             if (bp->pc == env->eip) {
 225                 if (bp->flags & BP_CPU) {
 226                     check_hw_breakpoints(env, true);
 227                     raise_exception(env, EXCP01_DB);
 228                 }
 229                 break;
 230             }
 231         }
 232     }
 233 }
 234 #endif
 235
 236 void helper_single_step(CPUX86State *env)
 237 {
 238 #ifndef CONFIG_USER_ONLY
 239     check_hw_breakpoints(env, true);
 240     env->dr[6] |= DR6_BS;
 241 #endif
 242     raise_exception(env, EXCP01_DB);
 243 }
 244
 245 void helper_set_dr(CPUX86State *env, int reg, target_ulong t0)
 246 {
 247 #ifndef CONFIG_USER_ONLY
 248     switch (reg) {
 249     case 0: case 1: case 2: case 3:
 250         if (hw_breakpoint_enabled(env->dr[7], reg)
 251             && hw_breakpoint_type(env->dr[7], reg) != DR7_TYPE_IO_RW) {
 252             hw_breakpoint_remove(env, reg);
 253             env->dr[reg] = t0;
 254             hw_breakpoint_insert(env, reg);
 255         } else {
 256             env->dr[reg] = t0;
 257         }
 258         return;
 259     case 4:
 260         if (env->cr[4] & CR4_DE_MASK) {
 261             break;
 262         }
 263         /* fallthru */
 264     case 6:
 265         env->dr[6] = t0 | DR6_FIXED_1;
 266         return;
 267     case 5:
 268         if (env->cr[4] & CR4_DE_MASK) {
 269             break;
 270         }
 271         /* fallthru */
 272     case 7:
 273         cpu_x86_update_dr7(env, t0);
 274         return;
 275     }
 276     raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
 277 #endif
 278 }
 279
 280 target_ulong helper_get_dr(CPUX86State *env, int reg)
 281 {
 282     switch (reg) {
 283     case 0: case 1: case 2: case 3: case 6: case 7:
 284         return env->dr[reg];
 285     case 4:
 286         if (env->cr[4] & CR4_DE_MASK) {
 287             break;
 288         } else {
 289             return env->dr[6];
 290         }
 291     case 5:
 292         if (env->cr[4] & CR4_DE_MASK) {
 293             break;
 294         } else {
 295             return env->dr[7];
 296         }
 297     }
 298     raise_exception_err_ra(env, EXCP06_ILLOP, 0, GETPC());
 299 }
 300
 301 /* Check if Port I/O is trapped by a breakpoint.  */
 302 void helper_bpt_io(CPUX86State *env, uint32_t port,
 303                    uint32_t size, target_ulong next_eip)
 304 {
 305 #ifndef CONFIG_USER_ONLY
 306     target_ulong dr7 = env->dr[7];
 307     int i, hit = 0;
 308
 309     for (i = 0; i < DR7_MAX_BP; ++i) {
 310         if (hw_breakpoint_type(dr7, i) == DR7_TYPE_IO_RW
 311             && hw_breakpoint_enabled(dr7, i)) {
 312             int bpt_len = hw_breakpoint_len(dr7, i);
 313             if (port + size - 1 >= env->dr[i]
 314                 && port <= env->dr[i] + bpt_len - 1) {
 315                 hit |= 1 << i;
 316             }
 317         }
 318     }
 319
 320     if (hit) {
 321         env->dr[6] = (env->dr[6] & ~0xf) | hit;
 322         env->eip = next_eip;
 323         raise_exception(env, EXCP01_DB);
 324     }
 325 #endif
 326 }