hw/arm/bast.c

   1 /* hw/bast.c
   2  *
   3  * System emulation for the Simtec Electronics BAST
   4  *
   5  * Copyright 2006, 2008 Daniel Silverstone and Vincent Sanders
   6  *
   7  * Copyright 2010, 2013 Stefan Weil
   8  *
   9  * This file is under the terms of the GNU General Public License Version 2.
  10  *
  11  * TODO:
  12  * * Undefined r/w at address 0x118002f9 (serial i/o?).
  13  * * Undefined r/w at address 0x118003f9 (serial i/o?).
  14  * * Undefined r/w at address 0x29000000 ff (ax88796).
  15  * * Undefined r/w at address 0x4b000000 ff.
  16  * * Undefined r/w at address 0x55000000 ff (iis).
  17  * * eth1 is 10 Mbps half duplex only.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "chardev/char.h"        /* qemu_chr_new */
  23 #include "hw/hw.h"
  24 #include "hw/arm/arm.h"
  25 #include "hw/loader.h"          /* load_image_targphys */
  26 #include "hw/i2c/smbus.h"
  27 #include "hw/devices.h"
  28 #include "hw/boards.h"
  29 #include "hw/ide/internal.h"    /* ide_cmd_write, ... */
  30 #include "s3c2410x.h"
  31 #include "hw/char/serial.h"     /* serial_isa_init */
  32 #include "hw/sysbus.h"          /* SYS_BUS_DEVICE, ... */
  33 #include "net/net.h"
  34 #include "sysemu/blockdev.h"    /* drive_get */
  35 #include "sysemu/dma.h"         /* QEMUSGList (in ide/internal.h) */
  36 #include "sysemu/sysemu.h"
  37 #include "exec/address-spaces.h" /* get_system_memory */
  38
  39 #define BIOS_FILENAME "able.bin"
  40
  41 #define MiB (1024 * 1024)
  42
  43 #define S3C24XX_DBF(format, ...) (void)0
  44
  45 typedef struct {
  46     MemoryRegion cpld1;
  47     MemoryRegion cpld5;
  48     S3CState *soc;
  49     DeviceState *nand[4];
  50     uint8_t cpld_ctrl2;
  51 } STCBState;
  52
  53 /* Useful defines */
  54 #define BAST_NOR_RO_BASE CPU_S3C2410X_CS0
  55 #define BAST_NOR_RW_BASE (CPU_S3C2410X_CS1 + 0x4000000)
  56 #define BAST_NOR_SIZE    (2 * MiB)
  57 #define BAST_BOARD_ID 331
  58
  59 #define BAST_CS1_CPLD_BASE (CPU_S3C2410X_CS1 | (0xc << 23))
  60 #define BAST_CS5_CPLD_BASE (CPU_S3C2410X_CS5 | (0xc << 23))
  61 #define BAST_CPLD_SIZE (4<<23)
  62
  63 static uint64_t cpld_read(void *opaque, hwaddr address,
  64                           unsigned size)
  65 {
  66     STCBState *stcb = opaque;
  67     int reg = (address >> 23) & 0xf;
  68     if (reg == 0xc) {
  69         return stcb->cpld_ctrl2;
  70     }
  71     return 0;
  72 }
  73
  74 static void cpld_write(void *opaque, hwaddr address,
  75                        uint64_t value, unsigned size)
  76 {
  77     STCBState *stcb = opaque;
  78     int reg = (address >> 23) & 0xf;
  79     if (reg == 0xc) {
  80         stcb->cpld_ctrl2 = value;
  81         s3c24xx_nand_attach(stcb->soc->nand, stcb->nand[stcb->cpld_ctrl2 & 3]);
  82     }
  83 }
  84
  85 static const MemoryRegionOps cpld_ops = {
  86     .read = cpld_read,
  87     .write = cpld_write,
  88     .endianness = DEVICE_NATIVE_ENDIAN,
  89     .valid = {
  90         .min_access_size = 4,
  91         .max_access_size = 4
  92     }
  93 };
  94
  95 static void stcb_cpld_register(STCBState *s)
  96 {
  97     MemoryRegion *sysmem = get_system_memory();
  98     memory_region_init_io(&s->cpld1, OBJECT(s),
  99                           &cpld_ops, s, "cpld1", BAST_CPLD_SIZE);
 100     memory_region_init_alias(&s->cpld5, NULL, "cpld5", &s->cpld1, 0, BAST_CPLD_SIZE);
 101     memory_region_add_subregion(sysmem, BAST_CS1_CPLD_BASE, &s->cpld1);
 102     memory_region_add_subregion(sysmem, BAST_CS5_CPLD_BASE, &s->cpld5);
 103     s->cpld_ctrl2 = 0;
 104 }
 105
 106 #define BAST_IDE_PRI_SLOW    (CPU_S3C2410X_CS3 | 0x02000000)
 107 #define BAST_IDE_SEC_SLOW    (CPU_S3C2410X_CS3 | 0x03000000)
 108 #define BAST_IDE_PRI_FAST    (CPU_S3C2410X_CS5 | 0x02000000)
 109 #define BAST_IDE_SEC_FAST    (CPU_S3C2410X_CS5 | 0x03000000)
 110
 111 #define BAST_IDE_PRI_SLOW_BYTE    (CPU_S3C2410X_CS2 | 0x02000000)
 112 #define BAST_IDE_SEC_SLOW_BYTE    (CPU_S3C2410X_CS2 | 0x03000000)
 113 #define BAST_IDE_PRI_FAST_BYTE    (CPU_S3C2410X_CS4 | 0x02000000)
 114 #define BAST_IDE_SEC_FAST_BYTE    (CPU_S3C2410X_CS4 | 0x03000000)
 115
 116 /* MMIO interface to IDE on Simtec's BAST
 117  *
 118  * Copyright Daniel Silverstone and Vincent Sanders
 119  *
 120  * This section of this file is under the terms of
 121  * the GNU General Public License Version 2
 122  */
 123
 124 /* Each BAST IDE region is 0x01000000 bytes long,
 125  * the second half is the "alternate" register set
 126  */
 127
 128 typedef struct {
 129     IDEBus bus;
 130     MemoryRegion slow;
 131     MemoryRegion fast;
 132     MemoryRegion slowb;
 133     MemoryRegion fastb;
 134     int shift;
 135 } MMIOState;
 136
 137 static void stcb_ide_write(void *opaque, hwaddr addr,
 138                            uint64_t val, unsigned size)
 139 {
 140     MMIOState *s= opaque;
 141     int reg = (addr & 0x3ff) >> 5; /* 0x200 long, 0x20 stride */
 142     int alt = (addr & 0x800000) != 0;
 143     S3C24XX_DBF("IDE write to addr %08x (reg %d) of value %04x\n", (unsigned int)addr, reg, val);
 144     if (alt) {
 145         ide_cmd_write(&s->bus, 0, val);
 146     }
 147     if (reg == 0) {
 148         /* Data register */
 149         ide_data_writew(&s->bus, 0, val);
 150     } else {
 151         /* Everything else */
 152         ide_ioport_write(&s->bus, reg, val);
 153     }
 154 }
 155
 156 static uint64_t stcb_ide_read(void *opaque, hwaddr addr,
 157                               unsigned size)
 158 {
 159     MMIOState *s= opaque;
 160     int reg = (addr & 0x3ff) >> 5; /* 0x200 long, 0x20 stride */
 161     int alt = (addr & 0x800000) != 0;
 162     S3C24XX_DBF("IDE read of addr %08x (reg %d)\n", (unsigned int)addr, reg);
 163     if (alt) {
 164         return ide_status_read(&s->bus, 0);
 165     }
 166     if (reg == 0) {
 167         return ide_data_readw(&s->bus, 0);
 168     } else {
 169         return ide_ioport_read(&s->bus, reg);
 170     }
 171 }
 172
 173 static const MemoryRegionOps stcb_ide_ops = {
 174     .read = stcb_ide_read,
 175     .write = stcb_ide_write,
 176     .endianness = DEVICE_NATIVE_ENDIAN,
 177     .valid = {
 178         .min_access_size = 4,
 179         .max_access_size = 4
 180     }
 181 };
 182
 183 /* hd_table must contain 2 block drivers */
 184 /* BAST uses memory mapped registers, not I/O. Return the memory
 185  * I/O tag to access the ide.
 186  * The BAST description will register it into the map in the right place.
 187  */
 188 static MMIOState *stcb_ide_init(DriveInfo *dinfo0, DriveInfo *dinfo1, qemu_irq irq)
 189 {
 190     MMIOState *s = g_malloc0(sizeof(MMIOState));
 191     // TODO
 192     //~ ide_init2_with_non_qdev_drives(&s->bus, dinfo0, dinfo1, irq);
 193     memory_region_init_io(&s->slow, OBJECT(s),
 194                           &stcb_ide_ops, s, "stcb-ide", 0x1000000);
 195     memory_region_init_alias(&s->fast, NULL, "stcb-ide", &s->slow, 0, 0x1000000);
 196     memory_region_init_alias(&s->slowb, NULL, "stcb-ide", &s->slow, 0, 0x1000000);
 197     memory_region_init_alias(&s->fastb, NULL, "stcb-ide", &s->slow, 0, 0x1000000);
 198     return s;
 199 }
 200
 201 static void stcb_register_ide(STCBState *stcb)
 202 {
 203     DriveInfo *dinfo0;
 204     DriveInfo *dinfo1;
 205     MMIOState *s;
 206     MemoryRegion *sysmem = get_system_memory();
 207
 208     if (drive_get_max_bus(IF_IDE) >= 2) {
 209         fprintf(stderr, "qemu: too many IDE busses\n");
 210         exit(1);
 211     }
 212
 213     dinfo0 = drive_get(IF_IDE, 0, 0);
 214     dinfo1 = drive_get(IF_IDE, 0, 1);
 215     s = stcb_ide_init(dinfo0, dinfo1, s3c24xx_get_eirq(stcb->soc->gpio, 16));
 216     memory_region_add_subregion(sysmem, BAST_IDE_PRI_SLOW, &s->slow);
 217     memory_region_add_subregion(sysmem, BAST_IDE_PRI_FAST, &s->fast);
 218     memory_region_add_subregion(sysmem, BAST_IDE_PRI_SLOW_BYTE, &s->slowb);
 219     memory_region_add_subregion(sysmem, BAST_IDE_PRI_FAST_BYTE, &s->fastb);
 220
 221     dinfo0 = drive_get(IF_IDE, 1, 0);
 222     dinfo1 = drive_get(IF_IDE, 1, 1);
 223     s = stcb_ide_init(dinfo0, dinfo1, s3c24xx_get_eirq(stcb->soc->gpio, 17));
 224     memory_region_add_subregion(sysmem, BAST_IDE_SEC_SLOW, &s->slow);
 225     memory_region_add_subregion(sysmem, BAST_IDE_SEC_FAST, &s->fast);
 226     memory_region_add_subregion(sysmem, BAST_IDE_SEC_SLOW_BYTE, &s->slowb);
 227     memory_region_add_subregion(sysmem, BAST_IDE_SEC_FAST_BYTE, &s->fastb);
 228 }
 229
 230 #define BAST_PA_ASIXNET 0x01000000
 231 #define BAST_PA_SUPERIO 0x01800000
 232
 233 #define SERIAL_BASE     (CPU_S3C2410X_CS2 + BAST_PA_SUPERIO)
 234 #define SERIAL_CLK      1843200
 235
 236 #define ASIXNET_BASE    (CPU_S3C2410X_CS5 + BAST_PA_ASIXNET)
 237 #define ASIXNET_SIZE    (0x400)
 238 #define AX88796_BASE    (CPU_S3C2410X_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20))
 239 #define AX88796_SIZE    (3 * 0x20)
 240
 241 #define DM9000_BASE     (0x2d000000)
 242 #define DM9000_IRQ      10
 243
 244 #define logout(fmt, ...) \
 245     fprintf(stderr, "AX88796\t%-24s" fmt, __func__, ##__VA_ARGS__)
 246
 247 #define TYPE_AX88796 "ax88796"
 248 #define AX88796(obj) OBJECT_CHECK(AX88796State, (obj), TYPE_AX88796)
 249
 250 typedef struct {
 251     SysBusDevice busdev;
 252     MemoryRegion mmio;
 253     NICState *nic;
 254     NICConf conf;
 255 } AX88796State;
 256
 257 static uint64_t ax88796_read(void *opaque, hwaddr offset,
 258                              unsigned size)
 259 {
 260     //~ AX88796State *s = opaque;
 261     uint32_t value = 0;
 262
 263     switch (offset) {
 264         case 0x0000:
 265         case 0x000d:
 266         case 0x0020:
 267         case 0x0040:
 268         case 0x0060:
 269         case 0x0080:
 270         case 0x00a0:
 271         case 0x00c0:
 272         case 0x00e0:
 273         case 0x02e0:
 274         case 0x03e0:
 275             ;
 276             //~ return 0; // FIXME
 277     }
 278
 279     logout("0x" TARGET_FMT_plx " 0x%08x\n", offset, value);
 280     return value;
 281 }
 282
 283 static void ax88796_write(void *opaque, hwaddr offset,
 284                           uint64_t value, unsigned size)
 285 {
 286     //~ AX88796State *s = opaque;
 287     switch (offset) {
 288         case 0x0000:
 289         case 0x000d:
 290         case 0x0020:
 291         case 0x0040:
 292         case 0x0060:
 293         case 0x0080:
 294         case 0x00a0:
 295         case 0x00c0:
 296         case 0x00e0:
 297         case 0x02e0:
 298         case 0x03e0:
 299             ;
 300             //~ return; // FIXME
 301     }
 302     logout("0x" TARGET_FMT_plx " 0x%08" PRIx64 "\n", offset, value);
 303 }
 304
 305 static const MemoryRegionOps ax88796_ops = {
 306     .read = ax88796_read,
 307     .write = ax88796_write,
 308     .endianness = DEVICE_NATIVE_ENDIAN,
 309     .valid = {
 310         .min_access_size = 4,
 311         .max_access_size = 4
 312     }
 313 };
 314
 315 static int ax88796_init(SysBusDevice *sbd)
 316 {
 317     DeviceState *dev = DEVICE(sbd);
 318     AX88796State *s = AX88796(dev);
 319
 320     logout("\n");
 321
 322     memory_region_init_io(&s->mmio, OBJECT(s),
 323                           &ax88796_ops, s, TYPE_AX88796, ASIXNET_SIZE);
 324     //~ sysbus_init_mmio(sbd, AX88796_SIZE, iomemtype);
 325     sysbus_init_mmio(sbd, &s->mmio);
 326     //~ sysbus_init_irq(dev, &s->irq);
 327     //~ ax88796_reset(s);
 328 #if 0
 329     isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
 330     ISANE2000State *isa = DO_UPCAST(ISANE2000State, dev, dev);
 331     NE2000State *s = &isa->ne2000;
 332
 333     register_ioport_write(isa->iobase, 16, 1, ne2000_ioport_write, s);
 334     register_ioport_read(isa->iobase, 16, 1, ne2000_ioport_read, s);
 335
 336     register_ioport_write(isa->iobase + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 337     register_ioport_read(isa->iobase + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 338     register_ioport_write(isa->iobase + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 339     register_ioport_read(isa->iobase + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 340
 341     register_ioport_write(isa->iobase + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 342     register_ioport_read(isa->iobase + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 343
 344     isa_init_irq(dev, &s->irq, isa->isairq);
 345
 346     qemu_macaddr_default_if_unset(&s->c.macaddr);
 347     ne2000_reset(s);
 348
 349     s->nic = qemu_new_nic(&net_ne2000_isa_info, &s->c,
 350                           object_get_typename(OBJECT(dev)), dev->qdev.id, s);
 351     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a);
 352 #endif
 353     return 0;
 354 }
 355
 356 static const VMStateDescription ax88796_vmsd = {
 357     .name = TYPE_AX88796,
 358     .version_id = 1,
 359     .minimum_version_id = 1,
 360     .minimum_version_id_old = 1,
 361     .fields = (VMStateField[]) {
 362         VMSTATE_END_OF_LIST()
 363     }
 364 };
 365
 366 static Property ax88796_properties[] = {
 367     DEFINE_NIC_PROPERTIES(AX88796State, conf),
 368     DEFINE_PROP_END_OF_LIST()
 369 };
 370
 371 static void ax88796_class_init(ObjectClass *klass, void *data)
 372 {
 373     DeviceClass *dc = DEVICE_CLASS(klass);
 374     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 375     dc->vmsd = &ax88796_vmsd;
 376     dc->props = ax88796_properties;
 377     k->init = ax88796_init;
 378 }
 379
 380 static const TypeInfo ax88796_info = {
 381     .name = TYPE_AX88796,
 382     .parent = TYPE_SYS_BUS_DEVICE,
 383     .instance_size = sizeof(AX88796State),
 384     .class_init = ax88796_class_init
 385 };
 386
 387 static void ax88796_register_types(void)
 388 {
 389     type_register_static(&ax88796_info);
 390 }
 391
 392 type_init(ax88796_register_types)
 393
 394
 395 static void stcb_i2c_setup(STCBState *stcb)
 396 {
 397     I2CBus *bus = s3c24xx_i2c_bus(stcb->soc->iic);
 398     uint8_t *eeprom_buf = g_malloc0(256);
 399     DeviceState *eeprom;
 400     eeprom = qdev_create((BusState *)bus, "smbus-eeprom");
 401     qdev_prop_set_uint8(eeprom, "address", 0x50);
 402     qdev_prop_set_ptr(eeprom, "data", eeprom_buf);
 403     qdev_init_nofail(eeprom);
 404
 405     i2c_create_slave(bus, "ch7xxx", 0x75);
 406     i2c_create_slave(bus, "stcpmu", 0x6B);
 407 }
 408
 409
 410 static struct arm_boot_info bast_binfo = {
 411     .board_id = BAST_BOARD_ID,
 412     .ram_size = 0x10000000, /* 256MB */
 413 };
 414
 415 static void stcb_init(MachineState *machine)
 416 {
 417     MemoryRegion *sysmem = get_system_memory();
 418     STCBState *stcb;
 419     Chardev *chr;
 420     DeviceState *dev;
 421     DriveInfo *dinfo;
 422     NICInfo *nd;
 423     SysBusDevice *s;
 424     int i;
 425     int ret;
 426     BlockBackend *flash_bds = NULL;
 427     //~ qemu_irq *i8259;
 428
 429     /* ensure memory is limited to 256MB */
 430     if (machine->ram_size > (256 * MiB)) {
 431         machine->ram_size = 256 * MiB;
 432     }
 433     ram_size = machine->ram_size;
 434
 435     /* initialise board informations */
 436     bast_binfo.ram_size = ram_size;
 437     bast_binfo.kernel_filename = machine->kernel_filename;
 438     bast_binfo.kernel_cmdline = machine->kernel_cmdline;
 439     bast_binfo.initrd_filename = machine->initrd_filename;
 440     bast_binfo.nb_cpus = 1;
 441     bast_binfo.loader_start = BAST_NOR_RO_BASE;
 442
 443     /* allocate storage for board state */
 444     stcb = g_malloc0(sizeof(STCBState));
 445
 446     /* Make sure all serial ports are associated with a device. */
 447     for (i = 0; i < serial_max_hds(); i++) {
 448 #if 1
 449         assert(serial_hd(i));
 450 #else
 451         /* TODO: This code no longer works. Remove or replace. */
 452         if (!serial_hd(i)) {
 453             char label[32];
 454             snprintf(label, sizeof(label), "serial%d", i);
 455             serial_hd(i) = qemu_chr_new(label, "vc:80Cx24C");
 456         }
 457 #endif
 458     }
 459
 460     /* initialise SOC */
 461     stcb->soc = s3c2410x_init(ram_size);
 462
 463     stcb_register_ide(stcb);
 464
 465     dinfo = drive_get(IF_PFLASH, 0, 0);
 466     /* Acquire flash contents and register pflash device */
 467     if (dinfo) {
 468         /* load from specified flash device */
 469         flash_bds = blk_by_legacy_dinfo(dinfo);
 470     } else {
 471         /* Try and load default bootloader image */
 472         char *filename= qemu_find_file(QEMU_FILE_TYPE_BIOS, BIOS_FILENAME);
 473         if (filename) {
 474             ret = load_image_targphys(filename,
 475                                       BAST_NOR_RO_BASE, BAST_NOR_SIZE);
 476             (void)ret;
 477             g_free(filename);
 478         }
 479     }
 480
 481     pflash_cfi02_register(BAST_NOR_RW_BASE, NULL, "bast.flash",
 482                           BAST_NOR_SIZE, flash_bds, 65536, 32, 1, 2,
 483                           0x00BF, 0x234B, 0x0000, 0x0000, 0x5555, 0x2AAA,
 484                           false);
 485     /* TODO: Read only ROM type mapping to address BAST_NOR_RO_BASE. */
 486
 487     /* if kernel is given, boot that directly */
 488     if (machine->kernel_filename != NULL) {
 489         bast_binfo.loader_start = CPU_S3C2410X_DRAM;
 490         //~ bast_binfo.loader_start = 0xc0108000 - 0x00010000;
 491         arm_load_kernel(stcb->soc->cpu, &bast_binfo);
 492     }
 493
 494     /* Setup initial (reset) program counter */
 495     stcb->soc->cpu->env.regs[15] = bast_binfo.loader_start;
 496
 497     nd = &nd_table[0];
 498     if (nd->used) {
 499         qemu_check_nic_model(nd, "dm9000");
 500         dev = qdev_create(NULL, "dm9000");
 501         qdev_set_nic_properties(dev, nd);
 502         qdev_init_nofail(dev);
 503         s = SYS_BUS_DEVICE(dev);
 504         sysbus_mmio_map(s, 0, DM9000_BASE);
 505         sysbus_connect_irq(s, 0, s3c24xx_get_eirq(stcb->soc->gpio, DM9000_IRQ));
 506     }
 507
 508     nd = &nd_table[1];
 509     if (nd->used) {
 510         qemu_check_nic_model(nd, TYPE_AX88796);
 511         dev = qdev_create(NULL, TYPE_AX88796);
 512         qdev_set_nic_properties(dev, nd);
 513         qdev_init_nofail(dev);
 514         s = SYS_BUS_DEVICE(dev);
 515         sysbus_mmio_map(s, 0, ASIXNET_BASE);
 516         logout("ASIXNET_BASE = 0x%08x\n", ASIXNET_BASE);
 517         logout("AX88796_BASE = 0x%08x\n", AX88796_BASE);
 518         //~ sysbus_connect_irq(s, 0, s3c24xx_get_eirq(stcb->soc->gpio, AX88796_IRQ));
 519     }
 520
 521     /* Initialise the BAST CPLD */
 522     stcb_cpld_register(stcb);
 523
 524     /* attach i2c devices */
 525     stcb_i2c_setup(stcb);
 526
 527     /* Attach some NAND devices */
 528     stcb->nand[0] = NULL;
 529     stcb->nand[1] = NULL;
 530     dinfo = drive_get(IF_MTD, 0, 0);
 531     if (!dinfo) {
 532         stcb->nand[2] = NULL;
 533     } else {
 534         stcb->nand[2] = nand_init(NULL, 0xEC, 0x79); /* 128MiB small-page */
 535     }
 536
 537     chr = qemu_chr_new("uart0", "vc:80Cx24C");
 538     serial_mm_init(sysmem, SERIAL_BASE + 0x2f8, 0,
 539                    s3c24xx_get_eirq(stcb->soc->gpio, 15),
 540                    SERIAL_CLK, chr, DEVICE_NATIVE_ENDIAN);
 541     chr = qemu_chr_new("uart1", "vc:80Cx24C");
 542     serial_mm_init(sysmem, SERIAL_BASE + 0x3f8, 0,
 543                    s3c24xx_get_eirq(stcb->soc->gpio, 14),
 544                    SERIAL_CLK, chr, DEVICE_NATIVE_ENDIAN);
 545 #if 0
 546     /* Super I/O */
 547     isa_bus_new(NULL);
 548     i8259 = i8259_init(s3c24xx_get_eirq(stcb->soc->gpio, 4));
 549     isa_bus_irqs(i8259);
 550     /*isa_dev =*/ isa_create_simple("i8042");
 551     serial_isa_init(0, serial_hd(0));
 552     serial_isa_init(1, serial_hd(1));
 553 #endif
 554 }
 555
 556 static void bast_machine_init(MachineClass *mc)
 557 {
 558     mc->desc = "Simtec Electronics BAST (S3C2410A, ARM920T)";
 559     mc->init = stcb_init;
 560     mc->max_cpus = 1;
 561 };
 562
 563 DEFINE_MACHINE("bast", bast_machine_init)