2 * ARM Nested Vectored Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
17 #include "hw/sysbus.h"
18 #include "qemu/timer.h"
19 #include "hw/arm/arm.h"
20 #include "hw/intc/armv7m_nvic.h"
21 #include "target/arm/cpu.h"
22 #include "exec/exec-all.h"
26 /* IRQ number counting:
28 * the num-irq property counts the number of external IRQ lines
30 * NVICState::num_irq counts the total number of exceptions
31 * (external IRQs, the 15 internal exceptions including reset,
32 * and one for the unused exception number 0).
34 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
36 * NVIC_MAX_VECTORS is the highest permitted number of exceptions.
38 * Iterating through all exceptions should typically be done with
39 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
41 * The external qemu_irq lines are the NVIC's external IRQ lines,
42 * so line 0 is exception 16.
44 * In the terminology of the architecture manual, "interrupts" are
45 * a subcategory of exception referring to the external interrupts
46 * (which are exception numbers NVIC_FIRST_IRQ and upward).
47 * For historical reasons QEMU tends to use "interrupt" and
48 * "exception" more or less interchangeably.
50 #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
51 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
53 /* Effective running priority of the CPU when no exception is active
54 * (higher than the highest possible priority value)
56 #define NVIC_NOEXC_PRIO 0x100
57 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
58 #define NVIC_NS_PRIO_LIMIT 0x80
60 static const uint8_t nvic_id
[] = {
61 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
64 static int nvic_pending_prio(NVICState
*s
)
66 /* return the group priority of the current pending interrupt,
67 * or NVIC_NOEXC_PRIO if no interrupt is pending
69 return s
->vectpending_prio
;
72 /* Return the value of the ISCR RETTOBASE bit:
73 * 1 if there is exactly one active exception
74 * 0 if there is more than one active exception
75 * UNKNOWN if there are no active exceptions (we choose 1,
76 * which matches the choice Cortex-M3 is documented as making).
78 * NB: some versions of the documentation talk about this
79 * counting "active exceptions other than the one shown by IPSR";
80 * this is only different in the obscure corner case where guest
81 * code has manually deactivated an exception and is about
82 * to fail an exception-return integrity check. The definition
83 * above is the one from the v8M ARM ARM and is also in line
84 * with the behaviour documented for the Cortex-M3.
86 static bool nvic_rettobase(NVICState
*s
)
89 bool check_sec
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
);
91 for (irq
= ARMV7M_EXCP_RESET
; irq
< s
->num_irq
; irq
++) {
92 if (s
->vectors
[irq
].active
||
93 (check_sec
&& irq
< NVIC_INTERNAL_VECTORS
&&
94 s
->sec_vectors
[irq
].active
)) {
105 /* Return the value of the ISCR ISRPENDING bit:
106 * 1 if an external interrupt is pending
107 * 0 if no external interrupt is pending
109 static bool nvic_isrpending(NVICState
*s
)
113 /* We can shortcut if the highest priority pending interrupt
114 * happens to be external or if there is nothing pending.
116 if (s
->vectpending
> NVIC_FIRST_IRQ
) {
119 if (s
->vectpending
== 0) {
123 for (irq
= NVIC_FIRST_IRQ
; irq
< s
->num_irq
; irq
++) {
124 if (s
->vectors
[irq
].pending
) {
131 static bool exc_is_banked(int exc
)
133 /* Return true if this is one of the limited set of exceptions which
134 * are banked (and thus have state in sec_vectors[])
136 return exc
== ARMV7M_EXCP_HARD
||
137 exc
== ARMV7M_EXCP_MEM
||
138 exc
== ARMV7M_EXCP_USAGE
||
139 exc
== ARMV7M_EXCP_SVC
||
140 exc
== ARMV7M_EXCP_PENDSV
||
141 exc
== ARMV7M_EXCP_SYSTICK
;
144 /* Return a mask word which clears the subpriority bits from
145 * a priority value for an M-profile exception, leaving only
146 * the group priority.
148 static inline uint32_t nvic_gprio_mask(NVICState
*s
, bool secure
)
150 return ~0U << (s
->prigroup
[secure
] + 1);
153 static bool exc_targets_secure(NVICState
*s
, int exc
)
155 /* Return true if this non-banked exception targets Secure state. */
156 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
160 if (exc
>= NVIC_FIRST_IRQ
) {
161 return !s
->itns
[exc
];
164 /* Function shouldn't be called for banked exceptions. */
165 assert(!exc_is_banked(exc
));
168 case ARMV7M_EXCP_NMI
:
169 case ARMV7M_EXCP_BUS
:
170 return !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
171 case ARMV7M_EXCP_SECURE
:
173 case ARMV7M_EXCP_DEBUG
:
174 /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
177 /* reset, and reserved (unused) low exception numbers.
178 * We'll get called by code that loops through all the exception
179 * numbers, but it doesn't matter what we return here as these
180 * non-existent exceptions will never be pended or active.
186 static int exc_group_prio(NVICState
*s
, int rawprio
, bool targets_secure
)
188 /* Return the group priority for this exception, given its raw
189 * (group-and-subgroup) priority value and whether it is targeting
190 * secure state or not.
195 rawprio
&= nvic_gprio_mask(s
, targets_secure
);
196 /* AIRCR.PRIS causes us to squash all NS priorities into the
197 * lower half of the total range
199 if (!targets_secure
&&
200 (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
)) {
201 rawprio
= (rawprio
>> 1) + NVIC_NS_PRIO_LIMIT
;
206 /* Recompute vectpending and exception_prio for a CPU which implements
207 * the Security extension
209 static void nvic_recompute_state_secure(NVICState
*s
)
212 int pend_prio
= NVIC_NOEXC_PRIO
;
213 int active_prio
= NVIC_NOEXC_PRIO
;
215 bool pending_is_s_banked
= false;
217 /* R_CQRV: precedence is by:
218 * - lowest group priority; if both the same then
219 * - lowest subpriority; if both the same then
220 * - lowest exception number; if both the same (ie banked) then
221 * - secure exception takes precedence
222 * Compare pseudocode RawExecutionPriority.
223 * Annoyingly, now we have two prigroup values (for S and NS)
224 * we can't do the loop comparison on raw priority values.
226 for (i
= 1; i
< s
->num_irq
; i
++) {
227 for (bank
= M_REG_S
; bank
>= M_REG_NS
; bank
--) {
232 if (bank
== M_REG_S
) {
233 if (!exc_is_banked(i
)) {
236 vec
= &s
->sec_vectors
[i
];
237 targets_secure
= true;
239 vec
= &s
->vectors
[i
];
240 targets_secure
= !exc_is_banked(i
) && exc_targets_secure(s
, i
);
243 prio
= exc_group_prio(s
, vec
->prio
, targets_secure
);
244 if (vec
->enabled
&& vec
->pending
&& prio
< pend_prio
) {
247 pending_is_s_banked
= (bank
== M_REG_S
);
249 if (vec
->active
&& prio
< active_prio
) {
255 s
->vectpending_is_s_banked
= pending_is_s_banked
;
256 s
->vectpending
= pend_irq
;
257 s
->vectpending_prio
= pend_prio
;
258 s
->exception_prio
= active_prio
;
260 trace_nvic_recompute_state_secure(s
->vectpending
,
261 s
->vectpending_is_s_banked
,
266 /* Recompute vectpending and exception_prio */
267 static void nvic_recompute_state(NVICState
*s
)
270 int pend_prio
= NVIC_NOEXC_PRIO
;
271 int active_prio
= NVIC_NOEXC_PRIO
;
274 /* In theory we could write one function that handled both
275 * the "security extension present" and "not present"; however
276 * the security related changes significantly complicate the
277 * recomputation just by themselves and mixing both cases together
278 * would be even worse, so we retain a separate non-secure-only
279 * version for CPUs which don't implement the security extension.
281 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
282 nvic_recompute_state_secure(s
);
286 for (i
= 1; i
< s
->num_irq
; i
++) {
287 VecInfo
*vec
= &s
->vectors
[i
];
289 if (vec
->enabled
&& vec
->pending
&& vec
->prio
< pend_prio
) {
290 pend_prio
= vec
->prio
;
293 if (vec
->active
&& vec
->prio
< active_prio
) {
294 active_prio
= vec
->prio
;
298 if (active_prio
> 0) {
299 active_prio
&= nvic_gprio_mask(s
, false);
303 pend_prio
&= nvic_gprio_mask(s
, false);
306 s
->vectpending
= pend_irq
;
307 s
->vectpending_prio
= pend_prio
;
308 s
->exception_prio
= active_prio
;
310 trace_nvic_recompute_state(s
->vectpending
,
315 /* Return the current execution priority of the CPU
316 * (equivalent to the pseudocode ExecutionPriority function).
317 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
319 static inline int nvic_exec_prio(NVICState
*s
)
321 CPUARMState
*env
= &s
->cpu
->env
;
322 int running
= NVIC_NOEXC_PRIO
;
324 if (env
->v7m
.basepri
[M_REG_NS
] > 0) {
325 running
= exc_group_prio(s
, env
->v7m
.basepri
[M_REG_NS
], M_REG_NS
);
328 if (env
->v7m
.basepri
[M_REG_S
] > 0) {
329 int basepri
= exc_group_prio(s
, env
->v7m
.basepri
[M_REG_S
], M_REG_S
);
330 if (running
> basepri
) {
335 if (env
->v7m
.primask
[M_REG_NS
]) {
336 if (env
->v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
) {
337 if (running
> NVIC_NS_PRIO_LIMIT
) {
338 running
= NVIC_NS_PRIO_LIMIT
;
345 if (env
->v7m
.primask
[M_REG_S
]) {
349 if (env
->v7m
.faultmask
[M_REG_NS
]) {
350 if (env
->v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
353 if (env
->v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
) {
354 if (running
> NVIC_NS_PRIO_LIMIT
) {
355 running
= NVIC_NS_PRIO_LIMIT
;
363 if (env
->v7m
.faultmask
[M_REG_S
]) {
364 running
= (env
->v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) ? -3 : -1;
367 /* consider priority of active handler */
368 return MIN(running
, s
->exception_prio
);
371 bool armv7m_nvic_neg_prio_requested(void *opaque
, bool secure
)
373 /* Return true if the requested execution priority is negative
374 * for the specified security state, ie that security state
375 * has an active NMI or HardFault or has set its FAULTMASK.
376 * Note that this is not the same as whether the execution
377 * priority is actually negative (for instance AIRCR.PRIS may
378 * mean we don't allow FAULTMASK_NS to actually make the execution
379 * priority negative). Compare pseudocode IsReqExcPriNeg().
381 NVICState
*s
= opaque
;
383 if (s
->cpu
->env
.v7m
.faultmask
[secure
]) {
387 if (secure
? s
->sec_vectors
[ARMV7M_EXCP_HARD
].active
:
388 s
->vectors
[ARMV7M_EXCP_HARD
].active
) {
392 if (s
->vectors
[ARMV7M_EXCP_NMI
].active
&&
393 exc_targets_secure(s
, ARMV7M_EXCP_NMI
) == secure
) {
400 bool armv7m_nvic_can_take_pending_exception(void *opaque
)
402 NVICState
*s
= opaque
;
404 return nvic_exec_prio(s
) > nvic_pending_prio(s
);
407 int armv7m_nvic_raw_execution_priority(void *opaque
)
409 NVICState
*s
= opaque
;
411 return s
->exception_prio
;
414 /* caller must call nvic_irq_update() after this.
415 * secure indicates the bank to use for banked exceptions (we assert if
416 * we are passed secure=true for a non-banked exception).
418 static void set_prio(NVICState
*s
, unsigned irq
, bool secure
, uint8_t prio
)
420 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
421 assert(irq
< s
->num_irq
);
424 assert(exc_is_banked(irq
));
425 s
->sec_vectors
[irq
].prio
= prio
;
427 s
->vectors
[irq
].prio
= prio
;
430 trace_nvic_set_prio(irq
, secure
, prio
);
433 /* Return the current raw priority register value.
434 * secure indicates the bank to use for banked exceptions (we assert if
435 * we are passed secure=true for a non-banked exception).
437 static int get_prio(NVICState
*s
, unsigned irq
, bool secure
)
439 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
440 assert(irq
< s
->num_irq
);
443 assert(exc_is_banked(irq
));
444 return s
->sec_vectors
[irq
].prio
;
446 return s
->vectors
[irq
].prio
;
450 /* Recompute state and assert irq line accordingly.
451 * Must be called after changes to:
452 * vec->active, vec->enabled, vec->pending or vec->prio for any vector
455 static void nvic_irq_update(NVICState
*s
)
460 nvic_recompute_state(s
);
461 pend_prio
= nvic_pending_prio(s
);
463 /* Raise NVIC output if this IRQ would be taken, except that we
464 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
465 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes
466 * to those CPU registers don't cause us to recalculate the NVIC
469 lvl
= (pend_prio
< s
->exception_prio
);
470 trace_nvic_irq_update(s
->vectpending
, pend_prio
, s
->exception_prio
, lvl
);
471 qemu_set_irq(s
->excpout
, lvl
);
475 * armv7m_nvic_clear_pending: mark the specified exception as not pending
477 * @irq: the exception number to mark as not pending
478 * @secure: false for non-banked exceptions or for the nonsecure
479 * version of a banked exception, true for the secure version of a banked
482 * Marks the specified exception as not pending. Note that we will assert()
483 * if @secure is true and @irq does not specify one of the fixed set
484 * of architecturally banked exceptions.
486 static void armv7m_nvic_clear_pending(void *opaque
, int irq
, bool secure
)
488 NVICState
*s
= (NVICState
*)opaque
;
491 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
494 assert(exc_is_banked(irq
));
495 vec
= &s
->sec_vectors
[irq
];
497 vec
= &s
->vectors
[irq
];
499 trace_nvic_clear_pending(irq
, secure
, vec
->enabled
, vec
->prio
);
506 void armv7m_nvic_set_pending(void *opaque
, int irq
, bool secure
)
508 NVICState
*s
= (NVICState
*)opaque
;
509 bool banked
= exc_is_banked(irq
);
512 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
513 assert(!secure
|| banked
);
515 vec
= (banked
&& secure
) ? &s
->sec_vectors
[irq
] : &s
->vectors
[irq
];
517 trace_nvic_set_pending(irq
, secure
, vec
->enabled
, vec
->prio
);
519 if (irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
) {
520 /* If a synchronous exception is pending then it may be
521 * escalated to HardFault if:
522 * * it is equal or lower priority to current execution
524 * (ie we need to take it immediately but we can't do so).
525 * Asynchronous exceptions (and interrupts) simply remain pending.
527 * For QEMU, we don't have any imprecise (asynchronous) faults,
528 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
530 * Debug exceptions are awkward because only Debug exceptions
531 * resulting from the BKPT instruction should be escalated,
532 * but we don't currently implement any Debug exceptions other
533 * than those that result from BKPT, so we treat all debug exceptions
534 * as needing escalation.
536 * This all means we can identify whether to escalate based only on
537 * the exception number and don't (yet) need the caller to explicitly
538 * tell us whether this exception is synchronous or not.
540 int running
= nvic_exec_prio(s
);
541 bool escalate
= false;
543 if (exc_group_prio(s
, vec
->prio
, secure
) >= running
) {
544 trace_nvic_escalate_prio(irq
, vec
->prio
, running
);
546 } else if (!vec
->enabled
) {
547 trace_nvic_escalate_disabled(irq
);
553 /* We need to escalate this exception to a synchronous HardFault.
554 * If BFHFNMINS is set then we escalate to the banked HF for
555 * the target security state of the original exception; otherwise
556 * we take a Secure HardFault.
558 irq
= ARMV7M_EXCP_HARD
;
559 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
) &&
561 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))) {
562 vec
= &s
->sec_vectors
[irq
];
564 vec
= &s
->vectors
[irq
];
566 if (running
<= vec
->prio
) {
567 /* We want to escalate to HardFault but we can't take the
568 * synchronous HardFault at this point either. This is a
569 * Lockup condition due to a guest bug. We don't model
570 * Lockup, so report via cpu_abort() instead.
572 cpu_abort(&s
->cpu
->parent_obj
,
573 "Lockup: can't escalate %d to HardFault "
574 "(current priority %d)\n", irq
, running
);
577 /* HF may be banked but there is only one shared HFSR */
578 s
->cpu
->env
.v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
588 /* Make pending IRQ active. */
589 bool armv7m_nvic_acknowledge_irq(void *opaque
)
591 NVICState
*s
= (NVICState
*)opaque
;
592 CPUARMState
*env
= &s
->cpu
->env
;
593 const int pending
= s
->vectpending
;
594 const int running
= nvic_exec_prio(s
);
598 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
600 if (s
->vectpending_is_s_banked
) {
601 vec
= &s
->sec_vectors
[pending
];
602 targets_secure
= true;
604 vec
= &s
->vectors
[pending
];
605 targets_secure
= !exc_is_banked(s
->vectpending
) &&
606 exc_targets_secure(s
, s
->vectpending
);
609 assert(vec
->enabled
);
610 assert(vec
->pending
);
612 assert(s
->vectpending_prio
< running
);
614 trace_nvic_acknowledge_irq(pending
, s
->vectpending_prio
, targets_secure
);
619 write_v7m_exception(env
, s
->vectpending
);
623 return targets_secure
;
626 int armv7m_nvic_complete_irq(void *opaque
, int irq
, bool secure
)
628 NVICState
*s
= (NVICState
*)opaque
;
632 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
634 if (secure
&& exc_is_banked(irq
)) {
635 vec
= &s
->sec_vectors
[irq
];
637 vec
= &s
->vectors
[irq
];
640 trace_nvic_complete_irq(irq
, secure
);
643 /* Tell the caller this was an illegal exception return */
647 ret
= nvic_rettobase(s
);
651 /* Re-pend the exception if it's still held high; only
652 * happens for extenal IRQs
654 assert(irq
>= NVIC_FIRST_IRQ
);
663 /* callback when external interrupt line is changed */
664 static void set_irq_level(void *opaque
, int n
, int level
)
666 NVICState
*s
= opaque
;
671 assert(n
>= NVIC_FIRST_IRQ
&& n
< s
->num_irq
);
673 trace_nvic_set_irq_level(n
, level
);
675 /* The pending status of an external interrupt is
676 * latched on rising edge and exception handler return.
678 * Pulsing the IRQ will always run the handler
679 * once, and the handler will re-run until the
680 * level is low when the handler completes.
682 vec
= &s
->vectors
[n
];
683 if (level
!= vec
->level
) {
686 armv7m_nvic_set_pending(s
, n
, false);
691 static uint32_t nvic_readl(NVICState
*s
, uint32_t offset
, MemTxAttrs attrs
)
693 ARMCPU
*cpu
= s
->cpu
;
697 case 4: /* Interrupt Control Type. */
698 return ((s
->num_irq
- NVIC_FIRST_IRQ
) / 32) - 1;
699 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
701 int startvec
= 32 * (offset
- 0x380) + NVIC_FIRST_IRQ
;
704 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
711 for (i
= 0; i
< 32 && startvec
+ i
< s
->num_irq
; i
++) {
712 if (s
->itns
[startvec
+ i
]) {
718 case 0xd00: /* CPUID Base. */
720 case 0xd04: /* Interrupt Control State (ICSR) */
722 val
= cpu
->env
.v7m
.exception
;
724 val
|= (s
->vectpending
& 0xff) << 12;
725 /* ISRPENDING - set if any external IRQ is pending */
726 if (nvic_isrpending(s
)) {
729 /* RETTOBASE - set if only one handler is active */
730 if (nvic_rettobase(s
)) {
735 if (s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
739 if (s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
744 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
748 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
753 if ((cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
754 s
->vectors
[ARMV7M_EXCP_NMI
].pending
) {
757 /* ISRPREEMPT: RES0 when halting debug not implemented */
758 /* STTNS: RES0 for the Main Extension */
760 case 0xd08: /* Vector Table Offset. */
761 return cpu
->env
.v7m
.vecbase
[attrs
.secure
];
762 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
763 val
= 0xfa050000 | (s
->prigroup
[attrs
.secure
] << 8);
765 /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
766 val
|= cpu
->env
.v7m
.aircr
;
768 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
769 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
770 * security isn't supported then BFHFNMINS is RAO (and
771 * the bit in env.v7m.aircr is always set).
773 val
|= cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
;
777 case 0xd10: /* System Control. */
778 /* TODO: Implement SLEEPONEXIT. */
780 case 0xd14: /* Configuration Control. */
781 /* The BFHFNMIGN bit is the only non-banked bit; we
782 * keep it in the non-secure copy of the register.
784 val
= cpu
->env
.v7m
.ccr
[attrs
.secure
];
785 val
|= cpu
->env
.v7m
.ccr
[M_REG_NS
] & R_V7M_CCR_BFHFNMIGN_MASK
;
787 case 0xd24: /* System Handler Control and State (SHCSR) */
790 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].active
) {
793 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].active
) {
796 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].active
) {
799 if (s
->sec_vectors
[ARMV7M_EXCP_SVC
].active
) {
802 if (s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].active
) {
805 if (s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
808 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].pending
) {
811 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].pending
) {
814 if (s
->sec_vectors
[ARMV7M_EXCP_SVC
].pending
) {
817 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].enabled
) {
820 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
823 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].pending
) {
826 /* SecureFault is not banked but is always RAZ/WI to NS */
827 if (s
->vectors
[ARMV7M_EXCP_SECURE
].active
) {
830 if (s
->vectors
[ARMV7M_EXCP_SECURE
].enabled
) {
833 if (s
->vectors
[ARMV7M_EXCP_SECURE
].pending
) {
837 if (s
->vectors
[ARMV7M_EXCP_MEM
].active
) {
840 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
841 /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
842 if (s
->vectors
[ARMV7M_EXCP_HARD
].active
) {
845 if (s
->vectors
[ARMV7M_EXCP_HARD
].pending
) {
849 if (s
->vectors
[ARMV7M_EXCP_USAGE
].active
) {
852 if (s
->vectors
[ARMV7M_EXCP_SVC
].active
) {
855 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].active
) {
858 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
861 if (s
->vectors
[ARMV7M_EXCP_USAGE
].pending
) {
864 if (s
->vectors
[ARMV7M_EXCP_MEM
].pending
) {
867 if (s
->vectors
[ARMV7M_EXCP_SVC
].pending
) {
870 if (s
->vectors
[ARMV7M_EXCP_MEM
].enabled
) {
873 if (s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
877 if (attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
878 if (s
->vectors
[ARMV7M_EXCP_BUS
].active
) {
881 if (s
->vectors
[ARMV7M_EXCP_BUS
].pending
) {
884 if (s
->vectors
[ARMV7M_EXCP_BUS
].enabled
) {
887 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
888 s
->vectors
[ARMV7M_EXCP_NMI
].active
) {
889 /* NMIACT is not present in v7M */
894 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
895 if (s
->vectors
[ARMV7M_EXCP_DEBUG
].active
) {
899 case 0xd28: /* Configurable Fault Status. */
900 /* The BFSR bits [15:8] are shared between security states
901 * and we store them in the NS copy
903 val
= cpu
->env
.v7m
.cfsr
[attrs
.secure
];
904 val
|= cpu
->env
.v7m
.cfsr
[M_REG_NS
] & R_V7M_CFSR_BFSR_MASK
;
906 case 0xd2c: /* Hard Fault Status. */
907 return cpu
->env
.v7m
.hfsr
;
908 case 0xd30: /* Debug Fault Status. */
909 return cpu
->env
.v7m
.dfsr
;
910 case 0xd34: /* MMFAR MemManage Fault Address */
911 return cpu
->env
.v7m
.mmfar
[attrs
.secure
];
912 case 0xd38: /* Bus Fault Address. */
913 return cpu
->env
.v7m
.bfar
;
914 case 0xd3c: /* Aux Fault Status. */
915 /* TODO: Implement fault status registers. */
916 qemu_log_mask(LOG_UNIMP
,
917 "Aux Fault status registers unimplemented\n");
919 case 0xd40: /* PFR0. */
921 case 0xd44: /* PRF1. */
923 case 0xd48: /* DFR0. */
925 case 0xd4c: /* AFR0. */
927 case 0xd50: /* MMFR0. */
929 case 0xd54: /* MMFR1. */
931 case 0xd58: /* MMFR2. */
933 case 0xd5c: /* MMFR3. */
935 case 0xd60: /* ISAR0. */
937 case 0xd64: /* ISAR1. */
939 case 0xd68: /* ISAR2. */
941 case 0xd6c: /* ISAR3. */
943 case 0xd70: /* ISAR4. */
945 /* TODO: Implement debug registers. */
946 case 0xd90: /* MPU_TYPE */
947 /* Unified MPU; if the MPU is not present this value is zero */
948 return cpu
->pmsav7_dregion
<< 8;
950 case 0xd94: /* MPU_CTRL */
951 return cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
];
952 case 0xd98: /* MPU_RNR */
953 return cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
954 case 0xd9c: /* MPU_RBAR */
955 case 0xda4: /* MPU_RBAR_A1 */
956 case 0xdac: /* MPU_RBAR_A2 */
957 case 0xdb4: /* MPU_RBAR_A3 */
959 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
961 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
962 /* PMSAv8M handling of the aliases is different from v7M:
963 * aliases A1, A2, A3 override the low two bits of the region
964 * number in MPU_RNR, and there is no 'region' field in the
967 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
969 region
= deposit32(region
, 0, 2, aliasno
);
971 if (region
>= cpu
->pmsav7_dregion
) {
974 return cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
];
977 if (region
>= cpu
->pmsav7_dregion
) {
980 return (cpu
->env
.pmsav7
.drbar
[region
] & 0x1f) | (region
& 0xf);
982 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
983 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
984 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
985 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
987 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
989 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
990 /* PMSAv8M handling of the aliases is different from v7M:
991 * aliases A1, A2, A3 override the low two bits of the region
994 int aliasno
= (offset
- 0xda0) / 8; /* 0..3 */
996 region
= deposit32(region
, 0, 2, aliasno
);
998 if (region
>= cpu
->pmsav7_dregion
) {
1001 return cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
];
1004 if (region
>= cpu
->pmsav7_dregion
) {
1007 return ((cpu
->env
.pmsav7
.dracr
[region
] & 0xffff) << 16) |
1008 (cpu
->env
.pmsav7
.drsr
[region
] & 0xffff);
1010 case 0xdc0: /* MPU_MAIR0 */
1011 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1014 return cpu
->env
.pmsav8
.mair0
[attrs
.secure
];
1015 case 0xdc4: /* MPU_MAIR1 */
1016 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1019 return cpu
->env
.pmsav8
.mair1
[attrs
.secure
];
1020 case 0xdd0: /* SAU_CTRL */
1021 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1024 if (!attrs
.secure
) {
1027 return cpu
->env
.sau
.ctrl
;
1028 case 0xdd4: /* SAU_TYPE */
1029 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1032 if (!attrs
.secure
) {
1035 return cpu
->sau_sregion
;
1036 case 0xdd8: /* SAU_RNR */
1037 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1040 if (!attrs
.secure
) {
1043 return cpu
->env
.sau
.rnr
;
1044 case 0xddc: /* SAU_RBAR */
1046 int region
= cpu
->env
.sau
.rnr
;
1048 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1051 if (!attrs
.secure
) {
1054 if (region
>= cpu
->sau_sregion
) {
1057 return cpu
->env
.sau
.rbar
[region
];
1059 case 0xde0: /* SAU_RLAR */
1061 int region
= cpu
->env
.sau
.rnr
;
1063 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1066 if (!attrs
.secure
) {
1069 if (region
>= cpu
->sau_sregion
) {
1072 return cpu
->env
.sau
.rlar
[region
];
1074 case 0xde4: /* SFSR */
1075 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1078 if (!attrs
.secure
) {
1081 return cpu
->env
.v7m
.sfsr
;
1082 case 0xde8: /* SFAR */
1083 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1086 if (!attrs
.secure
) {
1089 return cpu
->env
.v7m
.sfar
;
1092 qemu_log_mask(LOG_GUEST_ERROR
, "NVIC: Bad read offset 0x%x\n", offset
);
1097 static void nvic_writel(NVICState
*s
, uint32_t offset
, uint32_t value
,
1100 ARMCPU
*cpu
= s
->cpu
;
1103 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
1105 int startvec
= 32 * (offset
- 0x380) + NVIC_FIRST_IRQ
;
1108 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1111 if (!attrs
.secure
) {
1114 for (i
= 0; i
< 32 && startvec
+ i
< s
->num_irq
; i
++) {
1115 s
->itns
[startvec
+ i
] = (value
>> i
) & 1;
1120 case 0xd04: /* Interrupt Control State (ICSR) */
1121 if (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1122 if (value
& (1 << 31)) {
1123 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
, false);
1124 } else if (value
& (1 << 30) &&
1125 arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1126 /* PENDNMICLR didn't exist in v7M */
1127 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_NMI
, false);
1130 if (value
& (1 << 28)) {
1131 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_PENDSV
, attrs
.secure
);
1132 } else if (value
& (1 << 27)) {
1133 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_PENDSV
, attrs
.secure
);
1135 if (value
& (1 << 26)) {
1136 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
, attrs
.secure
);
1137 } else if (value
& (1 << 25)) {
1138 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_SYSTICK
, attrs
.secure
);
1141 case 0xd08: /* Vector Table Offset. */
1142 cpu
->env
.v7m
.vecbase
[attrs
.secure
] = value
& 0xffffff80;
1144 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
1145 if ((value
>> R_V7M_AIRCR_VECTKEY_SHIFT
) == 0x05fa) {
1146 if (value
& R_V7M_AIRCR_SYSRESETREQ_MASK
) {
1148 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_SYSRESETREQS_MASK
)) {
1149 qemu_irq_pulse(s
->sysresetreq
);
1152 if (value
& R_V7M_AIRCR_VECTCLRACTIVE_MASK
) {
1153 qemu_log_mask(LOG_GUEST_ERROR
,
1154 "Setting VECTCLRACTIVE when not in DEBUG mode "
1155 "is UNPREDICTABLE\n");
1157 if (value
& R_V7M_AIRCR_VECTRESET_MASK
) {
1158 /* NB: this bit is RES0 in v8M */
1159 qemu_log_mask(LOG_GUEST_ERROR
,
1160 "Setting VECTRESET when not in DEBUG mode "
1161 "is UNPREDICTABLE\n");
1163 s
->prigroup
[attrs
.secure
] = extract32(value
,
1164 R_V7M_AIRCR_PRIGROUP_SHIFT
,
1165 R_V7M_AIRCR_PRIGROUP_LENGTH
);
1167 /* These bits are only writable by secure */
1168 cpu
->env
.v7m
.aircr
= value
&
1169 (R_V7M_AIRCR_SYSRESETREQS_MASK
|
1170 R_V7M_AIRCR_BFHFNMINS_MASK
|
1171 R_V7M_AIRCR_PRIS_MASK
);
1172 /* BFHFNMINS changes the priority of Secure HardFault, and
1173 * allows a pending Non-secure HardFault to preempt (which
1174 * we implement by marking it enabled).
1176 if (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1177 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -3;
1178 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
1180 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
1181 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 0;
1187 case 0xd10: /* System Control. */
1188 /* TODO: Implement control registers. */
1189 qemu_log_mask(LOG_UNIMP
, "NVIC: SCR unimplemented\n");
1191 case 0xd14: /* Configuration Control. */
1192 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
1193 value
&= (R_V7M_CCR_STKALIGN_MASK
|
1194 R_V7M_CCR_BFHFNMIGN_MASK
|
1195 R_V7M_CCR_DIV_0_TRP_MASK
|
1196 R_V7M_CCR_UNALIGN_TRP_MASK
|
1197 R_V7M_CCR_USERSETMPEND_MASK
|
1198 R_V7M_CCR_NONBASETHRDENA_MASK
);
1200 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1201 /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
1202 value
|= R_V7M_CCR_NONBASETHRDENA_MASK
1203 | R_V7M_CCR_STKALIGN_MASK
;
1206 /* the BFHFNMIGN bit is not banked; keep that in the NS copy */
1207 cpu
->env
.v7m
.ccr
[M_REG_NS
] =
1208 (cpu
->env
.v7m
.ccr
[M_REG_NS
] & ~R_V7M_CCR_BFHFNMIGN_MASK
)
1209 | (value
& R_V7M_CCR_BFHFNMIGN_MASK
);
1210 value
&= ~R_V7M_CCR_BFHFNMIGN_MASK
;
1213 cpu
->env
.v7m
.ccr
[attrs
.secure
] = value
;
1215 case 0xd24: /* System Handler Control and State (SHCSR) */
1217 s
->sec_vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
1218 /* Secure HardFault active bit cannot be written */
1219 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
1220 s
->sec_vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
1221 s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].active
=
1222 (value
& (1 << 10)) != 0;
1223 s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].active
=
1224 (value
& (1 << 11)) != 0;
1225 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].pending
=
1226 (value
& (1 << 12)) != 0;
1227 s
->sec_vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
1228 s
->sec_vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
1229 s
->sec_vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
1230 s
->sec_vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
1231 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].enabled
=
1232 (value
& (1 << 18)) != 0;
1233 /* SecureFault not banked, but RAZ/WI to NS */
1234 s
->vectors
[ARMV7M_EXCP_SECURE
].active
= (value
& (1 << 4)) != 0;
1235 s
->vectors
[ARMV7M_EXCP_SECURE
].enabled
= (value
& (1 << 19)) != 0;
1236 s
->vectors
[ARMV7M_EXCP_SECURE
].pending
= (value
& (1 << 20)) != 0;
1238 s
->vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
1239 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1240 /* HARDFAULTPENDED is not present in v7M */
1241 s
->vectors
[ARMV7M_EXCP_HARD
].pending
= (value
& (1 << 21)) != 0;
1243 s
->vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
1244 s
->vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
1245 s
->vectors
[ARMV7M_EXCP_PENDSV
].active
= (value
& (1 << 10)) != 0;
1246 s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
= (value
& (1 << 11)) != 0;
1247 s
->vectors
[ARMV7M_EXCP_USAGE
].pending
= (value
& (1 << 12)) != 0;
1248 s
->vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
1249 s
->vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
1250 s
->vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
1251 s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
= (value
& (1 << 18)) != 0;
1253 if (attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1254 s
->vectors
[ARMV7M_EXCP_BUS
].active
= (value
& (1 << 1)) != 0;
1255 s
->vectors
[ARMV7M_EXCP_BUS
].pending
= (value
& (1 << 14)) != 0;
1256 s
->vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
1258 /* NMIACT can only be written if the write is of a zero, with
1259 * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
1261 if (!attrs
.secure
&& cpu
->env
.v7m
.secure
&&
1262 (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
1263 (value
& (1 << 5)) == 0) {
1264 s
->vectors
[ARMV7M_EXCP_NMI
].active
= 0;
1266 /* HARDFAULTACT can only be written if the write is of a zero
1267 * to the non-secure HardFault state by the CPU in secure state.
1268 * The only case where we can be targeting the non-secure HF state
1269 * when in secure state is if this is a write via the NS alias
1270 * and BFHFNMINS is 1.
1272 if (!attrs
.secure
&& cpu
->env
.v7m
.secure
&&
1273 (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
1274 (value
& (1 << 2)) == 0) {
1275 s
->vectors
[ARMV7M_EXCP_HARD
].active
= 0;
1278 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
1279 s
->vectors
[ARMV7M_EXCP_DEBUG
].active
= (value
& (1 << 8)) != 0;
1282 case 0xd28: /* Configurable Fault Status. */
1283 cpu
->env
.v7m
.cfsr
[attrs
.secure
] &= ~value
; /* W1C */
1285 /* The BFSR bits [15:8] are shared between security states
1286 * and we store them in the NS copy.
1288 cpu
->env
.v7m
.cfsr
[M_REG_NS
] &= ~(value
& R_V7M_CFSR_BFSR_MASK
);
1291 case 0xd2c: /* Hard Fault Status. */
1292 cpu
->env
.v7m
.hfsr
&= ~value
; /* W1C */
1294 case 0xd30: /* Debug Fault Status. */
1295 cpu
->env
.v7m
.dfsr
&= ~value
; /* W1C */
1297 case 0xd34: /* Mem Manage Address. */
1298 cpu
->env
.v7m
.mmfar
[attrs
.secure
] = value
;
1300 case 0xd38: /* Bus Fault Address. */
1301 cpu
->env
.v7m
.bfar
= value
;
1303 case 0xd3c: /* Aux Fault Status. */
1304 qemu_log_mask(LOG_UNIMP
,
1305 "NVIC: Aux fault status registers unimplemented\n");
1307 case 0xd90: /* MPU_TYPE */
1309 case 0xd94: /* MPU_CTRL */
1311 (R_V7M_MPU_CTRL_HFNMIENA_MASK
| R_V7M_MPU_CTRL_ENABLE_MASK
))
1312 == R_V7M_MPU_CTRL_HFNMIENA_MASK
) {
1313 qemu_log_mask(LOG_GUEST_ERROR
, "MPU_CTRL: HFNMIENA and !ENABLE is "
1316 cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
]
1317 = value
& (R_V7M_MPU_CTRL_ENABLE_MASK
|
1318 R_V7M_MPU_CTRL_HFNMIENA_MASK
|
1319 R_V7M_MPU_CTRL_PRIVDEFENA_MASK
);
1320 tlb_flush(CPU(cpu
));
1322 case 0xd98: /* MPU_RNR */
1323 if (value
>= cpu
->pmsav7_dregion
) {
1324 qemu_log_mask(LOG_GUEST_ERROR
, "MPU region out of range %"
1325 PRIu32
"/%" PRIu32
"\n",
1326 value
, cpu
->pmsav7_dregion
);
1328 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = value
;
1331 case 0xd9c: /* MPU_RBAR */
1332 case 0xda4: /* MPU_RBAR_A1 */
1333 case 0xdac: /* MPU_RBAR_A2 */
1334 case 0xdb4: /* MPU_RBAR_A3 */
1338 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1339 /* PMSAv8M handling of the aliases is different from v7M:
1340 * aliases A1, A2, A3 override the low two bits of the region
1341 * number in MPU_RNR, and there is no 'region' field in the
1344 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1346 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1348 region
= deposit32(region
, 0, 2, aliasno
);
1350 if (region
>= cpu
->pmsav7_dregion
) {
1353 cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
] = value
;
1354 tlb_flush(CPU(cpu
));
1358 if (value
& (1 << 4)) {
1359 /* VALID bit means use the region number specified in this
1360 * value and also update MPU_RNR.REGION with that value.
1362 region
= extract32(value
, 0, 4);
1363 if (region
>= cpu
->pmsav7_dregion
) {
1364 qemu_log_mask(LOG_GUEST_ERROR
,
1365 "MPU region out of range %u/%" PRIu32
"\n",
1366 region
, cpu
->pmsav7_dregion
);
1369 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = region
;
1371 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1374 if (region
>= cpu
->pmsav7_dregion
) {
1378 cpu
->env
.pmsav7
.drbar
[region
] = value
& ~0x1f;
1379 tlb_flush(CPU(cpu
));
1382 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
1383 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
1384 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
1385 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
1387 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1389 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1390 /* PMSAv8M handling of the aliases is different from v7M:
1391 * aliases A1, A2, A3 override the low two bits of the region
1392 * number in MPU_RNR.
1394 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1396 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1398 region
= deposit32(region
, 0, 2, aliasno
);
1400 if (region
>= cpu
->pmsav7_dregion
) {
1403 cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
] = value
;
1404 tlb_flush(CPU(cpu
));
1408 if (region
>= cpu
->pmsav7_dregion
) {
1412 cpu
->env
.pmsav7
.drsr
[region
] = value
& 0xff3f;
1413 cpu
->env
.pmsav7
.dracr
[region
] = (value
>> 16) & 0x173f;
1414 tlb_flush(CPU(cpu
));
1417 case 0xdc0: /* MPU_MAIR0 */
1418 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1421 if (cpu
->pmsav7_dregion
) {
1422 /* Register is RES0 if no MPU regions are implemented */
1423 cpu
->env
.pmsav8
.mair0
[attrs
.secure
] = value
;
1425 /* We don't need to do anything else because memory attributes
1426 * only affect cacheability, and we don't implement caching.
1429 case 0xdc4: /* MPU_MAIR1 */
1430 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1433 if (cpu
->pmsav7_dregion
) {
1434 /* Register is RES0 if no MPU regions are implemented */
1435 cpu
->env
.pmsav8
.mair1
[attrs
.secure
] = value
;
1437 /* We don't need to do anything else because memory attributes
1438 * only affect cacheability, and we don't implement caching.
1441 case 0xdd0: /* SAU_CTRL */
1442 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1445 if (!attrs
.secure
) {
1448 cpu
->env
.sau
.ctrl
= value
& 3;
1449 case 0xdd4: /* SAU_TYPE */
1450 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1454 case 0xdd8: /* SAU_RNR */
1455 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1458 if (!attrs
.secure
) {
1461 if (value
>= cpu
->sau_sregion
) {
1462 qemu_log_mask(LOG_GUEST_ERROR
, "SAU region out of range %"
1463 PRIu32
"/%" PRIu32
"\n",
1464 value
, cpu
->sau_sregion
);
1466 cpu
->env
.sau
.rnr
= value
;
1469 case 0xddc: /* SAU_RBAR */
1471 int region
= cpu
->env
.sau
.rnr
;
1473 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1476 if (!attrs
.secure
) {
1479 if (region
>= cpu
->sau_sregion
) {
1482 cpu
->env
.sau
.rbar
[region
] = value
& ~0x1f;
1483 tlb_flush(CPU(cpu
));
1486 case 0xde0: /* SAU_RLAR */
1488 int region
= cpu
->env
.sau
.rnr
;
1490 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1493 if (!attrs
.secure
) {
1496 if (region
>= cpu
->sau_sregion
) {
1499 cpu
->env
.sau
.rlar
[region
] = value
& ~0x1c;
1500 tlb_flush(CPU(cpu
));
1503 case 0xde4: /* SFSR */
1504 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1507 if (!attrs
.secure
) {
1510 cpu
->env
.v7m
.sfsr
&= ~value
; /* W1C */
1512 case 0xde8: /* SFAR */
1513 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1516 if (!attrs
.secure
) {
1519 cpu
->env
.v7m
.sfsr
= value
;
1521 case 0xf00: /* Software Triggered Interrupt Register */
1523 int excnum
= (value
& 0x1ff) + NVIC_FIRST_IRQ
;
1524 if (excnum
< s
->num_irq
) {
1525 armv7m_nvic_set_pending(s
, excnum
, false);
1531 qemu_log_mask(LOG_GUEST_ERROR
,
1532 "NVIC: Bad write offset 0x%x\n", offset
);
1536 static bool nvic_user_access_ok(NVICState
*s
, hwaddr offset
, MemTxAttrs attrs
)
1538 /* Return true if unprivileged access to this register is permitted. */
1540 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */
1541 /* For access via STIR_NS it is the NS CCR.USERSETMPEND that
1542 * controls access even though the CPU is in Secure state (I_QDKX).
1544 return s
->cpu
->env
.v7m
.ccr
[attrs
.secure
] & R_V7M_CCR_USERSETMPEND_MASK
;
1546 /* All other user accesses cause a BusFault unconditionally */
1551 static int shpr_bank(NVICState
*s
, int exc
, MemTxAttrs attrs
)
1553 /* Behaviour for the SHPR register field for this exception:
1554 * return M_REG_NS to use the nonsecure vector (including for
1555 * non-banked exceptions), M_REG_S for the secure version of
1556 * a banked exception, and -1 if this field should RAZ/WI.
1559 case ARMV7M_EXCP_MEM
:
1560 case ARMV7M_EXCP_USAGE
:
1561 case ARMV7M_EXCP_SVC
:
1562 case ARMV7M_EXCP_PENDSV
:
1563 case ARMV7M_EXCP_SYSTICK
:
1564 /* Banked exceptions */
1565 return attrs
.secure
;
1566 case ARMV7M_EXCP_BUS
:
1567 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
1568 if (!attrs
.secure
&&
1569 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1573 case ARMV7M_EXCP_SECURE
:
1574 /* Not banked, RAZ/WI from nonsecure */
1575 if (!attrs
.secure
) {
1579 case ARMV7M_EXCP_DEBUG
:
1580 /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
1587 /* Not reachable due to decode of SHPR register addresses */
1588 g_assert_not_reached();
1592 static MemTxResult
nvic_sysreg_read(void *opaque
, hwaddr addr
,
1593 uint64_t *data
, unsigned size
,
1596 NVICState
*s
= (NVICState
*)opaque
;
1597 uint32_t offset
= addr
;
1598 unsigned i
, startvec
, end
;
1601 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
1602 /* Generate BusFault for unprivileged accesses */
1607 /* reads of set and clear both return the status */
1608 case 0x100 ... 0x13f: /* NVIC Set enable */
1611 case 0x180 ... 0x1bf: /* NVIC Clear enable */
1613 startvec
= offset
- 0x180 + NVIC_FIRST_IRQ
; /* vector # */
1615 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1616 if (s
->vectors
[startvec
+ i
].enabled
&&
1617 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
1622 case 0x200 ... 0x23f: /* NVIC Set pend */
1625 case 0x280 ... 0x2bf: /* NVIC Clear pend */
1627 startvec
= offset
- 0x280 + NVIC_FIRST_IRQ
; /* vector # */
1628 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1629 if (s
->vectors
[startvec
+ i
].pending
&&
1630 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
1635 case 0x300 ... 0x33f: /* NVIC Active */
1637 startvec
= offset
- 0x300 + NVIC_FIRST_IRQ
; /* vector # */
1639 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1640 if (s
->vectors
[startvec
+ i
].active
&&
1641 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
1646 case 0x400 ... 0x5ef: /* NVIC Priority */
1648 startvec
= offset
- 0x400 + NVIC_FIRST_IRQ
; /* vector # */
1650 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
1651 if (attrs
.secure
|| s
->itns
[startvec
+ i
]) {
1652 val
|= s
->vectors
[startvec
+ i
].prio
<< (8 * i
);
1656 case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
1658 for (i
= 0; i
< size
; i
++) {
1659 unsigned hdlidx
= (offset
- 0xd14) + i
;
1660 int sbank
= shpr_bank(s
, hdlidx
, attrs
);
1665 val
= deposit32(val
, i
* 8, 8, get_prio(s
, hdlidx
, sbank
));
1668 case 0xfe0 ... 0xfff: /* ID. */
1672 val
= nvic_id
[(offset
- 0xfe0) >> 2];
1677 val
= nvic_readl(s
, offset
, attrs
);
1679 qemu_log_mask(LOG_GUEST_ERROR
,
1680 "NVIC: Bad read of size %d at offset 0x%x\n",
1686 trace_nvic_sysreg_read(addr
, val
, size
);
1691 static MemTxResult
nvic_sysreg_write(void *opaque
, hwaddr addr
,
1692 uint64_t value
, unsigned size
,
1695 NVICState
*s
= (NVICState
*)opaque
;
1696 uint32_t offset
= addr
;
1697 unsigned i
, startvec
, end
;
1698 unsigned setval
= 0;
1700 trace_nvic_sysreg_write(addr
, value
, size
);
1702 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
1703 /* Generate BusFault for unprivileged accesses */
1708 case 0x100 ... 0x13f: /* NVIC Set enable */
1712 case 0x180 ... 0x1bf: /* NVIC Clear enable */
1713 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
;
1715 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1716 if (value
& (1 << i
) &&
1717 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
1718 s
->vectors
[startvec
+ i
].enabled
= setval
;
1723 case 0x200 ... 0x23f: /* NVIC Set pend */
1724 /* the special logic in armv7m_nvic_set_pending()
1725 * is not needed since IRQs are never escalated
1730 case 0x280 ... 0x2bf: /* NVIC Clear pend */
1731 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
1733 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
1734 if (value
& (1 << i
) &&
1735 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
1736 s
->vectors
[startvec
+ i
].pending
= setval
;
1741 case 0x300 ... 0x33f: /* NVIC Active */
1742 return MEMTX_OK
; /* R/O */
1743 case 0x400 ... 0x5ef: /* NVIC Priority */
1744 startvec
= 8 * (offset
- 0x400) + NVIC_FIRST_IRQ
; /* vector # */
1746 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
1747 if (attrs
.secure
|| s
->itns
[startvec
+ i
]) {
1748 set_prio(s
, startvec
+ i
, false, (value
>> (i
* 8)) & 0xff);
1753 case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3) */
1754 for (i
= 0; i
< size
; i
++) {
1755 unsigned hdlidx
= (offset
- 0xd14) + i
;
1756 int newprio
= extract32(value
, i
* 8, 8);
1757 int sbank
= shpr_bank(s
, hdlidx
, attrs
);
1762 set_prio(s
, hdlidx
, sbank
, newprio
);
1768 nvic_writel(s
, offset
, value
, attrs
);
1771 qemu_log_mask(LOG_GUEST_ERROR
,
1772 "NVIC: Bad write of size %d at offset 0x%x\n", size
, offset
);
1773 /* This is UNPREDICTABLE; treat as RAZ/WI */
1777 static const MemoryRegionOps nvic_sysreg_ops
= {
1778 .read_with_attrs
= nvic_sysreg_read
,
1779 .write_with_attrs
= nvic_sysreg_write
,
1780 .endianness
= DEVICE_NATIVE_ENDIAN
,
1783 static MemTxResult
nvic_sysreg_ns_write(void *opaque
, hwaddr addr
,
1784 uint64_t value
, unsigned size
,
1788 /* S accesses to the alias act like NS accesses to the real region */
1790 return nvic_sysreg_write(opaque
, addr
, value
, size
, attrs
);
1792 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
1800 static MemTxResult
nvic_sysreg_ns_read(void *opaque
, hwaddr addr
,
1801 uint64_t *data
, unsigned size
,
1805 /* S accesses to the alias act like NS accesses to the real region */
1807 return nvic_sysreg_read(opaque
, addr
, data
, size
, attrs
);
1809 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
1818 static const MemoryRegionOps nvic_sysreg_ns_ops
= {
1819 .read_with_attrs
= nvic_sysreg_ns_read
,
1820 .write_with_attrs
= nvic_sysreg_ns_write
,
1821 .endianness
= DEVICE_NATIVE_ENDIAN
,
1824 static int nvic_post_load(void *opaque
, int version_id
)
1826 NVICState
*s
= opaque
;
1830 /* Check for out of range priority settings */
1831 resetprio
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? -4 : -3;
1833 if (s
->vectors
[ARMV7M_EXCP_RESET
].prio
!= resetprio
||
1834 s
->vectors
[ARMV7M_EXCP_NMI
].prio
!= -2 ||
1835 s
->vectors
[ARMV7M_EXCP_HARD
].prio
!= -1) {
1838 for (i
= ARMV7M_EXCP_MEM
; i
< s
->num_irq
; i
++) {
1839 if (s
->vectors
[i
].prio
& ~0xff) {
1844 nvic_recompute_state(s
);
1849 static const VMStateDescription vmstate_VecInfo
= {
1850 .name
= "armv7m_nvic_info",
1852 .minimum_version_id
= 1,
1853 .fields
= (VMStateField
[]) {
1854 VMSTATE_INT16(prio
, VecInfo
),
1855 VMSTATE_UINT8(enabled
, VecInfo
),
1856 VMSTATE_UINT8(pending
, VecInfo
),
1857 VMSTATE_UINT8(active
, VecInfo
),
1858 VMSTATE_UINT8(level
, VecInfo
),
1859 VMSTATE_END_OF_LIST()
1863 static bool nvic_security_needed(void *opaque
)
1865 NVICState
*s
= opaque
;
1867 return arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
);
1870 static int nvic_security_post_load(void *opaque
, int version_id
)
1872 NVICState
*s
= opaque
;
1875 /* Check for out of range priority settings */
1876 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
!= -1
1877 && s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
!= -3) {
1878 /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
1879 * if the CPU state has been migrated yet; a mismatch won't
1880 * cause the emulation to blow up, though.
1884 for (i
= ARMV7M_EXCP_MEM
; i
< ARRAY_SIZE(s
->sec_vectors
); i
++) {
1885 if (s
->sec_vectors
[i
].prio
& ~0xff) {
1892 static const VMStateDescription vmstate_nvic_security
= {
1893 .name
= "nvic/m-security",
1895 .minimum_version_id
= 1,
1896 .needed
= nvic_security_needed
,
1897 .post_load
= &nvic_security_post_load
,
1898 .fields
= (VMStateField
[]) {
1899 VMSTATE_STRUCT_ARRAY(sec_vectors
, NVICState
, NVIC_INTERNAL_VECTORS
, 1,
1900 vmstate_VecInfo
, VecInfo
),
1901 VMSTATE_UINT32(prigroup
[M_REG_S
], NVICState
),
1902 VMSTATE_BOOL_ARRAY(itns
, NVICState
, NVIC_MAX_VECTORS
),
1903 VMSTATE_END_OF_LIST()
1907 static const VMStateDescription vmstate_nvic
= {
1908 .name
= "armv7m_nvic",
1910 .minimum_version_id
= 4,
1911 .post_load
= &nvic_post_load
,
1912 .fields
= (VMStateField
[]) {
1913 VMSTATE_STRUCT_ARRAY(vectors
, NVICState
, NVIC_MAX_VECTORS
, 1,
1914 vmstate_VecInfo
, VecInfo
),
1915 VMSTATE_UINT32(prigroup
[M_REG_NS
], NVICState
),
1916 VMSTATE_END_OF_LIST()
1918 .subsections
= (const VMStateDescription
*[]) {
1919 &vmstate_nvic_security
,
1924 static Property props_nvic
[] = {
1925 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
1926 DEFINE_PROP_UINT32("num-irq", NVICState
, num_irq
, 64),
1927 DEFINE_PROP_END_OF_LIST()
1930 static void armv7m_nvic_reset(DeviceState
*dev
)
1933 NVICState
*s
= NVIC(dev
);
1935 memset(s
->vectors
, 0, sizeof(s
->vectors
));
1936 memset(s
->sec_vectors
, 0, sizeof(s
->sec_vectors
));
1937 s
->prigroup
[M_REG_NS
] = 0;
1938 s
->prigroup
[M_REG_S
] = 0;
1940 s
->vectors
[ARMV7M_EXCP_NMI
].enabled
= 1;
1941 /* MEM, BUS, and USAGE are enabled through
1942 * the System Handler Control register
1944 s
->vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
1945 s
->vectors
[ARMV7M_EXCP_DEBUG
].enabled
= 1;
1946 s
->vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
1947 s
->vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
1949 resetprio
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? -4 : -3;
1950 s
->vectors
[ARMV7M_EXCP_RESET
].prio
= resetprio
;
1951 s
->vectors
[ARMV7M_EXCP_NMI
].prio
= -2;
1952 s
->vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
1954 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1955 s
->sec_vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
1956 s
->sec_vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
1957 s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
1958 s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
1960 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
1961 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
1962 /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
1963 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 0;
1965 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
1968 /* Strictly speaking the reset handler should be enabled.
1969 * However, we don't simulate soft resets through the NVIC,
1970 * and the reset vector should never be pended.
1971 * So we leave it disabled to catch logic errors.
1974 s
->exception_prio
= NVIC_NOEXC_PRIO
;
1976 s
->vectpending_is_s_banked
= false;
1977 s
->vectpending_prio
= NVIC_NOEXC_PRIO
;
1979 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1980 memset(s
->itns
, 0, sizeof(s
->itns
));
1982 /* This state is constant and not guest accessible in a non-security
1983 * NVIC; we set the bits to true to avoid having to do a feature
1984 * bit check in the NVIC enable/pend/etc register accessors.
1988 for (i
= NVIC_FIRST_IRQ
; i
< ARRAY_SIZE(s
->itns
); i
++) {
1994 static void nvic_systick_trigger(void *opaque
, int n
, int level
)
1996 NVICState
*s
= opaque
;
1999 /* SysTick just asked us to pend its exception.
2000 * (This is different from an external interrupt line's
2002 * TODO: when we implement the banked systicks we must make
2003 * this pend the correct banked exception.
2005 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
, false);
2009 static void armv7m_nvic_realize(DeviceState
*dev
, Error
**errp
)
2011 NVICState
*s
= NVIC(dev
);
2012 SysBusDevice
*systick_sbd
;
2016 s
->cpu
= ARM_CPU(qemu_get_cpu(0));
2019 if (s
->num_irq
> NVIC_MAX_IRQ
) {
2020 error_setg(errp
, "num-irq %d exceeds NVIC maximum", s
->num_irq
);
2024 qdev_init_gpio_in(dev
, set_irq_level
, s
->num_irq
);
2026 /* include space for internal exception vectors */
2027 s
->num_irq
+= NVIC_FIRST_IRQ
;
2029 object_property_set_bool(OBJECT(&s
->systick
), true, "realized", &err
);
2031 error_propagate(errp
, err
);
2034 systick_sbd
= SYS_BUS_DEVICE(&s
->systick
);
2035 sysbus_connect_irq(systick_sbd
, 0,
2036 qdev_get_gpio_in_named(dev
, "systick-trigger", 0));
2038 /* The NVIC and System Control Space (SCS) starts at 0xe000e000
2039 * and looks like this:
2041 * 0x010 - 0xff - systick
2042 * 0x100..0x7ec - NVIC
2043 * 0x7f0..0xcff - Reserved
2044 * 0xd00..0xd3c - SCS registers
2045 * 0xd40..0xeff - Reserved or Not implemented
2048 * Some registers within this space are banked between security states.
2049 * In v8M there is a second range 0xe002e000..0xe002efff which is the
2050 * NonSecure alias SCS; secure accesses to this behave like NS accesses
2051 * to the main SCS range, and non-secure accesses (including when
2052 * the security extension is not implemented) are RAZ/WI.
2053 * Note that both the main SCS range and the alias range are defined
2054 * to be exempt from memory attribution (R_BLJT) and so the memory
2055 * transaction attribute always matches the current CPU security
2056 * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
2057 * wrappers we change attrs.secure to indicate the NS access; so
2058 * generally code determining which banked register to use should
2059 * use attrs.secure; code determining actual behaviour of the system
2060 * should use env->v7m.secure.
2062 regionlen
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? 0x21000 : 0x1000;
2063 memory_region_init(&s
->container
, OBJECT(s
), "nvic", regionlen
);
2064 /* The system register region goes at the bottom of the priority
2065 * stack as it covers the whole page.
2067 memory_region_init_io(&s
->sysregmem
, OBJECT(s
), &nvic_sysreg_ops
, s
,
2068 "nvic_sysregs", 0x1000);
2069 memory_region_add_subregion(&s
->container
, 0, &s
->sysregmem
);
2070 memory_region_add_subregion_overlap(&s
->container
, 0x10,
2071 sysbus_mmio_get_region(systick_sbd
, 0),
2074 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
)) {
2075 memory_region_init_io(&s
->sysreg_ns_mem
, OBJECT(s
),
2076 &nvic_sysreg_ns_ops
, s
,
2077 "nvic_sysregs_ns", 0x1000);
2078 memory_region_add_subregion(&s
->container
, 0x20000, &s
->sysreg_ns_mem
);
2081 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->container
);
2084 static void armv7m_nvic_instance_init(Object
*obj
)
2086 /* We have a different default value for the num-irq property
2087 * than our superclass. This function runs after qdev init
2088 * has set the defaults from the Property array and before
2089 * any user-specified property setting, so just modify the
2090 * value in the GICState struct.
2092 DeviceState
*dev
= DEVICE(obj
);
2093 NVICState
*nvic
= NVIC(obj
);
2094 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
2096 object_initialize(&nvic
->systick
, sizeof(nvic
->systick
), TYPE_SYSTICK
);
2097 qdev_set_parent_bus(DEVICE(&nvic
->systick
), sysbus_get_default());
2099 sysbus_init_irq(sbd
, &nvic
->excpout
);
2100 qdev_init_gpio_out_named(dev
, &nvic
->sysresetreq
, "SYSRESETREQ", 1);
2101 qdev_init_gpio_in_named(dev
, nvic_systick_trigger
, "systick-trigger", 1);
2104 static void armv7m_nvic_class_init(ObjectClass
*klass
, void *data
)
2106 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2108 dc
->vmsd
= &vmstate_nvic
;
2109 dc
->props
= props_nvic
;
2110 dc
->reset
= armv7m_nvic_reset
;
2111 dc
->realize
= armv7m_nvic_realize
;
2114 static const TypeInfo armv7m_nvic_info
= {
2116 .parent
= TYPE_SYS_BUS_DEVICE
,
2117 .instance_init
= armv7m_nvic_instance_init
,
2118 .instance_size
= sizeof(NVICState
),
2119 .class_init
= armv7m_nvic_class_init
,
2120 .class_size
= sizeof(SysBusDeviceClass
),
2123 static void armv7m_nvic_register_types(void)
2125 type_register_static(&armv7m_nvic_info
);
2128 type_init(armv7m_nvic_register_types
)