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pci core: assert ENOSPC when add capability
[qemu/ar7.git] / linux-user / main.c
blobf8a8764ae97a69b21ab4c1148b60835c8c517469
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/mman.h>
22 #include <sys/syscall.h>
23 #include <sys/resource.h>
24
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/cutils.h"
28 #include "qemu/help_option.h"
29 #include "cpu.h"
30 #include "exec/exec-all.h"
31 #include "tcg.h"
32 #include "qemu/timer.h"
33 #include "qemu/envlist.h"
34 #include "elf.h"
35 #include "exec/log.h"
36
37 char *exec_path;
38
39 int singlestep;
40 static const char *filename;
41 static const char *argv0;
42 static int gdbstub_port;
43 static envlist_t *envlist;
44 static const char *cpu_model;
45 unsigned long mmap_min_addr;
46 unsigned long guest_base;
47 int have_guest_base;
48
49 #define EXCP_DUMP(env, fmt, ...) \
50 do { \
51 CPUState *cs = ENV_GET_CPU(env); \
52 fprintf(stderr, fmt , ## __VA_ARGS__); \
53 cpu_dump_state(cs, stderr, fprintf, 0); \
54 if (qemu_log_separate()) { \
55 qemu_log(fmt, ## __VA_ARGS__); \
56 log_cpu_state(cs, 0); \
57 } \
58 } while (0)
59
60 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
61 /*
62 * When running 32-on-64 we should make sure we can fit all of the possible
63 * guest address space into a contiguous chunk of virtual host memory.
64 *
65 * This way we will never overlap with our own libraries or binaries or stack
66 * or anything else that QEMU maps.
67 */
68 # ifdef TARGET_MIPS
69 /* MIPS only supports 31 bits of virtual address space for user space */
70 unsigned long reserved_va = 0x77000000;
71 # else
72 unsigned long reserved_va = 0xf7000000;
73 # endif
74 #else
75 unsigned long reserved_va;
76 #endif
77
78 static void usage(int exitcode);
79
80 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
81 const char *qemu_uname_release;
82
83 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
84 we allocate a bigger stack. Need a better solution, for example
85 by remapping the process stack directly at the right place */
86 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
87
88 void gemu_log(const char *fmt, ...)
89 {
90 va_list ap;
91
92 va_start(ap, fmt);
93 vfprintf(stderr, fmt, ap);
94 va_end(ap);
95 }
96
97 #if defined(TARGET_I386)
98 int cpu_get_pic_interrupt(CPUX86State *env)
99 {
100 return -1;
101 }
102 #endif
103
104 /***********************************************************/
105 /* Helper routines for implementing atomic operations. */
106
107 /* To implement exclusive operations we force all cpus to syncronise.
108 We don't require a full sync, only that no cpus are executing guest code.
109 The alternative is to map target atomic ops onto host equivalents,
110 which requires quite a lot of per host/target work. */
111 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
112 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
113 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
114 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
115 static int pending_cpus;
116
117 /* Make sure everything is in a consistent state for calling fork(). */
118 void fork_start(void)
119 {
120 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
121 pthread_mutex_lock(&exclusive_lock);
122 mmap_fork_start();
123 }
124
125 void fork_end(int child)
126 {
127 mmap_fork_end(child);
128 if (child) {
129 CPUState *cpu, *next_cpu;
130 /* Child processes created by fork() only have a single thread.
131 Discard information about the parent threads. */
132 CPU_FOREACH_SAFE(cpu, next_cpu) {
133 if (cpu != thread_cpu) {
134 QTAILQ_REMOVE(&cpus, cpu, node);
135 }
136 }
137 pending_cpus = 0;
138 pthread_mutex_init(&exclusive_lock, NULL);
139 pthread_mutex_init(&cpu_list_mutex, NULL);
140 pthread_cond_init(&exclusive_cond, NULL);
141 pthread_cond_init(&exclusive_resume, NULL);
142 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
143 gdbserver_fork(thread_cpu);
144 } else {
145 pthread_mutex_unlock(&exclusive_lock);
146 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
147 }
148 }
149
150 /* Wait for pending exclusive operations to complete. The exclusive lock
151 must be held. */
152 static inline void exclusive_idle(void)
153 {
154 while (pending_cpus) {
155 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
156 }
157 }
158
159 /* Start an exclusive operation.
160 Must only be called from outside cpu_arm_exec. */
161 static inline void start_exclusive(void)
162 {
163 CPUState *other_cpu;
164
165 pthread_mutex_lock(&exclusive_lock);
166 exclusive_idle();
167
168 pending_cpus = 1;
169 /* Make all other cpus stop executing. */
170 CPU_FOREACH(other_cpu) {
171 if (other_cpu->running) {
172 pending_cpus++;
173 cpu_exit(other_cpu);
174 }
175 }
176 if (pending_cpus > 1) {
177 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
178 }
179 }
180
181 /* Finish an exclusive operation. */
182 static inline void __attribute__((unused)) end_exclusive(void)
183 {
184 pending_cpus = 0;
185 pthread_cond_broadcast(&exclusive_resume);
186 pthread_mutex_unlock(&exclusive_lock);
187 }
188
189 /* Wait for exclusive ops to finish, and begin cpu execution. */
190 static inline void cpu_exec_start(CPUState *cpu)
191 {
192 pthread_mutex_lock(&exclusive_lock);
193 exclusive_idle();
194 cpu->running = true;
195 pthread_mutex_unlock(&exclusive_lock);
196 }
197
198 /* Mark cpu as not executing, and release pending exclusive ops. */
199 static inline void cpu_exec_end(CPUState *cpu)
200 {
201 pthread_mutex_lock(&exclusive_lock);
202 cpu->running = false;
203 if (pending_cpus > 1) {
204 pending_cpus--;
205 if (pending_cpus == 1) {
206 pthread_cond_signal(&exclusive_cond);
207 }
208 }
209 exclusive_idle();
210 pthread_mutex_unlock(&exclusive_lock);
211 }
212
213 void cpu_list_lock(void)
214 {
215 pthread_mutex_lock(&cpu_list_mutex);
216 }
217
218 void cpu_list_unlock(void)
219 {
220 pthread_mutex_unlock(&cpu_list_mutex);
221 }
222
223
224 #ifdef TARGET_I386
225 /***********************************************************/
226 /* CPUX86 core interface */
227
228 uint64_t cpu_get_tsc(CPUX86State *env)
229 {
230 return cpu_get_host_ticks();
231 }
232
233 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
234 int flags)
235 {
236 unsigned int e1, e2;
237 uint32_t *p;
238 e1 = (addr << 16) | (limit & 0xffff);
239 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
240 e2 |= flags;
241 p = ptr;
242 p[0] = tswap32(e1);
243 p[1] = tswap32(e2);
244 }
245
246 static uint64_t *idt_table;
247 #ifdef TARGET_X86_64
248 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
249 uint64_t addr, unsigned int sel)
250 {
251 uint32_t *p, e1, e2;
252 e1 = (addr & 0xffff) | (sel << 16);
253 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
254 p = ptr;
255 p[0] = tswap32(e1);
256 p[1] = tswap32(e2);
257 p[2] = tswap32(addr >> 32);
258 p[3] = 0;
259 }
260 /* only dpl matters as we do only user space emulation */
261 static void set_idt(int n, unsigned int dpl)
262 {
263 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
264 }
265 #else
266 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
267 uint32_t addr, unsigned int sel)
268 {
269 uint32_t *p, e1, e2;
270 e1 = (addr & 0xffff) | (sel << 16);
271 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
272 p = ptr;
273 p[0] = tswap32(e1);
274 p[1] = tswap32(e2);
275 }
276
277 /* only dpl matters as we do only user space emulation */
278 static void set_idt(int n, unsigned int dpl)
279 {
280 set_gate(idt_table + n, 0, dpl, 0, 0);
281 }
282 #endif
283
284 void cpu_loop(CPUX86State *env)
285 {
286 CPUState *cs = CPU(x86_env_get_cpu(env));
287 int trapnr;
288 abi_ulong pc;
289 abi_ulong ret;
290 target_siginfo_t info;
291
292 for(;;) {
293 cpu_exec_start(cs);
294 trapnr = cpu_x86_exec(cs);
295 cpu_exec_end(cs);
296 switch(trapnr) {
297 case 0x80:
298 /* linux syscall from int $0x80 */
299 ret = do_syscall(env,
300 env->regs[R_EAX],
301 env->regs[R_EBX],
302 env->regs[R_ECX],
303 env->regs[R_EDX],
304 env->regs[R_ESI],
305 env->regs[R_EDI],
306 env->regs[R_EBP],
307 0, 0);
308 if (ret == -TARGET_ERESTARTSYS) {
309 env->eip -= 2;
310 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
311 env->regs[R_EAX] = ret;
312 }
313 break;
314 #ifndef TARGET_ABI32
315 case EXCP_SYSCALL:
316 /* linux syscall from syscall instruction */
317 ret = do_syscall(env,
318 env->regs[R_EAX],
319 env->regs[R_EDI],
320 env->regs[R_ESI],
321 env->regs[R_EDX],
322 env->regs[10],
323 env->regs[8],
324 env->regs[9],
325 0, 0);
326 if (ret == -TARGET_ERESTARTSYS) {
327 env->eip -= 2;
328 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
329 env->regs[R_EAX] = ret;
330 }
331 break;
332 #endif
333 case EXCP0B_NOSEG:
334 case EXCP0C_STACK:
335 info.si_signo = TARGET_SIGBUS;
336 info.si_errno = 0;
337 info.si_code = TARGET_SI_KERNEL;
338 info._sifields._sigfault._addr = 0;
339 queue_signal(env, info.si_signo, &info);
340 break;
341 case EXCP0D_GPF:
342 /* XXX: potential problem if ABI32 */
343 #ifndef TARGET_X86_64
344 if (env->eflags & VM_MASK) {
345 handle_vm86_fault(env);
346 } else
347 #endif
348 {
349 info.si_signo = TARGET_SIGSEGV;
350 info.si_errno = 0;
351 info.si_code = TARGET_SI_KERNEL;
352 info._sifields._sigfault._addr = 0;
353 queue_signal(env, info.si_signo, &info);
354 }
355 break;
356 case EXCP0E_PAGE:
357 info.si_signo = TARGET_SIGSEGV;
358 info.si_errno = 0;
359 if (!(env->error_code & 1))
360 info.si_code = TARGET_SEGV_MAPERR;
361 else
362 info.si_code = TARGET_SEGV_ACCERR;
363 info._sifields._sigfault._addr = env->cr[2];
364 queue_signal(env, info.si_signo, &info);
365 break;
366 case EXCP00_DIVZ:
367 #ifndef TARGET_X86_64
368 if (env->eflags & VM_MASK) {
369 handle_vm86_trap(env, trapnr);
370 } else
371 #endif
372 {
373 /* division by zero */
374 info.si_signo = TARGET_SIGFPE;
375 info.si_errno = 0;
376 info.si_code = TARGET_FPE_INTDIV;
377 info._sifields._sigfault._addr = env->eip;
378 queue_signal(env, info.si_signo, &info);
379 }
380 break;
381 case EXCP01_DB:
382 case EXCP03_INT3:
383 #ifndef TARGET_X86_64
384 if (env->eflags & VM_MASK) {
385 handle_vm86_trap(env, trapnr);
386 } else
387 #endif
388 {
389 info.si_signo = TARGET_SIGTRAP;
390 info.si_errno = 0;
391 if (trapnr == EXCP01_DB) {
392 info.si_code = TARGET_TRAP_BRKPT;
393 info._sifields._sigfault._addr = env->eip;
394 } else {
395 info.si_code = TARGET_SI_KERNEL;
396 info._sifields._sigfault._addr = 0;
397 }
398 queue_signal(env, info.si_signo, &info);
399 }
400 break;
401 case EXCP04_INTO:
402 case EXCP05_BOUND:
403 #ifndef TARGET_X86_64
404 if (env->eflags & VM_MASK) {
405 handle_vm86_trap(env, trapnr);
406 } else
407 #endif
408 {
409 info.si_signo = TARGET_SIGSEGV;
410 info.si_errno = 0;
411 info.si_code = TARGET_SI_KERNEL;
412 info._sifields._sigfault._addr = 0;
413 queue_signal(env, info.si_signo, &info);
414 }
415 break;
416 case EXCP06_ILLOP:
417 info.si_signo = TARGET_SIGILL;
418 info.si_errno = 0;
419 info.si_code = TARGET_ILL_ILLOPN;
420 info._sifields._sigfault._addr = env->eip;
421 queue_signal(env, info.si_signo, &info);
422 break;
423 case EXCP_INTERRUPT:
424 /* just indicate that signals should be handled asap */
425 break;
426 case EXCP_DEBUG:
427 {
428 int sig;
429
430 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
431 if (sig)
432 {
433 info.si_signo = sig;
434 info.si_errno = 0;
435 info.si_code = TARGET_TRAP_BRKPT;
436 queue_signal(env, info.si_signo, &info);
437 }
438 }
439 break;
440 default:
441 pc = env->segs[R_CS].base + env->eip;
442 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
443 (long)pc, trapnr);
444 abort();
445 }
446 process_pending_signals(env);
447 }
448 }
449 #endif
450
451 #ifdef TARGET_ARM
452
453 #define get_user_code_u32(x, gaddr, env) \
454 ({ abi_long __r = get_user_u32((x), (gaddr)); \
455 if (!__r && bswap_code(arm_sctlr_b(env))) { \
456 (x) = bswap32(x); \
457 } \
458 __r; \
459 })
460
461 #define get_user_code_u16(x, gaddr, env) \
462 ({ abi_long __r = get_user_u16((x), (gaddr)); \
463 if (!__r && bswap_code(arm_sctlr_b(env))) { \
464 (x) = bswap16(x); \
465 } \
466 __r; \
467 })
468
469 #define get_user_data_u32(x, gaddr, env) \
470 ({ abi_long __r = get_user_u32((x), (gaddr)); \
471 if (!__r && arm_cpu_bswap_data(env)) { \
472 (x) = bswap32(x); \
473 } \
474 __r; \
475 })
476
477 #define get_user_data_u16(x, gaddr, env) \
478 ({ abi_long __r = get_user_u16((x), (gaddr)); \
479 if (!__r && arm_cpu_bswap_data(env)) { \
480 (x) = bswap16(x); \
481 } \
482 __r; \
483 })
484
485 #define put_user_data_u32(x, gaddr, env) \
486 ({ typeof(x) __x = (x); \
487 if (arm_cpu_bswap_data(env)) { \
488 __x = bswap32(__x); \
489 } \
490 put_user_u32(__x, (gaddr)); \
491 })
492
493 #define put_user_data_u16(x, gaddr, env) \
494 ({ typeof(x) __x = (x); \
495 if (arm_cpu_bswap_data(env)) { \
496 __x = bswap16(__x); \
497 } \
498 put_user_u16(__x, (gaddr)); \
499 })
500
501 #ifdef TARGET_ABI32
502 /* Commpage handling -- there is no commpage for AArch64 */
503
504 /*
505 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
506 * Input:
507 * r0 = pointer to oldval
508 * r1 = pointer to newval
509 * r2 = pointer to target value
510 *
511 * Output:
512 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
513 * C set if *ptr was changed, clear if no exchange happened
514 *
515 * Note segv's in kernel helpers are a bit tricky, we can set the
516 * data address sensibly but the PC address is just the entry point.
517 */
518 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
519 {
520 uint64_t oldval, newval, val;
521 uint32_t addr, cpsr;
522 target_siginfo_t info;
523
524 /* Based on the 32 bit code in do_kernel_trap */
525
526 /* XXX: This only works between threads, not between processes.
527 It's probably possible to implement this with native host
528 operations. However things like ldrex/strex are much harder so
529 there's not much point trying. */
530 start_exclusive();
531 cpsr = cpsr_read(env);
532 addr = env->regs[2];
533
534 if (get_user_u64(oldval, env->regs[0])) {
535 env->exception.vaddress = env->regs[0];
536 goto segv;
537 };
538
539 if (get_user_u64(newval, env->regs[1])) {
540 env->exception.vaddress = env->regs[1];
541 goto segv;
542 };
543
544 if (get_user_u64(val, addr)) {
545 env->exception.vaddress = addr;
546 goto segv;
547 }
548
549 if (val == oldval) {
550 val = newval;
551
552 if (put_user_u64(val, addr)) {
553 env->exception.vaddress = addr;
554 goto segv;
555 };
556
557 env->regs[0] = 0;
558 cpsr |= CPSR_C;
559 } else {
560 env->regs[0] = -1;
561 cpsr &= ~CPSR_C;
562 }
563 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
564 end_exclusive();
565 return;
566
567 segv:
568 end_exclusive();
569 /* We get the PC of the entry address - which is as good as anything,
570 on a real kernel what you get depends on which mode it uses. */
571 info.si_signo = TARGET_SIGSEGV;
572 info.si_errno = 0;
573 /* XXX: check env->error_code */
574 info.si_code = TARGET_SEGV_MAPERR;
575 info._sifields._sigfault._addr = env->exception.vaddress;
576 queue_signal(env, info.si_signo, &info);
577 }
578
579 /* Handle a jump to the kernel code page. */
580 static int
581 do_kernel_trap(CPUARMState *env)
582 {
583 uint32_t addr;
584 uint32_t cpsr;
585 uint32_t val;
586
587 switch (env->regs[15]) {
588 case 0xffff0fa0: /* __kernel_memory_barrier */
589 /* ??? No-op. Will need to do better for SMP. */
590 break;
591 case 0xffff0fc0: /* __kernel_cmpxchg */
592 /* XXX: This only works between threads, not between processes.
593 It's probably possible to implement this with native host
594 operations. However things like ldrex/strex are much harder so
595 there's not much point trying. */
596 start_exclusive();
597 cpsr = cpsr_read(env);
598 addr = env->regs[2];
599 /* FIXME: This should SEGV if the access fails. */
600 if (get_user_u32(val, addr))
601 val = ~env->regs[0];
602 if (val == env->regs[0]) {
603 val = env->regs[1];
604 /* FIXME: Check for segfaults. */
605 put_user_u32(val, addr);
606 env->regs[0] = 0;
607 cpsr |= CPSR_C;
608 } else {
609 env->regs[0] = -1;
610 cpsr &= ~CPSR_C;
611 }
612 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
613 end_exclusive();
614 break;
615 case 0xffff0fe0: /* __kernel_get_tls */
616 env->regs[0] = cpu_get_tls(env);
617 break;
618 case 0xffff0f60: /* __kernel_cmpxchg64 */
619 arm_kernel_cmpxchg64_helper(env);
620 break;
621
622 default:
623 return 1;
624 }
625 /* Jump back to the caller. */
626 addr = env->regs[14];
627 if (addr & 1) {
628 env->thumb = 1;
629 addr &= ~1;
630 }
631 env->regs[15] = addr;
632
633 return 0;
634 }
635
636 /* Store exclusive handling for AArch32 */
637 static int do_strex(CPUARMState *env)
638 {
639 uint64_t val;
640 int size;
641 int rc = 1;
642 int segv = 0;
643 uint32_t addr;
644 start_exclusive();
645 if (env->exclusive_addr != env->exclusive_test) {
646 goto fail;
647 }
648 /* We know we're always AArch32 so the address is in uint32_t range
649 * unless it was the -1 exclusive-monitor-lost value (which won't
650 * match exclusive_test above).
651 */
652 assert(extract64(env->exclusive_addr, 32, 32) == 0);
653 addr = env->exclusive_addr;
654 size = env->exclusive_info & 0xf;
655 switch (size) {
656 case 0:
657 segv = get_user_u8(val, addr);
658 break;
659 case 1:
660 segv = get_user_data_u16(val, addr, env);
661 break;
662 case 2:
663 case 3:
664 segv = get_user_data_u32(val, addr, env);
665 break;
666 default:
667 abort();
668 }
669 if (segv) {
670 env->exception.vaddress = addr;
671 goto done;
672 }
673 if (size == 3) {
674 uint32_t valhi;
675 segv = get_user_data_u32(valhi, addr + 4, env);
676 if (segv) {
677 env->exception.vaddress = addr + 4;
678 goto done;
679 }
680 if (arm_cpu_bswap_data(env)) {
681 val = deposit64((uint64_t)valhi, 32, 32, val);
682 } else {
683 val = deposit64(val, 32, 32, valhi);
684 }
685 }
686 if (val != env->exclusive_val) {
687 goto fail;
688 }
689
690 val = env->regs[(env->exclusive_info >> 8) & 0xf];
691 switch (size) {
692 case 0:
693 segv = put_user_u8(val, addr);
694 break;
695 case 1:
696 segv = put_user_data_u16(val, addr, env);
697 break;
698 case 2:
699 case 3:
700 segv = put_user_data_u32(val, addr, env);
701 break;
702 }
703 if (segv) {
704 env->exception.vaddress = addr;
705 goto done;
706 }
707 if (size == 3) {
708 val = env->regs[(env->exclusive_info >> 12) & 0xf];
709 segv = put_user_data_u32(val, addr + 4, env);
710 if (segv) {
711 env->exception.vaddress = addr + 4;
712 goto done;
713 }
714 }
715 rc = 0;
716 fail:
717 env->regs[15] += 4;
718 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
719 done:
720 end_exclusive();
721 return segv;
722 }
723
724 void cpu_loop(CPUARMState *env)
725 {
726 CPUState *cs = CPU(arm_env_get_cpu(env));
727 int trapnr;
728 unsigned int n, insn;
729 target_siginfo_t info;
730 uint32_t addr;
731 abi_ulong ret;
732
733 for(;;) {
734 cpu_exec_start(cs);
735 trapnr = cpu_arm_exec(cs);
736 cpu_exec_end(cs);
737 switch(trapnr) {
738 case EXCP_UDEF:
739 {
740 TaskState *ts = cs->opaque;
741 uint32_t opcode;
742 int rc;
743
744 /* we handle the FPU emulation here, as Linux */
745 /* we get the opcode */
746 /* FIXME - what to do if get_user() fails? */
747 get_user_code_u32(opcode, env->regs[15], env);
748
749 rc = EmulateAll(opcode, &ts->fpa, env);
750 if (rc == 0) { /* illegal instruction */
751 info.si_signo = TARGET_SIGILL;
752 info.si_errno = 0;
753 info.si_code = TARGET_ILL_ILLOPN;
754 info._sifields._sigfault._addr = env->regs[15];
755 queue_signal(env, info.si_signo, &info);
756 } else if (rc < 0) { /* FP exception */
757 int arm_fpe=0;
758
759 /* translate softfloat flags to FPSR flags */
760 if (-rc & float_flag_invalid)
761 arm_fpe |= BIT_IOC;
762 if (-rc & float_flag_divbyzero)
763 arm_fpe |= BIT_DZC;
764 if (-rc & float_flag_overflow)
765 arm_fpe |= BIT_OFC;
766 if (-rc & float_flag_underflow)
767 arm_fpe |= BIT_UFC;
768 if (-rc & float_flag_inexact)
769 arm_fpe |= BIT_IXC;
770
771 FPSR fpsr = ts->fpa.fpsr;
772 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
773
774 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
775 info.si_signo = TARGET_SIGFPE;
776 info.si_errno = 0;
777
778 /* ordered by priority, least first */
779 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
780 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
781 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
782 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
783 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
784
785 info._sifields._sigfault._addr = env->regs[15];
786 queue_signal(env, info.si_signo, &info);
787 } else {
788 env->regs[15] += 4;
789 }
790
791 /* accumulate unenabled exceptions */
792 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
793 fpsr |= BIT_IXC;
794 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
795 fpsr |= BIT_UFC;
796 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
797 fpsr |= BIT_OFC;
798 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
799 fpsr |= BIT_DZC;
800 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
801 fpsr |= BIT_IOC;
802 ts->fpa.fpsr=fpsr;
803 } else { /* everything OK */
804 /* increment PC */
805 env->regs[15] += 4;
806 }
807 }
808 break;
809 case EXCP_SWI:
810 case EXCP_BKPT:
811 {
812 env->eabi = 1;
813 /* system call */
814 if (trapnr == EXCP_BKPT) {
815 if (env->thumb) {
816 /* FIXME - what to do if get_user() fails? */
817 get_user_code_u16(insn, env->regs[15], env);
818 n = insn & 0xff;
819 env->regs[15] += 2;
820 } else {
821 /* FIXME - what to do if get_user() fails? */
822 get_user_code_u32(insn, env->regs[15], env);
823 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
824 env->regs[15] += 4;
825 }
826 } else {
827 if (env->thumb) {
828 /* FIXME - what to do if get_user() fails? */
829 get_user_code_u16(insn, env->regs[15] - 2, env);
830 n = insn & 0xff;
831 } else {
832 /* FIXME - what to do if get_user() fails? */
833 get_user_code_u32(insn, env->regs[15] - 4, env);
834 n = insn & 0xffffff;
835 }
836 }
837
838 if (n == ARM_NR_cacheflush) {
839 /* nop */
840 } else if (n == ARM_NR_semihosting
841 || n == ARM_NR_thumb_semihosting) {
842 env->regs[0] = do_arm_semihosting (env);
843 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
844 /* linux syscall */
845 if (env->thumb || n == 0) {
846 n = env->regs[7];
847 } else {
848 n -= ARM_SYSCALL_BASE;
849 env->eabi = 0;
850 }
851 if ( n > ARM_NR_BASE) {
852 switch (n) {
853 case ARM_NR_cacheflush:
854 /* nop */
855 break;
856 case ARM_NR_set_tls:
857 cpu_set_tls(env, env->regs[0]);
858 env->regs[0] = 0;
859 break;
860 case ARM_NR_breakpoint:
861 env->regs[15] -= env->thumb ? 2 : 4;
862 goto excp_debug;
863 default:
864 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
865 n);
866 env->regs[0] = -TARGET_ENOSYS;
867 break;
868 }
869 } else {
870 ret = do_syscall(env,
871 n,
872 env->regs[0],
873 env->regs[1],
874 env->regs[2],
875 env->regs[3],
876 env->regs[4],
877 env->regs[5],
878 0, 0);
879 if (ret == -TARGET_ERESTARTSYS) {
880 env->regs[15] -= env->thumb ? 2 : 4;
881 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
882 env->regs[0] = ret;
883 }
884 }
885 } else {
886 goto error;
887 }
888 }
889 break;
890 case EXCP_INTERRUPT:
891 /* just indicate that signals should be handled asap */
892 break;
893 case EXCP_STREX:
894 if (!do_strex(env)) {
895 break;
896 }
897 /* fall through for segv */
898 case EXCP_PREFETCH_ABORT:
899 case EXCP_DATA_ABORT:
900 addr = env->exception.vaddress;
901 {
902 info.si_signo = TARGET_SIGSEGV;
903 info.si_errno = 0;
904 /* XXX: check env->error_code */
905 info.si_code = TARGET_SEGV_MAPERR;
906 info._sifields._sigfault._addr = addr;
907 queue_signal(env, info.si_signo, &info);
908 }
909 break;
910 case EXCP_DEBUG:
911 excp_debug:
912 {
913 int sig;
914
915 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
916 if (sig)
917 {
918 info.si_signo = sig;
919 info.si_errno = 0;
920 info.si_code = TARGET_TRAP_BRKPT;
921 queue_signal(env, info.si_signo, &info);
922 }
923 }
924 break;
925 case EXCP_KERNEL_TRAP:
926 if (do_kernel_trap(env))
927 goto error;
928 break;
929 case EXCP_YIELD:
930 /* nothing to do here for user-mode, just resume guest code */
931 break;
932 default:
933 error:
934 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
935 abort();
936 }
937 process_pending_signals(env);
938 }
939 }
940
941 #else
942
943 /*
944 * Handle AArch64 store-release exclusive
945 *
946 * rs = gets the status result of store exclusive
947 * rt = is the register that is stored
948 * rt2 = is the second register store (in STP)
949 *
950 */
951 static int do_strex_a64(CPUARMState *env)
952 {
953 uint64_t val;
954 int size;
955 bool is_pair;
956 int rc = 1;
957 int segv = 0;
958 uint64_t addr;
959 int rs, rt, rt2;
960
961 start_exclusive();
962 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
963 size = extract32(env->exclusive_info, 0, 2);
964 is_pair = extract32(env->exclusive_info, 2, 1);
965 rs = extract32(env->exclusive_info, 4, 5);
966 rt = extract32(env->exclusive_info, 9, 5);
967 rt2 = extract32(env->exclusive_info, 14, 5);
968
969 addr = env->exclusive_addr;
970
971 if (addr != env->exclusive_test) {
972 goto finish;
973 }
974
975 switch (size) {
976 case 0:
977 segv = get_user_u8(val, addr);
978 break;
979 case 1:
980 segv = get_user_u16(val, addr);
981 break;
982 case 2:
983 segv = get_user_u32(val, addr);
984 break;
985 case 3:
986 segv = get_user_u64(val, addr);
987 break;
988 default:
989 abort();
990 }
991 if (segv) {
992 env->exception.vaddress = addr;
993 goto error;
994 }
995 if (val != env->exclusive_val) {
996 goto finish;
997 }
998 if (is_pair) {
999 if (size == 2) {
1000 segv = get_user_u32(val, addr + 4);
1001 } else {
1002 segv = get_user_u64(val, addr + 8);
1003 }
1004 if (segv) {
1005 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1006 goto error;
1007 }
1008 if (val != env->exclusive_high) {
1009 goto finish;
1010 }
1011 }
1012 /* handle the zero register */
1013 val = rt == 31 ? 0 : env->xregs[rt];
1014 switch (size) {
1015 case 0:
1016 segv = put_user_u8(val, addr);
1017 break;
1018 case 1:
1019 segv = put_user_u16(val, addr);
1020 break;
1021 case 2:
1022 segv = put_user_u32(val, addr);
1023 break;
1024 case 3:
1025 segv = put_user_u64(val, addr);
1026 break;
1027 }
1028 if (segv) {
1029 goto error;
1030 }
1031 if (is_pair) {
1032 /* handle the zero register */
1033 val = rt2 == 31 ? 0 : env->xregs[rt2];
1034 if (size == 2) {
1035 segv = put_user_u32(val, addr + 4);
1036 } else {
1037 segv = put_user_u64(val, addr + 8);
1038 }
1039 if (segv) {
1040 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
1041 goto error;
1042 }
1043 }
1044 rc = 0;
1045 finish:
1046 env->pc += 4;
1047 /* rs == 31 encodes a write to the ZR, thus throwing away
1048 * the status return. This is rather silly but valid.
1049 */
1050 if (rs < 31) {
1051 env->xregs[rs] = rc;
1052 }
1053 error:
1054 /* instruction faulted, PC does not advance */
1055 /* either way a strex releases any exclusive lock we have */
1056 env->exclusive_addr = -1;
1057 end_exclusive();
1058 return segv;
1059 }
1060
1061 /* AArch64 main loop */
1062 void cpu_loop(CPUARMState *env)
1063 {
1064 CPUState *cs = CPU(arm_env_get_cpu(env));
1065 int trapnr, sig;
1066 abi_long ret;
1067 target_siginfo_t info;
1068
1069 for (;;) {
1070 cpu_exec_start(cs);
1071 trapnr = cpu_arm_exec(cs);
1072 cpu_exec_end(cs);
1073
1074 switch (trapnr) {
1075 case EXCP_SWI:
1076 ret = do_syscall(env,
1077 env->xregs[8],
1078 env->xregs[0],
1079 env->xregs[1],
1080 env->xregs[2],
1081 env->xregs[3],
1082 env->xregs[4],
1083 env->xregs[5],
1084 0, 0);
1085 if (ret == -TARGET_ERESTARTSYS) {
1086 env->pc -= 4;
1087 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1088 env->xregs[0] = ret;
1089 }
1090 break;
1091 case EXCP_INTERRUPT:
1092 /* just indicate that signals should be handled asap */
1093 break;
1094 case EXCP_UDEF:
1095 info.si_signo = TARGET_SIGILL;
1096 info.si_errno = 0;
1097 info.si_code = TARGET_ILL_ILLOPN;
1098 info._sifields._sigfault._addr = env->pc;
1099 queue_signal(env, info.si_signo, &info);
1100 break;
1101 case EXCP_STREX:
1102 if (!do_strex_a64(env)) {
1103 break;
1104 }
1105 /* fall through for segv */
1106 case EXCP_PREFETCH_ABORT:
1107 case EXCP_DATA_ABORT:
1108 info.si_signo = TARGET_SIGSEGV;
1109 info.si_errno = 0;
1110 /* XXX: check env->error_code */
1111 info.si_code = TARGET_SEGV_MAPERR;
1112 info._sifields._sigfault._addr = env->exception.vaddress;
1113 queue_signal(env, info.si_signo, &info);
1114 break;
1115 case EXCP_DEBUG:
1116 case EXCP_BKPT:
1117 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1118 if (sig) {
1119 info.si_signo = sig;
1120 info.si_errno = 0;
1121 info.si_code = TARGET_TRAP_BRKPT;
1122 queue_signal(env, info.si_signo, &info);
1123 }
1124 break;
1125 case EXCP_SEMIHOST:
1126 env->xregs[0] = do_arm_semihosting(env);
1127 break;
1128 case EXCP_YIELD:
1129 /* nothing to do here for user-mode, just resume guest code */
1130 break;
1131 default:
1132 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1133 abort();
1134 }
1135 process_pending_signals(env);
1136 /* Exception return on AArch64 always clears the exclusive monitor,
1137 * so any return to running guest code implies this.
1138 * A strex (successful or otherwise) also clears the monitor, so
1139 * we don't need to specialcase EXCP_STREX.
1140 */
1141 env->exclusive_addr = -1;
1142 }
1143 }
1144 #endif /* ndef TARGET_ABI32 */
1145
1146 #endif
1147
1148 #ifdef TARGET_UNICORE32
1149
1150 void cpu_loop(CPUUniCore32State *env)
1151 {
1152 CPUState *cs = CPU(uc32_env_get_cpu(env));
1153 int trapnr;
1154 unsigned int n, insn;
1155 target_siginfo_t info;
1156
1157 for (;;) {
1158 cpu_exec_start(cs);
1159 trapnr = uc32_cpu_exec(cs);
1160 cpu_exec_end(cs);
1161 switch (trapnr) {
1162 case UC32_EXCP_PRIV:
1163 {
1164 /* system call */
1165 get_user_u32(insn, env->regs[31] - 4);
1166 n = insn & 0xffffff;
1167
1168 if (n >= UC32_SYSCALL_BASE) {
1169 /* linux syscall */
1170 n -= UC32_SYSCALL_BASE;
1171 if (n == UC32_SYSCALL_NR_set_tls) {
1172 cpu_set_tls(env, env->regs[0]);
1173 env->regs[0] = 0;
1174 } else {
1175 abi_long ret = do_syscall(env,
1176 n,
1177 env->regs[0],
1178 env->regs[1],
1179 env->regs[2],
1180 env->regs[3],
1181 env->regs[4],
1182 env->regs[5],
1183 0, 0);
1184 if (ret == -TARGET_ERESTARTSYS) {
1185 env->regs[31] -= 4;
1186 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
1187 env->regs[0] = ret;
1188 }
1189 }
1190 } else {
1191 goto error;
1192 }
1193 }
1194 break;
1195 case UC32_EXCP_DTRAP:
1196 case UC32_EXCP_ITRAP:
1197 info.si_signo = TARGET_SIGSEGV;
1198 info.si_errno = 0;
1199 /* XXX: check env->error_code */
1200 info.si_code = TARGET_SEGV_MAPERR;
1201 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1202 queue_signal(env, info.si_signo, &info);
1203 break;
1204 case EXCP_INTERRUPT:
1205 /* just indicate that signals should be handled asap */
1206 break;
1207 case EXCP_DEBUG:
1208 {
1209 int sig;
1210
1211 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1212 if (sig) {
1213 info.si_signo = sig;
1214 info.si_errno = 0;
1215 info.si_code = TARGET_TRAP_BRKPT;
1216 queue_signal(env, info.si_signo, &info);
1217 }
1218 }
1219 break;
1220 default:
1221 goto error;
1222 }
1223 process_pending_signals(env);
1224 }
1225
1226 error:
1227 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1228 abort();
1229 }
1230 #endif
1231
1232 #ifdef TARGET_SPARC
1233 #define SPARC64_STACK_BIAS 2047
1234
1235 //#define DEBUG_WIN
1236
1237 /* WARNING: dealing with register windows _is_ complicated. More info
1238 can be found at http://www.sics.se/~psm/sparcstack.html */
1239 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1240 {
1241 index = (index + cwp * 16) % (16 * env->nwindows);
1242 /* wrap handling : if cwp is on the last window, then we use the
1243 registers 'after' the end */
1244 if (index < 8 && env->cwp == env->nwindows - 1)
1245 index += 16 * env->nwindows;
1246 return index;
1247 }
1248
1249 /* save the register window 'cwp1' */
1250 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1251 {
1252 unsigned int i;
1253 abi_ulong sp_ptr;
1254
1255 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1256 #ifdef TARGET_SPARC64
1257 if (sp_ptr & 3)
1258 sp_ptr += SPARC64_STACK_BIAS;
1259 #endif
1260 #if defined(DEBUG_WIN)
1261 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1262 sp_ptr, cwp1);
1263 #endif
1264 for(i = 0; i < 16; i++) {
1265 /* FIXME - what to do if put_user() fails? */
1266 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1267 sp_ptr += sizeof(abi_ulong);
1268 }
1269 }
1270
1271 static void save_window(CPUSPARCState *env)
1272 {
1273 #ifndef TARGET_SPARC64
1274 unsigned int new_wim;
1275 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1276 ((1LL << env->nwindows) - 1);
1277 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1278 env->wim = new_wim;
1279 #else
1280 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1281 env->cansave++;
1282 env->canrestore--;
1283 #endif
1284 }
1285
1286 static void restore_window(CPUSPARCState *env)
1287 {
1288 #ifndef TARGET_SPARC64
1289 unsigned int new_wim;
1290 #endif
1291 unsigned int i, cwp1;
1292 abi_ulong sp_ptr;
1293
1294 #ifndef TARGET_SPARC64
1295 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1296 ((1LL << env->nwindows) - 1);
1297 #endif
1298
1299 /* restore the invalid window */
1300 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1301 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1302 #ifdef TARGET_SPARC64
1303 if (sp_ptr & 3)
1304 sp_ptr += SPARC64_STACK_BIAS;
1305 #endif
1306 #if defined(DEBUG_WIN)
1307 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1308 sp_ptr, cwp1);
1309 #endif
1310 for(i = 0; i < 16; i++) {
1311 /* FIXME - what to do if get_user() fails? */
1312 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1313 sp_ptr += sizeof(abi_ulong);
1314 }
1315 #ifdef TARGET_SPARC64
1316 env->canrestore++;
1317 if (env->cleanwin < env->nwindows - 1)
1318 env->cleanwin++;
1319 env->cansave--;
1320 #else
1321 env->wim = new_wim;
1322 #endif
1323 }
1324
1325 static void flush_windows(CPUSPARCState *env)
1326 {
1327 int offset, cwp1;
1328
1329 offset = 1;
1330 for(;;) {
1331 /* if restore would invoke restore_window(), then we can stop */
1332 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1333 #ifndef TARGET_SPARC64
1334 if (env->wim & (1 << cwp1))
1335 break;
1336 #else
1337 if (env->canrestore == 0)
1338 break;
1339 env->cansave++;
1340 env->canrestore--;
1341 #endif
1342 save_window_offset(env, cwp1);
1343 offset++;
1344 }
1345 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1346 #ifndef TARGET_SPARC64
1347 /* set wim so that restore will reload the registers */
1348 env->wim = 1 << cwp1;
1349 #endif
1350 #if defined(DEBUG_WIN)
1351 printf("flush_windows: nb=%d\n", offset - 1);
1352 #endif
1353 }
1354
1355 void cpu_loop (CPUSPARCState *env)
1356 {
1357 CPUState *cs = CPU(sparc_env_get_cpu(env));
1358 int trapnr;
1359 abi_long ret;
1360 target_siginfo_t info;
1361
1362 while (1) {
1363 cpu_exec_start(cs);
1364 trapnr = cpu_sparc_exec(cs);
1365 cpu_exec_end(cs);
1366
1367 /* Compute PSR before exposing state. */
1368 if (env->cc_op != CC_OP_FLAGS) {
1369 cpu_get_psr(env);
1370 }
1371
1372 switch (trapnr) {
1373 #ifndef TARGET_SPARC64
1374 case 0x88:
1375 case 0x90:
1376 #else
1377 case 0x110:
1378 case 0x16d:
1379 #endif
1380 ret = do_syscall (env, env->gregs[1],
1381 env->regwptr[0], env->regwptr[1],
1382 env->regwptr[2], env->regwptr[3],
1383 env->regwptr[4], env->regwptr[5],
1384 0, 0);
1385 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1386 break;
1387 }
1388 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1389 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1390 env->xcc |= PSR_CARRY;
1391 #else
1392 env->psr |= PSR_CARRY;
1393 #endif
1394 ret = -ret;
1395 } else {
1396 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1397 env->xcc &= ~PSR_CARRY;
1398 #else
1399 env->psr &= ~PSR_CARRY;
1400 #endif
1401 }
1402 env->regwptr[0] = ret;
1403 /* next instruction */
1404 env->pc = env->npc;
1405 env->npc = env->npc + 4;
1406 break;
1407 case 0x83: /* flush windows */
1408 #ifdef TARGET_ABI32
1409 case 0x103:
1410 #endif
1411 flush_windows(env);
1412 /* next instruction */
1413 env->pc = env->npc;
1414 env->npc = env->npc + 4;
1415 break;
1416 #ifndef TARGET_SPARC64
1417 case TT_WIN_OVF: /* window overflow */
1418 save_window(env);
1419 break;
1420 case TT_WIN_UNF: /* window underflow */
1421 restore_window(env);
1422 break;
1423 case TT_TFAULT:
1424 case TT_DFAULT:
1425 {
1426 info.si_signo = TARGET_SIGSEGV;
1427 info.si_errno = 0;
1428 /* XXX: check env->error_code */
1429 info.si_code = TARGET_SEGV_MAPERR;
1430 info._sifields._sigfault._addr = env->mmuregs[4];
1431 queue_signal(env, info.si_signo, &info);
1432 }
1433 break;
1434 #else
1435 case TT_SPILL: /* window overflow */
1436 save_window(env);
1437 break;
1438 case TT_FILL: /* window underflow */
1439 restore_window(env);
1440 break;
1441 case TT_TFAULT:
1442 case TT_DFAULT:
1443 {
1444 info.si_signo = TARGET_SIGSEGV;
1445 info.si_errno = 0;
1446 /* XXX: check env->error_code */
1447 info.si_code = TARGET_SEGV_MAPERR;
1448 if (trapnr == TT_DFAULT)
1449 info._sifields._sigfault._addr = env->dmmuregs[4];
1450 else
1451 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1452 queue_signal(env, info.si_signo, &info);
1453 }
1454 break;
1455 #ifndef TARGET_ABI32
1456 case 0x16e:
1457 flush_windows(env);
1458 sparc64_get_context(env);
1459 break;
1460 case 0x16f:
1461 flush_windows(env);
1462 sparc64_set_context(env);
1463 break;
1464 #endif
1465 #endif
1466 case EXCP_INTERRUPT:
1467 /* just indicate that signals should be handled asap */
1468 break;
1469 case TT_ILL_INSN:
1470 {
1471 info.si_signo = TARGET_SIGILL;
1472 info.si_errno = 0;
1473 info.si_code = TARGET_ILL_ILLOPC;
1474 info._sifields._sigfault._addr = env->pc;
1475 queue_signal(env, info.si_signo, &info);
1476 }
1477 break;
1478 case EXCP_DEBUG:
1479 {
1480 int sig;
1481
1482 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1483 if (sig)
1484 {
1485 info.si_signo = sig;
1486 info.si_errno = 0;
1487 info.si_code = TARGET_TRAP_BRKPT;
1488 queue_signal(env, info.si_signo, &info);
1489 }
1490 }
1491 break;
1492 default:
1493 printf ("Unhandled trap: 0x%x\n", trapnr);
1494 cpu_dump_state(cs, stderr, fprintf, 0);
1495 exit(EXIT_FAILURE);
1496 }
1497 process_pending_signals (env);
1498 }
1499 }
1500
1501 #endif
1502
1503 #ifdef TARGET_PPC
1504 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1505 {
1506 return cpu_get_host_ticks();
1507 }
1508
1509 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1510 {
1511 return cpu_ppc_get_tb(env);
1512 }
1513
1514 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1515 {
1516 return cpu_ppc_get_tb(env) >> 32;
1517 }
1518
1519 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1520 {
1521 return cpu_ppc_get_tb(env);
1522 }
1523
1524 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1525 {
1526 return cpu_ppc_get_tb(env) >> 32;
1527 }
1528
1529 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1530 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1531
1532 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1533 {
1534 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1535 }
1536
1537 /* XXX: to be fixed */
1538 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1539 {
1540 return -1;
1541 }
1542
1543 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1544 {
1545 return -1;
1546 }
1547
1548 static int do_store_exclusive(CPUPPCState *env)
1549 {
1550 target_ulong addr;
1551 target_ulong page_addr;
1552 target_ulong val, val2 __attribute__((unused)) = 0;
1553 int flags;
1554 int segv = 0;
1555
1556 addr = env->reserve_ea;
1557 page_addr = addr & TARGET_PAGE_MASK;
1558 start_exclusive();
1559 mmap_lock();
1560 flags = page_get_flags(page_addr);
1561 if ((flags & PAGE_READ) == 0) {
1562 segv = 1;
1563 } else {
1564 int reg = env->reserve_info & 0x1f;
1565 int size = env->reserve_info >> 5;
1566 int stored = 0;
1567
1568 if (addr == env->reserve_addr) {
1569 switch (size) {
1570 case 1: segv = get_user_u8(val, addr); break;
1571 case 2: segv = get_user_u16(val, addr); break;
1572 case 4: segv = get_user_u32(val, addr); break;
1573 #if defined(TARGET_PPC64)
1574 case 8: segv = get_user_u64(val, addr); break;
1575 case 16: {
1576 segv = get_user_u64(val, addr);
1577 if (!segv) {
1578 segv = get_user_u64(val2, addr + 8);
1579 }
1580 break;
1581 }
1582 #endif
1583 default: abort();
1584 }
1585 if (!segv && val == env->reserve_val) {
1586 val = env->gpr[reg];
1587 switch (size) {
1588 case 1: segv = put_user_u8(val, addr); break;
1589 case 2: segv = put_user_u16(val, addr); break;
1590 case 4: segv = put_user_u32(val, addr); break;
1591 #if defined(TARGET_PPC64)
1592 case 8: segv = put_user_u64(val, addr); break;
1593 case 16: {
1594 if (val2 == env->reserve_val2) {
1595 if (msr_le) {
1596 val2 = val;
1597 val = env->gpr[reg+1];
1598 } else {
1599 val2 = env->gpr[reg+1];
1600 }
1601 segv = put_user_u64(val, addr);
1602 if (!segv) {
1603 segv = put_user_u64(val2, addr + 8);
1604 }
1605 }
1606 break;
1607 }
1608 #endif
1609 default: abort();
1610 }
1611 if (!segv) {
1612 stored = 1;
1613 }
1614 }
1615 }
1616 env->crf[0] = (stored << 1) | xer_so;
1617 env->reserve_addr = (target_ulong)-1;
1618 }
1619 if (!segv) {
1620 env->nip += 4;
1621 }
1622 mmap_unlock();
1623 end_exclusive();
1624 return segv;
1625 }
1626
1627 void cpu_loop(CPUPPCState *env)
1628 {
1629 CPUState *cs = CPU(ppc_env_get_cpu(env));
1630 target_siginfo_t info;
1631 int trapnr;
1632 target_ulong ret;
1633
1634 for(;;) {
1635 cpu_exec_start(cs);
1636 trapnr = cpu_ppc_exec(cs);
1637 cpu_exec_end(cs);
1638 switch(trapnr) {
1639 case POWERPC_EXCP_NONE:
1640 /* Just go on */
1641 break;
1642 case POWERPC_EXCP_CRITICAL: /* Critical input */
1643 cpu_abort(cs, "Critical interrupt while in user mode. "
1644 "Aborting\n");
1645 break;
1646 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1647 cpu_abort(cs, "Machine check exception while in user mode. "
1648 "Aborting\n");
1649 break;
1650 case POWERPC_EXCP_DSI: /* Data storage exception */
1651 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1652 env->spr[SPR_DAR]);
1653 /* XXX: check this. Seems bugged */
1654 switch (env->error_code & 0xFF000000) {
1655 case 0x40000000:
1656 info.si_signo = TARGET_SIGSEGV;
1657 info.si_errno = 0;
1658 info.si_code = TARGET_SEGV_MAPERR;
1659 break;
1660 case 0x04000000:
1661 info.si_signo = TARGET_SIGILL;
1662 info.si_errno = 0;
1663 info.si_code = TARGET_ILL_ILLADR;
1664 break;
1665 case 0x08000000:
1666 info.si_signo = TARGET_SIGSEGV;
1667 info.si_errno = 0;
1668 info.si_code = TARGET_SEGV_ACCERR;
1669 break;
1670 default:
1671 /* Let's send a regular segfault... */
1672 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1673 env->error_code);
1674 info.si_signo = TARGET_SIGSEGV;
1675 info.si_errno = 0;
1676 info.si_code = TARGET_SEGV_MAPERR;
1677 break;
1678 }
1679 info._sifields._sigfault._addr = env->nip;
1680 queue_signal(env, info.si_signo, &info);
1681 break;
1682 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1683 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1684 "\n", env->spr[SPR_SRR0]);
1685 /* XXX: check this */
1686 switch (env->error_code & 0xFF000000) {
1687 case 0x40000000:
1688 info.si_signo = TARGET_SIGSEGV;
1689 info.si_errno = 0;
1690 info.si_code = TARGET_SEGV_MAPERR;
1691 break;
1692 case 0x10000000:
1693 case 0x08000000:
1694 info.si_signo = TARGET_SIGSEGV;
1695 info.si_errno = 0;
1696 info.si_code = TARGET_SEGV_ACCERR;
1697 break;
1698 default:
1699 /* Let's send a regular segfault... */
1700 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1701 env->error_code);
1702 info.si_signo = TARGET_SIGSEGV;
1703 info.si_errno = 0;
1704 info.si_code = TARGET_SEGV_MAPERR;
1705 break;
1706 }
1707 info._sifields._sigfault._addr = env->nip - 4;
1708 queue_signal(env, info.si_signo, &info);
1709 break;
1710 case POWERPC_EXCP_EXTERNAL: /* External input */
1711 cpu_abort(cs, "External interrupt while in user mode. "
1712 "Aborting\n");
1713 break;
1714 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1715 EXCP_DUMP(env, "Unaligned memory access\n");
1716 /* XXX: check this */
1717 info.si_signo = TARGET_SIGBUS;
1718 info.si_errno = 0;
1719 info.si_code = TARGET_BUS_ADRALN;
1720 info._sifields._sigfault._addr = env->nip;
1721 queue_signal(env, info.si_signo, &info);
1722 break;
1723 case POWERPC_EXCP_PROGRAM: /* Program exception */
1724 /* XXX: check this */
1725 switch (env->error_code & ~0xF) {
1726 case POWERPC_EXCP_FP:
1727 EXCP_DUMP(env, "Floating point program exception\n");
1728 info.si_signo = TARGET_SIGFPE;
1729 info.si_errno = 0;
1730 switch (env->error_code & 0xF) {
1731 case POWERPC_EXCP_FP_OX:
1732 info.si_code = TARGET_FPE_FLTOVF;
1733 break;
1734 case POWERPC_EXCP_FP_UX:
1735 info.si_code = TARGET_FPE_FLTUND;
1736 break;
1737 case POWERPC_EXCP_FP_ZX:
1738 case POWERPC_EXCP_FP_VXZDZ:
1739 info.si_code = TARGET_FPE_FLTDIV;
1740 break;
1741 case POWERPC_EXCP_FP_XX:
1742 info.si_code = TARGET_FPE_FLTRES;
1743 break;
1744 case POWERPC_EXCP_FP_VXSOFT:
1745 info.si_code = TARGET_FPE_FLTINV;
1746 break;
1747 case POWERPC_EXCP_FP_VXSNAN:
1748 case POWERPC_EXCP_FP_VXISI:
1749 case POWERPC_EXCP_FP_VXIDI:
1750 case POWERPC_EXCP_FP_VXIMZ:
1751 case POWERPC_EXCP_FP_VXVC:
1752 case POWERPC_EXCP_FP_VXSQRT:
1753 case POWERPC_EXCP_FP_VXCVI:
1754 info.si_code = TARGET_FPE_FLTSUB;
1755 break;
1756 default:
1757 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1758 env->error_code);
1759 break;
1760 }
1761 break;
1762 case POWERPC_EXCP_INVAL:
1763 EXCP_DUMP(env, "Invalid instruction\n");
1764 info.si_signo = TARGET_SIGILL;
1765 info.si_errno = 0;
1766 switch (env->error_code & 0xF) {
1767 case POWERPC_EXCP_INVAL_INVAL:
1768 info.si_code = TARGET_ILL_ILLOPC;
1769 break;
1770 case POWERPC_EXCP_INVAL_LSWX:
1771 info.si_code = TARGET_ILL_ILLOPN;
1772 break;
1773 case POWERPC_EXCP_INVAL_SPR:
1774 info.si_code = TARGET_ILL_PRVREG;
1775 break;
1776 case POWERPC_EXCP_INVAL_FP:
1777 info.si_code = TARGET_ILL_COPROC;
1778 break;
1779 default:
1780 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1781 env->error_code & 0xF);
1782 info.si_code = TARGET_ILL_ILLADR;
1783 break;
1784 }
1785 break;
1786 case POWERPC_EXCP_PRIV:
1787 EXCP_DUMP(env, "Privilege violation\n");
1788 info.si_signo = TARGET_SIGILL;
1789 info.si_errno = 0;
1790 switch (env->error_code & 0xF) {
1791 case POWERPC_EXCP_PRIV_OPC:
1792 info.si_code = TARGET_ILL_PRVOPC;
1793 break;
1794 case POWERPC_EXCP_PRIV_REG:
1795 info.si_code = TARGET_ILL_PRVREG;
1796 break;
1797 default:
1798 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1799 env->error_code & 0xF);
1800 info.si_code = TARGET_ILL_PRVOPC;
1801 break;
1802 }
1803 break;
1804 case POWERPC_EXCP_TRAP:
1805 cpu_abort(cs, "Tried to call a TRAP\n");
1806 break;
1807 default:
1808 /* Should not happen ! */
1809 cpu_abort(cs, "Unknown program exception (%02x)\n",
1810 env->error_code);
1811 break;
1812 }
1813 info._sifields._sigfault._addr = env->nip - 4;
1814 queue_signal(env, info.si_signo, &info);
1815 break;
1816 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1817 EXCP_DUMP(env, "No floating point allowed\n");
1818 info.si_signo = TARGET_SIGILL;
1819 info.si_errno = 0;
1820 info.si_code = TARGET_ILL_COPROC;
1821 info._sifields._sigfault._addr = env->nip - 4;
1822 queue_signal(env, info.si_signo, &info);
1823 break;
1824 case POWERPC_EXCP_SYSCALL: /* System call exception */
1825 cpu_abort(cs, "Syscall exception while in user mode. "
1826 "Aborting\n");
1827 break;
1828 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1829 EXCP_DUMP(env, "No APU instruction allowed\n");
1830 info.si_signo = TARGET_SIGILL;
1831 info.si_errno = 0;
1832 info.si_code = TARGET_ILL_COPROC;
1833 info._sifields._sigfault._addr = env->nip - 4;
1834 queue_signal(env, info.si_signo, &info);
1835 break;
1836 case POWERPC_EXCP_DECR: /* Decrementer exception */
1837 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1838 "Aborting\n");
1839 break;
1840 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1841 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1842 "Aborting\n");
1843 break;
1844 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1845 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1846 "Aborting\n");
1847 break;
1848 case POWERPC_EXCP_DTLB: /* Data TLB error */
1849 cpu_abort(cs, "Data TLB exception while in user mode. "
1850 "Aborting\n");
1851 break;
1852 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1853 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1854 "Aborting\n");
1855 break;
1856 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1857 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1858 info.si_signo = TARGET_SIGILL;
1859 info.si_errno = 0;
1860 info.si_code = TARGET_ILL_COPROC;
1861 info._sifields._sigfault._addr = env->nip - 4;
1862 queue_signal(env, info.si_signo, &info);
1863 break;
1864 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1865 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1866 break;
1867 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1868 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1869 break;
1870 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1871 cpu_abort(cs, "Performance monitor exception not handled\n");
1872 break;
1873 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1874 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1875 "Aborting\n");
1876 break;
1877 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1878 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1879 "Aborting\n");
1880 break;
1881 case POWERPC_EXCP_RESET: /* System reset exception */
1882 cpu_abort(cs, "Reset interrupt while in user mode. "
1883 "Aborting\n");
1884 break;
1885 case POWERPC_EXCP_DSEG: /* Data segment exception */
1886 cpu_abort(cs, "Data segment exception while in user mode. "
1887 "Aborting\n");
1888 break;
1889 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1890 cpu_abort(cs, "Instruction segment exception "
1891 "while in user mode. Aborting\n");
1892 break;
1893 /* PowerPC 64 with hypervisor mode support */
1894 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1895 cpu_abort(cs, "Hypervisor decrementer interrupt "
1896 "while in user mode. Aborting\n");
1897 break;
1898 case POWERPC_EXCP_TRACE: /* Trace exception */
1899 /* Nothing to do:
1900 * we use this exception to emulate step-by-step execution mode.
1901 */
1902 break;
1903 /* PowerPC 64 with hypervisor mode support */
1904 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1905 cpu_abort(cs, "Hypervisor data storage exception "
1906 "while in user mode. Aborting\n");
1907 break;
1908 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1909 cpu_abort(cs, "Hypervisor instruction storage exception "
1910 "while in user mode. Aborting\n");
1911 break;
1912 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1913 cpu_abort(cs, "Hypervisor data segment exception "
1914 "while in user mode. Aborting\n");
1915 break;
1916 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1917 cpu_abort(cs, "Hypervisor instruction segment exception "
1918 "while in user mode. Aborting\n");
1919 break;
1920 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1921 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1922 info.si_signo = TARGET_SIGILL;
1923 info.si_errno = 0;
1924 info.si_code = TARGET_ILL_COPROC;
1925 info._sifields._sigfault._addr = env->nip - 4;
1926 queue_signal(env, info.si_signo, &info);
1927 break;
1928 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1929 cpu_abort(cs, "Programmable interval timer interrupt "
1930 "while in user mode. Aborting\n");
1931 break;
1932 case POWERPC_EXCP_IO: /* IO error exception */
1933 cpu_abort(cs, "IO error exception while in user mode. "
1934 "Aborting\n");
1935 break;
1936 case POWERPC_EXCP_RUNM: /* Run mode exception */
1937 cpu_abort(cs, "Run mode exception while in user mode. "
1938 "Aborting\n");
1939 break;
1940 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1941 cpu_abort(cs, "Emulation trap exception not handled\n");
1942 break;
1943 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1944 cpu_abort(cs, "Instruction fetch TLB exception "
1945 "while in user-mode. Aborting");
1946 break;
1947 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1948 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1949 "Aborting");
1950 break;
1951 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1952 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1953 "Aborting");
1954 break;
1955 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1956 cpu_abort(cs, "Floating-point assist exception not handled\n");
1957 break;
1958 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1959 cpu_abort(cs, "Instruction address breakpoint exception "
1960 "not handled\n");
1961 break;
1962 case POWERPC_EXCP_SMI: /* System management interrupt */
1963 cpu_abort(cs, "System management interrupt while in user mode. "
1964 "Aborting\n");
1965 break;
1966 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1967 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1968 "Aborting\n");
1969 break;
1970 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1971 cpu_abort(cs, "Performance monitor exception not handled\n");
1972 break;
1973 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1974 cpu_abort(cs, "Vector assist exception not handled\n");
1975 break;
1976 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1977 cpu_abort(cs, "Soft patch exception not handled\n");
1978 break;
1979 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1980 cpu_abort(cs, "Maintenance exception while in user mode. "
1981 "Aborting\n");
1982 break;
1983 case POWERPC_EXCP_STOP: /* stop translation */
1984 /* We did invalidate the instruction cache. Go on */
1985 break;
1986 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1987 /* We just stopped because of a branch. Go on */
1988 break;
1989 case POWERPC_EXCP_SYSCALL_USER:
1990 /* system call in user-mode emulation */
1991 /* WARNING:
1992 * PPC ABI uses overflow flag in cr0 to signal an error
1993 * in syscalls.
1994 */
1995 env->crf[0] &= ~0x1;
1996 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1997 env->gpr[5], env->gpr[6], env->gpr[7],
1998 env->gpr[8], 0, 0);
1999 if (ret == -TARGET_ERESTARTSYS) {
2000 env->nip -= 4;
2001 break;
2002 }
2003 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
2004 /* Returning from a successful sigreturn syscall.
2005 Avoid corrupting register state. */
2006 break;
2007 }
2008 if (ret > (target_ulong)(-515)) {
2009 env->crf[0] |= 0x1;
2010 ret = -ret;
2011 }
2012 env->gpr[3] = ret;
2013 break;
2014 case POWERPC_EXCP_STCX:
2015 if (do_store_exclusive(env)) {
2016 info.si_signo = TARGET_SIGSEGV;
2017 info.si_errno = 0;
2018 info.si_code = TARGET_SEGV_MAPERR;
2019 info._sifields._sigfault._addr = env->nip;
2020 queue_signal(env, info.si_signo, &info);
2021 }
2022 break;
2023 case EXCP_DEBUG:
2024 {
2025 int sig;
2026
2027 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2028 if (sig) {
2029 info.si_signo = sig;
2030 info.si_errno = 0;
2031 info.si_code = TARGET_TRAP_BRKPT;
2032 queue_signal(env, info.si_signo, &info);
2033 }
2034 }
2035 break;
2036 case EXCP_INTERRUPT:
2037 /* just indicate that signals should be handled asap */
2038 break;
2039 default:
2040 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
2041 break;
2042 }
2043 process_pending_signals(env);
2044 }
2045 }
2046 #endif
2047
2048 #ifdef TARGET_MIPS
2049
2050 # ifdef TARGET_ABI_MIPSO32
2051 # define MIPS_SYS(name, args) args,
2052 static const uint8_t mips_syscall_args[] = {
2053 MIPS_SYS(sys_syscall , 8) /* 4000 */
2054 MIPS_SYS(sys_exit , 1)
2055 MIPS_SYS(sys_fork , 0)
2056 MIPS_SYS(sys_read , 3)
2057 MIPS_SYS(sys_write , 3)
2058 MIPS_SYS(sys_open , 3) /* 4005 */
2059 MIPS_SYS(sys_close , 1)
2060 MIPS_SYS(sys_waitpid , 3)
2061 MIPS_SYS(sys_creat , 2)
2062 MIPS_SYS(sys_link , 2)
2063 MIPS_SYS(sys_unlink , 1) /* 4010 */
2064 MIPS_SYS(sys_execve , 0)
2065 MIPS_SYS(sys_chdir , 1)
2066 MIPS_SYS(sys_time , 1)
2067 MIPS_SYS(sys_mknod , 3)
2068 MIPS_SYS(sys_chmod , 2) /* 4015 */
2069 MIPS_SYS(sys_lchown , 3)
2070 MIPS_SYS(sys_ni_syscall , 0)
2071 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
2072 MIPS_SYS(sys_lseek , 3)
2073 MIPS_SYS(sys_getpid , 0) /* 4020 */
2074 MIPS_SYS(sys_mount , 5)
2075 MIPS_SYS(sys_umount , 1)
2076 MIPS_SYS(sys_setuid , 1)
2077 MIPS_SYS(sys_getuid , 0)
2078 MIPS_SYS(sys_stime , 1) /* 4025 */
2079 MIPS_SYS(sys_ptrace , 4)
2080 MIPS_SYS(sys_alarm , 1)
2081 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2082 MIPS_SYS(sys_pause , 0)
2083 MIPS_SYS(sys_utime , 2) /* 4030 */
2084 MIPS_SYS(sys_ni_syscall , 0)
2085 MIPS_SYS(sys_ni_syscall , 0)
2086 MIPS_SYS(sys_access , 2)
2087 MIPS_SYS(sys_nice , 1)
2088 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2089 MIPS_SYS(sys_sync , 0)
2090 MIPS_SYS(sys_kill , 2)
2091 MIPS_SYS(sys_rename , 2)
2092 MIPS_SYS(sys_mkdir , 2)
2093 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2094 MIPS_SYS(sys_dup , 1)
2095 MIPS_SYS(sys_pipe , 0)
2096 MIPS_SYS(sys_times , 1)
2097 MIPS_SYS(sys_ni_syscall , 0)
2098 MIPS_SYS(sys_brk , 1) /* 4045 */
2099 MIPS_SYS(sys_setgid , 1)
2100 MIPS_SYS(sys_getgid , 0)
2101 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2102 MIPS_SYS(sys_geteuid , 0)
2103 MIPS_SYS(sys_getegid , 0) /* 4050 */
2104 MIPS_SYS(sys_acct , 0)
2105 MIPS_SYS(sys_umount2 , 2)
2106 MIPS_SYS(sys_ni_syscall , 0)
2107 MIPS_SYS(sys_ioctl , 3)
2108 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2109 MIPS_SYS(sys_ni_syscall , 2)
2110 MIPS_SYS(sys_setpgid , 2)
2111 MIPS_SYS(sys_ni_syscall , 0)
2112 MIPS_SYS(sys_olduname , 1)
2113 MIPS_SYS(sys_umask , 1) /* 4060 */
2114 MIPS_SYS(sys_chroot , 1)
2115 MIPS_SYS(sys_ustat , 2)
2116 MIPS_SYS(sys_dup2 , 2)
2117 MIPS_SYS(sys_getppid , 0)
2118 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2119 MIPS_SYS(sys_setsid , 0)
2120 MIPS_SYS(sys_sigaction , 3)
2121 MIPS_SYS(sys_sgetmask , 0)
2122 MIPS_SYS(sys_ssetmask , 1)
2123 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2124 MIPS_SYS(sys_setregid , 2)
2125 MIPS_SYS(sys_sigsuspend , 0)
2126 MIPS_SYS(sys_sigpending , 1)
2127 MIPS_SYS(sys_sethostname , 2)
2128 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2129 MIPS_SYS(sys_getrlimit , 2)
2130 MIPS_SYS(sys_getrusage , 2)
2131 MIPS_SYS(sys_gettimeofday, 2)
2132 MIPS_SYS(sys_settimeofday, 2)
2133 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2134 MIPS_SYS(sys_setgroups , 2)
2135 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2136 MIPS_SYS(sys_symlink , 2)
2137 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2138 MIPS_SYS(sys_readlink , 3) /* 4085 */
2139 MIPS_SYS(sys_uselib , 1)
2140 MIPS_SYS(sys_swapon , 2)
2141 MIPS_SYS(sys_reboot , 3)
2142 MIPS_SYS(old_readdir , 3)
2143 MIPS_SYS(old_mmap , 6) /* 4090 */
2144 MIPS_SYS(sys_munmap , 2)
2145 MIPS_SYS(sys_truncate , 2)
2146 MIPS_SYS(sys_ftruncate , 2)
2147 MIPS_SYS(sys_fchmod , 2)
2148 MIPS_SYS(sys_fchown , 3) /* 4095 */
2149 MIPS_SYS(sys_getpriority , 2)
2150 MIPS_SYS(sys_setpriority , 3)
2151 MIPS_SYS(sys_ni_syscall , 0)
2152 MIPS_SYS(sys_statfs , 2)
2153 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2154 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2155 MIPS_SYS(sys_socketcall , 2)
2156 MIPS_SYS(sys_syslog , 3)
2157 MIPS_SYS(sys_setitimer , 3)
2158 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2159 MIPS_SYS(sys_newstat , 2)
2160 MIPS_SYS(sys_newlstat , 2)
2161 MIPS_SYS(sys_newfstat , 2)
2162 MIPS_SYS(sys_uname , 1)
2163 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2164 MIPS_SYS(sys_vhangup , 0)
2165 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2166 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2167 MIPS_SYS(sys_wait4 , 4)
2168 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2169 MIPS_SYS(sys_sysinfo , 1)
2170 MIPS_SYS(sys_ipc , 6)
2171 MIPS_SYS(sys_fsync , 1)
2172 MIPS_SYS(sys_sigreturn , 0)
2173 MIPS_SYS(sys_clone , 6) /* 4120 */
2174 MIPS_SYS(sys_setdomainname, 2)
2175 MIPS_SYS(sys_newuname , 1)
2176 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2177 MIPS_SYS(sys_adjtimex , 1)
2178 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2179 MIPS_SYS(sys_sigprocmask , 3)
2180 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2181 MIPS_SYS(sys_init_module , 5)
2182 MIPS_SYS(sys_delete_module, 1)
2183 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2184 MIPS_SYS(sys_quotactl , 0)
2185 MIPS_SYS(sys_getpgid , 1)
2186 MIPS_SYS(sys_fchdir , 1)
2187 MIPS_SYS(sys_bdflush , 2)
2188 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2189 MIPS_SYS(sys_personality , 1)
2190 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2191 MIPS_SYS(sys_setfsuid , 1)
2192 MIPS_SYS(sys_setfsgid , 1)
2193 MIPS_SYS(sys_llseek , 5) /* 4140 */
2194 MIPS_SYS(sys_getdents , 3)
2195 MIPS_SYS(sys_select , 5)
2196 MIPS_SYS(sys_flock , 2)
2197 MIPS_SYS(sys_msync , 3)
2198 MIPS_SYS(sys_readv , 3) /* 4145 */
2199 MIPS_SYS(sys_writev , 3)
2200 MIPS_SYS(sys_cacheflush , 3)
2201 MIPS_SYS(sys_cachectl , 3)
2202 MIPS_SYS(sys_sysmips , 4)
2203 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2204 MIPS_SYS(sys_getsid , 1)
2205 MIPS_SYS(sys_fdatasync , 0)
2206 MIPS_SYS(sys_sysctl , 1)
2207 MIPS_SYS(sys_mlock , 2)
2208 MIPS_SYS(sys_munlock , 2) /* 4155 */
2209 MIPS_SYS(sys_mlockall , 1)
2210 MIPS_SYS(sys_munlockall , 0)
2211 MIPS_SYS(sys_sched_setparam, 2)
2212 MIPS_SYS(sys_sched_getparam, 2)
2213 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2214 MIPS_SYS(sys_sched_getscheduler, 1)
2215 MIPS_SYS(sys_sched_yield , 0)
2216 MIPS_SYS(sys_sched_get_priority_max, 1)
2217 MIPS_SYS(sys_sched_get_priority_min, 1)
2218 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2219 MIPS_SYS(sys_nanosleep, 2)
2220 MIPS_SYS(sys_mremap , 5)
2221 MIPS_SYS(sys_accept , 3)
2222 MIPS_SYS(sys_bind , 3)
2223 MIPS_SYS(sys_connect , 3) /* 4170 */
2224 MIPS_SYS(sys_getpeername , 3)
2225 MIPS_SYS(sys_getsockname , 3)
2226 MIPS_SYS(sys_getsockopt , 5)
2227 MIPS_SYS(sys_listen , 2)
2228 MIPS_SYS(sys_recv , 4) /* 4175 */
2229 MIPS_SYS(sys_recvfrom , 6)
2230 MIPS_SYS(sys_recvmsg , 3)
2231 MIPS_SYS(sys_send , 4)
2232 MIPS_SYS(sys_sendmsg , 3)
2233 MIPS_SYS(sys_sendto , 6) /* 4180 */
2234 MIPS_SYS(sys_setsockopt , 5)
2235 MIPS_SYS(sys_shutdown , 2)
2236 MIPS_SYS(sys_socket , 3)
2237 MIPS_SYS(sys_socketpair , 4)
2238 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2239 MIPS_SYS(sys_getresuid , 3)
2240 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2241 MIPS_SYS(sys_poll , 3)
2242 MIPS_SYS(sys_nfsservctl , 3)
2243 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2244 MIPS_SYS(sys_getresgid , 3)
2245 MIPS_SYS(sys_prctl , 5)
2246 MIPS_SYS(sys_rt_sigreturn, 0)
2247 MIPS_SYS(sys_rt_sigaction, 4)
2248 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2249 MIPS_SYS(sys_rt_sigpending, 2)
2250 MIPS_SYS(sys_rt_sigtimedwait, 4)
2251 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2252 MIPS_SYS(sys_rt_sigsuspend, 0)
2253 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2254 MIPS_SYS(sys_pwrite64 , 6)
2255 MIPS_SYS(sys_chown , 3)
2256 MIPS_SYS(sys_getcwd , 2)
2257 MIPS_SYS(sys_capget , 2)
2258 MIPS_SYS(sys_capset , 2) /* 4205 */
2259 MIPS_SYS(sys_sigaltstack , 2)
2260 MIPS_SYS(sys_sendfile , 4)
2261 MIPS_SYS(sys_ni_syscall , 0)
2262 MIPS_SYS(sys_ni_syscall , 0)
2263 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2264 MIPS_SYS(sys_truncate64 , 4)
2265 MIPS_SYS(sys_ftruncate64 , 4)
2266 MIPS_SYS(sys_stat64 , 2)
2267 MIPS_SYS(sys_lstat64 , 2)
2268 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2269 MIPS_SYS(sys_pivot_root , 2)
2270 MIPS_SYS(sys_mincore , 3)
2271 MIPS_SYS(sys_madvise , 3)
2272 MIPS_SYS(sys_getdents64 , 3)
2273 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2274 MIPS_SYS(sys_ni_syscall , 0)
2275 MIPS_SYS(sys_gettid , 0)
2276 MIPS_SYS(sys_readahead , 5)
2277 MIPS_SYS(sys_setxattr , 5)
2278 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2279 MIPS_SYS(sys_fsetxattr , 5)
2280 MIPS_SYS(sys_getxattr , 4)
2281 MIPS_SYS(sys_lgetxattr , 4)
2282 MIPS_SYS(sys_fgetxattr , 4)
2283 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2284 MIPS_SYS(sys_llistxattr , 3)
2285 MIPS_SYS(sys_flistxattr , 3)
2286 MIPS_SYS(sys_removexattr , 2)
2287 MIPS_SYS(sys_lremovexattr, 2)
2288 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2289 MIPS_SYS(sys_tkill , 2)
2290 MIPS_SYS(sys_sendfile64 , 5)
2291 MIPS_SYS(sys_futex , 6)
2292 MIPS_SYS(sys_sched_setaffinity, 3)
2293 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2294 MIPS_SYS(sys_io_setup , 2)
2295 MIPS_SYS(sys_io_destroy , 1)
2296 MIPS_SYS(sys_io_getevents, 5)
2297 MIPS_SYS(sys_io_submit , 3)
2298 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2299 MIPS_SYS(sys_exit_group , 1)
2300 MIPS_SYS(sys_lookup_dcookie, 3)
2301 MIPS_SYS(sys_epoll_create, 1)
2302 MIPS_SYS(sys_epoll_ctl , 4)
2303 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2304 MIPS_SYS(sys_remap_file_pages, 5)
2305 MIPS_SYS(sys_set_tid_address, 1)
2306 MIPS_SYS(sys_restart_syscall, 0)
2307 MIPS_SYS(sys_fadvise64_64, 7)
2308 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2309 MIPS_SYS(sys_fstatfs64 , 2)
2310 MIPS_SYS(sys_timer_create, 3)
2311 MIPS_SYS(sys_timer_settime, 4)
2312 MIPS_SYS(sys_timer_gettime, 2)
2313 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2314 MIPS_SYS(sys_timer_delete, 1)
2315 MIPS_SYS(sys_clock_settime, 2)
2316 MIPS_SYS(sys_clock_gettime, 2)
2317 MIPS_SYS(sys_clock_getres, 2)
2318 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2319 MIPS_SYS(sys_tgkill , 3)
2320 MIPS_SYS(sys_utimes , 2)
2321 MIPS_SYS(sys_mbind , 4)
2322 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2323 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2324 MIPS_SYS(sys_mq_open , 4)
2325 MIPS_SYS(sys_mq_unlink , 1)
2326 MIPS_SYS(sys_mq_timedsend, 5)
2327 MIPS_SYS(sys_mq_timedreceive, 5)
2328 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2329 MIPS_SYS(sys_mq_getsetattr, 3)
2330 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2331 MIPS_SYS(sys_waitid , 4)
2332 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2333 MIPS_SYS(sys_add_key , 5)
2334 MIPS_SYS(sys_request_key, 4)
2335 MIPS_SYS(sys_keyctl , 5)
2336 MIPS_SYS(sys_set_thread_area, 1)
2337 MIPS_SYS(sys_inotify_init, 0)
2338 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2339 MIPS_SYS(sys_inotify_rm_watch, 2)
2340 MIPS_SYS(sys_migrate_pages, 4)
2341 MIPS_SYS(sys_openat, 4)
2342 MIPS_SYS(sys_mkdirat, 3)
2343 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2344 MIPS_SYS(sys_fchownat, 5)
2345 MIPS_SYS(sys_futimesat, 3)
2346 MIPS_SYS(sys_fstatat64, 4)
2347 MIPS_SYS(sys_unlinkat, 3)
2348 MIPS_SYS(sys_renameat, 4) /* 4295 */
2349 MIPS_SYS(sys_linkat, 5)
2350 MIPS_SYS(sys_symlinkat, 3)
2351 MIPS_SYS(sys_readlinkat, 4)
2352 MIPS_SYS(sys_fchmodat, 3)
2353 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2354 MIPS_SYS(sys_pselect6, 6)
2355 MIPS_SYS(sys_ppoll, 5)
2356 MIPS_SYS(sys_unshare, 1)
2357 MIPS_SYS(sys_splice, 6)
2358 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2359 MIPS_SYS(sys_tee, 4)
2360 MIPS_SYS(sys_vmsplice, 4)
2361 MIPS_SYS(sys_move_pages, 6)
2362 MIPS_SYS(sys_set_robust_list, 2)
2363 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2364 MIPS_SYS(sys_kexec_load, 4)
2365 MIPS_SYS(sys_getcpu, 3)
2366 MIPS_SYS(sys_epoll_pwait, 6)
2367 MIPS_SYS(sys_ioprio_set, 3)
2368 MIPS_SYS(sys_ioprio_get, 2)
2369 MIPS_SYS(sys_utimensat, 4)
2370 MIPS_SYS(sys_signalfd, 3)
2371 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2372 MIPS_SYS(sys_eventfd, 1)
2373 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2374 MIPS_SYS(sys_timerfd_create, 2)
2375 MIPS_SYS(sys_timerfd_gettime, 2)
2376 MIPS_SYS(sys_timerfd_settime, 4)
2377 MIPS_SYS(sys_signalfd4, 4)
2378 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2379 MIPS_SYS(sys_epoll_create1, 1)
2380 MIPS_SYS(sys_dup3, 3)
2381 MIPS_SYS(sys_pipe2, 2)
2382 MIPS_SYS(sys_inotify_init1, 1)
2383 MIPS_SYS(sys_preadv, 6) /* 4330 */
2384 MIPS_SYS(sys_pwritev, 6)
2385 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2386 MIPS_SYS(sys_perf_event_open, 5)
2387 MIPS_SYS(sys_accept4, 4)
2388 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2389 MIPS_SYS(sys_fanotify_init, 2)
2390 MIPS_SYS(sys_fanotify_mark, 6)
2391 MIPS_SYS(sys_prlimit64, 4)
2392 MIPS_SYS(sys_name_to_handle_at, 5)
2393 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2394 MIPS_SYS(sys_clock_adjtime, 2)
2395 MIPS_SYS(sys_syncfs, 1)
2396 };
2397 # undef MIPS_SYS
2398 # endif /* O32 */
2399
2400 static int do_store_exclusive(CPUMIPSState *env)
2401 {
2402 target_ulong addr;
2403 target_ulong page_addr;
2404 target_ulong val;
2405 int flags;
2406 int segv = 0;
2407 int reg;
2408 int d;
2409
2410 addr = env->lladdr;
2411 page_addr = addr & TARGET_PAGE_MASK;
2412 start_exclusive();
2413 mmap_lock();
2414 flags = page_get_flags(page_addr);
2415 if ((flags & PAGE_READ) == 0) {
2416 segv = 1;
2417 } else {
2418 reg = env->llreg & 0x1f;
2419 d = (env->llreg & 0x20) != 0;
2420 if (d) {
2421 segv = get_user_s64(val, addr);
2422 } else {
2423 segv = get_user_s32(val, addr);
2424 }
2425 if (!segv) {
2426 if (val != env->llval) {
2427 env->active_tc.gpr[reg] = 0;
2428 } else {
2429 if (d) {
2430 segv = put_user_u64(env->llnewval, addr);
2431 } else {
2432 segv = put_user_u32(env->llnewval, addr);
2433 }
2434 if (!segv) {
2435 env->active_tc.gpr[reg] = 1;
2436 }
2437 }
2438 }
2439 }
2440 env->lladdr = -1;
2441 if (!segv) {
2442 env->active_tc.PC += 4;
2443 }
2444 mmap_unlock();
2445 end_exclusive();
2446 return segv;
2447 }
2448
2449 /* Break codes */
2450 enum {
2451 BRK_OVERFLOW = 6,
2452 BRK_DIVZERO = 7
2453 };
2454
2455 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2456 unsigned int code)
2457 {
2458 int ret = -1;
2459
2460 switch (code) {
2461 case BRK_OVERFLOW:
2462 case BRK_DIVZERO:
2463 info->si_signo = TARGET_SIGFPE;
2464 info->si_errno = 0;
2465 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2466 queue_signal(env, info->si_signo, &*info);
2467 ret = 0;
2468 break;
2469 default:
2470 info->si_signo = TARGET_SIGTRAP;
2471 info->si_errno = 0;
2472 queue_signal(env, info->si_signo, &*info);
2473 ret = 0;
2474 break;
2475 }
2476
2477 return ret;
2478 }
2479
2480 void cpu_loop(CPUMIPSState *env)
2481 {
2482 CPUState *cs = CPU(mips_env_get_cpu(env));
2483 target_siginfo_t info;
2484 int trapnr;
2485 abi_long ret;
2486 # ifdef TARGET_ABI_MIPSO32
2487 unsigned int syscall_num;
2488 # endif
2489
2490 for(;;) {
2491 cpu_exec_start(cs);
2492 trapnr = cpu_mips_exec(cs);
2493 cpu_exec_end(cs);
2494 switch(trapnr) {
2495 case EXCP_SYSCALL:
2496 env->active_tc.PC += 4;
2497 # ifdef TARGET_ABI_MIPSO32
2498 syscall_num = env->active_tc.gpr[2] - 4000;
2499 if (syscall_num >= sizeof(mips_syscall_args)) {
2500 ret = -TARGET_ENOSYS;
2501 } else {
2502 int nb_args;
2503 abi_ulong sp_reg;
2504 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2505
2506 nb_args = mips_syscall_args[syscall_num];
2507 sp_reg = env->active_tc.gpr[29];
2508 switch (nb_args) {
2509 /* these arguments are taken from the stack */
2510 case 8:
2511 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2512 goto done_syscall;
2513 }
2514 case 7:
2515 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2516 goto done_syscall;
2517 }
2518 case 6:
2519 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2520 goto done_syscall;
2521 }
2522 case 5:
2523 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2524 goto done_syscall;
2525 }
2526 default:
2527 break;
2528 }
2529 ret = do_syscall(env, env->active_tc.gpr[2],
2530 env->active_tc.gpr[4],
2531 env->active_tc.gpr[5],
2532 env->active_tc.gpr[6],
2533 env->active_tc.gpr[7],
2534 arg5, arg6, arg7, arg8);
2535 }
2536 done_syscall:
2537 # else
2538 ret = do_syscall(env, env->active_tc.gpr[2],
2539 env->active_tc.gpr[4], env->active_tc.gpr[5],
2540 env->active_tc.gpr[6], env->active_tc.gpr[7],
2541 env->active_tc.gpr[8], env->active_tc.gpr[9],
2542 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2543 # endif /* O32 */
2544 if (ret == -TARGET_ERESTARTSYS) {
2545 env->active_tc.PC -= 4;
2546 break;
2547 }
2548 if (ret == -TARGET_QEMU_ESIGRETURN) {
2549 /* Returning from a successful sigreturn syscall.
2550 Avoid clobbering register state. */
2551 break;
2552 }
2553 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2554 env->active_tc.gpr[7] = 1; /* error flag */
2555 ret = -ret;
2556 } else {
2557 env->active_tc.gpr[7] = 0; /* error flag */
2558 }
2559 env->active_tc.gpr[2] = ret;
2560 break;
2561 case EXCP_TLBL:
2562 case EXCP_TLBS:
2563 case EXCP_AdEL:
2564 case EXCP_AdES:
2565 info.si_signo = TARGET_SIGSEGV;
2566 info.si_errno = 0;
2567 /* XXX: check env->error_code */
2568 info.si_code = TARGET_SEGV_MAPERR;
2569 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2570 queue_signal(env, info.si_signo, &info);
2571 break;
2572 case EXCP_CpU:
2573 case EXCP_RI:
2574 info.si_signo = TARGET_SIGILL;
2575 info.si_errno = 0;
2576 info.si_code = 0;
2577 queue_signal(env, info.si_signo, &info);
2578 break;
2579 case EXCP_INTERRUPT:
2580 /* just indicate that signals should be handled asap */
2581 break;
2582 case EXCP_DEBUG:
2583 {
2584 int sig;
2585
2586 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2587 if (sig)
2588 {
2589 info.si_signo = sig;
2590 info.si_errno = 0;
2591 info.si_code = TARGET_TRAP_BRKPT;
2592 queue_signal(env, info.si_signo, &info);
2593 }
2594 }
2595 break;
2596 case EXCP_SC:
2597 if (do_store_exclusive(env)) {
2598 info.si_signo = TARGET_SIGSEGV;
2599 info.si_errno = 0;
2600 info.si_code = TARGET_SEGV_MAPERR;
2601 info._sifields._sigfault._addr = env->active_tc.PC;
2602 queue_signal(env, info.si_signo, &info);
2603 }
2604 break;
2605 case EXCP_DSPDIS:
2606 info.si_signo = TARGET_SIGILL;
2607 info.si_errno = 0;
2608 info.si_code = TARGET_ILL_ILLOPC;
2609 queue_signal(env, info.si_signo, &info);
2610 break;
2611 /* The code below was inspired by the MIPS Linux kernel trap
2612 * handling code in arch/mips/kernel/traps.c.
2613 */
2614 case EXCP_BREAK:
2615 {
2616 abi_ulong trap_instr;
2617 unsigned int code;
2618
2619 if (env->hflags & MIPS_HFLAG_M16) {
2620 if (env->insn_flags & ASE_MICROMIPS) {
2621 /* microMIPS mode */
2622 ret = get_user_u16(trap_instr, env->active_tc.PC);
2623 if (ret != 0) {
2624 goto error;
2625 }
2626
2627 if ((trap_instr >> 10) == 0x11) {
2628 /* 16-bit instruction */
2629 code = trap_instr & 0xf;
2630 } else {
2631 /* 32-bit instruction */
2632 abi_ulong instr_lo;
2633
2634 ret = get_user_u16(instr_lo,
2635 env->active_tc.PC + 2);
2636 if (ret != 0) {
2637 goto error;
2638 }
2639 trap_instr = (trap_instr << 16) | instr_lo;
2640 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2641 /* Unfortunately, microMIPS also suffers from
2642 the old assembler bug... */
2643 if (code >= (1 << 10)) {
2644 code >>= 10;
2645 }
2646 }
2647 } else {
2648 /* MIPS16e mode */
2649 ret = get_user_u16(trap_instr, env->active_tc.PC);
2650 if (ret != 0) {
2651 goto error;
2652 }
2653 code = (trap_instr >> 6) & 0x3f;
2654 }
2655 } else {
2656 ret = get_user_u32(trap_instr, env->active_tc.PC);
2657 if (ret != 0) {
2658 goto error;
2659 }
2660
2661 /* As described in the original Linux kernel code, the
2662 * below checks on 'code' are to work around an old
2663 * assembly bug.
2664 */
2665 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2666 if (code >= (1 << 10)) {
2667 code >>= 10;
2668 }
2669 }
2670
2671 if (do_break(env, &info, code) != 0) {
2672 goto error;
2673 }
2674 }
2675 break;
2676 case EXCP_TRAP:
2677 {
2678 abi_ulong trap_instr;
2679 unsigned int code = 0;
2680
2681 if (env->hflags & MIPS_HFLAG_M16) {
2682 /* microMIPS mode */
2683 abi_ulong instr[2];
2684
2685 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2686 get_user_u16(instr[1], env->active_tc.PC + 2);
2687
2688 trap_instr = (instr[0] << 16) | instr[1];
2689 } else {
2690 ret = get_user_u32(trap_instr, env->active_tc.PC);
2691 }
2692
2693 if (ret != 0) {
2694 goto error;
2695 }
2696
2697 /* The immediate versions don't provide a code. */
2698 if (!(trap_instr & 0xFC000000)) {
2699 if (env->hflags & MIPS_HFLAG_M16) {
2700 /* microMIPS mode */
2701 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2702 } else {
2703 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2704 }
2705 }
2706
2707 if (do_break(env, &info, code) != 0) {
2708 goto error;
2709 }
2710 }
2711 break;
2712 default:
2713 error:
2714 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2715 abort();
2716 }
2717 process_pending_signals(env);
2718 }
2719 }
2720 #endif
2721
2722 #ifdef TARGET_OPENRISC
2723
2724 void cpu_loop(CPUOpenRISCState *env)
2725 {
2726 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2727 int trapnr, gdbsig;
2728 abi_long ret;
2729
2730 for (;;) {
2731 cpu_exec_start(cs);
2732 trapnr = cpu_openrisc_exec(cs);
2733 cpu_exec_end(cs);
2734 gdbsig = 0;
2735
2736 switch (trapnr) {
2737 case EXCP_RESET:
2738 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2739 exit(EXIT_FAILURE);
2740 break;
2741 case EXCP_BUSERR:
2742 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2743 gdbsig = TARGET_SIGBUS;
2744 break;
2745 case EXCP_DPF:
2746 case EXCP_IPF:
2747 cpu_dump_state(cs, stderr, fprintf, 0);
2748 gdbsig = TARGET_SIGSEGV;
2749 break;
2750 case EXCP_TICK:
2751 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2752 break;
2753 case EXCP_ALIGN:
2754 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2755 gdbsig = TARGET_SIGBUS;
2756 break;
2757 case EXCP_ILLEGAL:
2758 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2759 gdbsig = TARGET_SIGILL;
2760 break;
2761 case EXCP_INT:
2762 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2763 break;
2764 case EXCP_DTLBMISS:
2765 case EXCP_ITLBMISS:
2766 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2767 break;
2768 case EXCP_RANGE:
2769 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2770 gdbsig = TARGET_SIGSEGV;
2771 break;
2772 case EXCP_SYSCALL:
2773 env->pc += 4; /* 0xc00; */
2774 ret = do_syscall(env,
2775 env->gpr[11], /* return value */
2776 env->gpr[3], /* r3 - r7 are params */
2777 env->gpr[4],
2778 env->gpr[5],
2779 env->gpr[6],
2780 env->gpr[7],
2781 env->gpr[8], 0, 0);
2782 if (ret == -TARGET_ERESTARTSYS) {
2783 env->pc -= 4;
2784 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2785 env->gpr[11] = ret;
2786 }
2787 break;
2788 case EXCP_FPE:
2789 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2790 break;
2791 case EXCP_TRAP:
2792 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2793 gdbsig = TARGET_SIGTRAP;
2794 break;
2795 case EXCP_NR:
2796 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2797 break;
2798 default:
2799 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2800 trapnr);
2801 gdbsig = TARGET_SIGILL;
2802 break;
2803 }
2804 if (gdbsig) {
2805 gdb_handlesig(cs, gdbsig);
2806 if (gdbsig != TARGET_SIGTRAP) {
2807 exit(EXIT_FAILURE);
2808 }
2809 }
2810
2811 process_pending_signals(env);
2812 }
2813 }
2814
2815 #endif /* TARGET_OPENRISC */
2816
2817 #ifdef TARGET_SH4
2818 void cpu_loop(CPUSH4State *env)
2819 {
2820 CPUState *cs = CPU(sh_env_get_cpu(env));
2821 int trapnr, ret;
2822 target_siginfo_t info;
2823
2824 while (1) {
2825 cpu_exec_start(cs);
2826 trapnr = cpu_sh4_exec(cs);
2827 cpu_exec_end(cs);
2828
2829 switch (trapnr) {
2830 case 0x160:
2831 env->pc += 2;
2832 ret = do_syscall(env,
2833 env->gregs[3],
2834 env->gregs[4],
2835 env->gregs[5],
2836 env->gregs[6],
2837 env->gregs[7],
2838 env->gregs[0],
2839 env->gregs[1],
2840 0, 0);
2841 if (ret == -TARGET_ERESTARTSYS) {
2842 env->pc -= 2;
2843 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2844 env->gregs[0] = ret;
2845 }
2846 break;
2847 case EXCP_INTERRUPT:
2848 /* just indicate that signals should be handled asap */
2849 break;
2850 case EXCP_DEBUG:
2851 {
2852 int sig;
2853
2854 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2855 if (sig)
2856 {
2857 info.si_signo = sig;
2858 info.si_errno = 0;
2859 info.si_code = TARGET_TRAP_BRKPT;
2860 queue_signal(env, info.si_signo, &info);
2861 }
2862 }
2863 break;
2864 case 0xa0:
2865 case 0xc0:
2866 info.si_signo = TARGET_SIGSEGV;
2867 info.si_errno = 0;
2868 info.si_code = TARGET_SEGV_MAPERR;
2869 info._sifields._sigfault._addr = env->tea;
2870 queue_signal(env, info.si_signo, &info);
2871 break;
2872
2873 default:
2874 printf ("Unhandled trap: 0x%x\n", trapnr);
2875 cpu_dump_state(cs, stderr, fprintf, 0);
2876 exit(EXIT_FAILURE);
2877 }
2878 process_pending_signals (env);
2879 }
2880 }
2881 #endif
2882
2883 #ifdef TARGET_CRIS
2884 void cpu_loop(CPUCRISState *env)
2885 {
2886 CPUState *cs = CPU(cris_env_get_cpu(env));
2887 int trapnr, ret;
2888 target_siginfo_t info;
2889
2890 while (1) {
2891 cpu_exec_start(cs);
2892 trapnr = cpu_cris_exec(cs);
2893 cpu_exec_end(cs);
2894 switch (trapnr) {
2895 case 0xaa:
2896 {
2897 info.si_signo = TARGET_SIGSEGV;
2898 info.si_errno = 0;
2899 /* XXX: check env->error_code */
2900 info.si_code = TARGET_SEGV_MAPERR;
2901 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2902 queue_signal(env, info.si_signo, &info);
2903 }
2904 break;
2905 case EXCP_INTERRUPT:
2906 /* just indicate that signals should be handled asap */
2907 break;
2908 case EXCP_BREAK:
2909 ret = do_syscall(env,
2910 env->regs[9],
2911 env->regs[10],
2912 env->regs[11],
2913 env->regs[12],
2914 env->regs[13],
2915 env->pregs[7],
2916 env->pregs[11],
2917 0, 0);
2918 if (ret == -TARGET_ERESTARTSYS) {
2919 env->pc -= 2;
2920 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2921 env->regs[10] = ret;
2922 }
2923 break;
2924 case EXCP_DEBUG:
2925 {
2926 int sig;
2927
2928 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2929 if (sig)
2930 {
2931 info.si_signo = sig;
2932 info.si_errno = 0;
2933 info.si_code = TARGET_TRAP_BRKPT;
2934 queue_signal(env, info.si_signo, &info);
2935 }
2936 }
2937 break;
2938 default:
2939 printf ("Unhandled trap: 0x%x\n", trapnr);
2940 cpu_dump_state(cs, stderr, fprintf, 0);
2941 exit(EXIT_FAILURE);
2942 }
2943 process_pending_signals (env);
2944 }
2945 }
2946 #endif
2947
2948 #ifdef TARGET_MICROBLAZE
2949 void cpu_loop(CPUMBState *env)
2950 {
2951 CPUState *cs = CPU(mb_env_get_cpu(env));
2952 int trapnr, ret;
2953 target_siginfo_t info;
2954
2955 while (1) {
2956 cpu_exec_start(cs);
2957 trapnr = cpu_mb_exec(cs);
2958 cpu_exec_end(cs);
2959 switch (trapnr) {
2960 case 0xaa:
2961 {
2962 info.si_signo = TARGET_SIGSEGV;
2963 info.si_errno = 0;
2964 /* XXX: check env->error_code */
2965 info.si_code = TARGET_SEGV_MAPERR;
2966 info._sifields._sigfault._addr = 0;
2967 queue_signal(env, info.si_signo, &info);
2968 }
2969 break;
2970 case EXCP_INTERRUPT:
2971 /* just indicate that signals should be handled asap */
2972 break;
2973 case EXCP_BREAK:
2974 /* Return address is 4 bytes after the call. */
2975 env->regs[14] += 4;
2976 env->sregs[SR_PC] = env->regs[14];
2977 ret = do_syscall(env,
2978 env->regs[12],
2979 env->regs[5],
2980 env->regs[6],
2981 env->regs[7],
2982 env->regs[8],
2983 env->regs[9],
2984 env->regs[10],
2985 0, 0);
2986 if (ret == -TARGET_ERESTARTSYS) {
2987 /* Wind back to before the syscall. */
2988 env->sregs[SR_PC] -= 4;
2989 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2990 env->regs[3] = ret;
2991 }
2992 /* All syscall exits result in guest r14 being equal to the
2993 * PC we return to, because the kernel syscall exit "rtbd" does
2994 * this. (This is true even for sigreturn(); note that r14 is
2995 * not a userspace-usable register, as the kernel may clobber it
2996 * at any point.)
2997 */
2998 env->regs[14] = env->sregs[SR_PC];
2999 break;
3000 case EXCP_HW_EXCP:
3001 env->regs[17] = env->sregs[SR_PC] + 4;
3002 if (env->iflags & D_FLAG) {
3003 env->sregs[SR_ESR] |= 1 << 12;
3004 env->sregs[SR_PC] -= 4;
3005 /* FIXME: if branch was immed, replay the imm as well. */
3006 }
3007
3008 env->iflags &= ~(IMM_FLAG | D_FLAG);
3009
3010 switch (env->sregs[SR_ESR] & 31) {
3011 case ESR_EC_DIVZERO:
3012 info.si_signo = TARGET_SIGFPE;
3013 info.si_errno = 0;
3014 info.si_code = TARGET_FPE_FLTDIV;
3015 info._sifields._sigfault._addr = 0;
3016 queue_signal(env, info.si_signo, &info);
3017 break;
3018 case ESR_EC_FPU:
3019 info.si_signo = TARGET_SIGFPE;
3020 info.si_errno = 0;
3021 if (env->sregs[SR_FSR] & FSR_IO) {
3022 info.si_code = TARGET_FPE_FLTINV;
3023 }
3024 if (env->sregs[SR_FSR] & FSR_DZ) {
3025 info.si_code = TARGET_FPE_FLTDIV;
3026 }
3027 info._sifields._sigfault._addr = 0;
3028 queue_signal(env, info.si_signo, &info);
3029 break;
3030 default:
3031 printf ("Unhandled hw-exception: 0x%x\n",
3032 env->sregs[SR_ESR] & ESR_EC_MASK);
3033 cpu_dump_state(cs, stderr, fprintf, 0);
3034 exit(EXIT_FAILURE);
3035 break;
3036 }
3037 break;
3038 case EXCP_DEBUG:
3039 {
3040 int sig;
3041
3042 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3043 if (sig)
3044 {
3045 info.si_signo = sig;
3046 info.si_errno = 0;
3047 info.si_code = TARGET_TRAP_BRKPT;
3048 queue_signal(env, info.si_signo, &info);
3049 }
3050 }
3051 break;
3052 default:
3053 printf ("Unhandled trap: 0x%x\n", trapnr);
3054 cpu_dump_state(cs, stderr, fprintf, 0);
3055 exit(EXIT_FAILURE);
3056 }
3057 process_pending_signals (env);
3058 }
3059 }
3060 #endif
3061
3062 #ifdef TARGET_M68K
3063
3064 void cpu_loop(CPUM68KState *env)
3065 {
3066 CPUState *cs = CPU(m68k_env_get_cpu(env));
3067 int trapnr;
3068 unsigned int n;
3069 target_siginfo_t info;
3070 TaskState *ts = cs->opaque;
3071
3072 for(;;) {
3073 cpu_exec_start(cs);
3074 trapnr = cpu_m68k_exec(cs);
3075 cpu_exec_end(cs);
3076 switch(trapnr) {
3077 case EXCP_ILLEGAL:
3078 {
3079 if (ts->sim_syscalls) {
3080 uint16_t nr;
3081 get_user_u16(nr, env->pc + 2);
3082 env->pc += 4;
3083 do_m68k_simcall(env, nr);
3084 } else {
3085 goto do_sigill;
3086 }
3087 }
3088 break;
3089 case EXCP_HALT_INSN:
3090 /* Semihosing syscall. */
3091 env->pc += 4;
3092 do_m68k_semihosting(env, env->dregs[0]);
3093 break;
3094 case EXCP_LINEA:
3095 case EXCP_LINEF:
3096 case EXCP_UNSUPPORTED:
3097 do_sigill:
3098 info.si_signo = TARGET_SIGILL;
3099 info.si_errno = 0;
3100 info.si_code = TARGET_ILL_ILLOPN;
3101 info._sifields._sigfault._addr = env->pc;
3102 queue_signal(env, info.si_signo, &info);
3103 break;
3104 case EXCP_TRAP0:
3105 {
3106 abi_long ret;
3107 ts->sim_syscalls = 0;
3108 n = env->dregs[0];
3109 env->pc += 2;
3110 ret = do_syscall(env,
3111 n,
3112 env->dregs[1],
3113 env->dregs[2],
3114 env->dregs[3],
3115 env->dregs[4],
3116 env->dregs[5],
3117 env->aregs[0],
3118 0, 0);
3119 if (ret == -TARGET_ERESTARTSYS) {
3120 env->pc -= 2;
3121 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3122 env->dregs[0] = ret;
3123 }
3124 }
3125 break;
3126 case EXCP_INTERRUPT:
3127 /* just indicate that signals should be handled asap */
3128 break;
3129 case EXCP_ACCESS:
3130 {
3131 info.si_signo = TARGET_SIGSEGV;
3132 info.si_errno = 0;
3133 /* XXX: check env->error_code */
3134 info.si_code = TARGET_SEGV_MAPERR;
3135 info._sifields._sigfault._addr = env->mmu.ar;
3136 queue_signal(env, info.si_signo, &info);
3137 }
3138 break;
3139 case EXCP_DEBUG:
3140 {
3141 int sig;
3142
3143 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3144 if (sig)
3145 {
3146 info.si_signo = sig;
3147 info.si_errno = 0;
3148 info.si_code = TARGET_TRAP_BRKPT;
3149 queue_signal(env, info.si_signo, &info);
3150 }
3151 }
3152 break;
3153 default:
3154 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
3155 abort();
3156 }
3157 process_pending_signals(env);
3158 }
3159 }
3160 #endif /* TARGET_M68K */
3161
3162 #ifdef TARGET_ALPHA
3163 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3164 {
3165 target_ulong addr, val, tmp;
3166 target_siginfo_t info;
3167 int ret = 0;
3168
3169 addr = env->lock_addr;
3170 tmp = env->lock_st_addr;
3171 env->lock_addr = -1;
3172 env->lock_st_addr = 0;
3173
3174 start_exclusive();
3175 mmap_lock();
3176
3177 if (addr == tmp) {
3178 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3179 goto do_sigsegv;
3180 }
3181
3182 if (val == env->lock_value) {
3183 tmp = env->ir[reg];
3184 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3185 goto do_sigsegv;
3186 }
3187 ret = 1;
3188 }
3189 }
3190 env->ir[reg] = ret;
3191 env->pc += 4;
3192
3193 mmap_unlock();
3194 end_exclusive();
3195 return;
3196
3197 do_sigsegv:
3198 mmap_unlock();
3199 end_exclusive();
3200
3201 info.si_signo = TARGET_SIGSEGV;
3202 info.si_errno = 0;
3203 info.si_code = TARGET_SEGV_MAPERR;
3204 info._sifields._sigfault._addr = addr;
3205 queue_signal(env, TARGET_SIGSEGV, &info);
3206 }
3207
3208 void cpu_loop(CPUAlphaState *env)
3209 {
3210 CPUState *cs = CPU(alpha_env_get_cpu(env));
3211 int trapnr;
3212 target_siginfo_t info;
3213 abi_long sysret;
3214
3215 while (1) {
3216 cpu_exec_start(cs);
3217 trapnr = cpu_alpha_exec(cs);
3218 cpu_exec_end(cs);
3219
3220 /* All of the traps imply a transition through PALcode, which
3221 implies an REI instruction has been executed. Which means
3222 that the intr_flag should be cleared. */
3223 env->intr_flag = 0;
3224
3225 switch (trapnr) {
3226 case EXCP_RESET:
3227 fprintf(stderr, "Reset requested. Exit\n");
3228 exit(EXIT_FAILURE);
3229 break;
3230 case EXCP_MCHK:
3231 fprintf(stderr, "Machine check exception. Exit\n");
3232 exit(EXIT_FAILURE);
3233 break;
3234 case EXCP_SMP_INTERRUPT:
3235 case EXCP_CLK_INTERRUPT:
3236 case EXCP_DEV_INTERRUPT:
3237 fprintf(stderr, "External interrupt. Exit\n");
3238 exit(EXIT_FAILURE);
3239 break;
3240 case EXCP_MMFAULT:
3241 env->lock_addr = -1;
3242 info.si_signo = TARGET_SIGSEGV;
3243 info.si_errno = 0;
3244 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3245 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3246 info._sifields._sigfault._addr = env->trap_arg0;
3247 queue_signal(env, info.si_signo, &info);
3248 break;
3249 case EXCP_UNALIGN:
3250 env->lock_addr = -1;
3251 info.si_signo = TARGET_SIGBUS;
3252 info.si_errno = 0;
3253 info.si_code = TARGET_BUS_ADRALN;
3254 info._sifields._sigfault._addr = env->trap_arg0;
3255 queue_signal(env, info.si_signo, &info);
3256 break;
3257 case EXCP_OPCDEC:
3258 do_sigill:
3259 env->lock_addr = -1;
3260 info.si_signo = TARGET_SIGILL;
3261 info.si_errno = 0;
3262 info.si_code = TARGET_ILL_ILLOPC;
3263 info._sifields._sigfault._addr = env->pc;
3264 queue_signal(env, info.si_signo, &info);
3265 break;
3266 case EXCP_ARITH:
3267 env->lock_addr = -1;
3268 info.si_signo = TARGET_SIGFPE;
3269 info.si_errno = 0;
3270 info.si_code = TARGET_FPE_FLTINV;
3271 info._sifields._sigfault._addr = env->pc;
3272 queue_signal(env, info.si_signo, &info);
3273 break;
3274 case EXCP_FEN:
3275 /* No-op. Linux simply re-enables the FPU. */
3276 break;
3277 case EXCP_CALL_PAL:
3278 env->lock_addr = -1;
3279 switch (env->error_code) {
3280 case 0x80:
3281 /* BPT */
3282 info.si_signo = TARGET_SIGTRAP;
3283 info.si_errno = 0;
3284 info.si_code = TARGET_TRAP_BRKPT;
3285 info._sifields._sigfault._addr = env->pc;
3286 queue_signal(env, info.si_signo, &info);
3287 break;
3288 case 0x81:
3289 /* BUGCHK */
3290 info.si_signo = TARGET_SIGTRAP;
3291 info.si_errno = 0;
3292 info.si_code = 0;
3293 info._sifields._sigfault._addr = env->pc;
3294 queue_signal(env, info.si_signo, &info);
3295 break;
3296 case 0x83:
3297 /* CALLSYS */
3298 trapnr = env->ir[IR_V0];
3299 sysret = do_syscall(env, trapnr,
3300 env->ir[IR_A0], env->ir[IR_A1],
3301 env->ir[IR_A2], env->ir[IR_A3],
3302 env->ir[IR_A4], env->ir[IR_A5],
3303 0, 0);
3304 if (sysret == -TARGET_ERESTARTSYS) {
3305 env->pc -= 4;
3306 break;
3307 }
3308 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3309 break;
3310 }
3311 /* Syscall writes 0 to V0 to bypass error check, similar
3312 to how this is handled internal to Linux kernel.
3313 (Ab)use trapnr temporarily as boolean indicating error. */
3314 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3315 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3316 env->ir[IR_A3] = trapnr;
3317 break;
3318 case 0x86:
3319 /* IMB */
3320 /* ??? We can probably elide the code using page_unprotect
3321 that is checking for self-modifying code. Instead we
3322 could simply call tb_flush here. Until we work out the
3323 changes required to turn off the extra write protection,
3324 this can be a no-op. */
3325 break;
3326 case 0x9E:
3327 /* RDUNIQUE */
3328 /* Handled in the translator for usermode. */
3329 abort();
3330 case 0x9F:
3331 /* WRUNIQUE */
3332 /* Handled in the translator for usermode. */
3333 abort();
3334 case 0xAA:
3335 /* GENTRAP */
3336 info.si_signo = TARGET_SIGFPE;
3337 switch (env->ir[IR_A0]) {
3338 case TARGET_GEN_INTOVF:
3339 info.si_code = TARGET_FPE_INTOVF;
3340 break;
3341 case TARGET_GEN_INTDIV:
3342 info.si_code = TARGET_FPE_INTDIV;
3343 break;
3344 case TARGET_GEN_FLTOVF:
3345 info.si_code = TARGET_FPE_FLTOVF;
3346 break;
3347 case TARGET_GEN_FLTUND:
3348 info.si_code = TARGET_FPE_FLTUND;
3349 break;
3350 case TARGET_GEN_FLTINV:
3351 info.si_code = TARGET_FPE_FLTINV;
3352 break;
3353 case TARGET_GEN_FLTINE:
3354 info.si_code = TARGET_FPE_FLTRES;
3355 break;
3356 case TARGET_GEN_ROPRAND:
3357 info.si_code = 0;
3358 break;
3359 default:
3360 info.si_signo = TARGET_SIGTRAP;
3361 info.si_code = 0;
3362 break;
3363 }
3364 info.si_errno = 0;
3365 info._sifields._sigfault._addr = env->pc;
3366 queue_signal(env, info.si_signo, &info);
3367 break;
3368 default:
3369 goto do_sigill;
3370 }
3371 break;
3372 case EXCP_DEBUG:
3373 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3374 if (info.si_signo) {
3375 env->lock_addr = -1;
3376 info.si_errno = 0;
3377 info.si_code = TARGET_TRAP_BRKPT;
3378 queue_signal(env, info.si_signo, &info);
3379 }
3380 break;
3381 case EXCP_STL_C:
3382 case EXCP_STQ_C:
3383 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3384 break;
3385 case EXCP_INTERRUPT:
3386 /* Just indicate that signals should be handled asap. */
3387 break;
3388 default:
3389 printf ("Unhandled trap: 0x%x\n", trapnr);
3390 cpu_dump_state(cs, stderr, fprintf, 0);
3391 exit(EXIT_FAILURE);
3392 }
3393 process_pending_signals (env);
3394 }
3395 }
3396 #endif /* TARGET_ALPHA */
3397
3398 #ifdef TARGET_S390X
3399 void cpu_loop(CPUS390XState *env)
3400 {
3401 CPUState *cs = CPU(s390_env_get_cpu(env));
3402 int trapnr, n, sig;
3403 target_siginfo_t info;
3404 target_ulong addr;
3405 abi_long ret;
3406
3407 while (1) {
3408 cpu_exec_start(cs);
3409 trapnr = cpu_s390x_exec(cs);
3410 cpu_exec_end(cs);
3411 switch (trapnr) {
3412 case EXCP_INTERRUPT:
3413 /* Just indicate that signals should be handled asap. */
3414 break;
3415
3416 case EXCP_SVC:
3417 n = env->int_svc_code;
3418 if (!n) {
3419 /* syscalls > 255 */
3420 n = env->regs[1];
3421 }
3422 env->psw.addr += env->int_svc_ilen;
3423 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3424 env->regs[4], env->regs[5],
3425 env->regs[6], env->regs[7], 0, 0);
3426 if (ret == -TARGET_ERESTARTSYS) {
3427 env->psw.addr -= env->int_svc_ilen;
3428 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3429 env->regs[2] = ret;
3430 }
3431 break;
3432
3433 case EXCP_DEBUG:
3434 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3435 if (sig) {
3436 n = TARGET_TRAP_BRKPT;
3437 goto do_signal_pc;
3438 }
3439 break;
3440 case EXCP_PGM:
3441 n = env->int_pgm_code;
3442 switch (n) {
3443 case PGM_OPERATION:
3444 case PGM_PRIVILEGED:
3445 sig = TARGET_SIGILL;
3446 n = TARGET_ILL_ILLOPC;
3447 goto do_signal_pc;
3448 case PGM_PROTECTION:
3449 case PGM_ADDRESSING:
3450 sig = TARGET_SIGSEGV;
3451 /* XXX: check env->error_code */
3452 n = TARGET_SEGV_MAPERR;
3453 addr = env->__excp_addr;
3454 goto do_signal;
3455 case PGM_EXECUTE:
3456 case PGM_SPECIFICATION:
3457 case PGM_SPECIAL_OP:
3458 case PGM_OPERAND:
3459 do_sigill_opn:
3460 sig = TARGET_SIGILL;
3461 n = TARGET_ILL_ILLOPN;
3462 goto do_signal_pc;
3463
3464 case PGM_FIXPT_OVERFLOW:
3465 sig = TARGET_SIGFPE;
3466 n = TARGET_FPE_INTOVF;
3467 goto do_signal_pc;
3468 case PGM_FIXPT_DIVIDE:
3469 sig = TARGET_SIGFPE;
3470 n = TARGET_FPE_INTDIV;
3471 goto do_signal_pc;
3472
3473 case PGM_DATA:
3474 n = (env->fpc >> 8) & 0xff;
3475 if (n == 0xff) {
3476 /* compare-and-trap */
3477 goto do_sigill_opn;
3478 } else {
3479 /* An IEEE exception, simulated or otherwise. */
3480 if (n & 0x80) {
3481 n = TARGET_FPE_FLTINV;
3482 } else if (n & 0x40) {
3483 n = TARGET_FPE_FLTDIV;
3484 } else if (n & 0x20) {
3485 n = TARGET_FPE_FLTOVF;
3486 } else if (n & 0x10) {
3487 n = TARGET_FPE_FLTUND;
3488 } else if (n & 0x08) {
3489 n = TARGET_FPE_FLTRES;
3490 } else {
3491 /* ??? Quantum exception; BFP, DFP error. */
3492 goto do_sigill_opn;
3493 }
3494 sig = TARGET_SIGFPE;
3495 goto do_signal_pc;
3496 }
3497
3498 default:
3499 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3500 cpu_dump_state(cs, stderr, fprintf, 0);
3501 exit(EXIT_FAILURE);
3502 }
3503 break;
3504
3505 do_signal_pc:
3506 addr = env->psw.addr;
3507 do_signal:
3508 info.si_signo = sig;
3509 info.si_errno = 0;
3510 info.si_code = n;
3511 info._sifields._sigfault._addr = addr;
3512 queue_signal(env, info.si_signo, &info);
3513 break;
3514
3515 default:
3516 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3517 cpu_dump_state(cs, stderr, fprintf, 0);
3518 exit(EXIT_FAILURE);
3519 }
3520 process_pending_signals (env);
3521 }
3522 }
3523
3524 #endif /* TARGET_S390X */
3525
3526 #ifdef TARGET_TILEGX
3527
3528 static void gen_sigill_reg(CPUTLGState *env)
3529 {
3530 target_siginfo_t info;
3531
3532 info.si_signo = TARGET_SIGILL;
3533 info.si_errno = 0;
3534 info.si_code = TARGET_ILL_PRVREG;
3535 info._sifields._sigfault._addr = env->pc;
3536 queue_signal(env, info.si_signo, &info);
3537 }
3538
3539 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3540 {
3541 target_siginfo_t info;
3542
3543 info.si_signo = signo;
3544 info.si_errno = 0;
3545 info._sifields._sigfault._addr = env->pc;
3546
3547 if (signo == TARGET_SIGSEGV) {
3548 /* The passed in sigcode is a dummy; check for a page mapping
3549 and pass either MAPERR or ACCERR. */
3550 target_ulong addr = env->excaddr;
3551 info._sifields._sigfault._addr = addr;
3552 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3553 sigcode = TARGET_SEGV_MAPERR;
3554 } else {
3555 sigcode = TARGET_SEGV_ACCERR;
3556 }
3557 }
3558 info.si_code = sigcode;
3559
3560 queue_signal(env, info.si_signo, &info);
3561 }
3562
3563 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3564 {
3565 env->excaddr = addr;
3566 do_signal(env, TARGET_SIGSEGV, 0);
3567 }
3568
3569 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3570 {
3571 if (unlikely(reg >= TILEGX_R_COUNT)) {
3572 switch (reg) {
3573 case TILEGX_R_SN:
3574 case TILEGX_R_ZERO:
3575 return;
3576 case TILEGX_R_IDN0:
3577 case TILEGX_R_IDN1:
3578 case TILEGX_R_UDN0:
3579 case TILEGX_R_UDN1:
3580 case TILEGX_R_UDN2:
3581 case TILEGX_R_UDN3:
3582 gen_sigill_reg(env);
3583 return;
3584 default:
3585 g_assert_not_reached();
3586 }
3587 }
3588 env->regs[reg] = val;
3589 }
3590
3591 /*
3592 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3593 * memory at the address held in the first source register. If the values are
3594 * not equal, then no memory operation is performed. If the values are equal,
3595 * the 8-byte quantity from the second source register is written into memory
3596 * at the address held in the first source register. In either case, the result
3597 * of the instruction is the value read from memory. The compare and write to
3598 * memory are atomic and thus can be used for synchronization purposes. This
3599 * instruction only operates for addresses aligned to a 8-byte boundary.
3600 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3601 *
3602 * Functional Description (64-bit)
3603 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3604 * rf[Dest] = memVal;
3605 * if (memVal == SPR[CmpValueSPR])
3606 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3607 *
3608 * Functional Description (32-bit)
3609 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3610 * rf[Dest] = memVal;
3611 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3612 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3613 *
3614 *
3615 * This function also processes exch and exch4 which need not process SPR.
3616 */
3617 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3618 {
3619 target_ulong addr;
3620 target_long val, sprval;
3621
3622 start_exclusive();
3623
3624 addr = env->atomic_srca;
3625 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3626 goto sigsegv_maperr;
3627 }
3628
3629 if (cmp) {
3630 if (quad) {
3631 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3632 } else {
3633 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3634 }
3635 }
3636
3637 if (!cmp || val == sprval) {
3638 target_long valb = env->atomic_srcb;
3639 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3640 goto sigsegv_maperr;
3641 }
3642 }
3643
3644 set_regval(env, env->atomic_dstr, val);
3645 end_exclusive();
3646 return;
3647
3648 sigsegv_maperr:
3649 end_exclusive();
3650 gen_sigsegv_maperr(env, addr);
3651 }
3652
3653 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3654 {
3655 int8_t write = 1;
3656 target_ulong addr;
3657 target_long val, valb;
3658
3659 start_exclusive();
3660
3661 addr = env->atomic_srca;
3662 valb = env->atomic_srcb;
3663 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3664 goto sigsegv_maperr;
3665 }
3666
3667 switch (trapnr) {
3668 case TILEGX_EXCP_OPCODE_FETCHADD:
3669 case TILEGX_EXCP_OPCODE_FETCHADD4:
3670 valb += val;
3671 break;
3672 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3673 valb += val;
3674 if (valb < 0) {
3675 write = 0;
3676 }
3677 break;
3678 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3679 valb += val;
3680 if ((int32_t)valb < 0) {
3681 write = 0;
3682 }
3683 break;
3684 case TILEGX_EXCP_OPCODE_FETCHAND:
3685 case TILEGX_EXCP_OPCODE_FETCHAND4:
3686 valb &= val;
3687 break;
3688 case TILEGX_EXCP_OPCODE_FETCHOR:
3689 case TILEGX_EXCP_OPCODE_FETCHOR4:
3690 valb |= val;
3691 break;
3692 default:
3693 g_assert_not_reached();
3694 }
3695
3696 if (write) {
3697 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3698 goto sigsegv_maperr;
3699 }
3700 }
3701
3702 set_regval(env, env->atomic_dstr, val);
3703 end_exclusive();
3704 return;
3705
3706 sigsegv_maperr:
3707 end_exclusive();
3708 gen_sigsegv_maperr(env, addr);
3709 }
3710
3711 void cpu_loop(CPUTLGState *env)
3712 {
3713 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3714 int trapnr;
3715
3716 while (1) {
3717 cpu_exec_start(cs);
3718 trapnr = cpu_tilegx_exec(cs);
3719 cpu_exec_end(cs);
3720 switch (trapnr) {
3721 case TILEGX_EXCP_SYSCALL:
3722 {
3723 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3724 env->regs[0], env->regs[1],
3725 env->regs[2], env->regs[3],
3726 env->regs[4], env->regs[5],
3727 env->regs[6], env->regs[7]);
3728 if (ret == -TARGET_ERESTARTSYS) {
3729 env->pc -= 8;
3730 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3731 env->regs[TILEGX_R_RE] = ret;
3732 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3733 }
3734 break;
3735 }
3736 case TILEGX_EXCP_OPCODE_EXCH:
3737 do_exch(env, true, false);
3738 break;
3739 case TILEGX_EXCP_OPCODE_EXCH4:
3740 do_exch(env, false, false);
3741 break;
3742 case TILEGX_EXCP_OPCODE_CMPEXCH:
3743 do_exch(env, true, true);
3744 break;
3745 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3746 do_exch(env, false, true);
3747 break;
3748 case TILEGX_EXCP_OPCODE_FETCHADD:
3749 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3750 case TILEGX_EXCP_OPCODE_FETCHAND:
3751 case TILEGX_EXCP_OPCODE_FETCHOR:
3752 do_fetch(env, trapnr, true);
3753 break;
3754 case TILEGX_EXCP_OPCODE_FETCHADD4:
3755 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3756 case TILEGX_EXCP_OPCODE_FETCHAND4:
3757 case TILEGX_EXCP_OPCODE_FETCHOR4:
3758 do_fetch(env, trapnr, false);
3759 break;
3760 case TILEGX_EXCP_SIGNAL:
3761 do_signal(env, env->signo, env->sigcode);
3762 break;
3763 case TILEGX_EXCP_REG_IDN_ACCESS:
3764 case TILEGX_EXCP_REG_UDN_ACCESS:
3765 gen_sigill_reg(env);
3766 break;
3767 default:
3768 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3769 g_assert_not_reached();
3770 }
3771 process_pending_signals(env);
3772 }
3773 }
3774
3775 #endif
3776
3777 THREAD CPUState *thread_cpu;
3778
3779 void task_settid(TaskState *ts)
3780 {
3781 if (ts->ts_tid == 0) {
3782 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3783 }
3784 }
3785
3786 void stop_all_tasks(void)
3787 {
3788 /*
3789 * We trust that when using NPTL, start_exclusive()
3790 * handles thread stopping correctly.
3791 */
3792 start_exclusive();
3793 }
3794
3795 /* Assumes contents are already zeroed. */
3796 void init_task_state(TaskState *ts)
3797 {
3798 ts->used = 1;
3799 }
3800
3801 CPUArchState *cpu_copy(CPUArchState *env)
3802 {
3803 CPUState *cpu = ENV_GET_CPU(env);
3804 CPUState *new_cpu = cpu_init(cpu_model);
3805 CPUArchState *new_env = new_cpu->env_ptr;
3806 CPUBreakpoint *bp;
3807 CPUWatchpoint *wp;
3808
3809 /* Reset non arch specific state */
3810 cpu_reset(new_cpu);
3811
3812 memcpy(new_env, env, sizeof(CPUArchState));
3813
3814 /* Clone all break/watchpoints.
3815 Note: Once we support ptrace with hw-debug register access, make sure
3816 BP_CPU break/watchpoints are handled correctly on clone. */
3817 QTAILQ_INIT(&new_cpu->breakpoints);
3818 QTAILQ_INIT(&new_cpu->watchpoints);
3819 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3820 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3821 }
3822 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3823 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3824 }
3825
3826 return new_env;
3827 }
3828
3829 static void handle_arg_help(const char *arg)
3830 {
3831 usage(EXIT_SUCCESS);
3832 }
3833
3834 static void handle_arg_log(const char *arg)
3835 {
3836 int mask;
3837
3838 mask = qemu_str_to_log_mask(arg);
3839 if (!mask) {
3840 qemu_print_log_usage(stdout);
3841 exit(EXIT_FAILURE);
3842 }
3843 qemu_log_needs_buffers();
3844 qemu_set_log(mask);
3845 }
3846
3847 static void handle_arg_log_filename(const char *arg)
3848 {
3849 qemu_set_log_filename(arg);
3850 }
3851
3852 static void handle_arg_set_env(const char *arg)
3853 {
3854 char *r, *p, *token;
3855 r = p = strdup(arg);
3856 while ((token = strsep(&p, ",")) != NULL) {
3857 if (envlist_setenv(envlist, token) != 0) {
3858 usage(EXIT_FAILURE);
3859 }
3860 }
3861 free(r);
3862 }
3863
3864 static void handle_arg_unset_env(const char *arg)
3865 {
3866 char *r, *p, *token;
3867 r = p = strdup(arg);
3868 while ((token = strsep(&p, ",")) != NULL) {
3869 if (envlist_unsetenv(envlist, token) != 0) {
3870 usage(EXIT_FAILURE);
3871 }
3872 }
3873 free(r);
3874 }
3875
3876 static void handle_arg_argv0(const char *arg)
3877 {
3878 argv0 = strdup(arg);
3879 }
3880
3881 static void handle_arg_stack_size(const char *arg)
3882 {
3883 char *p;
3884 guest_stack_size = strtoul(arg, &p, 0);
3885 if (guest_stack_size == 0) {
3886 usage(EXIT_FAILURE);
3887 }
3888
3889 if (*p == 'M') {
3890 guest_stack_size *= 1024 * 1024;
3891 } else if (*p == 'k' || *p == 'K') {
3892 guest_stack_size *= 1024;
3893 }
3894 }
3895
3896 static void handle_arg_ld_prefix(const char *arg)
3897 {
3898 interp_prefix = strdup(arg);
3899 }
3900
3901 static void handle_arg_pagesize(const char *arg)
3902 {
3903 qemu_host_page_size = atoi(arg);
3904 if (qemu_host_page_size == 0 ||
3905 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3906 fprintf(stderr, "page size must be a power of two\n");
3907 exit(EXIT_FAILURE);
3908 }
3909 }
3910
3911 static void handle_arg_randseed(const char *arg)
3912 {
3913 unsigned long long seed;
3914
3915 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3916 fprintf(stderr, "Invalid seed number: %s\n", arg);
3917 exit(EXIT_FAILURE);
3918 }
3919 srand(seed);
3920 }
3921
3922 static void handle_arg_gdb(const char *arg)
3923 {
3924 gdbstub_port = atoi(arg);
3925 }
3926
3927 static void handle_arg_uname(const char *arg)
3928 {
3929 qemu_uname_release = strdup(arg);
3930 }
3931
3932 static void handle_arg_cpu(const char *arg)
3933 {
3934 cpu_model = strdup(arg);
3935 if (cpu_model == NULL || is_help_option(cpu_model)) {
3936 /* XXX: implement xxx_cpu_list for targets that still miss it */
3937 #if defined(cpu_list)
3938 cpu_list(stdout, &fprintf);
3939 #endif
3940 exit(EXIT_FAILURE);
3941 }
3942 }
3943
3944 static void handle_arg_guest_base(const char *arg)
3945 {
3946 guest_base = strtol(arg, NULL, 0);
3947 have_guest_base = 1;
3948 }
3949
3950 static void handle_arg_reserved_va(const char *arg)
3951 {
3952 char *p;
3953 int shift = 0;
3954 reserved_va = strtoul(arg, &p, 0);
3955 switch (*p) {
3956 case 'k':
3957 case 'K':
3958 shift = 10;
3959 break;
3960 case 'M':
3961 shift = 20;
3962 break;
3963 case 'G':
3964 shift = 30;
3965 break;
3966 }
3967 if (shift) {
3968 unsigned long unshifted = reserved_va;
3969 p++;
3970 reserved_va <<= shift;
3971 if (((reserved_va >> shift) != unshifted)
3972 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3973 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3974 #endif
3975 ) {
3976 fprintf(stderr, "Reserved virtual address too big\n");
3977 exit(EXIT_FAILURE);
3978 }
3979 }
3980 if (*p) {
3981 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3982 exit(EXIT_FAILURE);
3983 }
3984 }
3985
3986 static void handle_arg_singlestep(const char *arg)
3987 {
3988 singlestep = 1;
3989 }
3990
3991 static void handle_arg_strace(const char *arg)
3992 {
3993 do_strace = 1;
3994 }
3995
3996 static void handle_arg_version(const char *arg)
3997 {
3998 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3999 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
4000 exit(EXIT_SUCCESS);
4001 }
4002
4003 struct qemu_argument {
4004 const char *argv;
4005 const char *env;
4006 bool has_arg;
4007 void (*handle_opt)(const char *arg);
4008 const char *example;
4009 const char *help;
4010 };
4011
4012 static const struct qemu_argument arg_table[] = {
4013 {"h", "", false, handle_arg_help,
4014 "", "print this help"},
4015 {"help", "", false, handle_arg_help,
4016 "", ""},
4017 {"g", "QEMU_GDB", true, handle_arg_gdb,
4018 "port", "wait gdb connection to 'port'"},
4019 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
4020 "path", "set the elf interpreter prefix to 'path'"},
4021 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
4022 "size", "set the stack size to 'size' bytes"},
4023 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
4024 "model", "select CPU (-cpu help for list)"},
4025 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
4026 "var=value", "sets targets environment variable (see below)"},
4027 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
4028 "var", "unsets targets environment variable (see below)"},
4029 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
4030 "argv0", "forces target process argv[0] to be 'argv0'"},
4031 {"r", "QEMU_UNAME", true, handle_arg_uname,
4032 "uname", "set qemu uname release string to 'uname'"},
4033 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
4034 "address", "set guest_base address to 'address'"},
4035 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
4036 "size", "reserve 'size' bytes for guest virtual address space"},
4037 {"d", "QEMU_LOG", true, handle_arg_log,
4038 "item[,...]", "enable logging of specified items "
4039 "(use '-d help' for a list of items)"},
4040 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
4041 "logfile", "write logs to 'logfile' (default stderr)"},
4042 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
4043 "pagesize", "set the host page size to 'pagesize'"},
4044 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
4045 "", "run in singlestep mode"},
4046 {"strace", "QEMU_STRACE", false, handle_arg_strace,
4047 "", "log system calls"},
4048 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
4049 "", "Seed for pseudo-random number generator"},
4050 {"version", "QEMU_VERSION", false, handle_arg_version,
4051 "", "display version information and exit"},
4052 {NULL, NULL, false, NULL, NULL, NULL}
4053 };
4054
4055 static void usage(int exitcode)
4056 {
4057 const struct qemu_argument *arginfo;
4058 int maxarglen;
4059 int maxenvlen;
4060
4061 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
4062 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
4063 "\n"
4064 "Options and associated environment variables:\n"
4065 "\n");
4066
4067 /* Calculate column widths. We must always have at least enough space
4068 * for the column header.
4069 */
4070 maxarglen = strlen("Argument");
4071 maxenvlen = strlen("Env-variable");
4072
4073 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4074 int arglen = strlen(arginfo->argv);
4075 if (arginfo->has_arg) {
4076 arglen += strlen(arginfo->example) + 1;
4077 }
4078 if (strlen(arginfo->env) > maxenvlen) {
4079 maxenvlen = strlen(arginfo->env);
4080 }
4081 if (arglen > maxarglen) {
4082 maxarglen = arglen;
4083 }
4084 }
4085
4086 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4087 maxenvlen, "Env-variable");
4088
4089 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4090 if (arginfo->has_arg) {
4091 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4092 (int)(maxarglen - strlen(arginfo->argv) - 1),
4093 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4094 } else {
4095 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4096 maxenvlen, arginfo->env,
4097 arginfo->help);
4098 }
4099 }
4100
4101 printf("\n"
4102 "Defaults:\n"
4103 "QEMU_LD_PREFIX = %s\n"
4104 "QEMU_STACK_SIZE = %ld byte\n",
4105 interp_prefix,
4106 guest_stack_size);
4107
4108 printf("\n"
4109 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4110 "QEMU_UNSET_ENV environment variables to set and unset\n"
4111 "environment variables for the target process.\n"
4112 "It is possible to provide several variables by separating them\n"
4113 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4114 "provide the -E and -U options multiple times.\n"
4115 "The following lines are equivalent:\n"
4116 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4117 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4118 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4119 "Note that if you provide several changes to a single variable\n"
4120 "the last change will stay in effect.\n");
4121
4122 exit(exitcode);
4123 }
4124
4125 static int parse_args(int argc, char **argv)
4126 {
4127 const char *r;
4128 int optind;
4129 const struct qemu_argument *arginfo;
4130
4131 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4132 if (arginfo->env == NULL) {
4133 continue;
4134 }
4135
4136 r = getenv(arginfo->env);
4137 if (r != NULL) {
4138 arginfo->handle_opt(r);
4139 }
4140 }
4141
4142 optind = 1;
4143 for (;;) {
4144 if (optind >= argc) {
4145 break;
4146 }
4147 r = argv[optind];
4148 if (r[0] != '-') {
4149 break;
4150 }
4151 optind++;
4152 r++;
4153 if (!strcmp(r, "-")) {
4154 break;
4155 }
4156 /* Treat --foo the same as -foo. */
4157 if (r[0] == '-') {
4158 r++;
4159 }
4160
4161 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4162 if (!strcmp(r, arginfo->argv)) {
4163 if (arginfo->has_arg) {
4164 if (optind >= argc) {
4165 (void) fprintf(stderr,
4166 "qemu: missing argument for option '%s'\n", r);
4167 exit(EXIT_FAILURE);
4168 }
4169 arginfo->handle_opt(argv[optind]);
4170 optind++;
4171 } else {
4172 arginfo->handle_opt(NULL);
4173 }
4174 break;
4175 }
4176 }
4177
4178 /* no option matched the current argv */
4179 if (arginfo->handle_opt == NULL) {
4180 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4181 exit(EXIT_FAILURE);
4182 }
4183 }
4184
4185 if (optind >= argc) {
4186 (void) fprintf(stderr, "qemu: no user program specified\n");
4187 exit(EXIT_FAILURE);
4188 }
4189
4190 filename = argv[optind];
4191 exec_path = argv[optind];
4192
4193 return optind;
4194 }
4195
4196 int main(int argc, char **argv, char **envp)
4197 {
4198 struct target_pt_regs regs1, *regs = &regs1;
4199 struct image_info info1, *info = &info1;
4200 struct linux_binprm bprm;
4201 TaskState *ts;
4202 CPUArchState *env;
4203 CPUState *cpu;
4204 int optind;
4205 char **target_environ, **wrk;
4206 char **target_argv;
4207 int target_argc;
4208 int i;
4209 int ret;
4210 int execfd;
4211
4212 module_call_init(MODULE_INIT_QOM);
4213
4214 if ((envlist = envlist_create()) == NULL) {
4215 (void) fprintf(stderr, "Unable to allocate envlist\n");
4216 exit(EXIT_FAILURE);
4217 }
4218
4219 /* add current environment into the list */
4220 for (wrk = environ; *wrk != NULL; wrk++) {
4221 (void) envlist_setenv(envlist, *wrk);
4222 }
4223
4224 /* Read the stack limit from the kernel. If it's "unlimited",
4225 then we can do little else besides use the default. */
4226 {
4227 struct rlimit lim;
4228 if (getrlimit(RLIMIT_STACK, &lim) == 0
4229 && lim.rlim_cur != RLIM_INFINITY
4230 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4231 guest_stack_size = lim.rlim_cur;
4232 }
4233 }
4234
4235 cpu_model = NULL;
4236
4237 srand(time(NULL));
4238
4239 optind = parse_args(argc, argv);
4240
4241 /* Zero out regs */
4242 memset(regs, 0, sizeof(struct target_pt_regs));
4243
4244 /* Zero out image_info */
4245 memset(info, 0, sizeof(struct image_info));
4246
4247 memset(&bprm, 0, sizeof (bprm));
4248
4249 /* Scan interp_prefix dir for replacement files. */
4250 init_paths(interp_prefix);
4251
4252 init_qemu_uname_release();
4253
4254 if (cpu_model == NULL) {
4255 #if defined(TARGET_I386)
4256 #ifdef TARGET_X86_64
4257 cpu_model = "qemu64";
4258 #else
4259 cpu_model = "qemu32";
4260 #endif
4261 #elif defined(TARGET_ARM)
4262 cpu_model = "any";
4263 #elif defined(TARGET_UNICORE32)
4264 cpu_model = "any";
4265 #elif defined(TARGET_M68K)
4266 cpu_model = "any";
4267 #elif defined(TARGET_SPARC)
4268 #ifdef TARGET_SPARC64
4269 cpu_model = "TI UltraSparc II";
4270 #else
4271 cpu_model = "Fujitsu MB86904";
4272 #endif
4273 #elif defined(TARGET_MIPS)
4274 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4275 cpu_model = "5KEf";
4276 #else
4277 cpu_model = "24Kf";
4278 #endif
4279 #elif defined TARGET_OPENRISC
4280 cpu_model = "or1200";
4281 #elif defined(TARGET_PPC)
4282 # ifdef TARGET_PPC64
4283 cpu_model = "POWER8";
4284 # else
4285 cpu_model = "750";
4286 # endif
4287 #elif defined TARGET_SH4
4288 cpu_model = TYPE_SH7785_CPU;
4289 #else
4290 cpu_model = "any";
4291 #endif
4292 }
4293 tcg_exec_init(0);
4294 /* NOTE: we need to init the CPU at this stage to get
4295 qemu_host_page_size */
4296 cpu = cpu_init(cpu_model);
4297 if (!cpu) {
4298 fprintf(stderr, "Unable to find CPU definition\n");
4299 exit(EXIT_FAILURE);
4300 }
4301 env = cpu->env_ptr;
4302 cpu_reset(cpu);
4303
4304 thread_cpu = cpu;
4305
4306 if (getenv("QEMU_STRACE")) {
4307 do_strace = 1;
4308 }
4309
4310 if (getenv("QEMU_RAND_SEED")) {
4311 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4312 }
4313
4314 target_environ = envlist_to_environ(envlist, NULL);
4315 envlist_free(envlist);
4316
4317 /*
4318 * Now that page sizes are configured in cpu_init() we can do
4319 * proper page alignment for guest_base.
4320 */
4321 guest_base = HOST_PAGE_ALIGN(guest_base);
4322
4323 if (reserved_va || have_guest_base) {
4324 guest_base = init_guest_space(guest_base, reserved_va, 0,
4325 have_guest_base);
4326 if (guest_base == (unsigned long)-1) {
4327 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4328 "space for use as guest address space (check your virtual "
4329 "memory ulimit setting or reserve less using -R option)\n",
4330 reserved_va);
4331 exit(EXIT_FAILURE);
4332 }
4333
4334 if (reserved_va) {
4335 mmap_next_start = reserved_va;
4336 }
4337 }
4338
4339 /*
4340 * Read in mmap_min_addr kernel parameter. This value is used
4341 * When loading the ELF image to determine whether guest_base
4342 * is needed. It is also used in mmap_find_vma.
4343 */
4344 {
4345 FILE *fp;
4346
4347 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4348 unsigned long tmp;
4349 if (fscanf(fp, "%lu", &tmp) == 1) {
4350 mmap_min_addr = tmp;
4351 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4352 }
4353 fclose(fp);
4354 }
4355 }
4356
4357 /*
4358 * Prepare copy of argv vector for target.
4359 */
4360 target_argc = argc - optind;
4361 target_argv = calloc(target_argc + 1, sizeof (char *));
4362 if (target_argv == NULL) {
4363 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4364 exit(EXIT_FAILURE);
4365 }
4366
4367 /*
4368 * If argv0 is specified (using '-0' switch) we replace
4369 * argv[0] pointer with the given one.
4370 */
4371 i = 0;
4372 if (argv0 != NULL) {
4373 target_argv[i++] = strdup(argv0);
4374 }
4375 for (; i < target_argc; i++) {
4376 target_argv[i] = strdup(argv[optind + i]);
4377 }
4378 target_argv[target_argc] = NULL;
4379
4380 ts = g_new0(TaskState, 1);
4381 init_task_state(ts);
4382 /* build Task State */
4383 ts->info = info;
4384 ts->bprm = &bprm;
4385 cpu->opaque = ts;
4386 task_settid(ts);
4387
4388 execfd = qemu_getauxval(AT_EXECFD);
4389 if (execfd == 0) {
4390 execfd = open(filename, O_RDONLY);
4391 if (execfd < 0) {
4392 printf("Error while loading %s: %s\n", filename, strerror(errno));
4393 _exit(EXIT_FAILURE);
4394 }
4395 }
4396
4397 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4398 info, &bprm);
4399 if (ret != 0) {
4400 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4401 _exit(EXIT_FAILURE);
4402 }
4403
4404 for (wrk = target_environ; *wrk; wrk++) {
4405 free(*wrk);
4406 }
4407
4408 free(target_environ);
4409
4410 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4411 qemu_log("guest_base 0x%lx\n", guest_base);
4412 log_page_dump();
4413
4414 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4415 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4416 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4417 info->start_code);
4418 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4419 info->start_data);
4420 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4421 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4422 info->start_stack);
4423 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4424 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4425 }
4426
4427 target_set_brk(info->brk);
4428 syscall_init();
4429 signal_init();
4430
4431 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4432 generating the prologue until now so that the prologue can take
4433 the real value of GUEST_BASE into account. */
4434 tcg_prologue_init(&tcg_ctx);
4435
4436 #if defined(TARGET_I386)
4437 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4438 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4439 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4440 env->cr[4] |= CR4_OSFXSR_MASK;
4441 env->hflags |= HF_OSFXSR_MASK;
4442 }
4443 #ifndef TARGET_ABI32
4444 /* enable 64 bit mode if possible */
4445 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4446 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4447 exit(EXIT_FAILURE);
4448 }
4449 env->cr[4] |= CR4_PAE_MASK;
4450 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4451 env->hflags |= HF_LMA_MASK;
4452 #endif
4453
4454 /* flags setup : we activate the IRQs by default as in user mode */
4455 env->eflags |= IF_MASK;
4456
4457 /* linux register setup */
4458 #ifndef TARGET_ABI32
4459 env->regs[R_EAX] = regs->rax;
4460 env->regs[R_EBX] = regs->rbx;
4461 env->regs[R_ECX] = regs->rcx;
4462 env->regs[R_EDX] = regs->rdx;
4463 env->regs[R_ESI] = regs->rsi;
4464 env->regs[R_EDI] = regs->rdi;
4465 env->regs[R_EBP] = regs->rbp;
4466 env->regs[R_ESP] = regs->rsp;
4467 env->eip = regs->rip;
4468 #else
4469 env->regs[R_EAX] = regs->eax;
4470 env->regs[R_EBX] = regs->ebx;
4471 env->regs[R_ECX] = regs->ecx;
4472 env->regs[R_EDX] = regs->edx;
4473 env->regs[R_ESI] = regs->esi;
4474 env->regs[R_EDI] = regs->edi;
4475 env->regs[R_EBP] = regs->ebp;
4476 env->regs[R_ESP] = regs->esp;
4477 env->eip = regs->eip;
4478 #endif
4479
4480 /* linux interrupt setup */
4481 #ifndef TARGET_ABI32
4482 env->idt.limit = 511;
4483 #else
4484 env->idt.limit = 255;
4485 #endif
4486 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4487 PROT_READ|PROT_WRITE,
4488 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4489 idt_table = g2h(env->idt.base);
4490 set_idt(0, 0);
4491 set_idt(1, 0);
4492 set_idt(2, 0);
4493 set_idt(3, 3);
4494 set_idt(4, 3);
4495 set_idt(5, 0);
4496 set_idt(6, 0);
4497 set_idt(7, 0);
4498 set_idt(8, 0);
4499 set_idt(9, 0);
4500 set_idt(10, 0);
4501 set_idt(11, 0);
4502 set_idt(12, 0);
4503 set_idt(13, 0);
4504 set_idt(14, 0);
4505 set_idt(15, 0);
4506 set_idt(16, 0);
4507 set_idt(17, 0);
4508 set_idt(18, 0);
4509 set_idt(19, 0);
4510 set_idt(0x80, 3);
4511
4512 /* linux segment setup */
4513 {
4514 uint64_t *gdt_table;
4515 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4516 PROT_READ|PROT_WRITE,
4517 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4518 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4519 gdt_table = g2h(env->gdt.base);
4520 #ifdef TARGET_ABI32
4521 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4522 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4523 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4524 #else
4525 /* 64 bit code segment */
4526 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4527 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4528 DESC_L_MASK |
4529 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4530 #endif
4531 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4532 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4533 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4534 }
4535 cpu_x86_load_seg(env, R_CS, __USER_CS);
4536 cpu_x86_load_seg(env, R_SS, __USER_DS);
4537 #ifdef TARGET_ABI32
4538 cpu_x86_load_seg(env, R_DS, __USER_DS);
4539 cpu_x86_load_seg(env, R_ES, __USER_DS);
4540 cpu_x86_load_seg(env, R_FS, __USER_DS);
4541 cpu_x86_load_seg(env, R_GS, __USER_DS);
4542 /* This hack makes Wine work... */
4543 env->segs[R_FS].selector = 0;
4544 #else
4545 cpu_x86_load_seg(env, R_DS, 0);
4546 cpu_x86_load_seg(env, R_ES, 0);
4547 cpu_x86_load_seg(env, R_FS, 0);
4548 cpu_x86_load_seg(env, R_GS, 0);
4549 #endif
4550 #elif defined(TARGET_AARCH64)
4551 {
4552 int i;
4553
4554 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4555 fprintf(stderr,
4556 "The selected ARM CPU does not support 64 bit mode\n");
4557 exit(EXIT_FAILURE);
4558 }
4559
4560 for (i = 0; i < 31; i++) {
4561 env->xregs[i] = regs->regs[i];
4562 }
4563 env->pc = regs->pc;
4564 env->xregs[31] = regs->sp;
4565 }
4566 #elif defined(TARGET_ARM)
4567 {
4568 int i;
4569 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4570 CPSRWriteByInstr);
4571 for(i = 0; i < 16; i++) {
4572 env->regs[i] = regs->uregs[i];
4573 }
4574 #ifdef TARGET_WORDS_BIGENDIAN
4575 /* Enable BE8. */
4576 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4577 && (info->elf_flags & EF_ARM_BE8)) {
4578 env->uncached_cpsr |= CPSR_E;
4579 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4580 } else {
4581 env->cp15.sctlr_el[1] |= SCTLR_B;
4582 }
4583 #endif
4584 }
4585 #elif defined(TARGET_UNICORE32)
4586 {
4587 int i;
4588 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4589 for (i = 0; i < 32; i++) {
4590 env->regs[i] = regs->uregs[i];
4591 }
4592 }
4593 #elif defined(TARGET_SPARC)
4594 {
4595 int i;
4596 env->pc = regs->pc;
4597 env->npc = regs->npc;
4598 env->y = regs->y;
4599 for(i = 0; i < 8; i++)
4600 env->gregs[i] = regs->u_regs[i];
4601 for(i = 0; i < 8; i++)
4602 env->regwptr[i] = regs->u_regs[i + 8];
4603 }
4604 #elif defined(TARGET_PPC)
4605 {
4606 int i;
4607
4608 #if defined(TARGET_PPC64)
4609 #if defined(TARGET_ABI32)
4610 env->msr &= ~((target_ulong)1 << MSR_SF);
4611 #else
4612 env->msr |= (target_ulong)1 << MSR_SF;
4613 #endif
4614 #endif
4615 env->nip = regs->nip;
4616 for(i = 0; i < 32; i++) {
4617 env->gpr[i] = regs->gpr[i];
4618 }
4619 }
4620 #elif defined(TARGET_M68K)
4621 {
4622 env->pc = regs->pc;
4623 env->dregs[0] = regs->d0;
4624 env->dregs[1] = regs->d1;
4625 env->dregs[2] = regs->d2;
4626 env->dregs[3] = regs->d3;
4627 env->dregs[4] = regs->d4;
4628 env->dregs[5] = regs->d5;
4629 env->dregs[6] = regs->d6;
4630 env->dregs[7] = regs->d7;
4631 env->aregs[0] = regs->a0;
4632 env->aregs[1] = regs->a1;
4633 env->aregs[2] = regs->a2;
4634 env->aregs[3] = regs->a3;
4635 env->aregs[4] = regs->a4;
4636 env->aregs[5] = regs->a5;
4637 env->aregs[6] = regs->a6;
4638 env->aregs[7] = regs->usp;
4639 env->sr = regs->sr;
4640 ts->sim_syscalls = 1;
4641 }
4642 #elif defined(TARGET_MICROBLAZE)
4643 {
4644 env->regs[0] = regs->r0;
4645 env->regs[1] = regs->r1;
4646 env->regs[2] = regs->r2;
4647 env->regs[3] = regs->r3;
4648 env->regs[4] = regs->r4;
4649 env->regs[5] = regs->r5;
4650 env->regs[6] = regs->r6;
4651 env->regs[7] = regs->r7;
4652 env->regs[8] = regs->r8;
4653 env->regs[9] = regs->r9;
4654 env->regs[10] = regs->r10;
4655 env->regs[11] = regs->r11;
4656 env->regs[12] = regs->r12;
4657 env->regs[13] = regs->r13;
4658 env->regs[14] = regs->r14;
4659 env->regs[15] = regs->r15;
4660 env->regs[16] = regs->r16;
4661 env->regs[17] = regs->r17;
4662 env->regs[18] = regs->r18;
4663 env->regs[19] = regs->r19;
4664 env->regs[20] = regs->r20;
4665 env->regs[21] = regs->r21;
4666 env->regs[22] = regs->r22;
4667 env->regs[23] = regs->r23;
4668 env->regs[24] = regs->r24;
4669 env->regs[25] = regs->r25;
4670 env->regs[26] = regs->r26;
4671 env->regs[27] = regs->r27;
4672 env->regs[28] = regs->r28;
4673 env->regs[29] = regs->r29;
4674 env->regs[30] = regs->r30;
4675 env->regs[31] = regs->r31;
4676 env->sregs[SR_PC] = regs->pc;
4677 }
4678 #elif defined(TARGET_MIPS)
4679 {
4680 int i;
4681
4682 for(i = 0; i < 32; i++) {
4683 env->active_tc.gpr[i] = regs->regs[i];
4684 }
4685 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4686 if (regs->cp0_epc & 1) {
4687 env->hflags |= MIPS_HFLAG_M16;
4688 }
4689 }
4690 #elif defined(TARGET_OPENRISC)
4691 {
4692 int i;
4693
4694 for (i = 0; i < 32; i++) {
4695 env->gpr[i] = regs->gpr[i];
4696 }
4697
4698 env->sr = regs->sr;
4699 env->pc = regs->pc;
4700 }
4701 #elif defined(TARGET_SH4)
4702 {
4703 int i;
4704
4705 for(i = 0; i < 16; i++) {
4706 env->gregs[i] = regs->regs[i];
4707 }
4708 env->pc = regs->pc;
4709 }
4710 #elif defined(TARGET_ALPHA)
4711 {
4712 int i;
4713
4714 for(i = 0; i < 28; i++) {
4715 env->ir[i] = ((abi_ulong *)regs)[i];
4716 }
4717 env->ir[IR_SP] = regs->usp;
4718 env->pc = regs->pc;
4719 }
4720 #elif defined(TARGET_CRIS)
4721 {
4722 env->regs[0] = regs->r0;
4723 env->regs[1] = regs->r1;
4724 env->regs[2] = regs->r2;
4725 env->regs[3] = regs->r3;
4726 env->regs[4] = regs->r4;
4727 env->regs[5] = regs->r5;
4728 env->regs[6] = regs->r6;
4729 env->regs[7] = regs->r7;
4730 env->regs[8] = regs->r8;
4731 env->regs[9] = regs->r9;
4732 env->regs[10] = regs->r10;
4733 env->regs[11] = regs->r11;
4734 env->regs[12] = regs->r12;
4735 env->regs[13] = regs->r13;
4736 env->regs[14] = info->start_stack;
4737 env->regs[15] = regs->acr;
4738 env->pc = regs->erp;
4739 }
4740 #elif defined(TARGET_S390X)
4741 {
4742 int i;
4743 for (i = 0; i < 16; i++) {
4744 env->regs[i] = regs->gprs[i];
4745 }
4746 env->psw.mask = regs->psw.mask;
4747 env->psw.addr = regs->psw.addr;
4748 }
4749 #elif defined(TARGET_TILEGX)
4750 {
4751 int i;
4752 for (i = 0; i < TILEGX_R_COUNT; i++) {
4753 env->regs[i] = regs->regs[i];
4754 }
4755 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4756 env->spregs[i] = 0;
4757 }
4758 env->pc = regs->pc;
4759 }
4760 #else
4761 #error unsupported target CPU
4762 #endif
4763
4764 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4765 ts->stack_base = info->start_stack;
4766 ts->heap_base = info->brk;
4767 /* This will be filled in on the first SYS_HEAPINFO call. */
4768 ts->heap_limit = 0;
4769 #endif
4770
4771 if (gdbstub_port) {
4772 if (gdbserver_start(gdbstub_port) < 0) {
4773 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4774 gdbstub_port);
4775 exit(EXIT_FAILURE);
4776 }
4777 gdb_handlesig(cpu, 0);
4778 }
4779 cpu_loop(env);
4780 /* never exits */
4781 return 0;
4782 }
AR7 emulation for QEMU