target-sh4/op_helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #ifndef CONFIG_USER_ONLY
  26
  27 void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
  28               int mmu_idx, uintptr_t retaddr)
  29 {
  30     int ret;
  31
  32     ret = superh_cpu_handle_mmu_fault(cs, addr, access_type, mmu_idx);
  33     if (ret) {
  34         /* now we have a real cpu fault */
  35         if (retaddr) {
  36             cpu_restore_state(cs, retaddr);
  37         }
  38         cpu_loop_exit(cs);
  39     }
  40 }
  41
  42 #endif
  43
  44 #ifdef CONFIG_USER_ONLY
  45 void QEMU_NORETURN helper_ldtlb(CPUSH4State *env)
  46 #else
  47 void helper_ldtlb(CPUSH4State *env)
  48 #endif
  49 {
  50 #ifdef CONFIG_USER_ONLY
  51     SuperHCPU *cpu = sh_env_get_cpu(env);
  52
  53     /* XXXXX */
  54     cpu_abort(CPU(cpu), "Unhandled ldtlb");
  55 #else
  56     cpu_load_tlb(env);
  57 #endif
  58 }
  59
  60 static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
  61                                                  uintptr_t retaddr)
  62 {
  63     CPUState *cs = CPU(sh_env_get_cpu(env));
  64
  65     cs->exception_index = index;
  66     if (retaddr) {
  67         cpu_restore_state(cs, retaddr);
  68     }
  69     cpu_loop_exit(cs);
  70 }
  71
  72 void QEMU_NORETURN helper_raise_illegal_instruction(CPUSH4State *env)
  73 {
  74     raise_exception(env, 0x180, 0);
  75 }
  76
  77 void QEMU_NORETURN helper_raise_slot_illegal_instruction(CPUSH4State *env)
  78 {
  79     raise_exception(env, 0x1a0, 0);
  80 }
  81
  82 void QEMU_NORETURN helper_raise_fpu_disable(CPUSH4State *env)
  83 {
  84     raise_exception(env, 0x800, 0);
  85 }
  86
  87 void QEMU_NORETURN helper_raise_slot_fpu_disable(CPUSH4State *env)
  88 {
  89     raise_exception(env, 0x820, 0);
  90 }
  91
  92 void QEMU_NORETURN helper_debug(CPUSH4State *env)
  93 {
  94     raise_exception(env, EXCP_DEBUG, 0);
  95 }
  96
  97 void QEMU_NORETURN helper_sleep(CPUSH4State *env)
  98 {
  99     CPUState *cs = CPU(sh_env_get_cpu(env));
 100
 101     cs->halted = 1;
 102     env->in_sleep = 1;
 103     raise_exception(env, EXCP_HLT, 0);
 104 }
 105
 106 void QEMU_NORETURN helper_trapa(CPUSH4State *env, uint32_t tra)
 107 {
 108     env->tra = tra << 2;
 109     raise_exception(env, 0x160, 0);
 110 }
 111
 112 void helper_movcal(CPUSH4State *env, uint32_t address, uint32_t value)
 113 {
 114     if (cpu_sh4_is_cached (env, address))
 115     {
 116         memory_content *r = malloc (sizeof(memory_content));
 117         r->address = address;
 118         r->value = value;
 119         r->next = NULL;
 120
 121         *(env->movcal_backup_tail) = r;
 122         env->movcal_backup_tail = &(r->next);
 123     }
 124 }
 125
 126 void helper_discard_movcal_backup(CPUSH4State *env)
 127 {
 128     memory_content *current = env->movcal_backup;
 129
 130     while(current)
 131     {
 132         memory_content *next = current->next;
 133         free (current);
 134         env->movcal_backup = current = next;
 135         if (current == NULL)
 136             env->movcal_backup_tail = &(env->movcal_backup);
 137     }
 138 }
 139
 140 void helper_ocbi(CPUSH4State *env, uint32_t address)
 141 {
 142     memory_content **current = &(env->movcal_backup);
 143     while (*current)
 144     {
 145         uint32_t a = (*current)->address;
 146         if ((a & ~0x1F) == (address & ~0x1F))
 147         {
 148             memory_content *next = (*current)->next;
 149             cpu_stl_data(env, a, (*current)->value);
 150
 151             if (next == NULL)
 152             {
 153                 env->movcal_backup_tail = current;
 154             }
 155
 156             free (*current);
 157             *current = next;
 158             break;
 159         }
 160     }
 161 }
 162
 163 void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 164 {
 165     int64_t res;
 166
 167     res = ((uint64_t) env->mach << 32) | env->macl;
 168     res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
 169     env->mach = (res >> 32) & 0xffffffff;
 170     env->macl = res & 0xffffffff;
 171     if (env->sr & (1u << SR_S)) {
 172         if (res < 0)
 173             env->mach |= 0xffff0000;
 174         else
 175             env->mach &= 0x00007fff;
 176     }
 177 }
 178
 179 void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
 180 {
 181     int64_t res;
 182
 183     res = ((uint64_t) env->mach << 32) | env->macl;
 184     res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
 185     env->mach = (res >> 32) & 0xffffffff;
 186     env->macl = res & 0xffffffff;
 187     if (env->sr & (1u << SR_S)) {
 188         if (res < -0x80000000) {
 189             env->mach = 1;
 190             env->macl = 0x80000000;
 191         } else if (res > 0x000000007fffffff) {
 192             env->mach = 1;
 193             env->macl = 0x7fffffff;
 194         }
 195     }
 196 }
 197
 198 void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
 199 {
 200     env->fpscr = val & FPSCR_MASK;
 201     if ((val & FPSCR_RM_MASK) == FPSCR_RM_ZERO) {
 202         set_float_rounding_mode(float_round_to_zero, &env->fp_status);
 203     } else {
 204         set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 205     }
 206     set_flush_to_zero((val & FPSCR_DN) != 0, &env->fp_status);
 207 }
 208
 209 static void update_fpscr(CPUSH4State *env, uintptr_t retaddr)
 210 {
 211     int xcpt, cause, enable;
 212
 213     xcpt = get_float_exception_flags(&env->fp_status);
 214
 215     /* Clear the flag entries */
 216     env->fpscr &= ~FPSCR_FLAG_MASK;
 217
 218     if (unlikely(xcpt)) {
 219         if (xcpt & float_flag_invalid) {
 220             env->fpscr |= FPSCR_FLAG_V;
 221         }
 222         if (xcpt & float_flag_divbyzero) {
 223             env->fpscr |= FPSCR_FLAG_Z;
 224         }
 225         if (xcpt & float_flag_overflow) {
 226             env->fpscr |= FPSCR_FLAG_O;
 227         }
 228         if (xcpt & float_flag_underflow) {
 229             env->fpscr |= FPSCR_FLAG_U;
 230         }
 231         if (xcpt & float_flag_inexact) {
 232             env->fpscr |= FPSCR_FLAG_I;
 233         }
 234
 235         /* Accumulate in cause entries */
 236         env->fpscr |= (env->fpscr & FPSCR_FLAG_MASK)
 237                       << (FPSCR_CAUSE_SHIFT - FPSCR_FLAG_SHIFT);
 238
 239         /* Generate an exception if enabled */
 240         cause = (env->fpscr & FPSCR_CAUSE_MASK) >> FPSCR_CAUSE_SHIFT;
 241         enable = (env->fpscr & FPSCR_ENABLE_MASK) >> FPSCR_ENABLE_SHIFT;
 242         if (cause & enable) {
 243             raise_exception(env, 0x120, retaddr);
 244         }
 245     }
 246 }
 247
 248 float32 helper_fabs_FT(float32 t0)
 249 {
 250     return float32_abs(t0);
 251 }
 252
 253 float64 helper_fabs_DT(float64 t0)
 254 {
 255     return float64_abs(t0);
 256 }
 257
 258 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1)
 259 {
 260     set_float_exception_flags(0, &env->fp_status);
 261     t0 = float32_add(t0, t1, &env->fp_status);
 262     update_fpscr(env, GETPC());
 263     return t0;
 264 }
 265
 266 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1)
 267 {
 268     set_float_exception_flags(0, &env->fp_status);
 269     t0 = float64_add(t0, t1, &env->fp_status);
 270     update_fpscr(env, GETPC());
 271     return t0;
 272 }
 273
 274 void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
 275 {
 276     int relation;
 277
 278     set_float_exception_flags(0, &env->fp_status);
 279     relation = float32_compare(t0, t1, &env->fp_status);
 280     if (unlikely(relation == float_relation_unordered)) {
 281         update_fpscr(env, GETPC());
 282     } else {
 283         env->sr_t = (relation == float_relation_equal);
 284     }
 285 }
 286
 287 void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
 288 {
 289     int relation;
 290
 291     set_float_exception_flags(0, &env->fp_status);
 292     relation = float64_compare(t0, t1, &env->fp_status);
 293     if (unlikely(relation == float_relation_unordered)) {
 294         update_fpscr(env, GETPC());
 295     } else {
 296         env->sr_t = (relation == float_relation_equal);
 297     }
 298 }
 299
 300 void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
 301 {
 302     int relation;
 303
 304     set_float_exception_flags(0, &env->fp_status);
 305     relation = float32_compare(t0, t1, &env->fp_status);
 306     if (unlikely(relation == float_relation_unordered)) {
 307         update_fpscr(env, GETPC());
 308     } else {
 309         env->sr_t = (relation == float_relation_greater);
 310     }
 311 }
 312
 313 void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
 314 {
 315     int relation;
 316
 317     set_float_exception_flags(0, &env->fp_status);
 318     relation = float64_compare(t0, t1, &env->fp_status);
 319     if (unlikely(relation == float_relation_unordered)) {
 320         update_fpscr(env, GETPC());
 321     } else {
 322         env->sr_t = (relation == float_relation_greater);
 323     }
 324 }
 325
 326 float64 helper_fcnvsd_FT_DT(CPUSH4State *env, float32 t0)
 327 {
 328     float64 ret;
 329     set_float_exception_flags(0, &env->fp_status);
 330     ret = float32_to_float64(t0, &env->fp_status);
 331     update_fpscr(env, GETPC());
 332     return ret;
 333 }
 334
 335 float32 helper_fcnvds_DT_FT(CPUSH4State *env, float64 t0)
 336 {
 337     float32 ret;
 338     set_float_exception_flags(0, &env->fp_status);
 339     ret = float64_to_float32(t0, &env->fp_status);
 340     update_fpscr(env, GETPC());
 341     return ret;
 342 }
 343
 344 float32 helper_fdiv_FT(CPUSH4State *env, float32 t0, float32 t1)
 345 {
 346     set_float_exception_flags(0, &env->fp_status);
 347     t0 = float32_div(t0, t1, &env->fp_status);
 348     update_fpscr(env, GETPC());
 349     return t0;
 350 }
 351
 352 float64 helper_fdiv_DT(CPUSH4State *env, float64 t0, float64 t1)
 353 {
 354     set_float_exception_flags(0, &env->fp_status);
 355     t0 = float64_div(t0, t1, &env->fp_status);
 356     update_fpscr(env, GETPC());
 357     return t0;
 358 }
 359
 360 float32 helper_float_FT(CPUSH4State *env, uint32_t t0)
 361 {
 362     float32 ret;
 363     set_float_exception_flags(0, &env->fp_status);
 364     ret = int32_to_float32(t0, &env->fp_status);
 365     update_fpscr(env, GETPC());
 366     return ret;
 367 }
 368
 369 float64 helper_float_DT(CPUSH4State *env, uint32_t t0)
 370 {
 371     float64 ret;
 372     set_float_exception_flags(0, &env->fp_status);
 373     ret = int32_to_float64(t0, &env->fp_status);
 374     update_fpscr(env, GETPC());
 375     return ret;
 376 }
 377
 378 float32 helper_fmac_FT(CPUSH4State *env, float32 t0, float32 t1, float32 t2)
 379 {
 380     set_float_exception_flags(0, &env->fp_status);
 381     t0 = float32_muladd(t0, t1, t2, 0, &env->fp_status);
 382     update_fpscr(env, GETPC());
 383     return t0;
 384 }
 385
 386 float32 helper_fmul_FT(CPUSH4State *env, float32 t0, float32 t1)
 387 {
 388     set_float_exception_flags(0, &env->fp_status);
 389     t0 = float32_mul(t0, t1, &env->fp_status);
 390     update_fpscr(env, GETPC());
 391     return t0;
 392 }
 393
 394 float64 helper_fmul_DT(CPUSH4State *env, float64 t0, float64 t1)
 395 {
 396     set_float_exception_flags(0, &env->fp_status);
 397     t0 = float64_mul(t0, t1, &env->fp_status);
 398     update_fpscr(env, GETPC());
 399     return t0;
 400 }
 401
 402 float32 helper_fneg_T(float32 t0)
 403 {
 404     return float32_chs(t0);
 405 }
 406
 407 float32 helper_fsqrt_FT(CPUSH4State *env, float32 t0)
 408 {
 409     set_float_exception_flags(0, &env->fp_status);
 410     t0 = float32_sqrt(t0, &env->fp_status);
 411     update_fpscr(env, GETPC());
 412     return t0;
 413 }
 414
 415 float64 helper_fsqrt_DT(CPUSH4State *env, float64 t0)
 416 {
 417     set_float_exception_flags(0, &env->fp_status);
 418     t0 = float64_sqrt(t0, &env->fp_status);
 419     update_fpscr(env, GETPC());
 420     return t0;
 421 }
 422
 423 float32 helper_fsub_FT(CPUSH4State *env, float32 t0, float32 t1)
 424 {
 425     set_float_exception_flags(0, &env->fp_status);
 426     t0 = float32_sub(t0, t1, &env->fp_status);
 427     update_fpscr(env, GETPC());
 428     return t0;
 429 }
 430
 431 float64 helper_fsub_DT(CPUSH4State *env, float64 t0, float64 t1)
 432 {
 433     set_float_exception_flags(0, &env->fp_status);
 434     t0 = float64_sub(t0, t1, &env->fp_status);
 435     update_fpscr(env, GETPC());
 436     return t0;
 437 }
 438
 439 uint32_t helper_ftrc_FT(CPUSH4State *env, float32 t0)
 440 {
 441     uint32_t ret;
 442     set_float_exception_flags(0, &env->fp_status);
 443     ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
 444     update_fpscr(env, GETPC());
 445     return ret;
 446 }
 447
 448 uint32_t helper_ftrc_DT(CPUSH4State *env, float64 t0)
 449 {
 450     uint32_t ret;
 451     set_float_exception_flags(0, &env->fp_status);
 452     ret = float64_to_int32_round_to_zero(t0, &env->fp_status);
 453     update_fpscr(env, GETPC());
 454     return ret;
 455 }
 456
 457 void helper_fipr(CPUSH4State *env, uint32_t m, uint32_t n)
 458 {
 459     int bank, i;
 460     float32 r, p;
 461
 462     bank = (env->sr & FPSCR_FR) ? 16 : 0;
 463     r = float32_zero;
 464     set_float_exception_flags(0, &env->fp_status);
 465
 466     for (i = 0 ; i < 4 ; i++) {
 467         p = float32_mul(env->fregs[bank + m + i],
 468                         env->fregs[bank + n + i],
 469                         &env->fp_status);
 470         r = float32_add(r, p, &env->fp_status);
 471     }
 472     update_fpscr(env, GETPC());
 473
 474     env->fregs[bank + n + 3] = r;
 475 }
 476
 477 void helper_ftrv(CPUSH4State *env, uint32_t n)
 478 {
 479     int bank_matrix, bank_vector;
 480     int i, j;
 481     float32 r[4];
 482     float32 p;
 483
 484     bank_matrix = (env->sr & FPSCR_FR) ? 0 : 16;
 485     bank_vector = (env->sr & FPSCR_FR) ? 16 : 0;
 486     set_float_exception_flags(0, &env->fp_status);
 487     for (i = 0 ; i < 4 ; i++) {
 488         r[i] = float32_zero;
 489         for (j = 0 ; j < 4 ; j++) {
 490             p = float32_mul(env->fregs[bank_matrix + 4 * j + i],
 491                             env->fregs[bank_vector + j],
 492                             &env->fp_status);
 493             r[i] = float32_add(r[i], p, &env->fp_status);
 494         }
 495     }
 496     update_fpscr(env, GETPC());
 497
 498     for (i = 0 ; i < 4 ; i++) {
 499         env->fregs[bank_vector + i] = r[i];
 500     }
 501 }