Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / include / hw / char / serial.h
blob8a21ee0f1c322b032befc54f32931b9c3d7ca45a
1 /*
2 * QEMU 16550A UART emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2008 Citrix Systems, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
26 #ifndef HW_SERIAL_H
27 #define HW_SERIAL_H
29 #include "hw/hw.h"
30 #include "sysemu/sysemu.h"
31 #include "exec/memory.h"
32 #include "qemu/fifo8.h"
34 #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
36 struct SerialState {
37 uint16_t divider;
38 uint8_t rbr; /* receive register */
39 uint8_t thr; /* transmit holding register */
40 uint8_t tsr; /* transmit shift register */
41 uint8_t ier;
42 uint8_t iir; /* read only */
43 uint8_t lcr;
44 uint8_t mcr;
45 uint8_t lsr; /* read only */
46 uint8_t msr; /* read only */
47 uint8_t scr;
48 uint8_t fcr;
49 uint8_t fcr_vmstate; /* we can't write directly this value
50 it has side effects */
51 /* NOTE: this hidden state is necessary for tx irq generation as
52 it can be reset while reading iir */
53 int thr_ipending;
54 qemu_irq irq;
55 CharDriverState *chr;
56 hwaddr base;
57 int last_break_enable;
58 int it_shift;
59 int baudbase;
60 uint32_t tsr_retry;
61 guint watch_tag;
62 uint32_t wakeup;
64 /* Time when the last byte was successfully sent out of the tsr */
65 uint64_t last_xmit_ts;
66 Fifo8 recv_fifo;
67 Fifo8 xmit_fifo;
68 /* Interrupt trigger level for recv_fifo */
69 uint8_t recv_fifo_itl;
71 QEMUTimer *fifo_timeout_timer;
72 int timeout_ipending; /* timeout interrupt pending state */
74 uint64_t char_transmit_time; /* time to transmit a char in ticks */
75 int poll_msl;
77 QEMUTimer *modem_status_poll;
78 MemoryRegion io;
81 extern const VMStateDescription vmstate_serial;
82 extern const MemoryRegionOps serial_io_ops;
84 void serial_realize_core(SerialState *s, Error **errp);
85 void serial_exit_core(SerialState *s);
86 void serial_set_frequency(SerialState *s, uint32_t frequency);
88 SerialState *serial_16550_init(int base, qemu_irq irq, CharDriverState *chr);
89 uint64_t serial_mm_read(void *opaque, hwaddr addr, unsigned size);
90 void serial_mm_write(void *opaque, hwaddr addr,
91 uint64_t value, unsigned size);
93 /* legacy pre qom */
94 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
95 CharDriverState *chr, MemoryRegion *system_io);
96 SerialState *serial_mm_init(MemoryRegion *address_space,
97 hwaddr base, int it_shift,
98 qemu_irq irq, int baudbase,
99 CharDriverState *chr, enum device_endian end);
101 /* serial-isa.c */
102 #define TYPE_ISA_SERIAL "isa-serial"
103 void serial_hds_isa_init(ISABus *bus, int n);
105 #endif