hw/arm/aspeed_soc.c

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/arm/aspeed_soc.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22
  23 #define ASPEED_SOC_UART_5_BASE      0x00184000
  24 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
  25 #define ASPEED_SOC_IOMEM_BASE       0x1E600000
  26 #define ASPEED_SOC_FMC_BASE         0x1E620000
  27 #define ASPEED_SOC_SPI_BASE         0x1E630000
  28 #define ASPEED_SOC_SPI2_BASE        0x1E631000
  29 #define ASPEED_SOC_VIC_BASE         0x1E6C0000
  30 #define ASPEED_SOC_SDMC_BASE        0x1E6E0000
  31 #define ASPEED_SOC_SCU_BASE         0x1E6E2000
  32 #define ASPEED_SOC_SRAM_BASE        0x1E720000
  33 #define ASPEED_SOC_TIMER_BASE       0x1E782000
  34 #define ASPEED_SOC_I2C_BASE         0x1E78A000
  35
  36 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  37 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  38
  39 #define AST2400_SDRAM_BASE       0x40000000
  40 #define AST2500_SDRAM_BASE       0x80000000
  41
  42 static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
  43 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
  44
  45 static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
  46                                                        ASPEED_SOC_SPI2_BASE};
  47 static const char *aspeed_soc_ast2500_typenames[] = {
  48     "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
  49
  50 static const AspeedSoCInfo aspeed_socs[] = {
  51     {
  52         .name         = "ast2400-a0",
  53         .cpu_model    = "arm926",
  54         .silicon_rev  = AST2400_A0_SILICON_REV,
  55         .sdram_base   = AST2400_SDRAM_BASE,
  56         .sram_size    = 0x8000,
  57         .spis_num     = 1,
  58         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  59         .fmc_typename = "aspeed.smc.fmc",
  60         .spi_typename = aspeed_soc_ast2400_typenames,
  61     }, {
  62         .name         = "ast2400",
  63         .cpu_model    = "arm926",
  64         .silicon_rev  = AST2400_A0_SILICON_REV,
  65         .sdram_base   = AST2400_SDRAM_BASE,
  66         .sram_size    = 0x8000,
  67         .spis_num     = 1,
  68         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  69         .fmc_typename = "aspeed.smc.fmc",
  70         .spi_typename = aspeed_soc_ast2400_typenames,
  71     }, {
  72         .name         = "ast2500-a1",
  73         .cpu_model    = "arm1176",
  74         .silicon_rev  = AST2500_A1_SILICON_REV,
  75         .sdram_base   = AST2500_SDRAM_BASE,
  76         .sram_size    = 0x9000,
  77         .spis_num     = 2,
  78         .spi_bases    = aspeed_soc_ast2500_spi_bases,
  79         .fmc_typename = "aspeed.smc.ast2500-fmc",
  80         .spi_typename = aspeed_soc_ast2500_typenames,
  81     },
  82 };
  83
  84 /*
  85  * IO handlers: simply catch any reads/writes to IO addresses that aren't
  86  * handled by a device mapping.
  87  */
  88
  89 static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
  90 {
  91     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
  92                   __func__, offset, size);
  93     return 0;
  94 }
  95
  96 static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
  97                 unsigned size)
  98 {
  99     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
 100                   __func__, offset, value, size);
 101 }
 102
 103 static const MemoryRegionOps aspeed_soc_io_ops = {
 104     .read = aspeed_soc_io_read,
 105     .write = aspeed_soc_io_write,
 106     .endianness = DEVICE_LITTLE_ENDIAN,
 107 };
 108
 109 static void aspeed_soc_init(Object *obj)
 110 {
 111     AspeedSoCState *s = ASPEED_SOC(obj);
 112     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 113     char *cpu_typename;
 114     int i;
 115
 116     cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);
 117     object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);
 118     object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
 119     g_free(cpu_typename);
 120
 121     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
 122     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
 123     qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
 124
 125     object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
 126     object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
 127     qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
 128
 129     object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
 130     object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
 131     qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
 132
 133     object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
 134     object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
 135     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
 136     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
 137                          sc->info->silicon_rev);
 138     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
 139                               "hw-strap1", &error_abort);
 140     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
 141                               "hw-strap2", &error_abort);
 142
 143     object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
 144     object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
 145     qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
 146
 147     for (i = 0; i < sc->info->spis_num; i++) {
 148         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 149                           sc->info->spi_typename[i]);
 150         object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);
 151         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 152     }
 153
 154     object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
 155     object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
 156     qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
 157     qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
 158                          sc->info->silicon_rev);
 159     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
 160                               "ram-size", &error_abort);
 161 }
 162
 163 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 164 {
 165     int i;
 166     AspeedSoCState *s = ASPEED_SOC(dev);
 167     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 168     Error *err = NULL, *local_err = NULL;
 169
 170     /* IO space */
 171     memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
 172             "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
 173     memory_region_add_subregion_overlap(get_system_memory(),
 174                                         ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
 175
 176     /* CPU */
 177     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
 178     if (err) {
 179         error_propagate(errp, err);
 180         return;
 181     }
 182
 183     /* SRAM */
 184     memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
 185                            sc->info->sram_size, &err);
 186     if (err) {
 187         error_propagate(errp, err);
 188         return;
 189     }
 190     vmstate_register_ram_global(&s->sram);
 191     memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
 192                                 &s->sram);
 193
 194     /* VIC */
 195     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
 196     if (err) {
 197         error_propagate(errp, err);
 198         return;
 199     }
 200     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
 201     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 202                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 203     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 204                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 205
 206     /* Timer */
 207     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 208     if (err) {
 209         error_propagate(errp, err);
 210         return;
 211     }
 212     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
 213     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 214         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 215         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 216     }
 217
 218     /* SCU */
 219     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
 220     if (err) {
 221         error_propagate(errp, err);
 222         return;
 223     }
 224     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
 225
 226     /* UART - attach an 8250 to the IO space as our UART5 */
 227     if (serial_hds[0]) {
 228         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 229         serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
 230                        uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
 231     }
 232
 233     /* I2C */
 234     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 235     if (err) {
 236         error_propagate(errp, err);
 237         return;
 238     }
 239     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
 240     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 241                        qdev_get_gpio_in(DEVICE(&s->vic), 12));
 242
 243     /* FMC */
 244     object_property_set_int(OBJECT(&s->fmc), 1, "num-cs", &err);
 245     object_property_set_bool(OBJECT(&s->fmc), true, "realized", &local_err);
 246     error_propagate(&err, local_err);
 247     if (err) {
 248         error_propagate(errp, err);
 249         return;
 250     }
 251     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
 252     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
 253                     s->fmc.ctrl->flash_window_base);
 254     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
 255                        qdev_get_gpio_in(DEVICE(&s->vic), 19));
 256
 257     /* SPI */
 258     for (i = 0; i < sc->info->spis_num; i++) {
 259         object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
 260         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 261                                  &local_err);
 262         error_propagate(&err, local_err);
 263         if (err) {
 264             error_propagate(errp, err);
 265             return;
 266         }
 267         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
 268         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
 269                         s->spi[i].ctrl->flash_window_base);
 270     }
 271
 272     /* SDMC - SDRAM Memory Controller */
 273     object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
 274     if (err) {
 275         error_propagate(errp, err);
 276         return;
 277     }
 278     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
 279 }
 280
 281 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 282 {
 283     DeviceClass *dc = DEVICE_CLASS(oc);
 284     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 285
 286     sc->info = (AspeedSoCInfo *) data;
 287     dc->realize = aspeed_soc_realize;
 288 }
 289
 290 static const TypeInfo aspeed_soc_type_info = {
 291     .name           = TYPE_ASPEED_SOC,
 292     .parent         = TYPE_DEVICE,
 293     .instance_init  = aspeed_soc_init,
 294     .instance_size  = sizeof(AspeedSoCState),
 295     .class_size     = sizeof(AspeedSoCClass),
 296     .abstract       = true,
 297 };
 298
 299 static void aspeed_soc_register_types(void)
 300 {
 301     int i;
 302
 303     type_register_static(&aspeed_soc_type_info);
 304     for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
 305         TypeInfo ti = {
 306             .name       = aspeed_socs[i].name,
 307             .parent     = TYPE_ASPEED_SOC,
 308             .class_init = aspeed_soc_class_init,
 309             .class_data = (void *) &aspeed_socs[i],
 310         };
 311         type_register(&ti);
 312     }
 313 }
 314
 315 type_init(aspeed_soc_register_types)