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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / target / i386 / kvm.c
blob3a58b1a5c2571c120d658a2576b5b0b3001ea89d
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "exec/ioport.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "migration/blocker.h"
48 #include "exec/memattrs.h"
49 #include "trace.h"
50
51 //#define DEBUG_KVM
52
53 #ifdef DEBUG_KVM
54 #define DPRINTF(fmt, ...) \
55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF(fmt, ...) \
58 do { } while (0)
59 #endif
60
61 #define MSR_KVM_WALL_CLOCK 0x11
62 #define MSR_KVM_SYSTEM_TIME 0x12
63
64 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66 #define MSR_BUF_SIZE 4096
67
68 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73 };
74
75 static bool has_msr_star;
76 static bool has_msr_hsave_pa;
77 static bool has_msr_tsc_aux;
78 static bool has_msr_tsc_adjust;
79 static bool has_msr_tsc_deadline;
80 static bool has_msr_feature_control;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static int lm_capable_kernel;
85 static bool has_msr_hv_hypercall;
86 static bool has_msr_hv_crash;
87 static bool has_msr_hv_reset;
88 static bool has_msr_hv_vpindex;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_xss;
94
95 static bool has_msr_architectural_pmu;
96 static uint32_t num_architectural_pmu_counters;
97
98 static int has_xsave;
99 static int has_xcrs;
100 static int has_pit_state2;
101
102 static bool has_msr_mcg_ext_ctl;
103
104 static struct kvm_cpuid2 *cpuid_cache;
105
106 int kvm_has_pit_state2(void)
107 {
108 return has_pit_state2;
109 }
110
111 bool kvm_has_smm(void)
112 {
113 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
114 }
115
116 bool kvm_has_adjust_clock_stable(void)
117 {
118 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
119
120 return (ret == KVM_CLOCK_TSC_STABLE);
121 }
122
123 bool kvm_allows_irq0_override(void)
124 {
125 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
126 }
127
128 static bool kvm_x2apic_api_set_flags(uint64_t flags)
129 {
130 KVMState *s = KVM_STATE(current_machine->accelerator);
131
132 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
133 }
134
135 #define MEMORIZE(fn, _result) \
136 ({ \
137 static bool _memorized; \
138 \
139 if (_memorized) { \
140 return _result; \
141 } \
142 _memorized = true; \
143 _result = fn; \
144 })
145
146 static bool has_x2apic_api;
147
148 bool kvm_has_x2apic_api(void)
149 {
150 return has_x2apic_api;
151 }
152
153 bool kvm_enable_x2apic(void)
154 {
155 return MEMORIZE(
156 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
157 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
158 has_x2apic_api);
159 }
160
161 static int kvm_get_tsc(CPUState *cs)
162 {
163 X86CPU *cpu = X86_CPU(cs);
164 CPUX86State *env = &cpu->env;
165 struct {
166 struct kvm_msrs info;
167 struct kvm_msr_entry entries[1];
168 } msr_data;
169 int ret;
170
171 if (env->tsc_valid) {
172 return 0;
173 }
174
175 msr_data.info.nmsrs = 1;
176 msr_data.entries[0].index = MSR_IA32_TSC;
177 env->tsc_valid = !runstate_is_running();
178
179 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
180 if (ret < 0) {
181 return ret;
182 }
183
184 assert(ret == 1);
185 env->tsc = msr_data.entries[0].data;
186 return 0;
187 }
188
189 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
190 {
191 kvm_get_tsc(cpu);
192 }
193
194 void kvm_synchronize_all_tsc(void)
195 {
196 CPUState *cpu;
197
198 if (kvm_enabled()) {
199 CPU_FOREACH(cpu) {
200 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
201 }
202 }
203 }
204
205 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
206 {
207 struct kvm_cpuid2 *cpuid;
208 int r, size;
209
210 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
211 cpuid = g_malloc0(size);
212 cpuid->nent = max;
213 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
214 if (r == 0 && cpuid->nent >= max) {
215 r = -E2BIG;
216 }
217 if (r < 0) {
218 if (r == -E2BIG) {
219 g_free(cpuid);
220 return NULL;
221 } else {
222 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
223 strerror(-r));
224 exit(1);
225 }
226 }
227 return cpuid;
228 }
229
230 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
231 * for all entries.
232 */
233 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
234 {
235 struct kvm_cpuid2 *cpuid;
236 int max = 1;
237
238 if (cpuid_cache != NULL) {
239 return cpuid_cache;
240 }
241 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
242 max *= 2;
243 }
244 cpuid_cache = cpuid;
245 return cpuid;
246 }
247
248 static const struct kvm_para_features {
249 int cap;
250 int feature;
251 } para_features[] = {
252 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
253 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
254 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
255 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
256 };
257
258 static int get_para_features(KVMState *s)
259 {
260 int i, features = 0;
261
262 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
263 if (kvm_check_extension(s, para_features[i].cap)) {
264 features |= (1 << para_features[i].feature);
265 }
266 }
267
268 return features;
269 }
270
271 static bool host_tsx_blacklisted(void)
272 {
273 int family, model, stepping;\
274 char vendor[CPUID_VENDOR_SZ + 1];
275
276 host_vendor_fms(vendor, &family, &model, &stepping);
277
278 /* Check if we are running on a Haswell host known to have broken TSX */
279 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
280 (family == 6) &&
281 ((model == 63 && stepping < 4) ||
282 model == 60 || model == 69 || model == 70);
283 }
284
285 /* Returns the value for a specific register on the cpuid entry
286 */
287 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
288 {
289 uint32_t ret = 0;
290 switch (reg) {
291 case R_EAX:
292 ret = entry->eax;
293 break;
294 case R_EBX:
295 ret = entry->ebx;
296 break;
297 case R_ECX:
298 ret = entry->ecx;
299 break;
300 case R_EDX:
301 ret = entry->edx;
302 break;
303 }
304 return ret;
305 }
306
307 /* Find matching entry for function/index on kvm_cpuid2 struct
308 */
309 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
310 uint32_t function,
311 uint32_t index)
312 {
313 int i;
314 for (i = 0; i < cpuid->nent; ++i) {
315 if (cpuid->entries[i].function == function &&
316 cpuid->entries[i].index == index) {
317 return &cpuid->entries[i];
318 }
319 }
320 /* not found: */
321 return NULL;
322 }
323
324 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
325 uint32_t index, int reg)
326 {
327 struct kvm_cpuid2 *cpuid;
328 uint32_t ret = 0;
329 uint32_t cpuid_1_edx;
330 bool found = false;
331
332 cpuid = get_supported_cpuid(s);
333
334 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
335 if (entry) {
336 found = true;
337 ret = cpuid_entry_get_reg(entry, reg);
338 }
339
340 /* Fixups for the data returned by KVM, below */
341
342 if (function == 1 && reg == R_EDX) {
343 /* KVM before 2.6.30 misreports the following features */
344 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
345 } else if (function == 1 && reg == R_ECX) {
346 /* We can set the hypervisor flag, even if KVM does not return it on
347 * GET_SUPPORTED_CPUID
348 */
349 ret |= CPUID_EXT_HYPERVISOR;
350 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
351 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
352 * and the irqchip is in the kernel.
353 */
354 if (kvm_irqchip_in_kernel() &&
355 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
356 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
357 }
358
359 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
360 * without the in-kernel irqchip
361 */
362 if (!kvm_irqchip_in_kernel()) {
363 ret &= ~CPUID_EXT_X2APIC;
364 }
365 } else if (function == 6 && reg == R_EAX) {
366 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
367 } else if (function == 7 && index == 0 && reg == R_EBX) {
368 if (host_tsx_blacklisted()) {
369 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
370 }
371 } else if (function == 0x80000001 && reg == R_EDX) {
372 /* On Intel, kvm returns cpuid according to the Intel spec,
373 * so add missing bits according to the AMD spec:
374 */
375 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
376 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
377 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
378 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
379 * be enabled without the in-kernel irqchip
380 */
381 if (!kvm_irqchip_in_kernel()) {
382 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
383 }
384 }
385
386 /* fallback for older kernels */
387 if ((function == KVM_CPUID_FEATURES) && !found) {
388 ret = get_para_features(s);
389 }
390
391 return ret;
392 }
393
394 typedef struct HWPoisonPage {
395 ram_addr_t ram_addr;
396 QLIST_ENTRY(HWPoisonPage) list;
397 } HWPoisonPage;
398
399 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
400 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
401
402 static void kvm_unpoison_all(void *param)
403 {
404 HWPoisonPage *page, *next_page;
405
406 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
407 QLIST_REMOVE(page, list);
408 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
409 g_free(page);
410 }
411 }
412
413 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
414 {
415 HWPoisonPage *page;
416
417 QLIST_FOREACH(page, &hwpoison_page_list, list) {
418 if (page->ram_addr == ram_addr) {
419 return;
420 }
421 }
422 page = g_new(HWPoisonPage, 1);
423 page->ram_addr = ram_addr;
424 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
425 }
426
427 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
428 int *max_banks)
429 {
430 int r;
431
432 r = kvm_check_extension(s, KVM_CAP_MCE);
433 if (r > 0) {
434 *max_banks = r;
435 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
436 }
437 return -ENOSYS;
438 }
439
440 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
441 {
442 CPUState *cs = CPU(cpu);
443 CPUX86State *env = &cpu->env;
444 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
445 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
446 uint64_t mcg_status = MCG_STATUS_MCIP;
447 int flags = 0;
448
449 if (code == BUS_MCEERR_AR) {
450 status |= MCI_STATUS_AR | 0x134;
451 mcg_status |= MCG_STATUS_EIPV;
452 } else {
453 status |= 0xc0;
454 mcg_status |= MCG_STATUS_RIPV;
455 }
456
457 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
458 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
459 * guest kernel back into env->mcg_ext_ctl.
460 */
461 cpu_synchronize_state(cs);
462 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
463 mcg_status |= MCG_STATUS_LMCE;
464 flags = 0;
465 }
466
467 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
468 (MCM_ADDR_PHYS << 6) | 0xc, flags);
469 }
470
471 static void hardware_memory_error(void)
472 {
473 fprintf(stderr, "Hardware memory error!\n");
474 exit(1);
475 }
476
477 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
478 {
479 X86CPU *cpu = X86_CPU(c);
480 CPUX86State *env = &cpu->env;
481 ram_addr_t ram_addr;
482 hwaddr paddr;
483
484 /* If we get an action required MCE, it has been injected by KVM
485 * while the VM was running. An action optional MCE instead should
486 * be coming from the main thread, which qemu_init_sigbus identifies
487 * as the "early kill" thread.
488 */
489 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
490
491 if ((env->mcg_cap & MCG_SER_P) && addr) {
492 ram_addr = qemu_ram_addr_from_host(addr);
493 if (ram_addr != RAM_ADDR_INVALID &&
494 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
495 kvm_hwpoison_page_add(ram_addr);
496 kvm_mce_inject(cpu, paddr, code);
497 return;
498 }
499
500 fprintf(stderr, "Hardware memory error for memory used by "
501 "QEMU itself instead of guest system!\n");
502 }
503
504 if (code == BUS_MCEERR_AR) {
505 hardware_memory_error();
506 }
507
508 /* Hope we are lucky for AO MCE */
509 }
510
511 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
512 {
513 CPUX86State *env = &cpu->env;
514
515 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
516 unsigned int bank, bank_num = env->mcg_cap & 0xff;
517 struct kvm_x86_mce mce;
518
519 env->exception_injected = -1;
520
521 /*
522 * There must be at least one bank in use if an MCE is pending.
523 * Find it and use its values for the event injection.
524 */
525 for (bank = 0; bank < bank_num; bank++) {
526 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
527 break;
528 }
529 }
530 assert(bank < bank_num);
531
532 mce.bank = bank;
533 mce.status = env->mce_banks[bank * 4 + 1];
534 mce.mcg_status = env->mcg_status;
535 mce.addr = env->mce_banks[bank * 4 + 2];
536 mce.misc = env->mce_banks[bank * 4 + 3];
537
538 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
539 }
540 return 0;
541 }
542
543 static void cpu_update_state(void *opaque, int running, RunState state)
544 {
545 CPUX86State *env = opaque;
546
547 if (running) {
548 env->tsc_valid = false;
549 }
550 }
551
552 unsigned long kvm_arch_vcpu_id(CPUState *cs)
553 {
554 X86CPU *cpu = X86_CPU(cs);
555 return cpu->apic_id;
556 }
557
558 #ifndef KVM_CPUID_SIGNATURE_NEXT
559 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
560 #endif
561
562 static bool hyperv_hypercall_available(X86CPU *cpu)
563 {
564 return cpu->hyperv_vapic ||
565 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
566 }
567
568 static bool hyperv_enabled(X86CPU *cpu)
569 {
570 CPUState *cs = CPU(cpu);
571 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
572 (hyperv_hypercall_available(cpu) ||
573 cpu->hyperv_time ||
574 cpu->hyperv_relaxed_timing ||
575 cpu->hyperv_crash ||
576 cpu->hyperv_reset ||
577 cpu->hyperv_vpindex ||
578 cpu->hyperv_runtime ||
579 cpu->hyperv_synic ||
580 cpu->hyperv_stimer);
581 }
582
583 static int kvm_arch_set_tsc_khz(CPUState *cs)
584 {
585 X86CPU *cpu = X86_CPU(cs);
586 CPUX86State *env = &cpu->env;
587 int r;
588
589 if (!env->tsc_khz) {
590 return 0;
591 }
592
593 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
594 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
595 -ENOTSUP;
596 if (r < 0) {
597 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
598 * TSC frequency doesn't match the one we want.
599 */
600 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
601 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
602 -ENOTSUP;
603 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
604 warn_report("TSC frequency mismatch between "
605 "VM (%" PRId64 " kHz) and host (%d kHz), "
606 "and TSC scaling unavailable",
607 env->tsc_khz, cur_freq);
608 return r;
609 }
610 }
611
612 return 0;
613 }
614
615 static bool tsc_is_stable_and_known(CPUX86State *env)
616 {
617 if (!env->tsc_khz) {
618 return false;
619 }
620 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
621 || env->user_tsc_khz;
622 }
623
624 static int hyperv_handle_properties(CPUState *cs)
625 {
626 X86CPU *cpu = X86_CPU(cs);
627 CPUX86State *env = &cpu->env;
628
629 if (cpu->hyperv_time &&
630 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
631 cpu->hyperv_time = false;
632 }
633
634 if (cpu->hyperv_relaxed_timing) {
635 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
636 }
637 if (cpu->hyperv_vapic) {
638 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
639 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
640 }
641 if (cpu->hyperv_time) {
642 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
643 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
644 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
645
646 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
647 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
648 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
649 }
650 }
651 if (cpu->hyperv_crash && has_msr_hv_crash) {
652 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
653 }
654 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
655 if (cpu->hyperv_reset && has_msr_hv_reset) {
656 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
657 }
658 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
659 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
660 }
661 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
662 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
663 }
664 if (cpu->hyperv_synic) {
665 int sint;
666
667 if (!has_msr_hv_synic ||
668 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
669 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
670 return -ENOSYS;
671 }
672
673 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
674 env->msr_hv_synic_version = HV_SYNIC_VERSION;
675 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
676 env->msr_hv_synic_sint[sint] = HV_SINT_MASKED;
677 }
678 }
679 if (cpu->hyperv_stimer) {
680 if (!has_msr_hv_stimer) {
681 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
682 return -ENOSYS;
683 }
684 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
685 }
686 return 0;
687 }
688
689 static Error *invtsc_mig_blocker;
690
691 #define KVM_MAX_CPUID_ENTRIES 100
692
693 int kvm_arch_init_vcpu(CPUState *cs)
694 {
695 struct {
696 struct kvm_cpuid2 cpuid;
697 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
698 } QEMU_PACKED cpuid_data;
699 X86CPU *cpu = X86_CPU(cs);
700 CPUX86State *env = &cpu->env;
701 uint32_t limit, i, j, cpuid_i;
702 uint32_t unused;
703 struct kvm_cpuid_entry2 *c;
704 uint32_t signature[3];
705 int kvm_base = KVM_CPUID_SIGNATURE;
706 int r;
707 Error *local_err = NULL;
708
709 memset(&cpuid_data, 0, sizeof(cpuid_data));
710
711 cpuid_i = 0;
712
713 r = kvm_arch_set_tsc_khz(cs);
714 if (r < 0) {
715 goto fail;
716 }
717
718 /* vcpu's TSC frequency is either specified by user, or following
719 * the value used by KVM if the former is not present. In the
720 * latter case, we query it from KVM and record in env->tsc_khz,
721 * so that vcpu's TSC frequency can be migrated later via this field.
722 */
723 if (!env->tsc_khz) {
724 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
725 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
726 -ENOTSUP;
727 if (r > 0) {
728 env->tsc_khz = r;
729 }
730 }
731
732 /* Paravirtualization CPUIDs */
733 if (hyperv_enabled(cpu)) {
734 c = &cpuid_data.entries[cpuid_i++];
735 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
736 if (!cpu->hyperv_vendor_id) {
737 memcpy(signature, "Microsoft Hv", 12);
738 } else {
739 size_t len = strlen(cpu->hyperv_vendor_id);
740
741 if (len > 12) {
742 error_report("hv-vendor-id truncated to 12 characters");
743 len = 12;
744 }
745 memset(signature, 0, 12);
746 memcpy(signature, cpu->hyperv_vendor_id, len);
747 }
748 c->eax = HV_CPUID_MIN;
749 c->ebx = signature[0];
750 c->ecx = signature[1];
751 c->edx = signature[2];
752
753 c = &cpuid_data.entries[cpuid_i++];
754 c->function = HV_CPUID_INTERFACE;
755 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
756 c->eax = signature[0];
757 c->ebx = 0;
758 c->ecx = 0;
759 c->edx = 0;
760
761 c = &cpuid_data.entries[cpuid_i++];
762 c->function = HV_CPUID_VERSION;
763 c->eax = 0x00001bbc;
764 c->ebx = 0x00060001;
765
766 c = &cpuid_data.entries[cpuid_i++];
767 c->function = HV_CPUID_FEATURES;
768 r = hyperv_handle_properties(cs);
769 if (r) {
770 return r;
771 }
772 c->eax = env->features[FEAT_HYPERV_EAX];
773 c->ebx = env->features[FEAT_HYPERV_EBX];
774 c->edx = env->features[FEAT_HYPERV_EDX];
775
776 c = &cpuid_data.entries[cpuid_i++];
777 c->function = HV_CPUID_ENLIGHTMENT_INFO;
778 if (cpu->hyperv_relaxed_timing) {
779 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
780 }
781 if (cpu->hyperv_vapic) {
782 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
783 }
784 c->ebx = cpu->hyperv_spinlock_attempts;
785
786 c = &cpuid_data.entries[cpuid_i++];
787 c->function = HV_CPUID_IMPLEMENT_LIMITS;
788
789 c->eax = cpu->hv_max_vps;
790 c->ebx = 0x40;
791
792 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
793 has_msr_hv_hypercall = true;
794 }
795
796 if (cpu->expose_kvm) {
797 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
798 c = &cpuid_data.entries[cpuid_i++];
799 c->function = KVM_CPUID_SIGNATURE | kvm_base;
800 c->eax = KVM_CPUID_FEATURES | kvm_base;
801 c->ebx = signature[0];
802 c->ecx = signature[1];
803 c->edx = signature[2];
804
805 c = &cpuid_data.entries[cpuid_i++];
806 c->function = KVM_CPUID_FEATURES | kvm_base;
807 c->eax = env->features[FEAT_KVM];
808 }
809
810 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
811
812 for (i = 0; i <= limit; i++) {
813 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
814 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
815 abort();
816 }
817 c = &cpuid_data.entries[cpuid_i++];
818 assert(cpuid_i < 100);
819
820 switch (i) {
821 case 2: {
822 /* Keep reading function 2 till all the input is received */
823 int times;
824
825 c->function = i;
826 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
827 KVM_CPUID_FLAG_STATE_READ_NEXT;
828 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
829 times = c->eax & 0xff;
830
831 for (j = 1; j < times; ++j) {
832 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
833 fprintf(stderr, "cpuid_data is full, no space for "
834 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
835 abort();
836 }
837 c = &cpuid_data.entries[cpuid_i++];
838 c->function = i;
839 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
840 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
841 }
842 break;
843 }
844 case 4:
845 case 0xb:
846 case 0xd:
847 for (j = 0; ; j++) {
848 if (i == 0xd && j == 64) {
849 break;
850 }
851 c->function = i;
852 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
853 c->index = j;
854 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
855
856 if (i == 4 && c->eax == 0) {
857 break;
858 }
859 if (i == 0xb && !(c->ecx & 0xff00)) {
860 break;
861 }
862 if (i == 0xd && c->eax == 0) {
863 continue;
864 }
865 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
866 fprintf(stderr, "cpuid_data is full, no space for "
867 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
868 abort();
869 }
870 c = &cpuid_data.entries[cpuid_i++];
871 }
872 break;
873 default:
874 c->function = i;
875 c->flags = 0;
876 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
877 break;
878 }
879 }
880
881 if (limit >= 0x0a) {
882 uint32_t ver;
883
884 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
885 if ((ver & 0xff) > 0) {
886 has_msr_architectural_pmu = true;
887 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
888
889 /* Shouldn't be more than 32, since that's the number of bits
890 * available in EBX to tell us _which_ counters are available.
891 * Play it safe.
892 */
893 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
894 num_architectural_pmu_counters = MAX_GP_COUNTERS;
895 }
896 }
897 }
898
899 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
900
901 for (i = 0x80000000; i <= limit; i++) {
902 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
903 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
904 abort();
905 }
906 c = &cpuid_data.entries[cpuid_i++];
907 assert(cpuid_i < 100);
908
909 c->function = i;
910 c->flags = 0;
911 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
912 }
913
914 /* Call Centaur's CPUID instructions they are supported. */
915 if (env->cpuid_xlevel2 > 0) {
916 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
917
918 for (i = 0xC0000000; i <= limit; i++) {
919 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
920 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
921 abort();
922 }
923 c = &cpuid_data.entries[cpuid_i++];
924
925 c->function = i;
926 c->flags = 0;
927 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
928 }
929 }
930
931 cpuid_data.cpuid.nent = cpuid_i;
932
933 if (((env->cpuid_version >> 8)&0xF) >= 6
934 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
935 (CPUID_MCE | CPUID_MCA)
936 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
937 uint64_t mcg_cap, unsupported_caps;
938 int banks;
939 int ret;
940
941 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
942 if (ret < 0) {
943 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
944 return ret;
945 }
946
947 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
948 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
949 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
950 return -ENOTSUP;
951 }
952
953 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
954 if (unsupported_caps) {
955 if (unsupported_caps & MCG_LMCE_P) {
956 error_report("kvm: LMCE not supported");
957 return -ENOTSUP;
958 }
959 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
960 unsupported_caps);
961 }
962
963 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
964 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
965 if (ret < 0) {
966 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
967 return ret;
968 }
969 }
970
971 qemu_add_vm_change_state_handler(cpu_update_state, env);
972
973 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
974 if (c) {
975 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
976 !!(c->ecx & CPUID_EXT_SMX);
977 }
978
979 if (env->mcg_cap & MCG_LMCE_P) {
980 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
981 }
982
983 if (!env->user_tsc_khz) {
984 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
985 invtsc_mig_blocker == NULL) {
986 /* for migration */
987 error_setg(&invtsc_mig_blocker,
988 "State blocked by non-migratable CPU device"
989 " (invtsc flag)");
990 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
991 if (local_err) {
992 error_report_err(local_err);
993 error_free(invtsc_mig_blocker);
994 goto fail;
995 }
996 /* for savevm */
997 vmstate_x86_cpu.unmigratable = 1;
998 }
999 }
1000
1001 if (cpu->vmware_cpuid_freq
1002 /* Guests depend on 0x40000000 to detect this feature, so only expose
1003 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1004 && cpu->expose_kvm
1005 && kvm_base == KVM_CPUID_SIGNATURE
1006 /* TSC clock must be stable and known for this feature. */
1007 && tsc_is_stable_and_known(env)) {
1008
1009 c = &cpuid_data.entries[cpuid_i++];
1010 c->function = KVM_CPUID_SIGNATURE | 0x10;
1011 c->eax = env->tsc_khz;
1012 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1013 * APIC_BUS_CYCLE_NS */
1014 c->ebx = 1000000;
1015 c->ecx = c->edx = 0;
1016
1017 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1018 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1019 }
1020
1021 cpuid_data.cpuid.nent = cpuid_i;
1022
1023 cpuid_data.cpuid.padding = 0;
1024 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1025 if (r) {
1026 goto fail;
1027 }
1028
1029 if (has_xsave) {
1030 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1031 }
1032 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1033
1034 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1035 has_msr_tsc_aux = false;
1036 }
1037
1038 return 0;
1039
1040 fail:
1041 migrate_del_blocker(invtsc_mig_blocker);
1042 return r;
1043 }
1044
1045 void kvm_arch_reset_vcpu(X86CPU *cpu)
1046 {
1047 CPUX86State *env = &cpu->env;
1048
1049 env->exception_injected = -1;
1050 env->interrupt_injected = -1;
1051 env->xcr0 = 1;
1052 if (kvm_irqchip_in_kernel()) {
1053 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1054 KVM_MP_STATE_UNINITIALIZED;
1055 } else {
1056 env->mp_state = KVM_MP_STATE_RUNNABLE;
1057 }
1058 }
1059
1060 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1061 {
1062 CPUX86State *env = &cpu->env;
1063
1064 /* APs get directly into wait-for-SIPI state. */
1065 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1066 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1067 }
1068 }
1069
1070 static int kvm_get_supported_msrs(KVMState *s)
1071 {
1072 static int kvm_supported_msrs;
1073 int ret = 0;
1074
1075 /* first time */
1076 if (kvm_supported_msrs == 0) {
1077 struct kvm_msr_list msr_list, *kvm_msr_list;
1078
1079 kvm_supported_msrs = -1;
1080
1081 /* Obtain MSR list from KVM. These are the MSRs that we must
1082 * save/restore */
1083 msr_list.nmsrs = 0;
1084 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1085 if (ret < 0 && ret != -E2BIG) {
1086 return ret;
1087 }
1088 /* Old kernel modules had a bug and could write beyond the provided
1089 memory. Allocate at least a safe amount of 1K. */
1090 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1091 msr_list.nmsrs *
1092 sizeof(msr_list.indices[0])));
1093
1094 kvm_msr_list->nmsrs = msr_list.nmsrs;
1095 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1096 if (ret >= 0) {
1097 int i;
1098
1099 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1100 switch (kvm_msr_list->indices[i]) {
1101 case MSR_STAR:
1102 has_msr_star = true;
1103 break;
1104 case MSR_VM_HSAVE_PA:
1105 has_msr_hsave_pa = true;
1106 break;
1107 case MSR_TSC_AUX:
1108 has_msr_tsc_aux = true;
1109 break;
1110 case MSR_TSC_ADJUST:
1111 has_msr_tsc_adjust = true;
1112 break;
1113 case MSR_IA32_TSCDEADLINE:
1114 has_msr_tsc_deadline = true;
1115 break;
1116 case MSR_IA32_SMBASE:
1117 has_msr_smbase = true;
1118 break;
1119 case MSR_IA32_MISC_ENABLE:
1120 has_msr_misc_enable = true;
1121 break;
1122 case MSR_IA32_BNDCFGS:
1123 has_msr_bndcfgs = true;
1124 break;
1125 case MSR_IA32_XSS:
1126 has_msr_xss = true;
1127 break;
1128 case HV_X64_MSR_CRASH_CTL:
1129 has_msr_hv_crash = true;
1130 break;
1131 case HV_X64_MSR_RESET:
1132 has_msr_hv_reset = true;
1133 break;
1134 case HV_X64_MSR_VP_INDEX:
1135 has_msr_hv_vpindex = true;
1136 break;
1137 case HV_X64_MSR_VP_RUNTIME:
1138 has_msr_hv_runtime = true;
1139 break;
1140 case HV_X64_MSR_SCONTROL:
1141 has_msr_hv_synic = true;
1142 break;
1143 case HV_X64_MSR_STIMER0_CONFIG:
1144 has_msr_hv_stimer = true;
1145 break;
1146 case HV_X64_MSR_TSC_FREQUENCY:
1147 has_msr_hv_frequencies = true;
1148 break;
1149 }
1150 }
1151 }
1152
1153 g_free(kvm_msr_list);
1154 }
1155
1156 return ret;
1157 }
1158
1159 static Notifier smram_machine_done;
1160 static KVMMemoryListener smram_listener;
1161 static AddressSpace smram_address_space;
1162 static MemoryRegion smram_as_root;
1163 static MemoryRegion smram_as_mem;
1164
1165 static void register_smram_listener(Notifier *n, void *unused)
1166 {
1167 MemoryRegion *smram =
1168 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1169
1170 /* Outer container... */
1171 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1172 memory_region_set_enabled(&smram_as_root, true);
1173
1174 /* ... with two regions inside: normal system memory with low
1175 * priority, and...
1176 */
1177 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1178 get_system_memory(), 0, ~0ull);
1179 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1180 memory_region_set_enabled(&smram_as_mem, true);
1181
1182 if (smram) {
1183 /* ... SMRAM with higher priority */
1184 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1185 memory_region_set_enabled(smram, true);
1186 }
1187
1188 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1189 kvm_memory_listener_register(kvm_state, &smram_listener,
1190 &smram_address_space, 1);
1191 }
1192
1193 int kvm_arch_init(MachineState *ms, KVMState *s)
1194 {
1195 uint64_t identity_base = 0xfffbc000;
1196 uint64_t shadow_mem;
1197 int ret;
1198 struct utsname utsname;
1199
1200 #ifdef KVM_CAP_XSAVE
1201 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1202 #endif
1203
1204 #ifdef KVM_CAP_XCRS
1205 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1206 #endif
1207
1208 #ifdef KVM_CAP_PIT_STATE2
1209 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1210 #endif
1211
1212 ret = kvm_get_supported_msrs(s);
1213 if (ret < 0) {
1214 return ret;
1215 }
1216
1217 uname(&utsname);
1218 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1219
1220 /*
1221 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1222 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1223 * Since these must be part of guest physical memory, we need to allocate
1224 * them, both by setting their start addresses in the kernel and by
1225 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1226 *
1227 * Older KVM versions may not support setting the identity map base. In
1228 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1229 * size.
1230 */
1231 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1232 /* Allows up to 16M BIOSes. */
1233 identity_base = 0xfeffc000;
1234
1235 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1236 if (ret < 0) {
1237 return ret;
1238 }
1239 }
1240
1241 /* Set TSS base one page after EPT identity map. */
1242 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1243 if (ret < 0) {
1244 return ret;
1245 }
1246
1247 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1248 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1249 if (ret < 0) {
1250 fprintf(stderr, "e820_add_entry() table is full\n");
1251 return ret;
1252 }
1253 qemu_register_reset(kvm_unpoison_all, NULL);
1254
1255 shadow_mem = machine_kvm_shadow_mem(ms);
1256 if (shadow_mem != -1) {
1257 shadow_mem /= 4096;
1258 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1259 if (ret < 0) {
1260 return ret;
1261 }
1262 }
1263
1264 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1265 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1266 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1267 smram_machine_done.notify = register_smram_listener;
1268 qemu_add_machine_init_done_notifier(&smram_machine_done);
1269 }
1270 return 0;
1271 }
1272
1273 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1274 {
1275 lhs->selector = rhs->selector;
1276 lhs->base = rhs->base;
1277 lhs->limit = rhs->limit;
1278 lhs->type = 3;
1279 lhs->present = 1;
1280 lhs->dpl = 3;
1281 lhs->db = 0;
1282 lhs->s = 1;
1283 lhs->l = 0;
1284 lhs->g = 0;
1285 lhs->avl = 0;
1286 lhs->unusable = 0;
1287 }
1288
1289 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1290 {
1291 unsigned flags = rhs->flags;
1292 lhs->selector = rhs->selector;
1293 lhs->base = rhs->base;
1294 lhs->limit = rhs->limit;
1295 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1296 lhs->present = (flags & DESC_P_MASK) != 0;
1297 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1298 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1299 lhs->s = (flags & DESC_S_MASK) != 0;
1300 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1301 lhs->g = (flags & DESC_G_MASK) != 0;
1302 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1303 lhs->unusable = !lhs->present;
1304 lhs->padding = 0;
1305 }
1306
1307 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1308 {
1309 lhs->selector = rhs->selector;
1310 lhs->base = rhs->base;
1311 lhs->limit = rhs->limit;
1312 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1313 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1314 (rhs->dpl << DESC_DPL_SHIFT) |
1315 (rhs->db << DESC_B_SHIFT) |
1316 (rhs->s * DESC_S_MASK) |
1317 (rhs->l << DESC_L_SHIFT) |
1318 (rhs->g * DESC_G_MASK) |
1319 (rhs->avl * DESC_AVL_MASK);
1320 }
1321
1322 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1323 {
1324 if (set) {
1325 *kvm_reg = *qemu_reg;
1326 } else {
1327 *qemu_reg = *kvm_reg;
1328 }
1329 }
1330
1331 static int kvm_getput_regs(X86CPU *cpu, int set)
1332 {
1333 CPUX86State *env = &cpu->env;
1334 struct kvm_regs regs;
1335 int ret = 0;
1336
1337 if (!set) {
1338 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1339 if (ret < 0) {
1340 return ret;
1341 }
1342 }
1343
1344 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1345 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1346 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1347 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1348 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1349 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1350 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1351 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1352 #ifdef TARGET_X86_64
1353 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1354 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1355 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1356 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1357 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1358 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1359 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1360 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1361 #endif
1362
1363 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1364 kvm_getput_reg(&regs.rip, &env->eip, set);
1365
1366 if (set) {
1367 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1368 }
1369
1370 return ret;
1371 }
1372
1373 static int kvm_put_fpu(X86CPU *cpu)
1374 {
1375 CPUX86State *env = &cpu->env;
1376 struct kvm_fpu fpu;
1377 int i;
1378
1379 memset(&fpu, 0, sizeof fpu);
1380 fpu.fsw = env->fpus & ~(7 << 11);
1381 fpu.fsw |= (env->fpstt & 7) << 11;
1382 fpu.fcw = env->fpuc;
1383 fpu.last_opcode = env->fpop;
1384 fpu.last_ip = env->fpip;
1385 fpu.last_dp = env->fpdp;
1386 for (i = 0; i < 8; ++i) {
1387 fpu.ftwx |= (!env->fptags[i]) << i;
1388 }
1389 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1390 for (i = 0; i < CPU_NB_REGS; i++) {
1391 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1392 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1393 }
1394 fpu.mxcsr = env->mxcsr;
1395
1396 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1397 }
1398
1399 #define XSAVE_FCW_FSW 0
1400 #define XSAVE_FTW_FOP 1
1401 #define XSAVE_CWD_RIP 2
1402 #define XSAVE_CWD_RDP 4
1403 #define XSAVE_MXCSR 6
1404 #define XSAVE_ST_SPACE 8
1405 #define XSAVE_XMM_SPACE 40
1406 #define XSAVE_XSTATE_BV 128
1407 #define XSAVE_YMMH_SPACE 144
1408 #define XSAVE_BNDREGS 240
1409 #define XSAVE_BNDCSR 256
1410 #define XSAVE_OPMASK 272
1411 #define XSAVE_ZMM_Hi256 288
1412 #define XSAVE_Hi16_ZMM 416
1413 #define XSAVE_PKRU 672
1414
1415 #define XSAVE_BYTE_OFFSET(word_offset) \
1416 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1417
1418 #define ASSERT_OFFSET(word_offset, field) \
1419 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1420 offsetof(X86XSaveArea, field))
1421
1422 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1423 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1424 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1425 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1426 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1427 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1428 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1429 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1430 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1431 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1432 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1433 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1434 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1435 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1436 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1437
1438 static int kvm_put_xsave(X86CPU *cpu)
1439 {
1440 CPUX86State *env = &cpu->env;
1441 X86XSaveArea *xsave = env->kvm_xsave_buf;
1442
1443 if (!has_xsave) {
1444 return kvm_put_fpu(cpu);
1445 }
1446 x86_cpu_xsave_all_areas(cpu, xsave);
1447
1448 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1449 }
1450
1451 static int kvm_put_xcrs(X86CPU *cpu)
1452 {
1453 CPUX86State *env = &cpu->env;
1454 struct kvm_xcrs xcrs = {};
1455
1456 if (!has_xcrs) {
1457 return 0;
1458 }
1459
1460 xcrs.nr_xcrs = 1;
1461 xcrs.flags = 0;
1462 xcrs.xcrs[0].xcr = 0;
1463 xcrs.xcrs[0].value = env->xcr0;
1464 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1465 }
1466
1467 static int kvm_put_sregs(X86CPU *cpu)
1468 {
1469 CPUX86State *env = &cpu->env;
1470 struct kvm_sregs sregs;
1471
1472 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1473 if (env->interrupt_injected >= 0) {
1474 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1475 (uint64_t)1 << (env->interrupt_injected % 64);
1476 }
1477
1478 if ((env->eflags & VM_MASK)) {
1479 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1480 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1481 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1482 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1483 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1484 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1485 } else {
1486 set_seg(&sregs.cs, &env->segs[R_CS]);
1487 set_seg(&sregs.ds, &env->segs[R_DS]);
1488 set_seg(&sregs.es, &env->segs[R_ES]);
1489 set_seg(&sregs.fs, &env->segs[R_FS]);
1490 set_seg(&sregs.gs, &env->segs[R_GS]);
1491 set_seg(&sregs.ss, &env->segs[R_SS]);
1492 }
1493
1494 set_seg(&sregs.tr, &env->tr);
1495 set_seg(&sregs.ldt, &env->ldt);
1496
1497 sregs.idt.limit = env->idt.limit;
1498 sregs.idt.base = env->idt.base;
1499 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1500 sregs.gdt.limit = env->gdt.limit;
1501 sregs.gdt.base = env->gdt.base;
1502 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1503
1504 sregs.cr0 = env->cr[0];
1505 sregs.cr2 = env->cr[2];
1506 sregs.cr3 = env->cr[3];
1507 sregs.cr4 = env->cr[4];
1508
1509 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1510 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1511
1512 sregs.efer = env->efer;
1513
1514 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1515 }
1516
1517 static void kvm_msr_buf_reset(X86CPU *cpu)
1518 {
1519 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1520 }
1521
1522 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1523 {
1524 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1525 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1526 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1527
1528 assert((void *)(entry + 1) <= limit);
1529
1530 entry->index = index;
1531 entry->reserved = 0;
1532 entry->data = value;
1533 msrs->nmsrs++;
1534 }
1535
1536 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1537 {
1538 kvm_msr_buf_reset(cpu);
1539 kvm_msr_entry_add(cpu, index, value);
1540
1541 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1542 }
1543
1544 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1545 {
1546 int ret;
1547
1548 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1549 assert(ret == 1);
1550 }
1551
1552 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1553 {
1554 CPUX86State *env = &cpu->env;
1555 int ret;
1556
1557 if (!has_msr_tsc_deadline) {
1558 return 0;
1559 }
1560
1561 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1562 if (ret < 0) {
1563 return ret;
1564 }
1565
1566 assert(ret == 1);
1567 return 0;
1568 }
1569
1570 /*
1571 * Provide a separate write service for the feature control MSR in order to
1572 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1573 * before writing any other state because forcibly leaving nested mode
1574 * invalidates the VCPU state.
1575 */
1576 static int kvm_put_msr_feature_control(X86CPU *cpu)
1577 {
1578 int ret;
1579
1580 if (!has_msr_feature_control) {
1581 return 0;
1582 }
1583
1584 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1585 cpu->env.msr_ia32_feature_control);
1586 if (ret < 0) {
1587 return ret;
1588 }
1589
1590 assert(ret == 1);
1591 return 0;
1592 }
1593
1594 static int kvm_put_msrs(X86CPU *cpu, int level)
1595 {
1596 CPUX86State *env = &cpu->env;
1597 int i;
1598 int ret;
1599
1600 kvm_msr_buf_reset(cpu);
1601
1602 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1603 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1604 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1605 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1606 if (has_msr_star) {
1607 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1608 }
1609 if (has_msr_hsave_pa) {
1610 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1611 }
1612 if (has_msr_tsc_aux) {
1613 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1614 }
1615 if (has_msr_tsc_adjust) {
1616 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1617 }
1618 if (has_msr_misc_enable) {
1619 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1620 env->msr_ia32_misc_enable);
1621 }
1622 if (has_msr_smbase) {
1623 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1624 }
1625 if (has_msr_bndcfgs) {
1626 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1627 }
1628 if (has_msr_xss) {
1629 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1630 }
1631 #ifdef TARGET_X86_64
1632 if (lm_capable_kernel) {
1633 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1634 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1635 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1636 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1637 }
1638 #endif
1639 /*
1640 * The following MSRs have side effects on the guest or are too heavy
1641 * for normal writeback. Limit them to reset or full state updates.
1642 */
1643 if (level >= KVM_PUT_RESET_STATE) {
1644 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1645 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1646 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1647 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1648 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1649 }
1650 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1651 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1652 }
1653 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1654 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1655 }
1656 if (has_msr_architectural_pmu) {
1657 /* Stop the counter. */
1658 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1659 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1660
1661 /* Set the counter values. */
1662 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1663 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1664 env->msr_fixed_counters[i]);
1665 }
1666 for (i = 0; i < num_architectural_pmu_counters; i++) {
1667 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1668 env->msr_gp_counters[i]);
1669 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1670 env->msr_gp_evtsel[i]);
1671 }
1672 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1673 env->msr_global_status);
1674 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1675 env->msr_global_ovf_ctrl);
1676
1677 /* Now start the PMU. */
1678 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1679 env->msr_fixed_ctr_ctrl);
1680 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1681 env->msr_global_ctrl);
1682 }
1683 if (has_msr_hv_hypercall) {
1684 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1685 env->msr_hv_guest_os_id);
1686 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1687 env->msr_hv_hypercall);
1688 }
1689 if (cpu->hyperv_vapic) {
1690 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1691 env->msr_hv_vapic);
1692 }
1693 if (cpu->hyperv_time) {
1694 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1695 }
1696 if (has_msr_hv_crash) {
1697 int j;
1698
1699 for (j = 0; j < HV_CRASH_PARAMS; j++)
1700 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1701 env->msr_hv_crash_params[j]);
1702
1703 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1704 }
1705 if (has_msr_hv_runtime) {
1706 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1707 }
1708 if (cpu->hyperv_synic) {
1709 int j;
1710
1711 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1712 env->msr_hv_synic_control);
1713 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1714 env->msr_hv_synic_version);
1715 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1716 env->msr_hv_synic_evt_page);
1717 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1718 env->msr_hv_synic_msg_page);
1719
1720 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1721 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1722 env->msr_hv_synic_sint[j]);
1723 }
1724 }
1725 if (has_msr_hv_stimer) {
1726 int j;
1727
1728 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1729 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1730 env->msr_hv_stimer_config[j]);
1731 }
1732
1733 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1734 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1735 env->msr_hv_stimer_count[j]);
1736 }
1737 }
1738 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1739 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1740
1741 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1742 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1743 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1744 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1745 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1746 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1747 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1748 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1749 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1750 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1751 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1752 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1753 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1754 /* The CPU GPs if we write to a bit above the physical limit of
1755 * the host CPU (and KVM emulates that)
1756 */
1757 uint64_t mask = env->mtrr_var[i].mask;
1758 mask &= phys_mask;
1759
1760 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1761 env->mtrr_var[i].base);
1762 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1763 }
1764 }
1765
1766 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1767 * kvm_put_msr_feature_control. */
1768 }
1769 if (env->mcg_cap) {
1770 int i;
1771
1772 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1773 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1774 if (has_msr_mcg_ext_ctl) {
1775 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1776 }
1777 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1778 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1779 }
1780 }
1781
1782 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1783 if (ret < 0) {
1784 return ret;
1785 }
1786
1787 if (ret < cpu->kvm_msr_buf->nmsrs) {
1788 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1789 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1790 (uint32_t)e->index, (uint64_t)e->data);
1791 }
1792
1793 assert(ret == cpu->kvm_msr_buf->nmsrs);
1794 return 0;
1795 }
1796
1797
1798 static int kvm_get_fpu(X86CPU *cpu)
1799 {
1800 CPUX86State *env = &cpu->env;
1801 struct kvm_fpu fpu;
1802 int i, ret;
1803
1804 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1805 if (ret < 0) {
1806 return ret;
1807 }
1808
1809 env->fpstt = (fpu.fsw >> 11) & 7;
1810 env->fpus = fpu.fsw;
1811 env->fpuc = fpu.fcw;
1812 env->fpop = fpu.last_opcode;
1813 env->fpip = fpu.last_ip;
1814 env->fpdp = fpu.last_dp;
1815 for (i = 0; i < 8; ++i) {
1816 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1817 }
1818 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1819 for (i = 0; i < CPU_NB_REGS; i++) {
1820 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1821 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1822 }
1823 env->mxcsr = fpu.mxcsr;
1824
1825 return 0;
1826 }
1827
1828 static int kvm_get_xsave(X86CPU *cpu)
1829 {
1830 CPUX86State *env = &cpu->env;
1831 X86XSaveArea *xsave = env->kvm_xsave_buf;
1832 int ret;
1833
1834 if (!has_xsave) {
1835 return kvm_get_fpu(cpu);
1836 }
1837
1838 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1839 if (ret < 0) {
1840 return ret;
1841 }
1842 x86_cpu_xrstor_all_areas(cpu, xsave);
1843
1844 return 0;
1845 }
1846
1847 static int kvm_get_xcrs(X86CPU *cpu)
1848 {
1849 CPUX86State *env = &cpu->env;
1850 int i, ret;
1851 struct kvm_xcrs xcrs;
1852
1853 if (!has_xcrs) {
1854 return 0;
1855 }
1856
1857 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1858 if (ret < 0) {
1859 return ret;
1860 }
1861
1862 for (i = 0; i < xcrs.nr_xcrs; i++) {
1863 /* Only support xcr0 now */
1864 if (xcrs.xcrs[i].xcr == 0) {
1865 env->xcr0 = xcrs.xcrs[i].value;
1866 break;
1867 }
1868 }
1869 return 0;
1870 }
1871
1872 static int kvm_get_sregs(X86CPU *cpu)
1873 {
1874 CPUX86State *env = &cpu->env;
1875 struct kvm_sregs sregs;
1876 uint32_t hflags;
1877 int bit, i, ret;
1878
1879 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1880 if (ret < 0) {
1881 return ret;
1882 }
1883
1884 /* There can only be one pending IRQ set in the bitmap at a time, so try
1885 to find it and save its number instead (-1 for none). */
1886 env->interrupt_injected = -1;
1887 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1888 if (sregs.interrupt_bitmap[i]) {
1889 bit = ctz64(sregs.interrupt_bitmap[i]);
1890 env->interrupt_injected = i * 64 + bit;
1891 break;
1892 }
1893 }
1894
1895 get_seg(&env->segs[R_CS], &sregs.cs);
1896 get_seg(&env->segs[R_DS], &sregs.ds);
1897 get_seg(&env->segs[R_ES], &sregs.es);
1898 get_seg(&env->segs[R_FS], &sregs.fs);
1899 get_seg(&env->segs[R_GS], &sregs.gs);
1900 get_seg(&env->segs[R_SS], &sregs.ss);
1901
1902 get_seg(&env->tr, &sregs.tr);
1903 get_seg(&env->ldt, &sregs.ldt);
1904
1905 env->idt.limit = sregs.idt.limit;
1906 env->idt.base = sregs.idt.base;
1907 env->gdt.limit = sregs.gdt.limit;
1908 env->gdt.base = sregs.gdt.base;
1909
1910 env->cr[0] = sregs.cr0;
1911 env->cr[2] = sregs.cr2;
1912 env->cr[3] = sregs.cr3;
1913 env->cr[4] = sregs.cr4;
1914
1915 env->efer = sregs.efer;
1916
1917 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1918
1919 #define HFLAG_COPY_MASK \
1920 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1921 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1922 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1923 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1924
1925 hflags = env->hflags & HFLAG_COPY_MASK;
1926 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1927 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1928 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1929 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1930 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1931
1932 if (env->cr[4] & CR4_OSFXSR_MASK) {
1933 hflags |= HF_OSFXSR_MASK;
1934 }
1935
1936 if (env->efer & MSR_EFER_LMA) {
1937 hflags |= HF_LMA_MASK;
1938 }
1939
1940 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1941 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1942 } else {
1943 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1944 (DESC_B_SHIFT - HF_CS32_SHIFT);
1945 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1946 (DESC_B_SHIFT - HF_SS32_SHIFT);
1947 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1948 !(hflags & HF_CS32_MASK)) {
1949 hflags |= HF_ADDSEG_MASK;
1950 } else {
1951 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1952 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1953 }
1954 }
1955 env->hflags = hflags;
1956
1957 return 0;
1958 }
1959
1960 static int kvm_get_msrs(X86CPU *cpu)
1961 {
1962 CPUX86State *env = &cpu->env;
1963 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1964 int ret, i;
1965 uint64_t mtrr_top_bits;
1966
1967 kvm_msr_buf_reset(cpu);
1968
1969 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1970 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1971 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1972 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1973 if (has_msr_star) {
1974 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1975 }
1976 if (has_msr_hsave_pa) {
1977 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1978 }
1979 if (has_msr_tsc_aux) {
1980 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1981 }
1982 if (has_msr_tsc_adjust) {
1983 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
1984 }
1985 if (has_msr_tsc_deadline) {
1986 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
1987 }
1988 if (has_msr_misc_enable) {
1989 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
1990 }
1991 if (has_msr_smbase) {
1992 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
1993 }
1994 if (has_msr_feature_control) {
1995 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
1996 }
1997 if (has_msr_bndcfgs) {
1998 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
1999 }
2000 if (has_msr_xss) {
2001 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2002 }
2003
2004
2005 if (!env->tsc_valid) {
2006 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2007 env->tsc_valid = !runstate_is_running();
2008 }
2009
2010 #ifdef TARGET_X86_64
2011 if (lm_capable_kernel) {
2012 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2013 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2014 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2015 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2016 }
2017 #endif
2018 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2019 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2020 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2021 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2022 }
2023 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2024 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2025 }
2026 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2027 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2028 }
2029 if (has_msr_architectural_pmu) {
2030 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2031 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2032 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2033 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2034 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2035 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2036 }
2037 for (i = 0; i < num_architectural_pmu_counters; i++) {
2038 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2039 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2040 }
2041 }
2042
2043 if (env->mcg_cap) {
2044 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2045 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2046 if (has_msr_mcg_ext_ctl) {
2047 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2048 }
2049 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2050 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2051 }
2052 }
2053
2054 if (has_msr_hv_hypercall) {
2055 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2056 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2057 }
2058 if (cpu->hyperv_vapic) {
2059 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2060 }
2061 if (cpu->hyperv_time) {
2062 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2063 }
2064 if (has_msr_hv_crash) {
2065 int j;
2066
2067 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2068 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2069 }
2070 }
2071 if (has_msr_hv_runtime) {
2072 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2073 }
2074 if (cpu->hyperv_synic) {
2075 uint32_t msr;
2076
2077 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2078 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2079 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2080 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2081 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2082 kvm_msr_entry_add(cpu, msr, 0);
2083 }
2084 }
2085 if (has_msr_hv_stimer) {
2086 uint32_t msr;
2087
2088 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2089 msr++) {
2090 kvm_msr_entry_add(cpu, msr, 0);
2091 }
2092 }
2093 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2094 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2095 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2096 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2097 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2098 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2099 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2100 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2101 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2102 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2103 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2104 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2105 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2106 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2107 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2108 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2109 }
2110 }
2111
2112 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2113 if (ret < 0) {
2114 return ret;
2115 }
2116
2117 if (ret < cpu->kvm_msr_buf->nmsrs) {
2118 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2119 error_report("error: failed to get MSR 0x%" PRIx32,
2120 (uint32_t)e->index);
2121 }
2122
2123 assert(ret == cpu->kvm_msr_buf->nmsrs);
2124 /*
2125 * MTRR masks: Each mask consists of 5 parts
2126 * a 10..0: must be zero
2127 * b 11 : valid bit
2128 * c n-1.12: actual mask bits
2129 * d 51..n: reserved must be zero
2130 * e 63.52: reserved must be zero
2131 *
2132 * 'n' is the number of physical bits supported by the CPU and is
2133 * apparently always <= 52. We know our 'n' but don't know what
2134 * the destinations 'n' is; it might be smaller, in which case
2135 * it masks (c) on loading. It might be larger, in which case
2136 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2137 * we're migrating to.
2138 */
2139
2140 if (cpu->fill_mtrr_mask) {
2141 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2142 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2143 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2144 } else {
2145 mtrr_top_bits = 0;
2146 }
2147
2148 for (i = 0; i < ret; i++) {
2149 uint32_t index = msrs[i].index;
2150 switch (index) {
2151 case MSR_IA32_SYSENTER_CS:
2152 env->sysenter_cs = msrs[i].data;
2153 break;
2154 case MSR_IA32_SYSENTER_ESP:
2155 env->sysenter_esp = msrs[i].data;
2156 break;
2157 case MSR_IA32_SYSENTER_EIP:
2158 env->sysenter_eip = msrs[i].data;
2159 break;
2160 case MSR_PAT:
2161 env->pat = msrs[i].data;
2162 break;
2163 case MSR_STAR:
2164 env->star = msrs[i].data;
2165 break;
2166 #ifdef TARGET_X86_64
2167 case MSR_CSTAR:
2168 env->cstar = msrs[i].data;
2169 break;
2170 case MSR_KERNELGSBASE:
2171 env->kernelgsbase = msrs[i].data;
2172 break;
2173 case MSR_FMASK:
2174 env->fmask = msrs[i].data;
2175 break;
2176 case MSR_LSTAR:
2177 env->lstar = msrs[i].data;
2178 break;
2179 #endif
2180 case MSR_IA32_TSC:
2181 env->tsc = msrs[i].data;
2182 break;
2183 case MSR_TSC_AUX:
2184 env->tsc_aux = msrs[i].data;
2185 break;
2186 case MSR_TSC_ADJUST:
2187 env->tsc_adjust = msrs[i].data;
2188 break;
2189 case MSR_IA32_TSCDEADLINE:
2190 env->tsc_deadline = msrs[i].data;
2191 break;
2192 case MSR_VM_HSAVE_PA:
2193 env->vm_hsave = msrs[i].data;
2194 break;
2195 case MSR_KVM_SYSTEM_TIME:
2196 env->system_time_msr = msrs[i].data;
2197 break;
2198 case MSR_KVM_WALL_CLOCK:
2199 env->wall_clock_msr = msrs[i].data;
2200 break;
2201 case MSR_MCG_STATUS:
2202 env->mcg_status = msrs[i].data;
2203 break;
2204 case MSR_MCG_CTL:
2205 env->mcg_ctl = msrs[i].data;
2206 break;
2207 case MSR_MCG_EXT_CTL:
2208 env->mcg_ext_ctl = msrs[i].data;
2209 break;
2210 case MSR_IA32_MISC_ENABLE:
2211 env->msr_ia32_misc_enable = msrs[i].data;
2212 break;
2213 case MSR_IA32_SMBASE:
2214 env->smbase = msrs[i].data;
2215 break;
2216 case MSR_IA32_FEATURE_CONTROL:
2217 env->msr_ia32_feature_control = msrs[i].data;
2218 break;
2219 case MSR_IA32_BNDCFGS:
2220 env->msr_bndcfgs = msrs[i].data;
2221 break;
2222 case MSR_IA32_XSS:
2223 env->xss = msrs[i].data;
2224 break;
2225 default:
2226 if (msrs[i].index >= MSR_MC0_CTL &&
2227 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2228 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2229 }
2230 break;
2231 case MSR_KVM_ASYNC_PF_EN:
2232 env->async_pf_en_msr = msrs[i].data;
2233 break;
2234 case MSR_KVM_PV_EOI_EN:
2235 env->pv_eoi_en_msr = msrs[i].data;
2236 break;
2237 case MSR_KVM_STEAL_TIME:
2238 env->steal_time_msr = msrs[i].data;
2239 break;
2240 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2241 env->msr_fixed_ctr_ctrl = msrs[i].data;
2242 break;
2243 case MSR_CORE_PERF_GLOBAL_CTRL:
2244 env->msr_global_ctrl = msrs[i].data;
2245 break;
2246 case MSR_CORE_PERF_GLOBAL_STATUS:
2247 env->msr_global_status = msrs[i].data;
2248 break;
2249 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2250 env->msr_global_ovf_ctrl = msrs[i].data;
2251 break;
2252 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2253 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2254 break;
2255 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2256 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2257 break;
2258 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2259 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2260 break;
2261 case HV_X64_MSR_HYPERCALL:
2262 env->msr_hv_hypercall = msrs[i].data;
2263 break;
2264 case HV_X64_MSR_GUEST_OS_ID:
2265 env->msr_hv_guest_os_id = msrs[i].data;
2266 break;
2267 case HV_X64_MSR_APIC_ASSIST_PAGE:
2268 env->msr_hv_vapic = msrs[i].data;
2269 break;
2270 case HV_X64_MSR_REFERENCE_TSC:
2271 env->msr_hv_tsc = msrs[i].data;
2272 break;
2273 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2274 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2275 break;
2276 case HV_X64_MSR_VP_RUNTIME:
2277 env->msr_hv_runtime = msrs[i].data;
2278 break;
2279 case HV_X64_MSR_SCONTROL:
2280 env->msr_hv_synic_control = msrs[i].data;
2281 break;
2282 case HV_X64_MSR_SVERSION:
2283 env->msr_hv_synic_version = msrs[i].data;
2284 break;
2285 case HV_X64_MSR_SIEFP:
2286 env->msr_hv_synic_evt_page = msrs[i].data;
2287 break;
2288 case HV_X64_MSR_SIMP:
2289 env->msr_hv_synic_msg_page = msrs[i].data;
2290 break;
2291 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2292 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2293 break;
2294 case HV_X64_MSR_STIMER0_CONFIG:
2295 case HV_X64_MSR_STIMER1_CONFIG:
2296 case HV_X64_MSR_STIMER2_CONFIG:
2297 case HV_X64_MSR_STIMER3_CONFIG:
2298 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2299 msrs[i].data;
2300 break;
2301 case HV_X64_MSR_STIMER0_COUNT:
2302 case HV_X64_MSR_STIMER1_COUNT:
2303 case HV_X64_MSR_STIMER2_COUNT:
2304 case HV_X64_MSR_STIMER3_COUNT:
2305 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2306 msrs[i].data;
2307 break;
2308 case MSR_MTRRdefType:
2309 env->mtrr_deftype = msrs[i].data;
2310 break;
2311 case MSR_MTRRfix64K_00000:
2312 env->mtrr_fixed[0] = msrs[i].data;
2313 break;
2314 case MSR_MTRRfix16K_80000:
2315 env->mtrr_fixed[1] = msrs[i].data;
2316 break;
2317 case MSR_MTRRfix16K_A0000:
2318 env->mtrr_fixed[2] = msrs[i].data;
2319 break;
2320 case MSR_MTRRfix4K_C0000:
2321 env->mtrr_fixed[3] = msrs[i].data;
2322 break;
2323 case MSR_MTRRfix4K_C8000:
2324 env->mtrr_fixed[4] = msrs[i].data;
2325 break;
2326 case MSR_MTRRfix4K_D0000:
2327 env->mtrr_fixed[5] = msrs[i].data;
2328 break;
2329 case MSR_MTRRfix4K_D8000:
2330 env->mtrr_fixed[6] = msrs[i].data;
2331 break;
2332 case MSR_MTRRfix4K_E0000:
2333 env->mtrr_fixed[7] = msrs[i].data;
2334 break;
2335 case MSR_MTRRfix4K_E8000:
2336 env->mtrr_fixed[8] = msrs[i].data;
2337 break;
2338 case MSR_MTRRfix4K_F0000:
2339 env->mtrr_fixed[9] = msrs[i].data;
2340 break;
2341 case MSR_MTRRfix4K_F8000:
2342 env->mtrr_fixed[10] = msrs[i].data;
2343 break;
2344 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2345 if (index & 1) {
2346 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2347 mtrr_top_bits;
2348 } else {
2349 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2350 }
2351 break;
2352 }
2353 }
2354
2355 return 0;
2356 }
2357
2358 static int kvm_put_mp_state(X86CPU *cpu)
2359 {
2360 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2361
2362 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2363 }
2364
2365 static int kvm_get_mp_state(X86CPU *cpu)
2366 {
2367 CPUState *cs = CPU(cpu);
2368 CPUX86State *env = &cpu->env;
2369 struct kvm_mp_state mp_state;
2370 int ret;
2371
2372 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2373 if (ret < 0) {
2374 return ret;
2375 }
2376 env->mp_state = mp_state.mp_state;
2377 if (kvm_irqchip_in_kernel()) {
2378 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2379 }
2380 return 0;
2381 }
2382
2383 static int kvm_get_apic(X86CPU *cpu)
2384 {
2385 DeviceState *apic = cpu->apic_state;
2386 struct kvm_lapic_state kapic;
2387 int ret;
2388
2389 if (apic && kvm_irqchip_in_kernel()) {
2390 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2391 if (ret < 0) {
2392 return ret;
2393 }
2394
2395 kvm_get_apic_state(apic, &kapic);
2396 }
2397 return 0;
2398 }
2399
2400 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2401 {
2402 CPUState *cs = CPU(cpu);
2403 CPUX86State *env = &cpu->env;
2404 struct kvm_vcpu_events events = {};
2405
2406 if (!kvm_has_vcpu_events()) {
2407 return 0;
2408 }
2409
2410 events.exception.injected = (env->exception_injected >= 0);
2411 events.exception.nr = env->exception_injected;
2412 events.exception.has_error_code = env->has_error_code;
2413 events.exception.error_code = env->error_code;
2414 events.exception.pad = 0;
2415
2416 events.interrupt.injected = (env->interrupt_injected >= 0);
2417 events.interrupt.nr = env->interrupt_injected;
2418 events.interrupt.soft = env->soft_interrupt;
2419
2420 events.nmi.injected = env->nmi_injected;
2421 events.nmi.pending = env->nmi_pending;
2422 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2423 events.nmi.pad = 0;
2424
2425 events.sipi_vector = env->sipi_vector;
2426 events.flags = 0;
2427
2428 if (has_msr_smbase) {
2429 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2430 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2431 if (kvm_irqchip_in_kernel()) {
2432 /* As soon as these are moved to the kernel, remove them
2433 * from cs->interrupt_request.
2434 */
2435 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2436 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2437 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2438 } else {
2439 /* Keep these in cs->interrupt_request. */
2440 events.smi.pending = 0;
2441 events.smi.latched_init = 0;
2442 }
2443 /* Stop SMI delivery on old machine types to avoid a reboot
2444 * on an inward migration of an old VM.
2445 */
2446 if (!cpu->kvm_no_smi_migration) {
2447 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2448 }
2449 }
2450
2451 if (level >= KVM_PUT_RESET_STATE) {
2452 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2453 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2454 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2455 }
2456 }
2457
2458 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2459 }
2460
2461 static int kvm_get_vcpu_events(X86CPU *cpu)
2462 {
2463 CPUX86State *env = &cpu->env;
2464 struct kvm_vcpu_events events;
2465 int ret;
2466
2467 if (!kvm_has_vcpu_events()) {
2468 return 0;
2469 }
2470
2471 memset(&events, 0, sizeof(events));
2472 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2473 if (ret < 0) {
2474 return ret;
2475 }
2476 env->exception_injected =
2477 events.exception.injected ? events.exception.nr : -1;
2478 env->has_error_code = events.exception.has_error_code;
2479 env->error_code = events.exception.error_code;
2480
2481 env->interrupt_injected =
2482 events.interrupt.injected ? events.interrupt.nr : -1;
2483 env->soft_interrupt = events.interrupt.soft;
2484
2485 env->nmi_injected = events.nmi.injected;
2486 env->nmi_pending = events.nmi.pending;
2487 if (events.nmi.masked) {
2488 env->hflags2 |= HF2_NMI_MASK;
2489 } else {
2490 env->hflags2 &= ~HF2_NMI_MASK;
2491 }
2492
2493 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2494 if (events.smi.smm) {
2495 env->hflags |= HF_SMM_MASK;
2496 } else {
2497 env->hflags &= ~HF_SMM_MASK;
2498 }
2499 if (events.smi.pending) {
2500 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2501 } else {
2502 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2503 }
2504 if (events.smi.smm_inside_nmi) {
2505 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2506 } else {
2507 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2508 }
2509 if (events.smi.latched_init) {
2510 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2511 } else {
2512 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2513 }
2514 }
2515
2516 env->sipi_vector = events.sipi_vector;
2517
2518 return 0;
2519 }
2520
2521 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2522 {
2523 CPUState *cs = CPU(cpu);
2524 CPUX86State *env = &cpu->env;
2525 int ret = 0;
2526 unsigned long reinject_trap = 0;
2527
2528 if (!kvm_has_vcpu_events()) {
2529 if (env->exception_injected == 1) {
2530 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2531 } else if (env->exception_injected == 3) {
2532 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2533 }
2534 env->exception_injected = -1;
2535 }
2536
2537 /*
2538 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2539 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2540 * by updating the debug state once again if single-stepping is on.
2541 * Another reason to call kvm_update_guest_debug here is a pending debug
2542 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2543 * reinject them via SET_GUEST_DEBUG.
2544 */
2545 if (reinject_trap ||
2546 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2547 ret = kvm_update_guest_debug(cs, reinject_trap);
2548 }
2549 return ret;
2550 }
2551
2552 static int kvm_put_debugregs(X86CPU *cpu)
2553 {
2554 CPUX86State *env = &cpu->env;
2555 struct kvm_debugregs dbgregs;
2556 int i;
2557
2558 if (!kvm_has_debugregs()) {
2559 return 0;
2560 }
2561
2562 for (i = 0; i < 4; i++) {
2563 dbgregs.db[i] = env->dr[i];
2564 }
2565 dbgregs.dr6 = env->dr[6];
2566 dbgregs.dr7 = env->dr[7];
2567 dbgregs.flags = 0;
2568
2569 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2570 }
2571
2572 static int kvm_get_debugregs(X86CPU *cpu)
2573 {
2574 CPUX86State *env = &cpu->env;
2575 struct kvm_debugregs dbgregs;
2576 int i, ret;
2577
2578 if (!kvm_has_debugregs()) {
2579 return 0;
2580 }
2581
2582 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2583 if (ret < 0) {
2584 return ret;
2585 }
2586 for (i = 0; i < 4; i++) {
2587 env->dr[i] = dbgregs.db[i];
2588 }
2589 env->dr[4] = env->dr[6] = dbgregs.dr6;
2590 env->dr[5] = env->dr[7] = dbgregs.dr7;
2591
2592 return 0;
2593 }
2594
2595 int kvm_arch_put_registers(CPUState *cpu, int level)
2596 {
2597 X86CPU *x86_cpu = X86_CPU(cpu);
2598 int ret;
2599
2600 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2601
2602 if (level >= KVM_PUT_RESET_STATE) {
2603 ret = kvm_put_msr_feature_control(x86_cpu);
2604 if (ret < 0) {
2605 return ret;
2606 }
2607 }
2608
2609 if (level == KVM_PUT_FULL_STATE) {
2610 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2611 * because TSC frequency mismatch shouldn't abort migration,
2612 * unless the user explicitly asked for a more strict TSC
2613 * setting (e.g. using an explicit "tsc-freq" option).
2614 */
2615 kvm_arch_set_tsc_khz(cpu);
2616 }
2617
2618 ret = kvm_getput_regs(x86_cpu, 1);
2619 if (ret < 0) {
2620 return ret;
2621 }
2622 ret = kvm_put_xsave(x86_cpu);
2623 if (ret < 0) {
2624 return ret;
2625 }
2626 ret = kvm_put_xcrs(x86_cpu);
2627 if (ret < 0) {
2628 return ret;
2629 }
2630 ret = kvm_put_sregs(x86_cpu);
2631 if (ret < 0) {
2632 return ret;
2633 }
2634 /* must be before kvm_put_msrs */
2635 ret = kvm_inject_mce_oldstyle(x86_cpu);
2636 if (ret < 0) {
2637 return ret;
2638 }
2639 ret = kvm_put_msrs(x86_cpu, level);
2640 if (ret < 0) {
2641 return ret;
2642 }
2643 ret = kvm_put_vcpu_events(x86_cpu, level);
2644 if (ret < 0) {
2645 return ret;
2646 }
2647 if (level >= KVM_PUT_RESET_STATE) {
2648 ret = kvm_put_mp_state(x86_cpu);
2649 if (ret < 0) {
2650 return ret;
2651 }
2652 }
2653
2654 ret = kvm_put_tscdeadline_msr(x86_cpu);
2655 if (ret < 0) {
2656 return ret;
2657 }
2658 ret = kvm_put_debugregs(x86_cpu);
2659 if (ret < 0) {
2660 return ret;
2661 }
2662 /* must be last */
2663 ret = kvm_guest_debug_workarounds(x86_cpu);
2664 if (ret < 0) {
2665 return ret;
2666 }
2667 return 0;
2668 }
2669
2670 int kvm_arch_get_registers(CPUState *cs)
2671 {
2672 X86CPU *cpu = X86_CPU(cs);
2673 int ret;
2674
2675 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2676
2677 ret = kvm_get_vcpu_events(cpu);
2678 if (ret < 0) {
2679 goto out;
2680 }
2681 /*
2682 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2683 * KVM_GET_REGS and KVM_GET_SREGS.
2684 */
2685 ret = kvm_get_mp_state(cpu);
2686 if (ret < 0) {
2687 goto out;
2688 }
2689 ret = kvm_getput_regs(cpu, 0);
2690 if (ret < 0) {
2691 goto out;
2692 }
2693 ret = kvm_get_xsave(cpu);
2694 if (ret < 0) {
2695 goto out;
2696 }
2697 ret = kvm_get_xcrs(cpu);
2698 if (ret < 0) {
2699 goto out;
2700 }
2701 ret = kvm_get_sregs(cpu);
2702 if (ret < 0) {
2703 goto out;
2704 }
2705 ret = kvm_get_msrs(cpu);
2706 if (ret < 0) {
2707 goto out;
2708 }
2709 ret = kvm_get_apic(cpu);
2710 if (ret < 0) {
2711 goto out;
2712 }
2713 ret = kvm_get_debugregs(cpu);
2714 if (ret < 0) {
2715 goto out;
2716 }
2717 ret = 0;
2718 out:
2719 cpu_sync_bndcs_hflags(&cpu->env);
2720 return ret;
2721 }
2722
2723 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2724 {
2725 X86CPU *x86_cpu = X86_CPU(cpu);
2726 CPUX86State *env = &x86_cpu->env;
2727 int ret;
2728
2729 /* Inject NMI */
2730 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2731 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2732 qemu_mutex_lock_iothread();
2733 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2734 qemu_mutex_unlock_iothread();
2735 DPRINTF("injected NMI\n");
2736 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2737 if (ret < 0) {
2738 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2739 strerror(-ret));
2740 }
2741 }
2742 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2743 qemu_mutex_lock_iothread();
2744 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2745 qemu_mutex_unlock_iothread();
2746 DPRINTF("injected SMI\n");
2747 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2748 if (ret < 0) {
2749 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2750 strerror(-ret));
2751 }
2752 }
2753 }
2754
2755 if (!kvm_pic_in_kernel()) {
2756 qemu_mutex_lock_iothread();
2757 }
2758
2759 /* Force the VCPU out of its inner loop to process any INIT requests
2760 * or (for userspace APIC, but it is cheap to combine the checks here)
2761 * pending TPR access reports.
2762 */
2763 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2764 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2765 !(env->hflags & HF_SMM_MASK)) {
2766 cpu->exit_request = 1;
2767 }
2768 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2769 cpu->exit_request = 1;
2770 }
2771 }
2772
2773 if (!kvm_pic_in_kernel()) {
2774 /* Try to inject an interrupt if the guest can accept it */
2775 if (run->ready_for_interrupt_injection &&
2776 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2777 (env->eflags & IF_MASK)) {
2778 int irq;
2779
2780 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2781 irq = cpu_get_pic_interrupt(env);
2782 if (irq >= 0) {
2783 struct kvm_interrupt intr;
2784
2785 intr.irq = irq;
2786 DPRINTF("injected interrupt %d\n", irq);
2787 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2788 if (ret < 0) {
2789 fprintf(stderr,
2790 "KVM: injection failed, interrupt lost (%s)\n",
2791 strerror(-ret));
2792 }
2793 }
2794 }
2795
2796 /* If we have an interrupt but the guest is not ready to receive an
2797 * interrupt, request an interrupt window exit. This will
2798 * cause a return to userspace as soon as the guest is ready to
2799 * receive interrupts. */
2800 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2801 run->request_interrupt_window = 1;
2802 } else {
2803 run->request_interrupt_window = 0;
2804 }
2805
2806 DPRINTF("setting tpr\n");
2807 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2808
2809 qemu_mutex_unlock_iothread();
2810 }
2811 }
2812
2813 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2814 {
2815 X86CPU *x86_cpu = X86_CPU(cpu);
2816 CPUX86State *env = &x86_cpu->env;
2817
2818 if (run->flags & KVM_RUN_X86_SMM) {
2819 env->hflags |= HF_SMM_MASK;
2820 } else {
2821 env->hflags &= ~HF_SMM_MASK;
2822 }
2823 if (run->if_flag) {
2824 env->eflags |= IF_MASK;
2825 } else {
2826 env->eflags &= ~IF_MASK;
2827 }
2828
2829 /* We need to protect the apic state against concurrent accesses from
2830 * different threads in case the userspace irqchip is used. */
2831 if (!kvm_irqchip_in_kernel()) {
2832 qemu_mutex_lock_iothread();
2833 }
2834 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2835 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2836 if (!kvm_irqchip_in_kernel()) {
2837 qemu_mutex_unlock_iothread();
2838 }
2839 return cpu_get_mem_attrs(env);
2840 }
2841
2842 int kvm_arch_process_async_events(CPUState *cs)
2843 {
2844 X86CPU *cpu = X86_CPU(cs);
2845 CPUX86State *env = &cpu->env;
2846
2847 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2848 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2849 assert(env->mcg_cap);
2850
2851 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2852
2853 kvm_cpu_synchronize_state(cs);
2854
2855 if (env->exception_injected == EXCP08_DBLE) {
2856 /* this means triple fault */
2857 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2858 cs->exit_request = 1;
2859 return 0;
2860 }
2861 env->exception_injected = EXCP12_MCHK;
2862 env->has_error_code = 0;
2863
2864 cs->halted = 0;
2865 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2866 env->mp_state = KVM_MP_STATE_RUNNABLE;
2867 }
2868 }
2869
2870 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2871 !(env->hflags & HF_SMM_MASK)) {
2872 kvm_cpu_synchronize_state(cs);
2873 do_cpu_init(cpu);
2874 }
2875
2876 if (kvm_irqchip_in_kernel()) {
2877 return 0;
2878 }
2879
2880 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2881 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2882 apic_poll_irq(cpu->apic_state);
2883 }
2884 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2885 (env->eflags & IF_MASK)) ||
2886 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2887 cs->halted = 0;
2888 }
2889 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2890 kvm_cpu_synchronize_state(cs);
2891 do_cpu_sipi(cpu);
2892 }
2893 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2894 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2895 kvm_cpu_synchronize_state(cs);
2896 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2897 env->tpr_access_type);
2898 }
2899
2900 return cs->halted;
2901 }
2902
2903 static int kvm_handle_halt(X86CPU *cpu)
2904 {
2905 CPUState *cs = CPU(cpu);
2906 CPUX86State *env = &cpu->env;
2907
2908 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2909 (env->eflags & IF_MASK)) &&
2910 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2911 cs->halted = 1;
2912 return EXCP_HLT;
2913 }
2914
2915 return 0;
2916 }
2917
2918 static int kvm_handle_tpr_access(X86CPU *cpu)
2919 {
2920 CPUState *cs = CPU(cpu);
2921 struct kvm_run *run = cs->kvm_run;
2922
2923 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2924 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2925 : TPR_ACCESS_READ);
2926 return 1;
2927 }
2928
2929 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2930 {
2931 static const uint8_t int3 = 0xcc;
2932
2933 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2934 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2935 return -EINVAL;
2936 }
2937 return 0;
2938 }
2939
2940 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2941 {
2942 uint8_t int3;
2943
2944 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2945 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2946 return -EINVAL;
2947 }
2948 return 0;
2949 }
2950
2951 static struct {
2952 target_ulong addr;
2953 int len;
2954 int type;
2955 } hw_breakpoint[4];
2956
2957 static int nb_hw_breakpoint;
2958
2959 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2960 {
2961 int n;
2962
2963 for (n = 0; n < nb_hw_breakpoint; n++) {
2964 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2965 (hw_breakpoint[n].len == len || len == -1)) {
2966 return n;
2967 }
2968 }
2969 return -1;
2970 }
2971
2972 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2973 target_ulong len, int type)
2974 {
2975 switch (type) {
2976 case GDB_BREAKPOINT_HW:
2977 len = 1;
2978 break;
2979 case GDB_WATCHPOINT_WRITE:
2980 case GDB_WATCHPOINT_ACCESS:
2981 switch (len) {
2982 case 1:
2983 break;
2984 case 2:
2985 case 4:
2986 case 8:
2987 if (addr & (len - 1)) {
2988 return -EINVAL;
2989 }
2990 break;
2991 default:
2992 return -EINVAL;
2993 }
2994 break;
2995 default:
2996 return -ENOSYS;
2997 }
2998
2999 if (nb_hw_breakpoint == 4) {
3000 return -ENOBUFS;
3001 }
3002 if (find_hw_breakpoint(addr, len, type) >= 0) {
3003 return -EEXIST;
3004 }
3005 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3006 hw_breakpoint[nb_hw_breakpoint].len = len;
3007 hw_breakpoint[nb_hw_breakpoint].type = type;
3008 nb_hw_breakpoint++;
3009
3010 return 0;
3011 }
3012
3013 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3014 target_ulong len, int type)
3015 {
3016 int n;
3017
3018 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3019 if (n < 0) {
3020 return -ENOENT;
3021 }
3022 nb_hw_breakpoint--;
3023 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3024
3025 return 0;
3026 }
3027
3028 void kvm_arch_remove_all_hw_breakpoints(void)
3029 {
3030 nb_hw_breakpoint = 0;
3031 }
3032
3033 static CPUWatchpoint hw_watchpoint;
3034
3035 static int kvm_handle_debug(X86CPU *cpu,
3036 struct kvm_debug_exit_arch *arch_info)
3037 {
3038 CPUState *cs = CPU(cpu);
3039 CPUX86State *env = &cpu->env;
3040 int ret = 0;
3041 int n;
3042
3043 if (arch_info->exception == 1) {
3044 if (arch_info->dr6 & (1 << 14)) {
3045 if (cs->singlestep_enabled) {
3046 ret = EXCP_DEBUG;
3047 }
3048 } else {
3049 for (n = 0; n < 4; n++) {
3050 if (arch_info->dr6 & (1 << n)) {
3051 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3052 case 0x0:
3053 ret = EXCP_DEBUG;
3054 break;
3055 case 0x1:
3056 ret = EXCP_DEBUG;
3057 cs->watchpoint_hit = &hw_watchpoint;
3058 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3059 hw_watchpoint.flags = BP_MEM_WRITE;
3060 break;
3061 case 0x3:
3062 ret = EXCP_DEBUG;
3063 cs->watchpoint_hit = &hw_watchpoint;
3064 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3065 hw_watchpoint.flags = BP_MEM_ACCESS;
3066 break;
3067 }
3068 }
3069 }
3070 }
3071 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3072 ret = EXCP_DEBUG;
3073 }
3074 if (ret == 0) {
3075 cpu_synchronize_state(cs);
3076 assert(env->exception_injected == -1);
3077
3078 /* pass to guest */
3079 env->exception_injected = arch_info->exception;
3080 env->has_error_code = 0;
3081 }
3082
3083 return ret;
3084 }
3085
3086 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3087 {
3088 const uint8_t type_code[] = {
3089 [GDB_BREAKPOINT_HW] = 0x0,
3090 [GDB_WATCHPOINT_WRITE] = 0x1,
3091 [GDB_WATCHPOINT_ACCESS] = 0x3
3092 };
3093 const uint8_t len_code[] = {
3094 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3095 };
3096 int n;
3097
3098 if (kvm_sw_breakpoints_active(cpu)) {
3099 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3100 }
3101 if (nb_hw_breakpoint > 0) {
3102 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3103 dbg->arch.debugreg[7] = 0x0600;
3104 for (n = 0; n < nb_hw_breakpoint; n++) {
3105 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3106 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3107 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3108 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3109 }
3110 }
3111 }
3112
3113 static bool host_supports_vmx(void)
3114 {
3115 uint32_t ecx, unused;
3116
3117 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3118 return ecx & CPUID_EXT_VMX;
3119 }
3120
3121 #define VMX_INVALID_GUEST_STATE 0x80000021
3122
3123 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3124 {
3125 X86CPU *cpu = X86_CPU(cs);
3126 uint64_t code;
3127 int ret;
3128
3129 switch (run->exit_reason) {
3130 case KVM_EXIT_HLT:
3131 DPRINTF("handle_hlt\n");
3132 qemu_mutex_lock_iothread();
3133 ret = kvm_handle_halt(cpu);
3134 qemu_mutex_unlock_iothread();
3135 break;
3136 case KVM_EXIT_SET_TPR:
3137 ret = 0;
3138 break;
3139 case KVM_EXIT_TPR_ACCESS:
3140 qemu_mutex_lock_iothread();
3141 ret = kvm_handle_tpr_access(cpu);
3142 qemu_mutex_unlock_iothread();
3143 break;
3144 case KVM_EXIT_FAIL_ENTRY:
3145 code = run->fail_entry.hardware_entry_failure_reason;
3146 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3147 code);
3148 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3149 fprintf(stderr,
3150 "\nIf you're running a guest on an Intel machine without "
3151 "unrestricted mode\n"
3152 "support, the failure can be most likely due to the guest "
3153 "entering an invalid\n"
3154 "state for Intel VT. For example, the guest maybe running "
3155 "in big real mode\n"
3156 "which is not supported on less recent Intel processors."
3157 "\n\n");
3158 }
3159 ret = -1;
3160 break;
3161 case KVM_EXIT_EXCEPTION:
3162 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3163 run->ex.exception, run->ex.error_code);
3164 ret = -1;
3165 break;
3166 case KVM_EXIT_DEBUG:
3167 DPRINTF("kvm_exit_debug\n");
3168 qemu_mutex_lock_iothread();
3169 ret = kvm_handle_debug(cpu, &run->debug.arch);
3170 qemu_mutex_unlock_iothread();
3171 break;
3172 case KVM_EXIT_HYPERV:
3173 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3174 break;
3175 case KVM_EXIT_IOAPIC_EOI:
3176 ioapic_eoi_broadcast(run->eoi.vector);
3177 ret = 0;
3178 break;
3179 default:
3180 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3181 ret = -1;
3182 break;
3183 }
3184
3185 return ret;
3186 }
3187
3188 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3189 {
3190 X86CPU *cpu = X86_CPU(cs);
3191 CPUX86State *env = &cpu->env;
3192
3193 kvm_cpu_synchronize_state(cs);
3194 return !(env->cr[0] & CR0_PE_MASK) ||
3195 ((env->segs[R_CS].selector & 3) != 3);
3196 }
3197
3198 void kvm_arch_init_irq_routing(KVMState *s)
3199 {
3200 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3201 /* If kernel can't do irq routing, interrupt source
3202 * override 0->2 cannot be set up as required by HPET.
3203 * So we have to disable it.
3204 */
3205 no_hpet = 1;
3206 }
3207 /* We know at this point that we're using the in-kernel
3208 * irqchip, so we can use irqfds, and on x86 we know
3209 * we can use msi via irqfd and GSI routing.
3210 */
3211 kvm_msi_via_irqfd_allowed = true;
3212 kvm_gsi_routing_allowed = true;
3213
3214 if (kvm_irqchip_is_split()) {
3215 int i;
3216
3217 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3218 MSI routes for signaling interrupts to the local apics. */
3219 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3220 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3221 error_report("Could not enable split IRQ mode.");
3222 exit(1);
3223 }
3224 }
3225 }
3226 }
3227
3228 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3229 {
3230 int ret;
3231 if (machine_kernel_irqchip_split(ms)) {
3232 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3233 if (ret) {
3234 error_report("Could not enable split irqchip mode: %s",
3235 strerror(-ret));
3236 exit(1);
3237 } else {
3238 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3239 kvm_split_irqchip = true;
3240 return 1;
3241 }
3242 } else {
3243 return 0;
3244 }
3245 }
3246
3247 /* Classic KVM device assignment interface. Will remain x86 only. */
3248 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3249 uint32_t flags, uint32_t *dev_id)
3250 {
3251 struct kvm_assigned_pci_dev dev_data = {
3252 .segnr = dev_addr->domain,
3253 .busnr = dev_addr->bus,
3254 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3255 .flags = flags,
3256 };
3257 int ret;
3258
3259 dev_data.assigned_dev_id =
3260 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3261
3262 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3263 if (ret < 0) {
3264 return ret;
3265 }
3266
3267 *dev_id = dev_data.assigned_dev_id;
3268
3269 return 0;
3270 }
3271
3272 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3273 {
3274 struct kvm_assigned_pci_dev dev_data = {
3275 .assigned_dev_id = dev_id,
3276 };
3277
3278 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3279 }
3280
3281 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3282 uint32_t irq_type, uint32_t guest_irq)
3283 {
3284 struct kvm_assigned_irq assigned_irq = {
3285 .assigned_dev_id = dev_id,
3286 .guest_irq = guest_irq,
3287 .flags = irq_type,
3288 };
3289
3290 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3291 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3292 } else {
3293 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3294 }
3295 }
3296
3297 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3298 uint32_t guest_irq)
3299 {
3300 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3301 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3302
3303 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3304 }
3305
3306 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3307 {
3308 struct kvm_assigned_pci_dev dev_data = {
3309 .assigned_dev_id = dev_id,
3310 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3311 };
3312
3313 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3314 }
3315
3316 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3317 uint32_t type)
3318 {
3319 struct kvm_assigned_irq assigned_irq = {
3320 .assigned_dev_id = dev_id,
3321 .flags = type,
3322 };
3323
3324 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3325 }
3326
3327 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3328 {
3329 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3330 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3331 }
3332
3333 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3334 {
3335 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3336 KVM_DEV_IRQ_GUEST_MSI, virq);
3337 }
3338
3339 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3340 {
3341 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3342 KVM_DEV_IRQ_HOST_MSI);
3343 }
3344
3345 bool kvm_device_msix_supported(KVMState *s)
3346 {
3347 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3348 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3349 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3350 }
3351
3352 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3353 uint32_t nr_vectors)
3354 {
3355 struct kvm_assigned_msix_nr msix_nr = {
3356 .assigned_dev_id = dev_id,
3357 .entry_nr = nr_vectors,
3358 };
3359
3360 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3361 }
3362
3363 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3364 int virq)
3365 {
3366 struct kvm_assigned_msix_entry msix_entry = {
3367 .assigned_dev_id = dev_id,
3368 .gsi = virq,
3369 .entry = vector,
3370 };
3371
3372 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3373 }
3374
3375 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3376 {
3377 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3378 KVM_DEV_IRQ_GUEST_MSIX, 0);
3379 }
3380
3381 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3382 {
3383 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3384 KVM_DEV_IRQ_HOST_MSIX);
3385 }
3386
3387 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3388 uint64_t address, uint32_t data, PCIDevice *dev)
3389 {
3390 X86IOMMUState *iommu = x86_iommu_get_default();
3391
3392 if (iommu) {
3393 int ret;
3394 MSIMessage src, dst;
3395 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3396
3397 src.address = route->u.msi.address_hi;
3398 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3399 src.address |= route->u.msi.address_lo;
3400 src.data = route->u.msi.data;
3401
3402 ret = class->int_remap(iommu, &src, &dst, dev ? \
3403 pci_requester_id(dev) : \
3404 X86_IOMMU_SID_INVALID);
3405 if (ret) {
3406 trace_kvm_x86_fixup_msi_error(route->gsi);
3407 return 1;
3408 }
3409
3410 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3411 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3412 route->u.msi.data = dst.data;
3413 }
3414
3415 return 0;
3416 }
3417
3418 typedef struct MSIRouteEntry MSIRouteEntry;
3419
3420 struct MSIRouteEntry {
3421 PCIDevice *dev; /* Device pointer */
3422 int vector; /* MSI/MSIX vector index */
3423 int virq; /* Virtual IRQ index */
3424 QLIST_ENTRY(MSIRouteEntry) list;
3425 };
3426
3427 /* List of used GSI routes */
3428 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3429 QLIST_HEAD_INITIALIZER(msi_route_list);
3430
3431 static void kvm_update_msi_routes_all(void *private, bool global,
3432 uint32_t index, uint32_t mask)
3433 {
3434 int cnt = 0;
3435 MSIRouteEntry *entry;
3436 MSIMessage msg;
3437 PCIDevice *dev;
3438
3439 /* TODO: explicit route update */
3440 QLIST_FOREACH(entry, &msi_route_list, list) {
3441 cnt++;
3442 dev = entry->dev;
3443 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3444 continue;
3445 }
3446 msg = pci_get_msi_message(dev, entry->vector);
3447 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3448 }
3449 kvm_irqchip_commit_routes(kvm_state);
3450 trace_kvm_x86_update_msi_routes(cnt);
3451 }
3452
3453 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3454 int vector, PCIDevice *dev)
3455 {
3456 static bool notify_list_inited = false;
3457 MSIRouteEntry *entry;
3458
3459 if (!dev) {
3460 /* These are (possibly) IOAPIC routes only used for split
3461 * kernel irqchip mode, while what we are housekeeping are
3462 * PCI devices only. */
3463 return 0;
3464 }
3465
3466 entry = g_new0(MSIRouteEntry, 1);
3467 entry->dev = dev;
3468 entry->vector = vector;
3469 entry->virq = route->gsi;
3470 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3471
3472 trace_kvm_x86_add_msi_route(route->gsi);
3473
3474 if (!notify_list_inited) {
3475 /* For the first time we do add route, add ourselves into
3476 * IOMMU's IEC notify list if needed. */
3477 X86IOMMUState *iommu = x86_iommu_get_default();
3478 if (iommu) {
3479 x86_iommu_iec_register_notifier(iommu,
3480 kvm_update_msi_routes_all,
3481 NULL);
3482 }
3483 notify_list_inited = true;
3484 }
3485 return 0;
3486 }
3487
3488 int kvm_arch_release_virq_post(int virq)
3489 {
3490 MSIRouteEntry *entry, *next;
3491 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3492 if (entry->virq == virq) {
3493 trace_kvm_x86_remove_msi_route(virq);
3494 QLIST_REMOVE(entry, list);
3495 break;
3496 }
3497 }
3498 return 0;
3499 }
3500
3501 int kvm_arch_msi_data_to_gsi(uint32_t data)
3502 {
3503 abort();
3504 }
AR7 emulation for QEMU