target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 //#define DEBUG_OP
   5
   6 #define ALIGNED_ONLY
   7
   8 #define CPUArchState struct CPUMIPSState
   9
  10 #include "qemu-common.h"
  11 #include "cpu-qom.h"
  12 #include "mips-defs.h"
  13 #include "exec/cpu-defs.h"
  14 #include "fpu/softfloat.h"
  15
  16 struct CPUMIPSState;
  17
  18 typedef struct r4k_tlb_t r4k_tlb_t;
  19 struct r4k_tlb_t {
  20     target_ulong VPN;
  21     uint32_t PageMask;
  22     uint8_t ASID;
  23     unsigned int G:1;
  24     unsigned int C0:3;
  25     unsigned int C1:3;
  26     unsigned int V0:1;
  27     unsigned int V1:1;
  28     unsigned int D0:1;
  29     unsigned int D1:1;
  30     unsigned int XI0:1;
  31     unsigned int XI1:1;
  32     unsigned int RI0:1;
  33     unsigned int RI1:1;
  34     unsigned int EHINV:1;
  35     uint64_t PFN[2];
  36 };
  37
  38 #if !defined(CONFIG_USER_ONLY)
  39 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  40 struct CPUMIPSTLBContext {
  41     uint32_t nb_tlb;
  42     uint32_t tlb_in_use;
  43     int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
  44     void (*helper_tlbwi)(struct CPUMIPSState *env);
  45     void (*helper_tlbwr)(struct CPUMIPSState *env);
  46     void (*helper_tlbp)(struct CPUMIPSState *env);
  47     void (*helper_tlbr)(struct CPUMIPSState *env);
  48     void (*helper_tlbinv)(struct CPUMIPSState *env);
  49     void (*helper_tlbinvf)(struct CPUMIPSState *env);
  50     union {
  51         struct {
  52             r4k_tlb_t tlb[MIPS_TLB_MAX];
  53         } r4k;
  54     } mmu;
  55 };
  56 #endif
  57
  58 /* MSA Context */
  59 #define MSA_WRLEN (128)
  60
  61 enum CPUMIPSMSADataFormat {
  62     DF_BYTE = 0,
  63     DF_HALF,
  64     DF_WORD,
  65     DF_DOUBLE
  66 };
  67
  68 typedef union wr_t wr_t;
  69 union wr_t {
  70     int8_t  b[MSA_WRLEN/8];
  71     int16_t h[MSA_WRLEN/16];
  72     int32_t w[MSA_WRLEN/32];
  73     int64_t d[MSA_WRLEN/64];
  74 };
  75
  76 typedef union fpr_t fpr_t;
  77 union fpr_t {
  78     float64  fd;   /* ieee double precision */
  79     float32  fs[2];/* ieee single precision */
  80     uint64_t d;    /* binary double fixed-point */
  81     uint32_t w[2]; /* binary single fixed-point */
  82 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  83     wr_t     wr;   /* vector data */
  84 };
  85 /* define FP_ENDIAN_IDX to access the same location
  86  * in the fpr_t union regardless of the host endianness
  87  */
  88 #if defined(HOST_WORDS_BIGENDIAN)
  89 #  define FP_ENDIAN_IDX 1
  90 #else
  91 #  define FP_ENDIAN_IDX 0
  92 #endif
  93
  94 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  95 struct CPUMIPSFPUContext {
  96     /* Floating point registers */
  97     fpr_t fpr[32];
  98     float_status fp_status;
  99     /* fpu implementation/revision register (fir) */
 100     uint32_t fcr0;
 101 #define FCR0_FREP 29
 102 #define FCR0_UFRP 28
 103 #define FCR0_HAS2008 23
 104 #define FCR0_F64 22
 105 #define FCR0_L 21
 106 #define FCR0_W 20
 107 #define FCR0_3D 19
 108 #define FCR0_PS 18
 109 #define FCR0_D 17
 110 #define FCR0_S 16
 111 #define FCR0_PRID 8
 112 #define FCR0_REV 0
 113     /* fcsr */
 114     uint32_t fcr31_rw_bitmask;
 115     uint32_t fcr31;
 116 #define FCR31_FS 24
 117 #define FCR31_ABS2008 19
 118 #define FCR31_NAN2008 18
 119 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 120 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
 121 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
 122 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
 123 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
 124 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
 125 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
 126 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
 127 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
 128 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
 129 #define FP_INEXACT        1
 130 #define FP_UNDERFLOW      2
 131 #define FP_OVERFLOW       4
 132 #define FP_DIV0           8
 133 #define FP_INVALID        16
 134 #define FP_UNIMPLEMENTED  32
 135 };
 136
 137 #define NB_MMU_MODES 3
 138 #define TARGET_INSN_START_EXTRA_WORDS 2
 139
 140 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 141 struct CPUMIPSMVPContext {
 142     int32_t CP0_MVPControl;
 143 #define CP0MVPCo_CPA    3
 144 #define CP0MVPCo_STLB   2
 145 #define CP0MVPCo_VPC    1
 146 #define CP0MVPCo_EVP    0
 147     int32_t CP0_MVPConf0;
 148 #define CP0MVPC0_M      31
 149 #define CP0MVPC0_TLBS   29
 150 #define CP0MVPC0_GS     28
 151 #define CP0MVPC0_PCP    27
 152 #define CP0MVPC0_PTLBE  16
 153 #define CP0MVPC0_TCA    15
 154 #define CP0MVPC0_PVPE   10
 155 #define CP0MVPC0_PTC    0
 156     int32_t CP0_MVPConf1;
 157 #define CP0MVPC1_CIM    31
 158 #define CP0MVPC1_CIF    30
 159 #define CP0MVPC1_PCX    20
 160 #define CP0MVPC1_PCP2   10
 161 #define CP0MVPC1_PCP1   0
 162 };
 163
 164 typedef struct mips_def_t mips_def_t;
 165
 166 #define MIPS_SHADOW_SET_MAX 16
 167 #define MIPS_TC_MAX 5
 168 #define MIPS_FPU_MAX 1
 169 #define MIPS_DSP_ACC 4
 170 #define MIPS_KSCRATCH_NUM 6
 171 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
 172
 173 typedef struct TCState TCState;
 174 struct TCState {
 175     target_ulong gpr[32];
 176     target_ulong PC;
 177     target_ulong HI[MIPS_DSP_ACC];
 178     target_ulong LO[MIPS_DSP_ACC];
 179     target_ulong ACX[MIPS_DSP_ACC];
 180     target_ulong DSPControl;
 181     int32_t CP0_TCStatus;
 182 #define CP0TCSt_TCU3    31
 183 #define CP0TCSt_TCU2    30
 184 #define CP0TCSt_TCU1    29
 185 #define CP0TCSt_TCU0    28
 186 #define CP0TCSt_TMX     27
 187 #define CP0TCSt_RNST    23
 188 #define CP0TCSt_TDS     21
 189 #define CP0TCSt_DT      20
 190 #define CP0TCSt_DA      15
 191 #define CP0TCSt_A       13
 192 #define CP0TCSt_TKSU    11
 193 #define CP0TCSt_IXMT    10
 194 #define CP0TCSt_TASID   0
 195     int32_t CP0_TCBind;
 196 #define CP0TCBd_CurTC   21
 197 #define CP0TCBd_TBE     17
 198 #define CP0TCBd_CurVPE  0
 199     target_ulong CP0_TCHalt;
 200     target_ulong CP0_TCContext;
 201     target_ulong CP0_TCSchedule;
 202     target_ulong CP0_TCScheFBack;
 203     int32_t CP0_Debug_tcstatus;
 204     target_ulong CP0_UserLocal;
 205
 206     int32_t msacsr;
 207
 208 #define MSACSR_FS       24
 209 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 210 #define MSACSR_NX       18
 211 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 212 #define MSACSR_CEF      2
 213 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 214 #define MSACSR_RM       0
 215 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 216 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 217         MSACSR_FS_MASK)
 218
 219     float_status msa_fp_status;
 220 };
 221
 222 typedef struct CPUMIPSState CPUMIPSState;
 223 struct CPUMIPSState {
 224     TCState active_tc;
 225     CPUMIPSFPUContext active_fpu;
 226
 227     uint32_t current_tc;
 228     uint32_t current_fpu;
 229
 230     uint32_t SEGBITS;
 231     uint32_t PABITS;
 232 #if defined(TARGET_MIPS64)
 233 # define PABITS_BASE 36
 234 #else
 235 # define PABITS_BASE 32
 236 #endif
 237     target_ulong SEGMask;
 238     uint64_t PAMask;
 239 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 240
 241     int32_t msair;
 242 #define MSAIR_ProcID    8
 243 #define MSAIR_Rev       0
 244
 245     int32_t CP0_Index;
 246     /* CP0_MVP* are per MVP registers. */
 247     int32_t CP0_VPControl;
 248 #define CP0VPCtl_DIS    0
 249     int32_t CP0_Random;
 250     int32_t CP0_VPEControl;
 251 #define CP0VPECo_YSI    21
 252 #define CP0VPECo_GSI    20
 253 #define CP0VPECo_EXCPT  16
 254 #define CP0VPECo_TE     15
 255 #define CP0VPECo_TargTC 0
 256     int32_t CP0_VPEConf0;
 257 #define CP0VPEC0_M      31
 258 #define CP0VPEC0_XTC    21
 259 #define CP0VPEC0_TCS    19
 260 #define CP0VPEC0_SCS    18
 261 #define CP0VPEC0_DSC    17
 262 #define CP0VPEC0_ICS    16
 263 #define CP0VPEC0_MVP    1
 264 #define CP0VPEC0_VPA    0
 265     int32_t CP0_VPEConf1;
 266 #define CP0VPEC1_NCX    20
 267 #define CP0VPEC1_NCP2   10
 268 #define CP0VPEC1_NCP1   0
 269     target_ulong CP0_YQMask;
 270     target_ulong CP0_VPESchedule;
 271     target_ulong CP0_VPEScheFBack;
 272     int32_t CP0_VPEOpt;
 273 #define CP0VPEOpt_IWX7  15
 274 #define CP0VPEOpt_IWX6  14
 275 #define CP0VPEOpt_IWX5  13
 276 #define CP0VPEOpt_IWX4  12
 277 #define CP0VPEOpt_IWX3  11
 278 #define CP0VPEOpt_IWX2  10
 279 #define CP0VPEOpt_IWX1  9
 280 #define CP0VPEOpt_IWX0  8
 281 #define CP0VPEOpt_DWX7  7
 282 #define CP0VPEOpt_DWX6  6
 283 #define CP0VPEOpt_DWX5  5
 284 #define CP0VPEOpt_DWX4  4
 285 #define CP0VPEOpt_DWX3  3
 286 #define CP0VPEOpt_DWX2  2
 287 #define CP0VPEOpt_DWX1  1
 288 #define CP0VPEOpt_DWX0  0
 289     uint64_t CP0_EntryLo0;
 290     uint64_t CP0_EntryLo1;
 291 #if defined(TARGET_MIPS64)
 292 # define CP0EnLo_RI 63
 293 # define CP0EnLo_XI 62
 294 #else
 295 # define CP0EnLo_RI 31
 296 # define CP0EnLo_XI 30
 297 #endif
 298     int32_t CP0_GlobalNumber;
 299 #define CP0GN_VPId 0
 300     target_ulong CP0_Context;
 301     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 302     int32_t CP0_PageMask;
 303     int32_t CP0_PageGrain_rw_bitmask;
 304     int32_t CP0_PageGrain;
 305 #define CP0PG_RIE 31
 306 #define CP0PG_XIE 30
 307 #define CP0PG_ELPA 29
 308 #define CP0PG_IEC 27
 309     int32_t CP0_Wired;
 310     int32_t CP0_SRSConf0_rw_bitmask;
 311     int32_t CP0_SRSConf0;
 312 #define CP0SRSC0_M      31
 313 #define CP0SRSC0_SRS3   20
 314 #define CP0SRSC0_SRS2   10
 315 #define CP0SRSC0_SRS1   0
 316     int32_t CP0_SRSConf1_rw_bitmask;
 317     int32_t CP0_SRSConf1;
 318 #define CP0SRSC1_M      31
 319 #define CP0SRSC1_SRS6   20
 320 #define CP0SRSC1_SRS5   10
 321 #define CP0SRSC1_SRS4   0
 322     int32_t CP0_SRSConf2_rw_bitmask;
 323     int32_t CP0_SRSConf2;
 324 #define CP0SRSC2_M      31
 325 #define CP0SRSC2_SRS9   20
 326 #define CP0SRSC2_SRS8   10
 327 #define CP0SRSC2_SRS7   0
 328     int32_t CP0_SRSConf3_rw_bitmask;
 329     int32_t CP0_SRSConf3;
 330 #define CP0SRSC3_M      31
 331 #define CP0SRSC3_SRS12  20
 332 #define CP0SRSC3_SRS11  10
 333 #define CP0SRSC3_SRS10  0
 334     int32_t CP0_SRSConf4_rw_bitmask;
 335     int32_t CP0_SRSConf4;
 336 #define CP0SRSC4_SRS15  20
 337 #define CP0SRSC4_SRS14  10
 338 #define CP0SRSC4_SRS13  0
 339     int32_t CP0_HWREna;
 340     target_ulong CP0_BadVAddr;
 341     uint32_t CP0_BadInstr;
 342     uint32_t CP0_BadInstrP;
 343     int32_t CP0_Count;
 344     target_ulong CP0_EntryHi;
 345 #define CP0EnHi_EHINV 10
 346     int32_t CP0_Compare;
 347     int32_t CP0_Status;
 348 #define CP0St_CU3   31
 349 #define CP0St_CU2   30
 350 #define CP0St_CU1   29
 351 #define CP0St_CU0   28
 352 #define CP0St_RP    27
 353 #define CP0St_FR    26
 354 #define CP0St_RE    25
 355 #define CP0St_MX    24
 356 #define CP0St_PX    23
 357 #define CP0St_BEV   22
 358 #define CP0St_TS    21
 359 #define CP0St_SR    20
 360 #define CP0St_NMI   19
 361 #define CP0St_IM    8
 362 #define CP0St_KX    7
 363 #define CP0St_SX    6
 364 #define CP0St_UX    5
 365 #define CP0St_KSU   3
 366 #define CP0St_ERL   2
 367 #define CP0St_EXL   1
 368 #define CP0St_IE    0
 369     int32_t CP0_IntCtl;
 370 #define CP0IntCtl_IPTI 29
 371 #define CP0IntCtl_IPPCI 26
 372 #define CP0IntCtl_VS 5
 373     int32_t CP0_SRSCtl;
 374 #define CP0SRSCtl_HSS 26
 375 #define CP0SRSCtl_EICSS 18
 376 #define CP0SRSCtl_ESS 12
 377 #define CP0SRSCtl_PSS 6
 378 #define CP0SRSCtl_CSS 0
 379     int32_t CP0_SRSMap;
 380 #define CP0SRSMap_SSV7 28
 381 #define CP0SRSMap_SSV6 24
 382 #define CP0SRSMap_SSV5 20
 383 #define CP0SRSMap_SSV4 16
 384 #define CP0SRSMap_SSV3 12
 385 #define CP0SRSMap_SSV2 8
 386 #define CP0SRSMap_SSV1 4
 387 #define CP0SRSMap_SSV0 0
 388     int32_t CP0_Cause;
 389 #define CP0Ca_BD   31
 390 #define CP0Ca_TI   30
 391 #define CP0Ca_CE   28
 392 #define CP0Ca_DC   27
 393 #define CP0Ca_PCI  26
 394 #define CP0Ca_IV   23
 395 #define CP0Ca_WP   22
 396 #define CP0Ca_IP    8
 397 #define CP0Ca_IP_mask 0x0000FF00
 398 #define CP0Ca_EC    2
 399     target_ulong CP0_EPC;
 400     int32_t CP0_PRid;
 401     int32_t CP0_EBase;
 402     target_ulong CP0_CMGCRBase;
 403     int32_t CP0_Config0;
 404 #define CP0C0_M    31
 405 #define CP0C0_K23  28
 406 #define CP0C0_KU   25
 407 #define CP0C0_MDU  20
 408 #define CP0C0_MM   18
 409 #define CP0C0_BM   16
 410 #define CP0C0_BE   15
 411 #define CP0C0_AT   13
 412 #define CP0C0_AR   10
 413 #define CP0C0_MT   7
 414 #define CP0C0_VI   3
 415 #define CP0C0_K0   0
 416     int32_t CP0_Config1;
 417 #define CP0C1_M    31
 418 #define CP0C1_MMU  25
 419 #define CP0C1_IS   22
 420 #define CP0C1_IL   19
 421 #define CP0C1_IA   16
 422 #define CP0C1_DS   13
 423 #define CP0C1_DL   10
 424 #define CP0C1_DA   7
 425 #define CP0C1_C2   6
 426 #define CP0C1_MD   5
 427 #define CP0C1_PC   4
 428 #define CP0C1_WR   3
 429 #define CP0C1_CA   2
 430 #define CP0C1_EP   1
 431 #define CP0C1_FP   0
 432     int32_t CP0_Config2;
 433 #define CP0C2_M    31
 434 #define CP0C2_TU   28
 435 #define CP0C2_TS   24
 436 #define CP0C2_TL   20
 437 #define CP0C2_TA   16
 438 #define CP0C2_SU   12
 439 #define CP0C2_SS   8
 440 #define CP0C2_SL   4
 441 #define CP0C2_SA   0
 442     int32_t CP0_Config3;
 443 #define CP0C3_M    31
 444 #define CP0C3_BPG  30
 445 #define CP0C3_CMGCR 29
 446 #define CP0C3_MSAP  28
 447 #define CP0C3_BP 27
 448 #define CP0C3_BI 26
 449 #define CP0C3_IPLW 21
 450 #define CP0C3_MMAR 18
 451 #define CP0C3_MCU  17
 452 #define CP0C3_ISA_ON_EXC 16
 453 #define CP0C3_ISA  14
 454 #define CP0C3_ULRI 13
 455 #define CP0C3_RXI  12
 456 #define CP0C3_DSP2P 11
 457 #define CP0C3_DSPP 10
 458 #define CP0C3_LPA  7
 459 #define CP0C3_VEIC 6
 460 #define CP0C3_VInt 5
 461 #define CP0C3_SP   4
 462 #define CP0C3_CDMM 3
 463 #define CP0C3_MT   2
 464 #define CP0C3_SM   1
 465 #define CP0C3_TL   0
 466     int32_t CP0_Config4;
 467     int32_t CP0_Config4_rw_bitmask;
 468 #define CP0C4_M    31
 469 #define CP0C4_IE   29
 470 #define CP0C4_KScrExist 16
 471 #define CP0C4_MMUExtDef 14
 472 #define CP0C4_FTLBPageSize 8
 473 #define CP0C4_FTLBWays 4
 474 #define CP0C4_FTLBSets 0
 475 #define CP0C4_MMUSizeExt 0
 476     int32_t CP0_Config5;
 477     int32_t CP0_Config5_rw_bitmask;
 478 #define CP0C5_M          31
 479 #define CP0C5_K          30
 480 #define CP0C5_CV         29
 481 #define CP0C5_EVA        28
 482 #define CP0C5_MSAEn      27
 483 #define CP0C5_XNP        13
 484 #define CP0C5_UFE        9
 485 #define CP0C5_FRE        8
 486 #define CP0C5_VP         7
 487 #define CP0C5_SBRI       6
 488 #define CP0C5_MVH        5
 489 #define CP0C5_LLB        4
 490 #define CP0C5_MRP        3
 491 #define CP0C5_UFR        2
 492 #define CP0C5_NFExists   0
 493     int32_t CP0_Config6;
 494     int32_t CP0_Config7;
 495     uint64_t CP0_MAAR[MIPS_MAAR_MAX];
 496     int32_t CP0_MAARI;
 497     /* XXX: Maybe make LLAddr per-TC? */
 498     uint64_t lladdr;
 499     target_ulong llval;
 500     target_ulong llnewval;
 501     target_ulong llreg;
 502     uint64_t CP0_LLAddr_rw_bitmask;
 503     int CP0_LLAddr_shift;
 504     target_ulong CP0_WatchLo[8];
 505     int32_t CP0_WatchHi[8];
 506     target_ulong CP0_XContext;
 507     int32_t CP0_Framemask;
 508     int32_t CP0_Debug;
 509 #define CP0DB_DBD  31
 510 #define CP0DB_DM   30
 511 #define CP0DB_LSNM 28
 512 #define CP0DB_Doze 27
 513 #define CP0DB_Halt 26
 514 #define CP0DB_CNT  25
 515 #define CP0DB_IBEP 24
 516 #define CP0DB_DBEP 21
 517 #define CP0DB_IEXI 20
 518 #define CP0DB_VER  15
 519 #define CP0DB_DEC  10
 520 #define CP0DB_SSt  8
 521 #define CP0DB_DINT 5
 522 #define CP0DB_DIB  4
 523 #define CP0DB_DDBS 3
 524 #define CP0DB_DDBL 2
 525 #define CP0DB_DBp  1
 526 #define CP0DB_DSS  0
 527     target_ulong CP0_DEPC;
 528     int32_t CP0_Performance0;
 529     int32_t CP0_ErrCtl;
 530 #define CP0EC_WST 29
 531 #define CP0EC_SPR 28
 532 #define CP0EC_ITC 26
 533     uint64_t CP0_TagLo;
 534     int32_t CP0_DataLo;
 535     int32_t CP0_TagHi;
 536     int32_t CP0_DataHi;
 537     target_ulong CP0_ErrorEPC;
 538     int32_t CP0_DESAVE;
 539     /* We waste some space so we can handle shadow registers like TCs. */
 540     TCState tcs[MIPS_SHADOW_SET_MAX];
 541     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 542     /* QEMU */
 543     int error_code;
 544 #define EXCP_TLB_NOMATCH   0x1
 545 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
 546     uint32_t hflags;    /* CPU State */
 547     /* TMASK defines different execution modes */
 548 #define MIPS_HFLAG_TMASK  0xF5807FF
 549 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
 550     /* The KSU flags must be the lowest bits in hflags. The flag order
 551        must be the same as defined for CP0 Status. This allows to use
 552        the bits as the value of mmu_idx. */
 553 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
 554 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
 555 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
 556 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
 557 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
 558 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
 559 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
 560 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
 561 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
 562     /* True if the MIPS IV COP1X instructions can be used.  This also
 563        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 564        and RSQRT.D.  */
 565 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
 566 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
 567 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
 568 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
 569 #define MIPS_HFLAG_M16_SHIFT 10
 570     /* If translation is interrupted between the branch instruction and
 571      * the delay slot, record what type of branch it is so that we can
 572      * resume translation properly.  It might be possible to reduce
 573      * this from three bits to two.  */
 574 #define MIPS_HFLAG_BMASK_BASE  0x803800
 575 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
 576 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
 577 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
 578 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
 579     /* Extra flags about the current pending branch.  */
 580 #define MIPS_HFLAG_BMASK_EXT 0x7C000
 581 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
 582 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
 583 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
 584 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
 585 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
 586 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
 587     /* MIPS DSP resources access. */
 588 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 589 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
 590     /* Extra flag about HWREna register. */
 591 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 592 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
 593 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
 594 #define MIPS_HFLAG_MSA   0x1000000
 595 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
 596 #define MIPS_HFLAG_ELPA  0x4000000
 597 #define MIPS_HFLAG_ITC_CACHE  0x8000000 /* CACHE instr. operates on ITC tag */
 598     target_ulong btarget;        /* Jump / branch target               */
 599     target_ulong bcond;          /* Branch condition (if needed)       */
 600
 601     int SYNCI_Step; /* Address step size for SYNCI */
 602     int CCRes; /* Cycle count resolution/divisor */
 603     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 604     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 605     int insn_flags; /* Supported instruction set */
 606
 607     CPU_COMMON
 608
 609     /* Fields from here on are preserved across CPU reset. */
 610     CPUMIPSMVPContext *mvp;
 611 #if !defined(CONFIG_USER_ONLY)
 612     CPUMIPSTLBContext *tlb;
 613 #endif
 614
 615     const mips_def_t *cpu_model;
 616     void *irq[8];
 617     QEMUTimer *timer; /* Internal timer */
 618     MemoryRegion *itc_tag; /* ITC Configuration Tags */
 619 };
 620
 621 /**
 622  * MIPSCPU:
 623  * @env: #CPUMIPSState
 624  *
 625  * A MIPS CPU.
 626  */
 627 struct MIPSCPU {
 628     /*< private >*/
 629     CPUState parent_obj;
 630     /*< public >*/
 631
 632     CPUMIPSState env;
 633 };
 634
 635 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
 636 {
 637     return container_of(env, MIPSCPU, env);
 638 }
 639
 640 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
 641
 642 #define ENV_OFFSET offsetof(MIPSCPU, env)
 643
 644 #ifndef CONFIG_USER_ONLY
 645 extern const struct VMStateDescription vmstate_mips_cpu;
 646 #endif
 647
 648 void mips_cpu_do_interrupt(CPUState *cpu);
 649 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
 650 void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 651                          int flags);
 652 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 653 int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 654 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 655 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 656                                   int is_write, int is_user, uintptr_t retaddr);
 657
 658 #if !defined(CONFIG_USER_ONLY)
 659 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 660                         target_ulong address, int rw, int access_type);
 661 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 662                            target_ulong address, int rw, int access_type);
 663 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
 664                      target_ulong address, int rw, int access_type);
 665 void r4k_helper_tlbwi(CPUMIPSState *env);
 666 void r4k_helper_tlbwr(CPUMIPSState *env);
 667 void r4k_helper_tlbp(CPUMIPSState *env);
 668 void r4k_helper_tlbr(CPUMIPSState *env);
 669 void r4k_helper_tlbinv(CPUMIPSState *env);
 670 void r4k_helper_tlbinvf(CPUMIPSState *env);
 671
 672 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 673                                 bool is_write, bool is_exec, int unused,
 674                                 unsigned size);
 675 #endif
 676
 677 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
 678
 679 #define cpu_signal_handler cpu_mips_signal_handler
 680 #define cpu_list mips_cpu_list
 681
 682 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
 683 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
 684
 685 /* MMU modes definitions. We carefully match the indices with our
 686    hflags layout. */
 687 #define MMU_MODE0_SUFFIX _kernel
 688 #define MMU_MODE1_SUFFIX _super
 689 #define MMU_MODE2_SUFFIX _user
 690 #define MMU_USER_IDX 2
 691 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
 692 {
 693     return env->hflags & MIPS_HFLAG_KSU;
 694 }
 695
 696 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 697 {
 698     return (env->CP0_Status & (1 << CP0St_IE)) &&
 699         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 700         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 701         !(env->hflags & MIPS_HFLAG_DM) &&
 702         /* Note that the TCStatus IXMT field is initialized to zero,
 703            and only MT capable cores can set it to one. So we don't
 704            need to check for MT capabilities here.  */
 705         !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
 706 }
 707
 708 /* Check if there is pending and not masked out interrupt */
 709 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
 710 {
 711     int32_t pending;
 712     int32_t status;
 713     bool r;
 714
 715     pending = env->CP0_Cause & CP0Ca_IP_mask;
 716     status = env->CP0_Status & CP0Ca_IP_mask;
 717
 718     if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 719         /* A MIPS configured with a vectorizing external interrupt controller
 720            will feed a vector into the Cause pending lines. The core treats
 721            the status lines as a vector level, not as indiviual masks.  */
 722         r = pending > status;
 723     } else {
 724         /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
 725            treats the pending lines as individual interrupt lines, the status
 726            lines are individual masks.  */
 727         r = (pending & status) != 0;
 728     }
 729     return r;
 730 }
 731
 732 #include "exec/cpu-all.h"
 733
 734 /* Memory access type :
 735  * may be needed for precise access rights control and precise exceptions.
 736  */
 737 enum {
 738     /* 1 bit to define user level / supervisor access */
 739     ACCESS_USER  = 0x00,
 740     ACCESS_SUPER = 0x01,
 741     /* 1 bit to indicate direction */
 742     ACCESS_STORE = 0x02,
 743     /* Type of instruction that generated the access */
 744     ACCESS_CODE  = 0x10, /* Code fetch access                */
 745     ACCESS_INT   = 0x20, /* Integer load/store access        */
 746     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 747 };
 748
 749 /* Exceptions */
 750 enum {
 751     EXCP_NONE          = -1,
 752     EXCP_RESET         = 0,
 753     EXCP_SRESET,
 754     EXCP_DSS,
 755     EXCP_DINT,
 756     EXCP_DDBL,
 757     EXCP_DDBS,
 758     EXCP_NMI,
 759     EXCP_MCHECK,
 760     EXCP_EXT_INTERRUPT, /* 8 */
 761     EXCP_DFWATCH,
 762     EXCP_DIB,
 763     EXCP_IWATCH,
 764     EXCP_AdEL,
 765     EXCP_AdES,
 766     EXCP_TLBF,
 767     EXCP_IBE,
 768     EXCP_DBp, /* 16 */
 769     EXCP_SYSCALL,
 770     EXCP_BREAK,
 771     EXCP_CpU,
 772     EXCP_RI,
 773     EXCP_OVERFLOW,
 774     EXCP_TRAP,
 775     EXCP_FPE,
 776     EXCP_DWATCH, /* 24 */
 777     EXCP_LTLBL,
 778     EXCP_TLBL,
 779     EXCP_TLBS,
 780     EXCP_DBE,
 781     EXCP_THREAD,
 782     EXCP_MDMX,
 783     EXCP_C2E,
 784     EXCP_CACHE, /* 32 */
 785     EXCP_DSPDIS,
 786     EXCP_MSADIS,
 787     EXCP_MSAFPE,
 788     EXCP_TLBXI,
 789     EXCP_TLBRI,
 790
 791     EXCP_LAST = EXCP_TLBRI,
 792 };
 793 /* Dummy exception for conditional stores.  */
 794 #define EXCP_SC 0x100
 795
 796 /*
 797  * This is an interrnally generated WAKE request line.
 798  * It is driven by the CPU itself. Raised when the MT
 799  * block wants to wake a VPE from an inactive state and
 800  * cleared when VPE goes from active to inactive.
 801  */
 802 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
 803
 804 void mips_tcg_init(void);
 805 MIPSCPU *cpu_mips_init(const char *cpu_model);
 806 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 807
 808 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
 809 bool cpu_supports_cps_smp(const char *cpu_model);
 810
 811 /* TODO QOM'ify CPU reset and remove */
 812 void cpu_state_reset(CPUMIPSState *s);
 813
 814 /* mips_timer.c */
 815 uint32_t cpu_mips_get_random (CPUMIPSState *env);
 816 uint32_t cpu_mips_get_count (CPUMIPSState *env);
 817 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
 818 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
 819 void cpu_mips_start_count(CPUMIPSState *env);
 820 void cpu_mips_stop_count(CPUMIPSState *env);
 821
 822 /* mips_int.c */
 823 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
 824
 825 /* helper.c */
 826 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 827                               int mmu_idx);
 828
 829 /* op_helper.c */
 830 uint32_t float_class_s(uint32_t arg, float_status *fst);
 831 uint64_t float_class_d(uint64_t arg, float_status *fst);
 832
 833 #if !defined(CONFIG_USER_ONLY)
 834 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
 835 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
 836                                                int rw);
 837 #endif
 838 target_ulong exception_resume_pc (CPUMIPSState *env);
 839
 840 /* op_helper.c */
 841 extern unsigned int ieee_rm[];
 842 int ieee_ex_to_mips(int xcpt);
 843
 844 static inline void restore_rounding_mode(CPUMIPSState *env)
 845 {
 846     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
 847                             &env->active_fpu.fp_status);
 848 }
 849
 850 static inline void restore_flush_mode(CPUMIPSState *env)
 851 {
 852     set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
 853                       &env->active_fpu.fp_status);
 854 }
 855
 856 static inline void restore_snan_bit_mode(CPUMIPSState *env)
 857 {
 858     set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
 859                         &env->active_fpu.fp_status);
 860 }
 861
 862 static inline void restore_fp_status(CPUMIPSState *env)
 863 {
 864     restore_rounding_mode(env);
 865     restore_flush_mode(env);
 866     restore_snan_bit_mode(env);
 867 }
 868
 869 static inline void restore_msa_fp_status(CPUMIPSState *env)
 870 {
 871     float_status *status = &env->active_tc.msa_fp_status;
 872     int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
 873     bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
 874
 875     set_float_rounding_mode(ieee_rm[rounding_mode], status);
 876     set_flush_to_zero(flush_to_zero, status);
 877     set_flush_inputs_to_zero(flush_to_zero, status);
 878 }
 879
 880 static inline void restore_pamask(CPUMIPSState *env)
 881 {
 882     if (env->hflags & MIPS_HFLAG_ELPA) {
 883         env->PAMask = (1ULL << env->PABITS) - 1;
 884     } else {
 885         env->PAMask = PAMASK_BASE;
 886     }
 887 }
 888
 889 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
 890                                         target_ulong *cs_base, uint32_t *flags)
 891 {
 892     *pc = env->active_tc.PC;
 893     *cs_base = 0;
 894     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
 895                             MIPS_HFLAG_HWRENA_ULR);
 896 }
 897
 898 static inline int mips_vpe_active(CPUMIPSState *env)
 899 {
 900     int active = 1;
 901
 902     /* Check that the VPE is enabled.  */
 903     if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
 904         active = 0;
 905     }
 906     /* Check that the VPE is activated.  */
 907     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
 908         active = 0;
 909     }
 910
 911     /* Now verify that there are active thread contexts in the VPE.
 912
 913        This assumes the CPU model will internally reschedule threads
 914        if the active one goes to sleep. If there are no threads available
 915        the active one will be in a sleeping state, and we can turn off
 916        the entire VPE.  */
 917     if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
 918         /* TC is not activated.  */
 919         active = 0;
 920     }
 921     if (env->active_tc.CP0_TCHalt & 1) {
 922         /* TC is in halt state.  */
 923         active = 0;
 924     }
 925
 926     return active;
 927 }
 928
 929 static inline int mips_vp_active(CPUMIPSState *env)
 930 {
 931     CPUState *other_cs = first_cpu;
 932
 933     /* Check if the VP disabled other VPs (which means the VP is enabled) */
 934     if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
 935         return 1;
 936     }
 937
 938     /* Check if the virtual processor is disabled due to a DVP */
 939     CPU_FOREACH(other_cs) {
 940         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
 941         if ((&other_cpu->env != env) &&
 942             ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
 943             return 0;
 944         }
 945     }
 946     return 1;
 947 }
 948
 949 static inline void compute_hflags(CPUMIPSState *env)
 950 {
 951     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
 952                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
 953                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
 954                      MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
 955                      MIPS_HFLAG_ELPA);
 956     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
 957         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 958         !(env->hflags & MIPS_HFLAG_DM)) {
 959         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
 960     }
 961 #if defined(TARGET_MIPS64)
 962     if ((env->insn_flags & ISA_MIPS3) &&
 963         (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
 964          (env->CP0_Status & (1 << CP0St_PX)) ||
 965          (env->CP0_Status & (1 << CP0St_UX)))) {
 966         env->hflags |= MIPS_HFLAG_64;
 967     }
 968
 969     if (!(env->insn_flags & ISA_MIPS3)) {
 970         env->hflags |= MIPS_HFLAG_AWRAP;
 971     } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
 972                !(env->CP0_Status & (1 << CP0St_UX))) {
 973         env->hflags |= MIPS_HFLAG_AWRAP;
 974     } else if (env->insn_flags & ISA_MIPS64R6) {
 975         /* Address wrapping for Supervisor and Kernel is specified in R6 */
 976         if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
 977              !(env->CP0_Status & (1 << CP0St_SX))) ||
 978             (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
 979              !(env->CP0_Status & (1 << CP0St_KX)))) {
 980             env->hflags |= MIPS_HFLAG_AWRAP;
 981         }
 982     }
 983 #endif
 984     if (((env->CP0_Status & (1 << CP0St_CU0)) &&
 985          !(env->insn_flags & ISA_MIPS32R6)) ||
 986         !(env->hflags & MIPS_HFLAG_KSU)) {
 987         env->hflags |= MIPS_HFLAG_CP0;
 988     }
 989     if (env->CP0_Status & (1 << CP0St_CU1)) {
 990         env->hflags |= MIPS_HFLAG_FPU;
 991     }
 992     if (env->CP0_Status & (1 << CP0St_FR)) {
 993         env->hflags |= MIPS_HFLAG_F64;
 994     }
 995     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
 996         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
 997         env->hflags |= MIPS_HFLAG_SBRI;
 998     }
 999     if (env->insn_flags & ASE_DSPR2) {
1000         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
1001            so enable to access DSPR2 resources. */
1002         if (env->CP0_Status & (1 << CP0St_MX)) {
1003             env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
1004         }
1005
1006     } else if (env->insn_flags & ASE_DSP) {
1007         /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
1008            so enable to access DSP resources. */
1009         if (env->CP0_Status & (1 << CP0St_MX)) {
1010             env->hflags |= MIPS_HFLAG_DSP;
1011         }
1012
1013     }
1014     if (env->insn_flags & ISA_MIPS32R2) {
1015         if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
1016             env->hflags |= MIPS_HFLAG_COP1X;
1017         }
1018     } else if (env->insn_flags & ISA_MIPS32) {
1019         if (env->hflags & MIPS_HFLAG_64) {
1020             env->hflags |= MIPS_HFLAG_COP1X;
1021         }
1022     } else if (env->insn_flags & ISA_MIPS4) {
1023         /* All supported MIPS IV CPUs use the XX (CU3) to enable
1024            and disable the MIPS IV extensions to the MIPS III ISA.
1025            Some other MIPS IV CPUs ignore the bit, so the check here
1026            would be too restrictive for them.  */
1027         if (env->CP0_Status & (1U << CP0St_CU3)) {
1028             env->hflags |= MIPS_HFLAG_COP1X;
1029         }
1030     }
1031     if (env->insn_flags & ASE_MSA) {
1032         if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
1033             env->hflags |= MIPS_HFLAG_MSA;
1034         }
1035     }
1036     if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
1037         if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
1038             env->hflags |= MIPS_HFLAG_FRE;
1039         }
1040     }
1041     if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
1042         if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
1043             env->hflags |= MIPS_HFLAG_ELPA;
1044         }
1045     }
1046 }
1047
1048 void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global);
1049 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
1050 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
1051 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
1052
1053 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
1054                                           int error_code, uintptr_t pc);
1055
1056 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
1057                                                     uint32_t exception,
1058                                                     uintptr_t pc)
1059 {
1060     do_raise_exception_err(env, exception, 0, pc);
1061 }
1062
1063 #endif /* !defined (__MIPS_CPU_H__) */