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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / target / m68k / translate.c
blob0f5904776c7e6bf156e5bb0caec02e2bb3e40a18
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/log.h"
27 #include "exec/cpu_ldst.h"
28 #include "exec/translator.h"
29
30 #include "exec/helper-proto.h"
31 #include "exec/helper-gen.h"
32
33 #include "trace-tcg.h"
34 #include "exec/log.h"
35
36 //#define DEBUG_DISPATCH 1
37
38 #define DEFO32(name, offset) static TCGv QREG_##name;
39 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
40 #include "qregs.def"
41 #undef DEFO32
42 #undef DEFO64
43
44 static TCGv_i32 cpu_halted;
45 static TCGv_i32 cpu_exception_index;
46
47 static char cpu_reg_names[2 * 8 * 3 + 5 * 4];
48 static TCGv cpu_dregs[8];
49 static TCGv cpu_aregs[8];
50 static TCGv_i64 cpu_macc[4];
51
52 #define REG(insn, pos) (((insn) >> (pos)) & 7)
53 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
54 #define AREG(insn, pos) get_areg(s, REG(insn, pos))
55 #define MACREG(acc) cpu_macc[acc]
56 #define QREG_SP get_areg(s, 7)
57
58 static TCGv NULL_QREG;
59 #define IS_NULL_QREG(t) (t == NULL_QREG)
60 /* Used to distinguish stores from bad addressing modes. */
61 static TCGv store_dummy;
62
63 #include "exec/gen-icount.h"
64
65 void m68k_tcg_init(void)
66 {
67 char *p;
68 int i;
69
70 #define DEFO32(name, offset) \
71 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
72 offsetof(CPUM68KState, offset), #name);
73 #define DEFO64(name, offset) \
74 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
75 offsetof(CPUM68KState, offset), #name);
76 #include "qregs.def"
77 #undef DEFO32
78 #undef DEFO64
79
80 cpu_halted = tcg_global_mem_new_i32(cpu_env,
81 -offsetof(M68kCPU, env) +
82 offsetof(CPUState, halted), "HALTED");
83 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
84 -offsetof(M68kCPU, env) +
85 offsetof(CPUState, exception_index),
86 "EXCEPTION");
87
88 p = cpu_reg_names;
89 for (i = 0; i < 8; i++) {
90 sprintf(p, "D%d", i);
91 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
92 offsetof(CPUM68KState, dregs[i]), p);
93 p += 3;
94 sprintf(p, "A%d", i);
95 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
96 offsetof(CPUM68KState, aregs[i]), p);
97 p += 3;
98 }
99 for (i = 0; i < 4; i++) {
100 sprintf(p, "ACC%d", i);
101 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
102 offsetof(CPUM68KState, macc[i]), p);
103 p += 5;
104 }
105
106 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
107 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
108 }
109
110 /* internal defines */
111 typedef struct DisasContext {
112 CPUM68KState *env;
113 target_ulong insn_pc; /* Start of the current instruction. */
114 target_ulong pc;
115 int is_jmp;
116 CCOp cc_op; /* Current CC operation */
117 int cc_op_synced;
118 int user;
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
121 TCGv_i64 mactmp;
122 int done_mac;
123 int writeback_mask;
124 TCGv writeback[8];
125 } DisasContext;
126
127 static TCGv get_areg(DisasContext *s, unsigned regno)
128 {
129 if (s->writeback_mask & (1 << regno)) {
130 return s->writeback[regno];
131 } else {
132 return cpu_aregs[regno];
133 }
134 }
135
136 static void delay_set_areg(DisasContext *s, unsigned regno,
137 TCGv val, bool give_temp)
138 {
139 if (s->writeback_mask & (1 << regno)) {
140 if (give_temp) {
141 tcg_temp_free(s->writeback[regno]);
142 s->writeback[regno] = val;
143 } else {
144 tcg_gen_mov_i32(s->writeback[regno], val);
145 }
146 } else {
147 s->writeback_mask |= 1 << regno;
148 if (give_temp) {
149 s->writeback[regno] = val;
150 } else {
151 TCGv tmp = tcg_temp_new();
152 s->writeback[regno] = tmp;
153 tcg_gen_mov_i32(tmp, val);
154 }
155 }
156 }
157
158 static void do_writebacks(DisasContext *s)
159 {
160 unsigned mask = s->writeback_mask;
161 if (mask) {
162 s->writeback_mask = 0;
163 do {
164 unsigned regno = ctz32(mask);
165 tcg_gen_mov_i32(cpu_aregs[regno], s->writeback[regno]);
166 tcg_temp_free(s->writeback[regno]);
167 mask &= mask - 1;
168 } while (mask);
169 }
170 }
171
172 /* is_jmp field values */
173 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
174 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
175 #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
176 #define DISAS_JUMP_NEXT DISAS_TARGET_3
177
178 #if defined(CONFIG_USER_ONLY)
179 #define IS_USER(s) 1
180 #else
181 #define IS_USER(s) s->user
182 #endif
183
184 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
185
186 #ifdef DEBUG_DISPATCH
187 #define DISAS_INSN(name) \
188 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
189 uint16_t insn); \
190 static void disas_##name(CPUM68KState *env, DisasContext *s, \
191 uint16_t insn) \
192 { \
193 qemu_log("Dispatch " #name "\n"); \
194 real_disas_##name(env, s, insn); \
195 } \
196 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
197 uint16_t insn)
198 #else
199 #define DISAS_INSN(name) \
200 static void disas_##name(CPUM68KState *env, DisasContext *s, \
201 uint16_t insn)
202 #endif
203
204 static const uint8_t cc_op_live[CC_OP_NB] = {
205 [CC_OP_DYNAMIC] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
206 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
207 [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
208 [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
209 [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
210 [CC_OP_LOGIC] = CCF_X | CCF_N
211 };
212
213 static void set_cc_op(DisasContext *s, CCOp op)
214 {
215 CCOp old_op = s->cc_op;
216 int dead;
217
218 if (old_op == op) {
219 return;
220 }
221 s->cc_op = op;
222 s->cc_op_synced = 0;
223
224 /* Discard CC computation that will no longer be used.
225 Note that X and N are never dead. */
226 dead = cc_op_live[old_op] & ~cc_op_live[op];
227 if (dead & CCF_C) {
228 tcg_gen_discard_i32(QREG_CC_C);
229 }
230 if (dead & CCF_Z) {
231 tcg_gen_discard_i32(QREG_CC_Z);
232 }
233 if (dead & CCF_V) {
234 tcg_gen_discard_i32(QREG_CC_V);
235 }
236 }
237
238 /* Update the CPU env CC_OP state. */
239 static void update_cc_op(DisasContext *s)
240 {
241 if (!s->cc_op_synced) {
242 s->cc_op_synced = 1;
243 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
244 }
245 }
246
247 /* Generate a jump to an immediate address. */
248 static void gen_jmp_im(DisasContext *s, uint32_t dest)
249 {
250 update_cc_op(s);
251 tcg_gen_movi_i32(QREG_PC, dest);
252 s->is_jmp = DISAS_JUMP;
253 }
254
255 /* Generate a jump to the address in qreg DEST. */
256 static void gen_jmp(DisasContext *s, TCGv dest)
257 {
258 update_cc_op(s);
259 tcg_gen_mov_i32(QREG_PC, dest);
260 s->is_jmp = DISAS_JUMP;
261 }
262
263 static void gen_raise_exception(int nr)
264 {
265 TCGv_i32 tmp = tcg_const_i32(nr);
266
267 gen_helper_raise_exception(cpu_env, tmp);
268 tcg_temp_free_i32(tmp);
269 }
270
271 static void gen_exception(DisasContext *s, uint32_t where, int nr)
272 {
273 update_cc_op(s);
274 gen_jmp_im(s, where);
275 gen_raise_exception(nr);
276 }
277
278 static inline void gen_addr_fault(DisasContext *s)
279 {
280 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
281 }
282
283 /* Generate a load from the specified address. Narrow values are
284 sign extended to full register width. */
285 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
286 {
287 TCGv tmp;
288 int index = IS_USER(s);
289 tmp = tcg_temp_new_i32();
290 switch(opsize) {
291 case OS_BYTE:
292 if (sign)
293 tcg_gen_qemu_ld8s(tmp, addr, index);
294 else
295 tcg_gen_qemu_ld8u(tmp, addr, index);
296 break;
297 case OS_WORD:
298 if (sign)
299 tcg_gen_qemu_ld16s(tmp, addr, index);
300 else
301 tcg_gen_qemu_ld16u(tmp, addr, index);
302 break;
303 case OS_LONG:
304 tcg_gen_qemu_ld32u(tmp, addr, index);
305 break;
306 default:
307 g_assert_not_reached();
308 }
309 return tmp;
310 }
311
312 /* Generate a store. */
313 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
314 {
315 int index = IS_USER(s);
316 switch(opsize) {
317 case OS_BYTE:
318 tcg_gen_qemu_st8(val, addr, index);
319 break;
320 case OS_WORD:
321 tcg_gen_qemu_st16(val, addr, index);
322 break;
323 case OS_LONG:
324 tcg_gen_qemu_st32(val, addr, index);
325 break;
326 default:
327 g_assert_not_reached();
328 }
329 }
330
331 typedef enum {
332 EA_STORE,
333 EA_LOADU,
334 EA_LOADS
335 } ea_what;
336
337 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
338 otherwise generate a store. */
339 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
340 ea_what what)
341 {
342 if (what == EA_STORE) {
343 gen_store(s, opsize, addr, val);
344 return store_dummy;
345 } else {
346 return gen_load(s, opsize, addr, what == EA_LOADS);
347 }
348 }
349
350 /* Read a 16-bit immediate constant */
351 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
352 {
353 uint16_t im;
354 im = cpu_lduw_code(env, s->pc);
355 s->pc += 2;
356 return im;
357 }
358
359 /* Read an 8-bit immediate constant */
360 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
361 {
362 return read_im16(env, s);
363 }
364
365 /* Read a 32-bit immediate constant. */
366 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
367 {
368 uint32_t im;
369 im = read_im16(env, s) << 16;
370 im |= 0xffff & read_im16(env, s);
371 return im;
372 }
373
374 /* Read a 64-bit immediate constant. */
375 static inline uint64_t read_im64(CPUM68KState *env, DisasContext *s)
376 {
377 uint64_t im;
378 im = (uint64_t)read_im32(env, s) << 32;
379 im |= (uint64_t)read_im32(env, s);
380 return im;
381 }
382
383 /* Calculate and address index. */
384 static TCGv gen_addr_index(DisasContext *s, uint16_t ext, TCGv tmp)
385 {
386 TCGv add;
387 int scale;
388
389 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
390 if ((ext & 0x800) == 0) {
391 tcg_gen_ext16s_i32(tmp, add);
392 add = tmp;
393 }
394 scale = (ext >> 9) & 3;
395 if (scale != 0) {
396 tcg_gen_shli_i32(tmp, add, scale);
397 add = tmp;
398 }
399 return add;
400 }
401
402 /* Handle a base + index + displacement effective addresss.
403 A NULL_QREG base means pc-relative. */
404 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
405 {
406 uint32_t offset;
407 uint16_t ext;
408 TCGv add;
409 TCGv tmp;
410 uint32_t bd, od;
411
412 offset = s->pc;
413 ext = read_im16(env, s);
414
415 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
416 return NULL_QREG;
417
418 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
419 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
420 ext &= ~(3 << 9);
421 }
422
423 if (ext & 0x100) {
424 /* full extension word format */
425 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
426 return NULL_QREG;
427
428 if ((ext & 0x30) > 0x10) {
429 /* base displacement */
430 if ((ext & 0x30) == 0x20) {
431 bd = (int16_t)read_im16(env, s);
432 } else {
433 bd = read_im32(env, s);
434 }
435 } else {
436 bd = 0;
437 }
438 tmp = tcg_temp_new();
439 if ((ext & 0x44) == 0) {
440 /* pre-index */
441 add = gen_addr_index(s, ext, tmp);
442 } else {
443 add = NULL_QREG;
444 }
445 if ((ext & 0x80) == 0) {
446 /* base not suppressed */
447 if (IS_NULL_QREG(base)) {
448 base = tcg_const_i32(offset + bd);
449 bd = 0;
450 }
451 if (!IS_NULL_QREG(add)) {
452 tcg_gen_add_i32(tmp, add, base);
453 add = tmp;
454 } else {
455 add = base;
456 }
457 }
458 if (!IS_NULL_QREG(add)) {
459 if (bd != 0) {
460 tcg_gen_addi_i32(tmp, add, bd);
461 add = tmp;
462 }
463 } else {
464 add = tcg_const_i32(bd);
465 }
466 if ((ext & 3) != 0) {
467 /* memory indirect */
468 base = gen_load(s, OS_LONG, add, 0);
469 if ((ext & 0x44) == 4) {
470 add = gen_addr_index(s, ext, tmp);
471 tcg_gen_add_i32(tmp, add, base);
472 add = tmp;
473 } else {
474 add = base;
475 }
476 if ((ext & 3) > 1) {
477 /* outer displacement */
478 if ((ext & 3) == 2) {
479 od = (int16_t)read_im16(env, s);
480 } else {
481 od = read_im32(env, s);
482 }
483 } else {
484 od = 0;
485 }
486 if (od != 0) {
487 tcg_gen_addi_i32(tmp, add, od);
488 add = tmp;
489 }
490 }
491 } else {
492 /* brief extension word format */
493 tmp = tcg_temp_new();
494 add = gen_addr_index(s, ext, tmp);
495 if (!IS_NULL_QREG(base)) {
496 tcg_gen_add_i32(tmp, add, base);
497 if ((int8_t)ext)
498 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
499 } else {
500 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
501 }
502 add = tmp;
503 }
504 return add;
505 }
506
507 /* Sign or zero extend a value. */
508
509 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
510 {
511 switch (opsize) {
512 case OS_BYTE:
513 if (sign) {
514 tcg_gen_ext8s_i32(res, val);
515 } else {
516 tcg_gen_ext8u_i32(res, val);
517 }
518 break;
519 case OS_WORD:
520 if (sign) {
521 tcg_gen_ext16s_i32(res, val);
522 } else {
523 tcg_gen_ext16u_i32(res, val);
524 }
525 break;
526 case OS_LONG:
527 tcg_gen_mov_i32(res, val);
528 break;
529 default:
530 g_assert_not_reached();
531 }
532 }
533
534 /* Evaluate all the CC flags. */
535
536 static void gen_flush_flags(DisasContext *s)
537 {
538 TCGv t0, t1;
539
540 switch (s->cc_op) {
541 case CC_OP_FLAGS:
542 return;
543
544 case CC_OP_ADDB:
545 case CC_OP_ADDW:
546 case CC_OP_ADDL:
547 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
548 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
549 /* Compute signed overflow for addition. */
550 t0 = tcg_temp_new();
551 t1 = tcg_temp_new();
552 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
553 gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
554 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
555 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
556 tcg_temp_free(t0);
557 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
558 tcg_temp_free(t1);
559 break;
560
561 case CC_OP_SUBB:
562 case CC_OP_SUBW:
563 case CC_OP_SUBL:
564 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
565 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
566 /* Compute signed overflow for subtraction. */
567 t0 = tcg_temp_new();
568 t1 = tcg_temp_new();
569 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
570 gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
571 tcg_gen_xor_i32(t1, QREG_CC_N, t0);
572 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
573 tcg_temp_free(t0);
574 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
575 tcg_temp_free(t1);
576 break;
577
578 case CC_OP_CMPB:
579 case CC_OP_CMPW:
580 case CC_OP_CMPL:
581 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
582 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
583 gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
584 /* Compute signed overflow for subtraction. */
585 t0 = tcg_temp_new();
586 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
587 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
588 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
589 tcg_temp_free(t0);
590 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
591 break;
592
593 case CC_OP_LOGIC:
594 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
595 tcg_gen_movi_i32(QREG_CC_C, 0);
596 tcg_gen_movi_i32(QREG_CC_V, 0);
597 break;
598
599 case CC_OP_DYNAMIC:
600 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
601 s->cc_op_synced = 1;
602 break;
603
604 default:
605 t0 = tcg_const_i32(s->cc_op);
606 gen_helper_flush_flags(cpu_env, t0);
607 tcg_temp_free(t0);
608 s->cc_op_synced = 1;
609 break;
610 }
611
612 /* Note that flush_flags also assigned to env->cc_op. */
613 s->cc_op = CC_OP_FLAGS;
614 }
615
616 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
617 {
618 TCGv tmp;
619
620 if (opsize == OS_LONG) {
621 tmp = val;
622 } else {
623 tmp = tcg_temp_new();
624 gen_ext(tmp, val, opsize, sign);
625 }
626
627 return tmp;
628 }
629
630 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
631 {
632 gen_ext(QREG_CC_N, val, opsize, 1);
633 set_cc_op(s, CC_OP_LOGIC);
634 }
635
636 static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
637 {
638 tcg_gen_mov_i32(QREG_CC_N, dest);
639 tcg_gen_mov_i32(QREG_CC_V, src);
640 set_cc_op(s, CC_OP_CMPB + opsize);
641 }
642
643 static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
644 {
645 gen_ext(QREG_CC_N, dest, opsize, 1);
646 tcg_gen_mov_i32(QREG_CC_V, src);
647 }
648
649 static inline int opsize_bytes(int opsize)
650 {
651 switch (opsize) {
652 case OS_BYTE: return 1;
653 case OS_WORD: return 2;
654 case OS_LONG: return 4;
655 case OS_SINGLE: return 4;
656 case OS_DOUBLE: return 8;
657 case OS_EXTENDED: return 12;
658 case OS_PACKED: return 12;
659 default:
660 g_assert_not_reached();
661 }
662 }
663
664 static inline int insn_opsize(int insn)
665 {
666 switch ((insn >> 6) & 3) {
667 case 0: return OS_BYTE;
668 case 1: return OS_WORD;
669 case 2: return OS_LONG;
670 default:
671 g_assert_not_reached();
672 }
673 /* Should never happen. */
674 return -1;
675 }
676
677 static inline int ext_opsize(int ext, int pos)
678 {
679 switch ((ext >> pos) & 7) {
680 case 0: return OS_LONG;
681 case 1: return OS_SINGLE;
682 case 2: return OS_EXTENDED;
683 case 3: return OS_PACKED;
684 case 4: return OS_WORD;
685 case 5: return OS_DOUBLE;
686 case 6: return OS_BYTE;
687 default:
688 g_assert_not_reached();
689 }
690 }
691
692 /* Assign value to a register. If the width is less than the register width
693 only the low part of the register is set. */
694 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
695 {
696 TCGv tmp;
697 switch (opsize) {
698 case OS_BYTE:
699 tcg_gen_andi_i32(reg, reg, 0xffffff00);
700 tmp = tcg_temp_new();
701 tcg_gen_ext8u_i32(tmp, val);
702 tcg_gen_or_i32(reg, reg, tmp);
703 tcg_temp_free(tmp);
704 break;
705 case OS_WORD:
706 tcg_gen_andi_i32(reg, reg, 0xffff0000);
707 tmp = tcg_temp_new();
708 tcg_gen_ext16u_i32(tmp, val);
709 tcg_gen_or_i32(reg, reg, tmp);
710 tcg_temp_free(tmp);
711 break;
712 case OS_LONG:
713 case OS_SINGLE:
714 tcg_gen_mov_i32(reg, val);
715 break;
716 default:
717 g_assert_not_reached();
718 }
719 }
720
721 /* Generate code for an "effective address". Does not adjust the base
722 register for autoincrement addressing modes. */
723 static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s,
724 int mode, int reg0, int opsize)
725 {
726 TCGv reg;
727 TCGv tmp;
728 uint16_t ext;
729 uint32_t offset;
730
731 switch (mode) {
732 case 0: /* Data register direct. */
733 case 1: /* Address register direct. */
734 return NULL_QREG;
735 case 3: /* Indirect postincrement. */
736 if (opsize == OS_UNSIZED) {
737 return NULL_QREG;
738 }
739 /* fallthru */
740 case 2: /* Indirect register */
741 return get_areg(s, reg0);
742 case 4: /* Indirect predecrememnt. */
743 if (opsize == OS_UNSIZED) {
744 return NULL_QREG;
745 }
746 reg = get_areg(s, reg0);
747 tmp = tcg_temp_new();
748 if (reg0 == 7 && opsize == OS_BYTE &&
749 m68k_feature(s->env, M68K_FEATURE_M68000)) {
750 tcg_gen_subi_i32(tmp, reg, 2);
751 } else {
752 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
753 }
754 return tmp;
755 case 5: /* Indirect displacement. */
756 reg = get_areg(s, reg0);
757 tmp = tcg_temp_new();
758 ext = read_im16(env, s);
759 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
760 return tmp;
761 case 6: /* Indirect index + displacement. */
762 reg = get_areg(s, reg0);
763 return gen_lea_indexed(env, s, reg);
764 case 7: /* Other */
765 switch (reg0) {
766 case 0: /* Absolute short. */
767 offset = (int16_t)read_im16(env, s);
768 return tcg_const_i32(offset);
769 case 1: /* Absolute long. */
770 offset = read_im32(env, s);
771 return tcg_const_i32(offset);
772 case 2: /* pc displacement */
773 offset = s->pc;
774 offset += (int16_t)read_im16(env, s);
775 return tcg_const_i32(offset);
776 case 3: /* pc index+displacement. */
777 return gen_lea_indexed(env, s, NULL_QREG);
778 case 4: /* Immediate. */
779 default:
780 return NULL_QREG;
781 }
782 }
783 /* Should never happen. */
784 return NULL_QREG;
785 }
786
787 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
788 int opsize)
789 {
790 int mode = extract32(insn, 3, 3);
791 int reg0 = REG(insn, 0);
792 return gen_lea_mode(env, s, mode, reg0, opsize);
793 }
794
795 /* Generate code to load/store a value from/into an EA. If WHAT > 0 this is
796 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
797 ADDRP is non-null for readwrite operands. */
798 static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0,
799 int opsize, TCGv val, TCGv *addrp, ea_what what)
800 {
801 TCGv reg, tmp, result;
802 int32_t offset;
803
804 switch (mode) {
805 case 0: /* Data register direct. */
806 reg = cpu_dregs[reg0];
807 if (what == EA_STORE) {
808 gen_partset_reg(opsize, reg, val);
809 return store_dummy;
810 } else {
811 return gen_extend(reg, opsize, what == EA_LOADS);
812 }
813 case 1: /* Address register direct. */
814 reg = get_areg(s, reg0);
815 if (what == EA_STORE) {
816 tcg_gen_mov_i32(reg, val);
817 return store_dummy;
818 } else {
819 return gen_extend(reg, opsize, what == EA_LOADS);
820 }
821 case 2: /* Indirect register */
822 reg = get_areg(s, reg0);
823 return gen_ldst(s, opsize, reg, val, what);
824 case 3: /* Indirect postincrement. */
825 reg = get_areg(s, reg0);
826 result = gen_ldst(s, opsize, reg, val, what);
827 if (what == EA_STORE || !addrp) {
828 TCGv tmp = tcg_temp_new();
829 if (reg0 == 7 && opsize == OS_BYTE &&
830 m68k_feature(s->env, M68K_FEATURE_M68000)) {
831 tcg_gen_addi_i32(tmp, reg, 2);
832 } else {
833 tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize));
834 }
835 delay_set_areg(s, reg0, tmp, true);
836 }
837 return result;
838 case 4: /* Indirect predecrememnt. */
839 if (addrp && what == EA_STORE) {
840 tmp = *addrp;
841 } else {
842 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
843 if (IS_NULL_QREG(tmp)) {
844 return tmp;
845 }
846 if (addrp) {
847 *addrp = tmp;
848 }
849 }
850 result = gen_ldst(s, opsize, tmp, val, what);
851 if (what == EA_STORE || !addrp) {
852 delay_set_areg(s, reg0, tmp, false);
853 }
854 return result;
855 case 5: /* Indirect displacement. */
856 case 6: /* Indirect index + displacement. */
857 do_indirect:
858 if (addrp && what == EA_STORE) {
859 tmp = *addrp;
860 } else {
861 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
862 if (IS_NULL_QREG(tmp)) {
863 return tmp;
864 }
865 if (addrp) {
866 *addrp = tmp;
867 }
868 }
869 return gen_ldst(s, opsize, tmp, val, what);
870 case 7: /* Other */
871 switch (reg0) {
872 case 0: /* Absolute short. */
873 case 1: /* Absolute long. */
874 case 2: /* pc displacement */
875 case 3: /* pc index+displacement. */
876 goto do_indirect;
877 case 4: /* Immediate. */
878 /* Sign extend values for consistency. */
879 switch (opsize) {
880 case OS_BYTE:
881 if (what == EA_LOADS) {
882 offset = (int8_t)read_im8(env, s);
883 } else {
884 offset = read_im8(env, s);
885 }
886 break;
887 case OS_WORD:
888 if (what == EA_LOADS) {
889 offset = (int16_t)read_im16(env, s);
890 } else {
891 offset = read_im16(env, s);
892 }
893 break;
894 case OS_LONG:
895 offset = read_im32(env, s);
896 break;
897 default:
898 g_assert_not_reached();
899 }
900 return tcg_const_i32(offset);
901 default:
902 return NULL_QREG;
903 }
904 }
905 /* Should never happen. */
906 return NULL_QREG;
907 }
908
909 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
910 int opsize, TCGv val, TCGv *addrp, ea_what what)
911 {
912 int mode = extract32(insn, 3, 3);
913 int reg0 = REG(insn, 0);
914 return gen_ea_mode(env, s, mode, reg0, opsize, val, addrp, what);
915 }
916
917 static TCGv_ptr gen_fp_ptr(int freg)
918 {
919 TCGv_ptr fp = tcg_temp_new_ptr();
920 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg]));
921 return fp;
922 }
923
924 static TCGv_ptr gen_fp_result_ptr(void)
925 {
926 TCGv_ptr fp = tcg_temp_new_ptr();
927 tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result));
928 return fp;
929 }
930
931 static void gen_fp_move(TCGv_ptr dest, TCGv_ptr src)
932 {
933 TCGv t32;
934 TCGv_i64 t64;
935
936 t32 = tcg_temp_new();
937 tcg_gen_ld16u_i32(t32, src, offsetof(FPReg, l.upper));
938 tcg_gen_st16_i32(t32, dest, offsetof(FPReg, l.upper));
939 tcg_temp_free(t32);
940
941 t64 = tcg_temp_new_i64();
942 tcg_gen_ld_i64(t64, src, offsetof(FPReg, l.lower));
943 tcg_gen_st_i64(t64, dest, offsetof(FPReg, l.lower));
944 tcg_temp_free_i64(t64);
945 }
946
947 static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
948 {
949 TCGv tmp;
950 TCGv_i64 t64;
951 int index = IS_USER(s);
952
953 t64 = tcg_temp_new_i64();
954 tmp = tcg_temp_new();
955 switch (opsize) {
956 case OS_BYTE:
957 tcg_gen_qemu_ld8s(tmp, addr, index);
958 gen_helper_exts32(cpu_env, fp, tmp);
959 break;
960 case OS_WORD:
961 tcg_gen_qemu_ld16s(tmp, addr, index);
962 gen_helper_exts32(cpu_env, fp, tmp);
963 break;
964 case OS_LONG:
965 tcg_gen_qemu_ld32u(tmp, addr, index);
966 gen_helper_exts32(cpu_env, fp, tmp);
967 break;
968 case OS_SINGLE:
969 tcg_gen_qemu_ld32u(tmp, addr, index);
970 gen_helper_extf32(cpu_env, fp, tmp);
971 break;
972 case OS_DOUBLE:
973 tcg_gen_qemu_ld64(t64, addr, index);
974 gen_helper_extf64(cpu_env, fp, t64);
975 tcg_temp_free_i64(t64);
976 break;
977 case OS_EXTENDED:
978 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
979 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
980 break;
981 }
982 tcg_gen_qemu_ld32u(tmp, addr, index);
983 tcg_gen_shri_i32(tmp, tmp, 16);
984 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
985 tcg_gen_addi_i32(tmp, addr, 4);
986 tcg_gen_qemu_ld64(t64, tmp, index);
987 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
988 break;
989 case OS_PACKED:
990 /* unimplemented data type on 68040/ColdFire
991 * FIXME if needed for another FPU
992 */
993 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
994 break;
995 default:
996 g_assert_not_reached();
997 }
998 tcg_temp_free(tmp);
999 tcg_temp_free_i64(t64);
1000 }
1001
1002 static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp)
1003 {
1004 TCGv tmp;
1005 TCGv_i64 t64;
1006 int index = IS_USER(s);
1007
1008 t64 = tcg_temp_new_i64();
1009 tmp = tcg_temp_new();
1010 switch (opsize) {
1011 case OS_BYTE:
1012 gen_helper_reds32(tmp, cpu_env, fp);
1013 tcg_gen_qemu_st8(tmp, addr, index);
1014 break;
1015 case OS_WORD:
1016 gen_helper_reds32(tmp, cpu_env, fp);
1017 tcg_gen_qemu_st16(tmp, addr, index);
1018 break;
1019 case OS_LONG:
1020 gen_helper_reds32(tmp, cpu_env, fp);
1021 tcg_gen_qemu_st32(tmp, addr, index);
1022 break;
1023 case OS_SINGLE:
1024 gen_helper_redf32(tmp, cpu_env, fp);
1025 tcg_gen_qemu_st32(tmp, addr, index);
1026 break;
1027 case OS_DOUBLE:
1028 gen_helper_redf64(t64, cpu_env, fp);
1029 tcg_gen_qemu_st64(t64, addr, index);
1030 break;
1031 case OS_EXTENDED:
1032 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1033 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1034 break;
1035 }
1036 tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
1037 tcg_gen_shli_i32(tmp, tmp, 16);
1038 tcg_gen_qemu_st32(tmp, addr, index);
1039 tcg_gen_addi_i32(tmp, addr, 4);
1040 tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
1041 tcg_gen_qemu_st64(t64, tmp, index);
1042 break;
1043 case OS_PACKED:
1044 /* unimplemented data type on 68040/ColdFire
1045 * FIXME if needed for another FPU
1046 */
1047 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1048 break;
1049 default:
1050 g_assert_not_reached();
1051 }
1052 tcg_temp_free(tmp);
1053 tcg_temp_free_i64(t64);
1054 }
1055
1056 static void gen_ldst_fp(DisasContext *s, int opsize, TCGv addr,
1057 TCGv_ptr fp, ea_what what)
1058 {
1059 if (what == EA_STORE) {
1060 gen_store_fp(s, opsize, addr, fp);
1061 } else {
1062 gen_load_fp(s, opsize, addr, fp);
1063 }
1064 }
1065
1066 static int gen_ea_mode_fp(CPUM68KState *env, DisasContext *s, int mode,
1067 int reg0, int opsize, TCGv_ptr fp, ea_what what)
1068 {
1069 TCGv reg, addr, tmp;
1070 TCGv_i64 t64;
1071
1072 switch (mode) {
1073 case 0: /* Data register direct. */
1074 reg = cpu_dregs[reg0];
1075 if (what == EA_STORE) {
1076 switch (opsize) {
1077 case OS_BYTE:
1078 case OS_WORD:
1079 case OS_LONG:
1080 gen_helper_reds32(reg, cpu_env, fp);
1081 break;
1082 case OS_SINGLE:
1083 gen_helper_redf32(reg, cpu_env, fp);
1084 break;
1085 default:
1086 g_assert_not_reached();
1087 }
1088 } else {
1089 tmp = tcg_temp_new();
1090 switch (opsize) {
1091 case OS_BYTE:
1092 tcg_gen_ext8s_i32(tmp, reg);
1093 gen_helper_exts32(cpu_env, fp, tmp);
1094 break;
1095 case OS_WORD:
1096 tcg_gen_ext16s_i32(tmp, reg);
1097 gen_helper_exts32(cpu_env, fp, tmp);
1098 break;
1099 case OS_LONG:
1100 gen_helper_exts32(cpu_env, fp, reg);
1101 break;
1102 case OS_SINGLE:
1103 gen_helper_extf32(cpu_env, fp, reg);
1104 break;
1105 default:
1106 g_assert_not_reached();
1107 }
1108 tcg_temp_free(tmp);
1109 }
1110 return 0;
1111 case 1: /* Address register direct. */
1112 return -1;
1113 case 2: /* Indirect register */
1114 addr = get_areg(s, reg0);
1115 gen_ldst_fp(s, opsize, addr, fp, what);
1116 return 0;
1117 case 3: /* Indirect postincrement. */
1118 addr = cpu_aregs[reg0];
1119 gen_ldst_fp(s, opsize, addr, fp, what);
1120 tcg_gen_addi_i32(addr, addr, opsize_bytes(opsize));
1121 return 0;
1122 case 4: /* Indirect predecrememnt. */
1123 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1124 if (IS_NULL_QREG(addr)) {
1125 return -1;
1126 }
1127 gen_ldst_fp(s, opsize, addr, fp, what);
1128 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
1129 return 0;
1130 case 5: /* Indirect displacement. */
1131 case 6: /* Indirect index + displacement. */
1132 do_indirect:
1133 addr = gen_lea_mode(env, s, mode, reg0, opsize);
1134 if (IS_NULL_QREG(addr)) {
1135 return -1;
1136 }
1137 gen_ldst_fp(s, opsize, addr, fp, what);
1138 return 0;
1139 case 7: /* Other */
1140 switch (reg0) {
1141 case 0: /* Absolute short. */
1142 case 1: /* Absolute long. */
1143 case 2: /* pc displacement */
1144 case 3: /* pc index+displacement. */
1145 goto do_indirect;
1146 case 4: /* Immediate. */
1147 if (what == EA_STORE) {
1148 return -1;
1149 }
1150 switch (opsize) {
1151 case OS_BYTE:
1152 tmp = tcg_const_i32((int8_t)read_im8(env, s));
1153 gen_helper_exts32(cpu_env, fp, tmp);
1154 tcg_temp_free(tmp);
1155 break;
1156 case OS_WORD:
1157 tmp = tcg_const_i32((int16_t)read_im16(env, s));
1158 gen_helper_exts32(cpu_env, fp, tmp);
1159 tcg_temp_free(tmp);
1160 break;
1161 case OS_LONG:
1162 tmp = tcg_const_i32(read_im32(env, s));
1163 gen_helper_exts32(cpu_env, fp, tmp);
1164 tcg_temp_free(tmp);
1165 break;
1166 case OS_SINGLE:
1167 tmp = tcg_const_i32(read_im32(env, s));
1168 gen_helper_extf32(cpu_env, fp, tmp);
1169 tcg_temp_free(tmp);
1170 break;
1171 case OS_DOUBLE:
1172 t64 = tcg_const_i64(read_im64(env, s));
1173 gen_helper_extf64(cpu_env, fp, t64);
1174 tcg_temp_free_i64(t64);
1175 break;
1176 case OS_EXTENDED:
1177 if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
1178 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1179 break;
1180 }
1181 tmp = tcg_const_i32(read_im32(env, s) >> 16);
1182 tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
1183 tcg_temp_free(tmp);
1184 t64 = tcg_const_i64(read_im64(env, s));
1185 tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
1186 tcg_temp_free_i64(t64);
1187 break;
1188 case OS_PACKED:
1189 /* unimplemented data type on 68040/ColdFire
1190 * FIXME if needed for another FPU
1191 */
1192 gen_exception(s, s->insn_pc, EXCP_FP_UNIMP);
1193 break;
1194 default:
1195 g_assert_not_reached();
1196 }
1197 return 0;
1198 default:
1199 return -1;
1200 }
1201 }
1202 return -1;
1203 }
1204
1205 static int gen_ea_fp(CPUM68KState *env, DisasContext *s, uint16_t insn,
1206 int opsize, TCGv_ptr fp, ea_what what)
1207 {
1208 int mode = extract32(insn, 3, 3);
1209 int reg0 = REG(insn, 0);
1210 return gen_ea_mode_fp(env, s, mode, reg0, opsize, fp, what);
1211 }
1212
1213 typedef struct {
1214 TCGCond tcond;
1215 bool g1;
1216 bool g2;
1217 TCGv v1;
1218 TCGv v2;
1219 } DisasCompare;
1220
1221 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
1222 {
1223 TCGv tmp, tmp2;
1224 TCGCond tcond;
1225 CCOp op = s->cc_op;
1226
1227 /* The CC_OP_CMP form can handle most normal comparisons directly. */
1228 if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
1229 c->g1 = c->g2 = 1;
1230 c->v1 = QREG_CC_N;
1231 c->v2 = QREG_CC_V;
1232 switch (cond) {
1233 case 2: /* HI */
1234 case 3: /* LS */
1235 tcond = TCG_COND_LEU;
1236 goto done;
1237 case 4: /* CC */
1238 case 5: /* CS */
1239 tcond = TCG_COND_LTU;
1240 goto done;
1241 case 6: /* NE */
1242 case 7: /* EQ */
1243 tcond = TCG_COND_EQ;
1244 goto done;
1245 case 10: /* PL */
1246 case 11: /* MI */
1247 c->g1 = c->g2 = 0;
1248 c->v2 = tcg_const_i32(0);
1249 c->v1 = tmp = tcg_temp_new();
1250 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
1251 gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
1252 /* fallthru */
1253 case 12: /* GE */
1254 case 13: /* LT */
1255 tcond = TCG_COND_LT;
1256 goto done;
1257 case 14: /* GT */
1258 case 15: /* LE */
1259 tcond = TCG_COND_LE;
1260 goto done;
1261 }
1262 }
1263
1264 c->g1 = 1;
1265 c->g2 = 0;
1266 c->v2 = tcg_const_i32(0);
1267
1268 switch (cond) {
1269 case 0: /* T */
1270 case 1: /* F */
1271 c->v1 = c->v2;
1272 tcond = TCG_COND_NEVER;
1273 goto done;
1274 case 14: /* GT (!(Z || (N ^ V))) */
1275 case 15: /* LE (Z || (N ^ V)) */
1276 /* Logic operations clear V, which simplifies LE to (Z || N),
1277 and since Z and N are co-located, this becomes a normal
1278 comparison vs N. */
1279 if (op == CC_OP_LOGIC) {
1280 c->v1 = QREG_CC_N;
1281 tcond = TCG_COND_LE;
1282 goto done;
1283 }
1284 break;
1285 case 12: /* GE (!(N ^ V)) */
1286 case 13: /* LT (N ^ V) */
1287 /* Logic operations clear V, which simplifies this to N. */
1288 if (op != CC_OP_LOGIC) {
1289 break;
1290 }
1291 /* fallthru */
1292 case 10: /* PL (!N) */
1293 case 11: /* MI (N) */
1294 /* Several cases represent N normally. */
1295 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1296 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1297 op == CC_OP_LOGIC) {
1298 c->v1 = QREG_CC_N;
1299 tcond = TCG_COND_LT;
1300 goto done;
1301 }
1302 break;
1303 case 6: /* NE (!Z) */
1304 case 7: /* EQ (Z) */
1305 /* Some cases fold Z into N. */
1306 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1307 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
1308 op == CC_OP_LOGIC) {
1309 tcond = TCG_COND_EQ;
1310 c->v1 = QREG_CC_N;
1311 goto done;
1312 }
1313 break;
1314 case 4: /* CC (!C) */
1315 case 5: /* CS (C) */
1316 /* Some cases fold C into X. */
1317 if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
1318 op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL) {
1319 tcond = TCG_COND_NE;
1320 c->v1 = QREG_CC_X;
1321 goto done;
1322 }
1323 /* fallthru */
1324 case 8: /* VC (!V) */
1325 case 9: /* VS (V) */
1326 /* Logic operations clear V and C. */
1327 if (op == CC_OP_LOGIC) {
1328 tcond = TCG_COND_NEVER;
1329 c->v1 = c->v2;
1330 goto done;
1331 }
1332 break;
1333 }
1334
1335 /* Otherwise, flush flag state to CC_OP_FLAGS. */
1336 gen_flush_flags(s);
1337
1338 switch (cond) {
1339 case 0: /* T */
1340 case 1: /* F */
1341 default:
1342 /* Invalid, or handled above. */
1343 abort();
1344 case 2: /* HI (!C && !Z) -> !(C || Z)*/
1345 case 3: /* LS (C || Z) */
1346 c->v1 = tmp = tcg_temp_new();
1347 c->g1 = 0;
1348 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1349 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
1350 tcond = TCG_COND_NE;
1351 break;
1352 case 4: /* CC (!C) */
1353 case 5: /* CS (C) */
1354 c->v1 = QREG_CC_C;
1355 tcond = TCG_COND_NE;
1356 break;
1357 case 6: /* NE (!Z) */
1358 case 7: /* EQ (Z) */
1359 c->v1 = QREG_CC_Z;
1360 tcond = TCG_COND_EQ;
1361 break;
1362 case 8: /* VC (!V) */
1363 case 9: /* VS (V) */
1364 c->v1 = QREG_CC_V;
1365 tcond = TCG_COND_LT;
1366 break;
1367 case 10: /* PL (!N) */
1368 case 11: /* MI (N) */
1369 c->v1 = QREG_CC_N;
1370 tcond = TCG_COND_LT;
1371 break;
1372 case 12: /* GE (!(N ^ V)) */
1373 case 13: /* LT (N ^ V) */
1374 c->v1 = tmp = tcg_temp_new();
1375 c->g1 = 0;
1376 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
1377 tcond = TCG_COND_LT;
1378 break;
1379 case 14: /* GT (!(Z || (N ^ V))) */
1380 case 15: /* LE (Z || (N ^ V)) */
1381 c->v1 = tmp = tcg_temp_new();
1382 c->g1 = 0;
1383 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
1384 tcg_gen_neg_i32(tmp, tmp);
1385 tmp2 = tcg_temp_new();
1386 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
1387 tcg_gen_or_i32(tmp, tmp, tmp2);
1388 tcg_temp_free(tmp2);
1389 tcond = TCG_COND_LT;
1390 break;
1391 }
1392
1393 done:
1394 if ((cond & 1) == 0) {
1395 tcond = tcg_invert_cond(tcond);
1396 }
1397 c->tcond = tcond;
1398 }
1399
1400 static void free_cond(DisasCompare *c)
1401 {
1402 if (!c->g1) {
1403 tcg_temp_free(c->v1);
1404 }
1405 if (!c->g2) {
1406 tcg_temp_free(c->v2);
1407 }
1408 }
1409
1410 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1411 {
1412 DisasCompare c;
1413
1414 gen_cc_cond(&c, s, cond);
1415 update_cc_op(s);
1416 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1417 free_cond(&c);
1418 }
1419
1420 /* Force a TB lookup after an instruction that changes the CPU state. */
1421 static void gen_lookup_tb(DisasContext *s)
1422 {
1423 update_cc_op(s);
1424 tcg_gen_movi_i32(QREG_PC, s->pc);
1425 s->is_jmp = DISAS_UPDATE;
1426 }
1427
1428 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1429 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1430 op_sign ? EA_LOADS : EA_LOADU); \
1431 if (IS_NULL_QREG(result)) { \
1432 gen_addr_fault(s); \
1433 return; \
1434 } \
1435 } while (0)
1436
1437 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1438 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1439 if (IS_NULL_QREG(ea_result)) { \
1440 gen_addr_fault(s); \
1441 return; \
1442 } \
1443 } while (0)
1444
1445 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1446 {
1447 #ifndef CONFIG_USER_ONLY
1448 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
1449 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1450 #else
1451 return true;
1452 #endif
1453 }
1454
1455 /* Generate a jump to an immediate address. */
1456 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1457 {
1458 if (unlikely(s->singlestep_enabled)) {
1459 gen_exception(s, dest, EXCP_DEBUG);
1460 } else if (use_goto_tb(s, dest)) {
1461 tcg_gen_goto_tb(n);
1462 tcg_gen_movi_i32(QREG_PC, dest);
1463 tcg_gen_exit_tb((uintptr_t)s->tb + n);
1464 } else {
1465 gen_jmp_im(s, dest);
1466 tcg_gen_exit_tb(0);
1467 }
1468 s->is_jmp = DISAS_TB_JUMP;
1469 }
1470
1471 DISAS_INSN(scc)
1472 {
1473 DisasCompare c;
1474 int cond;
1475 TCGv tmp;
1476
1477 cond = (insn >> 8) & 0xf;
1478 gen_cc_cond(&c, s, cond);
1479
1480 tmp = tcg_temp_new();
1481 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1482 free_cond(&c);
1483
1484 tcg_gen_neg_i32(tmp, tmp);
1485 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
1486 tcg_temp_free(tmp);
1487 }
1488
1489 DISAS_INSN(dbcc)
1490 {
1491 TCGLabel *l1;
1492 TCGv reg;
1493 TCGv tmp;
1494 int16_t offset;
1495 uint32_t base;
1496
1497 reg = DREG(insn, 0);
1498 base = s->pc;
1499 offset = (int16_t)read_im16(env, s);
1500 l1 = gen_new_label();
1501 gen_jmpcc(s, (insn >> 8) & 0xf, l1);
1502
1503 tmp = tcg_temp_new();
1504 tcg_gen_ext16s_i32(tmp, reg);
1505 tcg_gen_addi_i32(tmp, tmp, -1);
1506 gen_partset_reg(OS_WORD, reg, tmp);
1507 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1);
1508 gen_jmp_tb(s, 1, base + offset);
1509 gen_set_label(l1);
1510 gen_jmp_tb(s, 0, s->pc);
1511 }
1512
1513 DISAS_INSN(undef_mac)
1514 {
1515 gen_exception(s, s->pc - 2, EXCP_LINEA);
1516 }
1517
1518 DISAS_INSN(undef_fpu)
1519 {
1520 gen_exception(s, s->pc - 2, EXCP_LINEF);
1521 }
1522
1523 DISAS_INSN(undef)
1524 {
1525 /* ??? This is both instructions that are as yet unimplemented
1526 for the 680x0 series, as well as those that are implemented
1527 but actually illegal for CPU32 or pre-68020. */
1528 qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x",
1529 insn, s->pc - 2);
1530 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
1531 }
1532
1533 DISAS_INSN(mulw)
1534 {
1535 TCGv reg;
1536 TCGv tmp;
1537 TCGv src;
1538 int sign;
1539
1540 sign = (insn & 0x100) != 0;
1541 reg = DREG(insn, 9);
1542 tmp = tcg_temp_new();
1543 if (sign)
1544 tcg_gen_ext16s_i32(tmp, reg);
1545 else
1546 tcg_gen_ext16u_i32(tmp, reg);
1547 SRC_EA(env, src, OS_WORD, sign, NULL);
1548 tcg_gen_mul_i32(tmp, tmp, src);
1549 tcg_gen_mov_i32(reg, tmp);
1550 gen_logic_cc(s, tmp, OS_LONG);
1551 tcg_temp_free(tmp);
1552 }
1553
1554 DISAS_INSN(divw)
1555 {
1556 int sign;
1557 TCGv src;
1558 TCGv destr;
1559
1560 /* divX.w <EA>,Dn 32/16 -> 16r:16q */
1561
1562 sign = (insn & 0x100) != 0;
1563
1564 /* dest.l / src.w */
1565
1566 SRC_EA(env, src, OS_WORD, sign, NULL);
1567 destr = tcg_const_i32(REG(insn, 9));
1568 if (sign) {
1569 gen_helper_divsw(cpu_env, destr, src);
1570 } else {
1571 gen_helper_divuw(cpu_env, destr, src);
1572 }
1573 tcg_temp_free(destr);
1574
1575 set_cc_op(s, CC_OP_FLAGS);
1576 }
1577
1578 DISAS_INSN(divl)
1579 {
1580 TCGv num, reg, den;
1581 int sign;
1582 uint16_t ext;
1583
1584 ext = read_im16(env, s);
1585
1586 sign = (ext & 0x0800) != 0;
1587
1588 if (ext & 0x400) {
1589 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
1590 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
1591 return;
1592 }
1593
1594 /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
1595
1596 SRC_EA(env, den, OS_LONG, 0, NULL);
1597 num = tcg_const_i32(REG(ext, 12));
1598 reg = tcg_const_i32(REG(ext, 0));
1599 if (sign) {
1600 gen_helper_divsll(cpu_env, num, reg, den);
1601 } else {
1602 gen_helper_divull(cpu_env, num, reg, den);
1603 }
1604 tcg_temp_free(reg);
1605 tcg_temp_free(num);
1606 set_cc_op(s, CC_OP_FLAGS);
1607 return;
1608 }
1609
1610 /* divX.l <EA>, Dq 32/32 -> 32q */
1611 /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
1612
1613 SRC_EA(env, den, OS_LONG, 0, NULL);
1614 num = tcg_const_i32(REG(ext, 12));
1615 reg = tcg_const_i32(REG(ext, 0));
1616 if (sign) {
1617 gen_helper_divsl(cpu_env, num, reg, den);
1618 } else {
1619 gen_helper_divul(cpu_env, num, reg, den);
1620 }
1621 tcg_temp_free(reg);
1622 tcg_temp_free(num);
1623
1624 set_cc_op(s, CC_OP_FLAGS);
1625 }
1626
1627 static void bcd_add(TCGv dest, TCGv src)
1628 {
1629 TCGv t0, t1;
1630
1631 /* dest10 = dest10 + src10 + X
1632 *
1633 * t1 = src
1634 * t2 = t1 + 0x066
1635 * t3 = t2 + dest + X
1636 * t4 = t2 ^ dest
1637 * t5 = t3 ^ t4
1638 * t6 = ~t5 & 0x110
1639 * t7 = (t6 >> 2) | (t6 >> 3)
1640 * return t3 - t7
1641 */
1642
1643 /* t1 = (src + 0x066) + dest + X
1644 * = result with some possible exceding 0x6
1645 */
1646
1647 t0 = tcg_const_i32(0x066);
1648 tcg_gen_add_i32(t0, t0, src);
1649
1650 t1 = tcg_temp_new();
1651 tcg_gen_add_i32(t1, t0, dest);
1652 tcg_gen_add_i32(t1, t1, QREG_CC_X);
1653
1654 /* we will remove exceding 0x6 where there is no carry */
1655
1656 /* t0 = (src + 0x0066) ^ dest
1657 * = t1 without carries
1658 */
1659
1660 tcg_gen_xor_i32(t0, t0, dest);
1661
1662 /* extract the carries
1663 * t0 = t0 ^ t1
1664 * = only the carries
1665 */
1666
1667 tcg_gen_xor_i32(t0, t0, t1);
1668
1669 /* generate 0x1 where there is no carry
1670 * and for each 0x10, generate a 0x6
1671 */
1672
1673 tcg_gen_shri_i32(t0, t0, 3);
1674 tcg_gen_not_i32(t0, t0);
1675 tcg_gen_andi_i32(t0, t0, 0x22);
1676 tcg_gen_add_i32(dest, t0, t0);
1677 tcg_gen_add_i32(dest, dest, t0);
1678 tcg_temp_free(t0);
1679
1680 /* remove the exceding 0x6
1681 * for digits that have not generated a carry
1682 */
1683
1684 tcg_gen_sub_i32(dest, t1, dest);
1685 tcg_temp_free(t1);
1686 }
1687
1688 static void bcd_sub(TCGv dest, TCGv src)
1689 {
1690 TCGv t0, t1, t2;
1691
1692 /* dest10 = dest10 - src10 - X
1693 * = bcd_add(dest + 1 - X, 0x199 - src)
1694 */
1695
1696 /* t0 = 0x066 + (0x199 - src) */
1697
1698 t0 = tcg_temp_new();
1699 tcg_gen_subfi_i32(t0, 0x1ff, src);
1700
1701 /* t1 = t0 + dest + 1 - X*/
1702
1703 t1 = tcg_temp_new();
1704 tcg_gen_add_i32(t1, t0, dest);
1705 tcg_gen_addi_i32(t1, t1, 1);
1706 tcg_gen_sub_i32(t1, t1, QREG_CC_X);
1707
1708 /* t2 = t0 ^ dest */
1709
1710 t2 = tcg_temp_new();
1711 tcg_gen_xor_i32(t2, t0, dest);
1712
1713 /* t0 = t1 ^ t2 */
1714
1715 tcg_gen_xor_i32(t0, t1, t2);
1716
1717 /* t2 = ~t0 & 0x110
1718 * t0 = (t2 >> 2) | (t2 >> 3)
1719 *
1720 * to fit on 8bit operands, changed in:
1721 *
1722 * t2 = ~(t0 >> 3) & 0x22
1723 * t0 = t2 + t2
1724 * t0 = t0 + t2
1725 */
1726
1727 tcg_gen_shri_i32(t2, t0, 3);
1728 tcg_gen_not_i32(t2, t2);
1729 tcg_gen_andi_i32(t2, t2, 0x22);
1730 tcg_gen_add_i32(t0, t2, t2);
1731 tcg_gen_add_i32(t0, t0, t2);
1732 tcg_temp_free(t2);
1733
1734 /* return t1 - t0 */
1735
1736 tcg_gen_sub_i32(dest, t1, t0);
1737 tcg_temp_free(t0);
1738 tcg_temp_free(t1);
1739 }
1740
1741 static void bcd_flags(TCGv val)
1742 {
1743 tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
1744 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
1745
1746 tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
1747
1748 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
1749 }
1750
1751 DISAS_INSN(abcd_reg)
1752 {
1753 TCGv src;
1754 TCGv dest;
1755
1756 gen_flush_flags(s); /* !Z is sticky */
1757
1758 src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1759 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1760 bcd_add(dest, src);
1761 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1762
1763 bcd_flags(dest);
1764 }
1765
1766 DISAS_INSN(abcd_mem)
1767 {
1768 TCGv src, dest, addr;
1769
1770 gen_flush_flags(s); /* !Z is sticky */
1771
1772 /* Indirect pre-decrement load (mode 4) */
1773
1774 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1775 NULL_QREG, NULL, EA_LOADU);
1776 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1777 NULL_QREG, &addr, EA_LOADU);
1778
1779 bcd_add(dest, src);
1780
1781 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE);
1782
1783 bcd_flags(dest);
1784 }
1785
1786 DISAS_INSN(sbcd_reg)
1787 {
1788 TCGv src, dest;
1789
1790 gen_flush_flags(s); /* !Z is sticky */
1791
1792 src = gen_extend(DREG(insn, 0), OS_BYTE, 0);
1793 dest = gen_extend(DREG(insn, 9), OS_BYTE, 0);
1794
1795 bcd_sub(dest, src);
1796
1797 gen_partset_reg(OS_BYTE, DREG(insn, 9), dest);
1798
1799 bcd_flags(dest);
1800 }
1801
1802 DISAS_INSN(sbcd_mem)
1803 {
1804 TCGv src, dest, addr;
1805
1806 gen_flush_flags(s); /* !Z is sticky */
1807
1808 /* Indirect pre-decrement load (mode 4) */
1809
1810 src = gen_ea_mode(env, s, 4, REG(insn, 0), OS_BYTE,
1811 NULL_QREG, NULL, EA_LOADU);
1812 dest = gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE,
1813 NULL_QREG, &addr, EA_LOADU);
1814
1815 bcd_sub(dest, src);
1816
1817 gen_ea_mode(env, s, 4, REG(insn, 9), OS_BYTE, dest, &addr, EA_STORE);
1818
1819 bcd_flags(dest);
1820 }
1821
1822 DISAS_INSN(nbcd)
1823 {
1824 TCGv src, dest;
1825 TCGv addr;
1826
1827 gen_flush_flags(s); /* !Z is sticky */
1828
1829 SRC_EA(env, src, OS_BYTE, 0, &addr);
1830
1831 dest = tcg_const_i32(0);
1832 bcd_sub(dest, src);
1833
1834 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1835
1836 bcd_flags(dest);
1837
1838 tcg_temp_free(dest);
1839 }
1840
1841 DISAS_INSN(addsub)
1842 {
1843 TCGv reg;
1844 TCGv dest;
1845 TCGv src;
1846 TCGv tmp;
1847 TCGv addr;
1848 int add;
1849 int opsize;
1850
1851 add = (insn & 0x4000) != 0;
1852 opsize = insn_opsize(insn);
1853 reg = gen_extend(DREG(insn, 9), opsize, 1);
1854 dest = tcg_temp_new();
1855 if (insn & 0x100) {
1856 SRC_EA(env, tmp, opsize, 1, &addr);
1857 src = reg;
1858 } else {
1859 tmp = reg;
1860 SRC_EA(env, src, opsize, 1, NULL);
1861 }
1862 if (add) {
1863 tcg_gen_add_i32(dest, tmp, src);
1864 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1865 set_cc_op(s, CC_OP_ADDB + opsize);
1866 } else {
1867 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1868 tcg_gen_sub_i32(dest, tmp, src);
1869 set_cc_op(s, CC_OP_SUBB + opsize);
1870 }
1871 gen_update_cc_add(dest, src, opsize);
1872 if (insn & 0x100) {
1873 DEST_EA(env, insn, opsize, dest, &addr);
1874 } else {
1875 gen_partset_reg(opsize, DREG(insn, 9), dest);
1876 }
1877 tcg_temp_free(dest);
1878 }
1879
1880 /* Reverse the order of the bits in REG. */
1881 DISAS_INSN(bitrev)
1882 {
1883 TCGv reg;
1884 reg = DREG(insn, 0);
1885 gen_helper_bitrev(reg, reg);
1886 }
1887
1888 DISAS_INSN(bitop_reg)
1889 {
1890 int opsize;
1891 int op;
1892 TCGv src1;
1893 TCGv src2;
1894 TCGv tmp;
1895 TCGv addr;
1896 TCGv dest;
1897
1898 if ((insn & 0x38) != 0)
1899 opsize = OS_BYTE;
1900 else
1901 opsize = OS_LONG;
1902 op = (insn >> 6) & 3;
1903 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1904
1905 gen_flush_flags(s);
1906 src2 = tcg_temp_new();
1907 if (opsize == OS_BYTE)
1908 tcg_gen_andi_i32(src2, DREG(insn, 9), 7);
1909 else
1910 tcg_gen_andi_i32(src2, DREG(insn, 9), 31);
1911
1912 tmp = tcg_const_i32(1);
1913 tcg_gen_shl_i32(tmp, tmp, src2);
1914 tcg_temp_free(src2);
1915
1916 tcg_gen_and_i32(QREG_CC_Z, src1, tmp);
1917
1918 dest = tcg_temp_new();
1919 switch (op) {
1920 case 1: /* bchg */
1921 tcg_gen_xor_i32(dest, src1, tmp);
1922 break;
1923 case 2: /* bclr */
1924 tcg_gen_andc_i32(dest, src1, tmp);
1925 break;
1926 case 3: /* bset */
1927 tcg_gen_or_i32(dest, src1, tmp);
1928 break;
1929 default: /* btst */
1930 break;
1931 }
1932 tcg_temp_free(tmp);
1933 if (op) {
1934 DEST_EA(env, insn, opsize, dest, &addr);
1935 }
1936 tcg_temp_free(dest);
1937 }
1938
1939 DISAS_INSN(sats)
1940 {
1941 TCGv reg;
1942 reg = DREG(insn, 0);
1943 gen_flush_flags(s);
1944 gen_helper_sats(reg, reg, QREG_CC_V);
1945 gen_logic_cc(s, reg, OS_LONG);
1946 }
1947
1948 static void gen_push(DisasContext *s, TCGv val)
1949 {
1950 TCGv tmp;
1951
1952 tmp = tcg_temp_new();
1953 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1954 gen_store(s, OS_LONG, tmp, val);
1955 tcg_gen_mov_i32(QREG_SP, tmp);
1956 tcg_temp_free(tmp);
1957 }
1958
1959 static TCGv mreg(int reg)
1960 {
1961 if (reg < 8) {
1962 /* Dx */
1963 return cpu_dregs[reg];
1964 }
1965 /* Ax */
1966 return cpu_aregs[reg & 7];
1967 }
1968
1969 DISAS_INSN(movem)
1970 {
1971 TCGv addr, incr, tmp, r[16];
1972 int is_load = (insn & 0x0400) != 0;
1973 int opsize = (insn & 0x40) != 0 ? OS_LONG : OS_WORD;
1974 uint16_t mask = read_im16(env, s);
1975 int mode = extract32(insn, 3, 3);
1976 int reg0 = REG(insn, 0);
1977 int i;
1978
1979 tmp = cpu_aregs[reg0];
1980
1981 switch (mode) {
1982 case 0: /* data register direct */
1983 case 1: /* addr register direct */
1984 do_addr_fault:
1985 gen_addr_fault(s);
1986 return;
1987
1988 case 2: /* indirect */
1989 break;
1990
1991 case 3: /* indirect post-increment */
1992 if (!is_load) {
1993 /* post-increment is not allowed */
1994 goto do_addr_fault;
1995 }
1996 break;
1997
1998 case 4: /* indirect pre-decrement */
1999 if (is_load) {
2000 /* pre-decrement is not allowed */
2001 goto do_addr_fault;
2002 }
2003 /* We want a bare copy of the address reg, without any pre-decrement
2004 adjustment, as gen_lea would provide. */
2005 break;
2006
2007 default:
2008 tmp = gen_lea_mode(env, s, mode, reg0, opsize);
2009 if (IS_NULL_QREG(tmp)) {
2010 goto do_addr_fault;
2011 }
2012 break;
2013 }
2014
2015 addr = tcg_temp_new();
2016 tcg_gen_mov_i32(addr, tmp);
2017 incr = tcg_const_i32(opsize_bytes(opsize));
2018
2019 if (is_load) {
2020 /* memory to register */
2021 for (i = 0; i < 16; i++) {
2022 if (mask & (1 << i)) {
2023 r[i] = gen_load(s, opsize, addr, 1);
2024 tcg_gen_add_i32(addr, addr, incr);
2025 }
2026 }
2027 for (i = 0; i < 16; i++) {
2028 if (mask & (1 << i)) {
2029 tcg_gen_mov_i32(mreg(i), r[i]);
2030 tcg_temp_free(r[i]);
2031 }
2032 }
2033 if (mode == 3) {
2034 /* post-increment: movem (An)+,X */
2035 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2036 }
2037 } else {
2038 /* register to memory */
2039 if (mode == 4) {
2040 /* pre-decrement: movem X,-(An) */
2041 for (i = 15; i >= 0; i--) {
2042 if ((mask << i) & 0x8000) {
2043 tcg_gen_sub_i32(addr, addr, incr);
2044 if (reg0 + 8 == i &&
2045 m68k_feature(s->env, M68K_FEATURE_EXT_FULL)) {
2046 /* M68020+: if the addressing register is the
2047 * register moved to memory, the value written
2048 * is the initial value decremented by the size of
2049 * the operation, regardless of how many actual
2050 * stores have been performed until this point.
2051 * M68000/M68010: the value is the initial value.
2052 */
2053 tmp = tcg_temp_new();
2054 tcg_gen_sub_i32(tmp, cpu_aregs[reg0], incr);
2055 gen_store(s, opsize, addr, tmp);
2056 tcg_temp_free(tmp);
2057 } else {
2058 gen_store(s, opsize, addr, mreg(i));
2059 }
2060 }
2061 }
2062 tcg_gen_mov_i32(cpu_aregs[reg0], addr);
2063 } else {
2064 for (i = 0; i < 16; i++) {
2065 if (mask & (1 << i)) {
2066 gen_store(s, opsize, addr, mreg(i));
2067 tcg_gen_add_i32(addr, addr, incr);
2068 }
2069 }
2070 }
2071 }
2072
2073 tcg_temp_free(incr);
2074 tcg_temp_free(addr);
2075 }
2076
2077 DISAS_INSN(bitop_im)
2078 {
2079 int opsize;
2080 int op;
2081 TCGv src1;
2082 uint32_t mask;
2083 int bitnum;
2084 TCGv tmp;
2085 TCGv addr;
2086
2087 if ((insn & 0x38) != 0)
2088 opsize = OS_BYTE;
2089 else
2090 opsize = OS_LONG;
2091 op = (insn >> 6) & 3;
2092
2093 bitnum = read_im16(env, s);
2094 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2095 if (bitnum & 0xfe00) {
2096 disas_undef(env, s, insn);
2097 return;
2098 }
2099 } else {
2100 if (bitnum & 0xff00) {
2101 disas_undef(env, s, insn);
2102 return;
2103 }
2104 }
2105
2106 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
2107
2108 gen_flush_flags(s);
2109 if (opsize == OS_BYTE)
2110 bitnum &= 7;
2111 else
2112 bitnum &= 31;
2113 mask = 1 << bitnum;
2114
2115 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
2116
2117 if (op) {
2118 tmp = tcg_temp_new();
2119 switch (op) {
2120 case 1: /* bchg */
2121 tcg_gen_xori_i32(tmp, src1, mask);
2122 break;
2123 case 2: /* bclr */
2124 tcg_gen_andi_i32(tmp, src1, ~mask);
2125 break;
2126 case 3: /* bset */
2127 tcg_gen_ori_i32(tmp, src1, mask);
2128 break;
2129 default: /* btst */
2130 break;
2131 }
2132 DEST_EA(env, insn, opsize, tmp, &addr);
2133 tcg_temp_free(tmp);
2134 }
2135 }
2136
2137 DISAS_INSN(arith_im)
2138 {
2139 int op;
2140 TCGv im;
2141 TCGv src1;
2142 TCGv dest;
2143 TCGv addr;
2144 int opsize;
2145
2146 op = (insn >> 9) & 7;
2147 opsize = insn_opsize(insn);
2148 switch (opsize) {
2149 case OS_BYTE:
2150 im = tcg_const_i32((int8_t)read_im8(env, s));
2151 break;
2152 case OS_WORD:
2153 im = tcg_const_i32((int16_t)read_im16(env, s));
2154 break;
2155 case OS_LONG:
2156 im = tcg_const_i32(read_im32(env, s));
2157 break;
2158 default:
2159 abort();
2160 }
2161 SRC_EA(env, src1, opsize, 1, (op == 6) ? NULL : &addr);
2162 dest = tcg_temp_new();
2163 switch (op) {
2164 case 0: /* ori */
2165 tcg_gen_or_i32(dest, src1, im);
2166 gen_logic_cc(s, dest, opsize);
2167 break;
2168 case 1: /* andi */
2169 tcg_gen_and_i32(dest, src1, im);
2170 gen_logic_cc(s, dest, opsize);
2171 break;
2172 case 2: /* subi */
2173 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, src1, im);
2174 tcg_gen_sub_i32(dest, src1, im);
2175 gen_update_cc_add(dest, im, opsize);
2176 set_cc_op(s, CC_OP_SUBB + opsize);
2177 break;
2178 case 3: /* addi */
2179 tcg_gen_add_i32(dest, src1, im);
2180 gen_update_cc_add(dest, im, opsize);
2181 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
2182 set_cc_op(s, CC_OP_ADDB + opsize);
2183 break;
2184 case 5: /* eori */
2185 tcg_gen_xor_i32(dest, src1, im);
2186 gen_logic_cc(s, dest, opsize);
2187 break;
2188 case 6: /* cmpi */
2189 gen_update_cc_cmp(s, src1, im, opsize);
2190 break;
2191 default:
2192 abort();
2193 }
2194 tcg_temp_free(im);
2195 if (op != 6) {
2196 DEST_EA(env, insn, opsize, dest, &addr);
2197 }
2198 tcg_temp_free(dest);
2199 }
2200
2201 DISAS_INSN(cas)
2202 {
2203 int opsize;
2204 TCGv addr;
2205 uint16_t ext;
2206 TCGv load;
2207 TCGv cmp;
2208 TCGMemOp opc;
2209
2210 switch ((insn >> 9) & 3) {
2211 case 1:
2212 opsize = OS_BYTE;
2213 opc = MO_SB;
2214 break;
2215 case 2:
2216 opsize = OS_WORD;
2217 opc = MO_TESW;
2218 break;
2219 case 3:
2220 opsize = OS_LONG;
2221 opc = MO_TESL;
2222 break;
2223 default:
2224 g_assert_not_reached();
2225 }
2226
2227 ext = read_im16(env, s);
2228
2229 /* cas Dc,Du,<EA> */
2230
2231 addr = gen_lea(env, s, insn, opsize);
2232 if (IS_NULL_QREG(addr)) {
2233 gen_addr_fault(s);
2234 return;
2235 }
2236
2237 cmp = gen_extend(DREG(ext, 0), opsize, 1);
2238
2239 /* if <EA> == Dc then
2240 * <EA> = Du
2241 * Dc = <EA> (because <EA> == Dc)
2242 * else
2243 * Dc = <EA>
2244 */
2245
2246 load = tcg_temp_new();
2247 tcg_gen_atomic_cmpxchg_i32(load, addr, cmp, DREG(ext, 6),
2248 IS_USER(s), opc);
2249 /* update flags before setting cmp to load */
2250 gen_update_cc_cmp(s, load, cmp, opsize);
2251 gen_partset_reg(opsize, DREG(ext, 0), load);
2252
2253 tcg_temp_free(load);
2254
2255 switch (extract32(insn, 3, 3)) {
2256 case 3: /* Indirect postincrement. */
2257 tcg_gen_addi_i32(AREG(insn, 0), addr, opsize_bytes(opsize));
2258 break;
2259 case 4: /* Indirect predecrememnt. */
2260 tcg_gen_mov_i32(AREG(insn, 0), addr);
2261 break;
2262 }
2263 }
2264
2265 DISAS_INSN(cas2w)
2266 {
2267 uint16_t ext1, ext2;
2268 TCGv addr1, addr2;
2269 TCGv regs;
2270
2271 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2272
2273 ext1 = read_im16(env, s);
2274
2275 if (ext1 & 0x8000) {
2276 /* Address Register */
2277 addr1 = AREG(ext1, 12);
2278 } else {
2279 /* Data Register */
2280 addr1 = DREG(ext1, 12);
2281 }
2282
2283 ext2 = read_im16(env, s);
2284 if (ext2 & 0x8000) {
2285 /* Address Register */
2286 addr2 = AREG(ext2, 12);
2287 } else {
2288 /* Data Register */
2289 addr2 = DREG(ext2, 12);
2290 }
2291
2292 /* if (R1) == Dc1 && (R2) == Dc2 then
2293 * (R1) = Du1
2294 * (R2) = Du2
2295 * else
2296 * Dc1 = (R1)
2297 * Dc2 = (R2)
2298 */
2299
2300 regs = tcg_const_i32(REG(ext2, 6) |
2301 (REG(ext1, 6) << 3) |
2302 (REG(ext2, 0) << 6) |
2303 (REG(ext1, 0) << 9));
2304 if (tb_cflags(s->tb) & CF_PARALLEL) {
2305 gen_helper_exit_atomic(cpu_env);
2306 } else {
2307 gen_helper_cas2w(cpu_env, regs, addr1, addr2);
2308 }
2309 tcg_temp_free(regs);
2310
2311 /* Note that cas2w also assigned to env->cc_op. */
2312 s->cc_op = CC_OP_CMPW;
2313 s->cc_op_synced = 1;
2314 }
2315
2316 DISAS_INSN(cas2l)
2317 {
2318 uint16_t ext1, ext2;
2319 TCGv addr1, addr2, regs;
2320
2321 /* cas2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) */
2322
2323 ext1 = read_im16(env, s);
2324
2325 if (ext1 & 0x8000) {
2326 /* Address Register */
2327 addr1 = AREG(ext1, 12);
2328 } else {
2329 /* Data Register */
2330 addr1 = DREG(ext1, 12);
2331 }
2332
2333 ext2 = read_im16(env, s);
2334 if (ext2 & 0x8000) {
2335 /* Address Register */
2336 addr2 = AREG(ext2, 12);
2337 } else {
2338 /* Data Register */
2339 addr2 = DREG(ext2, 12);
2340 }
2341
2342 /* if (R1) == Dc1 && (R2) == Dc2 then
2343 * (R1) = Du1
2344 * (R2) = Du2
2345 * else
2346 * Dc1 = (R1)
2347 * Dc2 = (R2)
2348 */
2349
2350 regs = tcg_const_i32(REG(ext2, 6) |
2351 (REG(ext1, 6) << 3) |
2352 (REG(ext2, 0) << 6) |
2353 (REG(ext1, 0) << 9));
2354 if (tb_cflags(s->tb) & CF_PARALLEL) {
2355 gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2);
2356 } else {
2357 gen_helper_cas2l(cpu_env, regs, addr1, addr2);
2358 }
2359 tcg_temp_free(regs);
2360
2361 /* Note that cas2l also assigned to env->cc_op. */
2362 s->cc_op = CC_OP_CMPL;
2363 s->cc_op_synced = 1;
2364 }
2365
2366 DISAS_INSN(byterev)
2367 {
2368 TCGv reg;
2369
2370 reg = DREG(insn, 0);
2371 tcg_gen_bswap32_i32(reg, reg);
2372 }
2373
2374 DISAS_INSN(move)
2375 {
2376 TCGv src;
2377 TCGv dest;
2378 int op;
2379 int opsize;
2380
2381 switch (insn >> 12) {
2382 case 1: /* move.b */
2383 opsize = OS_BYTE;
2384 break;
2385 case 2: /* move.l */
2386 opsize = OS_LONG;
2387 break;
2388 case 3: /* move.w */
2389 opsize = OS_WORD;
2390 break;
2391 default:
2392 abort();
2393 }
2394 SRC_EA(env, src, opsize, 1, NULL);
2395 op = (insn >> 6) & 7;
2396 if (op == 1) {
2397 /* movea */
2398 /* The value will already have been sign extended. */
2399 dest = AREG(insn, 9);
2400 tcg_gen_mov_i32(dest, src);
2401 } else {
2402 /* normal move */
2403 uint16_t dest_ea;
2404 dest_ea = ((insn >> 9) & 7) | (op << 3);
2405 DEST_EA(env, dest_ea, opsize, src, NULL);
2406 /* This will be correct because loads sign extend. */
2407 gen_logic_cc(s, src, opsize);
2408 }
2409 }
2410
2411 DISAS_INSN(negx)
2412 {
2413 TCGv z;
2414 TCGv src;
2415 TCGv addr;
2416 int opsize;
2417
2418 opsize = insn_opsize(insn);
2419 SRC_EA(env, src, opsize, 1, &addr);
2420
2421 gen_flush_flags(s); /* compute old Z */
2422
2423 /* Perform substract with borrow.
2424 * (X, N) = -(src + X);
2425 */
2426
2427 z = tcg_const_i32(0);
2428 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, z, QREG_CC_X, z);
2429 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, z, z, QREG_CC_N, QREG_CC_X);
2430 tcg_temp_free(z);
2431 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2432
2433 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2434
2435 /* Compute signed-overflow for negation. The normal formula for
2436 * subtraction is (res ^ src) & (src ^ dest), but with dest==0
2437 * this simplies to res & src.
2438 */
2439
2440 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src);
2441
2442 /* Copy the rest of the results into place. */
2443 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2444 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2445
2446 set_cc_op(s, CC_OP_FLAGS);
2447
2448 /* result is in QREG_CC_N */
2449
2450 DEST_EA(env, insn, opsize, QREG_CC_N, &addr);
2451 }
2452
2453 DISAS_INSN(lea)
2454 {
2455 TCGv reg;
2456 TCGv tmp;
2457
2458 reg = AREG(insn, 9);
2459 tmp = gen_lea(env, s, insn, OS_LONG);
2460 if (IS_NULL_QREG(tmp)) {
2461 gen_addr_fault(s);
2462 return;
2463 }
2464 tcg_gen_mov_i32(reg, tmp);
2465 }
2466
2467 DISAS_INSN(clr)
2468 {
2469 int opsize;
2470 TCGv zero;
2471
2472 zero = tcg_const_i32(0);
2473
2474 opsize = insn_opsize(insn);
2475 DEST_EA(env, insn, opsize, zero, NULL);
2476 gen_logic_cc(s, zero, opsize);
2477 tcg_temp_free(zero);
2478 }
2479
2480 static TCGv gen_get_ccr(DisasContext *s)
2481 {
2482 TCGv dest;
2483
2484 gen_flush_flags(s);
2485 update_cc_op(s);
2486 dest = tcg_temp_new();
2487 gen_helper_get_ccr(dest, cpu_env);
2488 return dest;
2489 }
2490
2491 DISAS_INSN(move_from_ccr)
2492 {
2493 TCGv ccr;
2494
2495 ccr = gen_get_ccr(s);
2496 DEST_EA(env, insn, OS_WORD, ccr, NULL);
2497 }
2498
2499 DISAS_INSN(neg)
2500 {
2501 TCGv src1;
2502 TCGv dest;
2503 TCGv addr;
2504 int opsize;
2505
2506 opsize = insn_opsize(insn);
2507 SRC_EA(env, src1, opsize, 1, &addr);
2508 dest = tcg_temp_new();
2509 tcg_gen_neg_i32(dest, src1);
2510 set_cc_op(s, CC_OP_SUBB + opsize);
2511 gen_update_cc_add(dest, src1, opsize);
2512 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, dest, 0);
2513 DEST_EA(env, insn, opsize, dest, &addr);
2514 tcg_temp_free(dest);
2515 }
2516
2517 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
2518 {
2519 if (ccr_only) {
2520 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
2521 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
2522 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
2523 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
2524 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
2525 } else {
2526 gen_helper_set_sr(cpu_env, tcg_const_i32(val));
2527 }
2528 set_cc_op(s, CC_OP_FLAGS);
2529 }
2530
2531 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
2532 int ccr_only)
2533 {
2534 if ((insn & 0x38) == 0) {
2535 if (ccr_only) {
2536 gen_helper_set_ccr(cpu_env, DREG(insn, 0));
2537 } else {
2538 gen_helper_set_sr(cpu_env, DREG(insn, 0));
2539 }
2540 set_cc_op(s, CC_OP_FLAGS);
2541 } else if ((insn & 0x3f) == 0x3c) {
2542 uint16_t val;
2543 val = read_im16(env, s);
2544 gen_set_sr_im(s, val, ccr_only);
2545 } else {
2546 disas_undef(env, s, insn);
2547 }
2548 }
2549
2550
2551 DISAS_INSN(move_to_ccr)
2552 {
2553 gen_set_sr(env, s, insn, 1);
2554 }
2555
2556 DISAS_INSN(not)
2557 {
2558 TCGv src1;
2559 TCGv dest;
2560 TCGv addr;
2561 int opsize;
2562
2563 opsize = insn_opsize(insn);
2564 SRC_EA(env, src1, opsize, 1, &addr);
2565 dest = tcg_temp_new();
2566 tcg_gen_not_i32(dest, src1);
2567 DEST_EA(env, insn, opsize, dest, &addr);
2568 gen_logic_cc(s, dest, opsize);
2569 }
2570
2571 DISAS_INSN(swap)
2572 {
2573 TCGv src1;
2574 TCGv src2;
2575 TCGv reg;
2576
2577 src1 = tcg_temp_new();
2578 src2 = tcg_temp_new();
2579 reg = DREG(insn, 0);
2580 tcg_gen_shli_i32(src1, reg, 16);
2581 tcg_gen_shri_i32(src2, reg, 16);
2582 tcg_gen_or_i32(reg, src1, src2);
2583 tcg_temp_free(src2);
2584 tcg_temp_free(src1);
2585 gen_logic_cc(s, reg, OS_LONG);
2586 }
2587
2588 DISAS_INSN(bkpt)
2589 {
2590 gen_exception(s, s->pc - 2, EXCP_DEBUG);
2591 }
2592
2593 DISAS_INSN(pea)
2594 {
2595 TCGv tmp;
2596
2597 tmp = gen_lea(env, s, insn, OS_LONG);
2598 if (IS_NULL_QREG(tmp)) {
2599 gen_addr_fault(s);
2600 return;
2601 }
2602 gen_push(s, tmp);
2603 }
2604
2605 DISAS_INSN(ext)
2606 {
2607 int op;
2608 TCGv reg;
2609 TCGv tmp;
2610
2611 reg = DREG(insn, 0);
2612 op = (insn >> 6) & 7;
2613 tmp = tcg_temp_new();
2614 if (op == 3)
2615 tcg_gen_ext16s_i32(tmp, reg);
2616 else
2617 tcg_gen_ext8s_i32(tmp, reg);
2618 if (op == 2)
2619 gen_partset_reg(OS_WORD, reg, tmp);
2620 else
2621 tcg_gen_mov_i32(reg, tmp);
2622 gen_logic_cc(s, tmp, OS_LONG);
2623 tcg_temp_free(tmp);
2624 }
2625
2626 DISAS_INSN(tst)
2627 {
2628 int opsize;
2629 TCGv tmp;
2630
2631 opsize = insn_opsize(insn);
2632 SRC_EA(env, tmp, opsize, 1, NULL);
2633 gen_logic_cc(s, tmp, opsize);
2634 }
2635
2636 DISAS_INSN(pulse)
2637 {
2638 /* Implemented as a NOP. */
2639 }
2640
2641 DISAS_INSN(illegal)
2642 {
2643 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
2644 }
2645
2646 /* ??? This should be atomic. */
2647 DISAS_INSN(tas)
2648 {
2649 TCGv dest;
2650 TCGv src1;
2651 TCGv addr;
2652
2653 dest = tcg_temp_new();
2654 SRC_EA(env, src1, OS_BYTE, 1, &addr);
2655 gen_logic_cc(s, src1, OS_BYTE);
2656 tcg_gen_ori_i32(dest, src1, 0x80);
2657 DEST_EA(env, insn, OS_BYTE, dest, &addr);
2658 tcg_temp_free(dest);
2659 }
2660
2661 DISAS_INSN(mull)
2662 {
2663 uint16_t ext;
2664 TCGv src1;
2665 int sign;
2666
2667 ext = read_im16(env, s);
2668
2669 sign = ext & 0x800;
2670
2671 if (ext & 0x400) {
2672 if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
2673 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
2674 return;
2675 }
2676
2677 SRC_EA(env, src1, OS_LONG, 0, NULL);
2678
2679 if (sign) {
2680 tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2681 } else {
2682 tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
2683 }
2684 /* if Dl == Dh, 68040 returns low word */
2685 tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
2686 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
2687 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
2688
2689 tcg_gen_movi_i32(QREG_CC_V, 0);
2690 tcg_gen_movi_i32(QREG_CC_C, 0);
2691
2692 set_cc_op(s, CC_OP_FLAGS);
2693 return;
2694 }
2695 SRC_EA(env, src1, OS_LONG, 0, NULL);
2696 if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
2697 tcg_gen_movi_i32(QREG_CC_C, 0);
2698 if (sign) {
2699 tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2700 /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
2701 tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
2702 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
2703 } else {
2704 tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
2705 /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
2706 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
2707 }
2708 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
2709 tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
2710
2711 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
2712
2713 set_cc_op(s, CC_OP_FLAGS);
2714 } else {
2715 /* The upper 32 bits of the product are discarded, so
2716 muls.l and mulu.l are functionally equivalent. */
2717 tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
2718 gen_logic_cc(s, DREG(ext, 12), OS_LONG);
2719 }
2720 }
2721
2722 static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
2723 {
2724 TCGv reg;
2725 TCGv tmp;
2726
2727 reg = AREG(insn, 0);
2728 tmp = tcg_temp_new();
2729 tcg_gen_subi_i32(tmp, QREG_SP, 4);
2730 gen_store(s, OS_LONG, tmp, reg);
2731 if ((insn & 7) != 7) {
2732 tcg_gen_mov_i32(reg, tmp);
2733 }
2734 tcg_gen_addi_i32(QREG_SP, tmp, offset);
2735 tcg_temp_free(tmp);
2736 }
2737
2738 DISAS_INSN(link)
2739 {
2740 int16_t offset;
2741
2742 offset = read_im16(env, s);
2743 gen_link(s, insn, offset);
2744 }
2745
2746 DISAS_INSN(linkl)
2747 {
2748 int32_t offset;
2749
2750 offset = read_im32(env, s);
2751 gen_link(s, insn, offset);
2752 }
2753
2754 DISAS_INSN(unlk)
2755 {
2756 TCGv src;
2757 TCGv reg;
2758 TCGv tmp;
2759
2760 src = tcg_temp_new();
2761 reg = AREG(insn, 0);
2762 tcg_gen_mov_i32(src, reg);
2763 tmp = gen_load(s, OS_LONG, src, 0);
2764 tcg_gen_mov_i32(reg, tmp);
2765 tcg_gen_addi_i32(QREG_SP, src, 4);
2766 tcg_temp_free(src);
2767 }
2768
2769 DISAS_INSN(nop)
2770 {
2771 }
2772
2773 DISAS_INSN(rtd)
2774 {
2775 TCGv tmp;
2776 int16_t offset = read_im16(env, s);
2777
2778 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
2779 tcg_gen_addi_i32(QREG_SP, QREG_SP, offset + 4);
2780 gen_jmp(s, tmp);
2781 }
2782
2783 DISAS_INSN(rts)
2784 {
2785 TCGv tmp;
2786
2787 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
2788 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
2789 gen_jmp(s, tmp);
2790 }
2791
2792 DISAS_INSN(jump)
2793 {
2794 TCGv tmp;
2795
2796 /* Load the target address first to ensure correct exception
2797 behavior. */
2798 tmp = gen_lea(env, s, insn, OS_LONG);
2799 if (IS_NULL_QREG(tmp)) {
2800 gen_addr_fault(s);
2801 return;
2802 }
2803 if ((insn & 0x40) == 0) {
2804 /* jsr */
2805 gen_push(s, tcg_const_i32(s->pc));
2806 }
2807 gen_jmp(s, tmp);
2808 }
2809
2810 DISAS_INSN(addsubq)
2811 {
2812 TCGv src;
2813 TCGv dest;
2814 TCGv val;
2815 int imm;
2816 TCGv addr;
2817 int opsize;
2818
2819 if ((insn & 070) == 010) {
2820 /* Operation on address register is always long. */
2821 opsize = OS_LONG;
2822 } else {
2823 opsize = insn_opsize(insn);
2824 }
2825 SRC_EA(env, src, opsize, 1, &addr);
2826 imm = (insn >> 9) & 7;
2827 if (imm == 0) {
2828 imm = 8;
2829 }
2830 val = tcg_const_i32(imm);
2831 dest = tcg_temp_new();
2832 tcg_gen_mov_i32(dest, src);
2833 if ((insn & 0x38) == 0x08) {
2834 /* Don't update condition codes if the destination is an
2835 address register. */
2836 if (insn & 0x0100) {
2837 tcg_gen_sub_i32(dest, dest, val);
2838 } else {
2839 tcg_gen_add_i32(dest, dest, val);
2840 }
2841 } else {
2842 if (insn & 0x0100) {
2843 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2844 tcg_gen_sub_i32(dest, dest, val);
2845 set_cc_op(s, CC_OP_SUBB + opsize);
2846 } else {
2847 tcg_gen_add_i32(dest, dest, val);
2848 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, val);
2849 set_cc_op(s, CC_OP_ADDB + opsize);
2850 }
2851 gen_update_cc_add(dest, val, opsize);
2852 }
2853 tcg_temp_free(val);
2854 DEST_EA(env, insn, opsize, dest, &addr);
2855 tcg_temp_free(dest);
2856 }
2857
2858 DISAS_INSN(tpf)
2859 {
2860 switch (insn & 7) {
2861 case 2: /* One extension word. */
2862 s->pc += 2;
2863 break;
2864 case 3: /* Two extension words. */
2865 s->pc += 4;
2866 break;
2867 case 4: /* No extension words. */
2868 break;
2869 default:
2870 disas_undef(env, s, insn);
2871 }
2872 }
2873
2874 DISAS_INSN(branch)
2875 {
2876 int32_t offset;
2877 uint32_t base;
2878 int op;
2879 TCGLabel *l1;
2880
2881 base = s->pc;
2882 op = (insn >> 8) & 0xf;
2883 offset = (int8_t)insn;
2884 if (offset == 0) {
2885 offset = (int16_t)read_im16(env, s);
2886 } else if (offset == -1) {
2887 offset = read_im32(env, s);
2888 }
2889 if (op == 1) {
2890 /* bsr */
2891 gen_push(s, tcg_const_i32(s->pc));
2892 }
2893 if (op > 1) {
2894 /* Bcc */
2895 l1 = gen_new_label();
2896 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
2897 gen_jmp_tb(s, 1, base + offset);
2898 gen_set_label(l1);
2899 gen_jmp_tb(s, 0, s->pc);
2900 } else {
2901 /* Unconditional branch. */
2902 gen_jmp_tb(s, 0, base + offset);
2903 }
2904 }
2905
2906 DISAS_INSN(moveq)
2907 {
2908 tcg_gen_movi_i32(DREG(insn, 9), (int8_t)insn);
2909 gen_logic_cc(s, DREG(insn, 9), OS_LONG);
2910 }
2911
2912 DISAS_INSN(mvzs)
2913 {
2914 int opsize;
2915 TCGv src;
2916 TCGv reg;
2917
2918 if (insn & 0x40)
2919 opsize = OS_WORD;
2920 else
2921 opsize = OS_BYTE;
2922 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
2923 reg = DREG(insn, 9);
2924 tcg_gen_mov_i32(reg, src);
2925 gen_logic_cc(s, src, opsize);
2926 }
2927
2928 DISAS_INSN(or)
2929 {
2930 TCGv reg;
2931 TCGv dest;
2932 TCGv src;
2933 TCGv addr;
2934 int opsize;
2935
2936 opsize = insn_opsize(insn);
2937 reg = gen_extend(DREG(insn, 9), opsize, 0);
2938 dest = tcg_temp_new();
2939 if (insn & 0x100) {
2940 SRC_EA(env, src, opsize, 0, &addr);
2941 tcg_gen_or_i32(dest, src, reg);
2942 DEST_EA(env, insn, opsize, dest, &addr);
2943 } else {
2944 SRC_EA(env, src, opsize, 0, NULL);
2945 tcg_gen_or_i32(dest, src, reg);
2946 gen_partset_reg(opsize, DREG(insn, 9), dest);
2947 }
2948 gen_logic_cc(s, dest, opsize);
2949 tcg_temp_free(dest);
2950 }
2951
2952 DISAS_INSN(suba)
2953 {
2954 TCGv src;
2955 TCGv reg;
2956
2957 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
2958 reg = AREG(insn, 9);
2959 tcg_gen_sub_i32(reg, reg, src);
2960 }
2961
2962 static inline void gen_subx(DisasContext *s, TCGv src, TCGv dest, int opsize)
2963 {
2964 TCGv tmp;
2965
2966 gen_flush_flags(s); /* compute old Z */
2967
2968 /* Perform substract with borrow.
2969 * (X, N) = dest - (src + X);
2970 */
2971
2972 tmp = tcg_const_i32(0);
2973 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, src, tmp, QREG_CC_X, tmp);
2974 tcg_gen_sub2_i32(QREG_CC_N, QREG_CC_X, dest, tmp, QREG_CC_N, QREG_CC_X);
2975 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
2976 tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1);
2977
2978 /* Compute signed-overflow for substract. */
2979
2980 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest);
2981 tcg_gen_xor_i32(tmp, dest, src);
2982 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, tmp);
2983 tcg_temp_free(tmp);
2984
2985 /* Copy the rest of the results into place. */
2986 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
2987 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
2988
2989 set_cc_op(s, CC_OP_FLAGS);
2990
2991 /* result is in QREG_CC_N */
2992 }
2993
2994 DISAS_INSN(subx_reg)
2995 {
2996 TCGv dest;
2997 TCGv src;
2998 int opsize;
2999
3000 opsize = insn_opsize(insn);
3001
3002 src = gen_extend(DREG(insn, 0), opsize, 1);
3003 dest = gen_extend(DREG(insn, 9), opsize, 1);
3004
3005 gen_subx(s, src, dest, opsize);
3006
3007 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3008 }
3009
3010 DISAS_INSN(subx_mem)
3011 {
3012 TCGv src;
3013 TCGv addr_src;
3014 TCGv dest;
3015 TCGv addr_dest;
3016 int opsize;
3017
3018 opsize = insn_opsize(insn);
3019
3020 addr_src = AREG(insn, 0);
3021 tcg_gen_subi_i32(addr_src, addr_src, opsize);
3022 src = gen_load(s, opsize, addr_src, 1);
3023
3024 addr_dest = AREG(insn, 9);
3025 tcg_gen_subi_i32(addr_dest, addr_dest, opsize);
3026 dest = gen_load(s, opsize, addr_dest, 1);
3027
3028 gen_subx(s, src, dest, opsize);
3029
3030 gen_store(s, opsize, addr_dest, QREG_CC_N);
3031 }
3032
3033 DISAS_INSN(mov3q)
3034 {
3035 TCGv src;
3036 int val;
3037
3038 val = (insn >> 9) & 7;
3039 if (val == 0)
3040 val = -1;
3041 src = tcg_const_i32(val);
3042 gen_logic_cc(s, src, OS_LONG);
3043 DEST_EA(env, insn, OS_LONG, src, NULL);
3044 tcg_temp_free(src);
3045 }
3046
3047 DISAS_INSN(cmp)
3048 {
3049 TCGv src;
3050 TCGv reg;
3051 int opsize;
3052
3053 opsize = insn_opsize(insn);
3054 SRC_EA(env, src, opsize, 1, NULL);
3055 reg = gen_extend(DREG(insn, 9), opsize, 1);
3056 gen_update_cc_cmp(s, reg, src, opsize);
3057 }
3058
3059 DISAS_INSN(cmpa)
3060 {
3061 int opsize;
3062 TCGv src;
3063 TCGv reg;
3064
3065 if (insn & 0x100) {
3066 opsize = OS_LONG;
3067 } else {
3068 opsize = OS_WORD;
3069 }
3070 SRC_EA(env, src, opsize, 1, NULL);
3071 reg = AREG(insn, 9);
3072 gen_update_cc_cmp(s, reg, src, OS_LONG);
3073 }
3074
3075 DISAS_INSN(cmpm)
3076 {
3077 int opsize = insn_opsize(insn);
3078 TCGv src, dst;
3079
3080 /* Post-increment load (mode 3) from Ay. */
3081 src = gen_ea_mode(env, s, 3, REG(insn, 0), opsize,
3082 NULL_QREG, NULL, EA_LOADS);
3083 /* Post-increment load (mode 3) from Ax. */
3084 dst = gen_ea_mode(env, s, 3, REG(insn, 9), opsize,
3085 NULL_QREG, NULL, EA_LOADS);
3086
3087 gen_update_cc_cmp(s, dst, src, opsize);
3088 }
3089
3090 DISAS_INSN(eor)
3091 {
3092 TCGv src;
3093 TCGv dest;
3094 TCGv addr;
3095 int opsize;
3096
3097 opsize = insn_opsize(insn);
3098
3099 SRC_EA(env, src, opsize, 0, &addr);
3100 dest = tcg_temp_new();
3101 tcg_gen_xor_i32(dest, src, DREG(insn, 9));
3102 gen_logic_cc(s, dest, opsize);
3103 DEST_EA(env, insn, opsize, dest, &addr);
3104 tcg_temp_free(dest);
3105 }
3106
3107 static void do_exg(TCGv reg1, TCGv reg2)
3108 {
3109 TCGv temp = tcg_temp_new();
3110 tcg_gen_mov_i32(temp, reg1);
3111 tcg_gen_mov_i32(reg1, reg2);
3112 tcg_gen_mov_i32(reg2, temp);
3113 tcg_temp_free(temp);
3114 }
3115
3116 DISAS_INSN(exg_dd)
3117 {
3118 /* exchange Dx and Dy */
3119 do_exg(DREG(insn, 9), DREG(insn, 0));
3120 }
3121
3122 DISAS_INSN(exg_aa)
3123 {
3124 /* exchange Ax and Ay */
3125 do_exg(AREG(insn, 9), AREG(insn, 0));
3126 }
3127
3128 DISAS_INSN(exg_da)
3129 {
3130 /* exchange Dx and Ay */
3131 do_exg(DREG(insn, 9), AREG(insn, 0));
3132 }
3133
3134 DISAS_INSN(and)
3135 {
3136 TCGv src;
3137 TCGv reg;
3138 TCGv dest;
3139 TCGv addr;
3140 int opsize;
3141
3142 dest = tcg_temp_new();
3143
3144 opsize = insn_opsize(insn);
3145 reg = DREG(insn, 9);
3146 if (insn & 0x100) {
3147 SRC_EA(env, src, opsize, 0, &addr);
3148 tcg_gen_and_i32(dest, src, reg);
3149 DEST_EA(env, insn, opsize, dest, &addr);
3150 } else {
3151 SRC_EA(env, src, opsize, 0, NULL);
3152 tcg_gen_and_i32(dest, src, reg);
3153 gen_partset_reg(opsize, reg, dest);
3154 }
3155 gen_logic_cc(s, dest, opsize);
3156 tcg_temp_free(dest);
3157 }
3158
3159 DISAS_INSN(adda)
3160 {
3161 TCGv src;
3162 TCGv reg;
3163
3164 SRC_EA(env, src, (insn & 0x100) ? OS_LONG : OS_WORD, 1, NULL);
3165 reg = AREG(insn, 9);
3166 tcg_gen_add_i32(reg, reg, src);
3167 }
3168
3169 static inline void gen_addx(DisasContext *s, TCGv src, TCGv dest, int opsize)
3170 {
3171 TCGv tmp;
3172
3173 gen_flush_flags(s); /* compute old Z */
3174
3175 /* Perform addition with carry.
3176 * (X, N) = src + dest + X;
3177 */
3178
3179 tmp = tcg_const_i32(0);
3180 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_X, tmp, dest, tmp);
3181 tcg_gen_add2_i32(QREG_CC_N, QREG_CC_X, QREG_CC_N, QREG_CC_X, src, tmp);
3182 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3183
3184 /* Compute signed-overflow for addition. */
3185
3186 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3187 tcg_gen_xor_i32(tmp, dest, src);
3188 tcg_gen_andc_i32(QREG_CC_V, QREG_CC_V, tmp);
3189 tcg_temp_free(tmp);
3190
3191 /* Copy the rest of the results into place. */
3192 tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N); /* !Z is sticky */
3193 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
3194
3195 set_cc_op(s, CC_OP_FLAGS);
3196
3197 /* result is in QREG_CC_N */
3198 }
3199
3200 DISAS_INSN(addx_reg)
3201 {
3202 TCGv dest;
3203 TCGv src;
3204 int opsize;
3205
3206 opsize = insn_opsize(insn);
3207
3208 dest = gen_extend(DREG(insn, 9), opsize, 1);
3209 src = gen_extend(DREG(insn, 0), opsize, 1);
3210
3211 gen_addx(s, src, dest, opsize);
3212
3213 gen_partset_reg(opsize, DREG(insn, 9), QREG_CC_N);
3214 }
3215
3216 DISAS_INSN(addx_mem)
3217 {
3218 TCGv src;
3219 TCGv addr_src;
3220 TCGv dest;
3221 TCGv addr_dest;
3222 int opsize;
3223
3224 opsize = insn_opsize(insn);
3225
3226 addr_src = AREG(insn, 0);
3227 tcg_gen_subi_i32(addr_src, addr_src, opsize_bytes(opsize));
3228 src = gen_load(s, opsize, addr_src, 1);
3229
3230 addr_dest = AREG(insn, 9);
3231 tcg_gen_subi_i32(addr_dest, addr_dest, opsize_bytes(opsize));
3232 dest = gen_load(s, opsize, addr_dest, 1);
3233
3234 gen_addx(s, src, dest, opsize);
3235
3236 gen_store(s, opsize, addr_dest, QREG_CC_N);
3237 }
3238
3239 static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
3240 {
3241 int count = (insn >> 9) & 7;
3242 int logical = insn & 8;
3243 int left = insn & 0x100;
3244 int bits = opsize_bytes(opsize) * 8;
3245 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3246
3247 if (count == 0) {
3248 count = 8;
3249 }
3250
3251 tcg_gen_movi_i32(QREG_CC_V, 0);
3252 if (left) {
3253 tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
3254 tcg_gen_shli_i32(QREG_CC_N, reg, count);
3255
3256 /* Note that ColdFire always clears V (done above),
3257 while M68000 sets if the most significant bit is changed at
3258 any time during the shift operation */
3259 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3260 /* if shift count >= bits, V is (reg != 0) */
3261 if (count >= bits) {
3262 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
3263 } else {
3264 TCGv t0 = tcg_temp_new();
3265 tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1);
3266 tcg_gen_sari_i32(t0, reg, bits - count - 1);
3267 tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
3268 tcg_temp_free(t0);
3269 }
3270 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3271 }
3272 } else {
3273 tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
3274 if (logical) {
3275 tcg_gen_shri_i32(QREG_CC_N, reg, count);
3276 } else {
3277 tcg_gen_sari_i32(QREG_CC_N, reg, count);
3278 }
3279 }
3280
3281 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3282 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3283 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3284 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3285
3286 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3287 set_cc_op(s, CC_OP_FLAGS);
3288 }
3289
3290 static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
3291 {
3292 int logical = insn & 8;
3293 int left = insn & 0x100;
3294 int bits = opsize_bytes(opsize) * 8;
3295 TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
3296 TCGv s32;
3297 TCGv_i64 t64, s64;
3298
3299 t64 = tcg_temp_new_i64();
3300 s64 = tcg_temp_new_i64();
3301 s32 = tcg_temp_new();
3302
3303 /* Note that m68k truncates the shift count modulo 64, not 32.
3304 In addition, a 64-bit shift makes it easy to find "the last
3305 bit shifted out", for the carry flag. */
3306 tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
3307 tcg_gen_extu_i32_i64(s64, s32);
3308 tcg_gen_extu_i32_i64(t64, reg);
3309
3310 /* Optimistically set V=0. Also used as a zero source below. */
3311 tcg_gen_movi_i32(QREG_CC_V, 0);
3312 if (left) {
3313 tcg_gen_shl_i64(t64, t64, s64);
3314
3315 if (opsize == OS_LONG) {
3316 tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
3317 /* Note that C=0 if shift count is 0, and we get that for free. */
3318 } else {
3319 TCGv zero = tcg_const_i32(0);
3320 tcg_gen_extrl_i64_i32(QREG_CC_N, t64);
3321 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_N, bits);
3322 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3323 s32, zero, zero, QREG_CC_C);
3324 tcg_temp_free(zero);
3325 }
3326 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3327
3328 /* X = C, but only if the shift count was non-zero. */
3329 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3330 QREG_CC_C, QREG_CC_X);
3331
3332 /* M68000 sets V if the most significant bit is changed at
3333 * any time during the shift operation. Do this via creating
3334 * an extension of the sign bit, comparing, and discarding
3335 * the bits below the sign bit. I.e.
3336 * int64_t s = (intN_t)reg;
3337 * int64_t t = (int64_t)(intN_t)reg << count;
3338 * V = ((s ^ t) & (-1 << (bits - 1))) != 0
3339 */
3340 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3341 TCGv_i64 tt = tcg_const_i64(32);
3342 /* if shift is greater than 32, use 32 */
3343 tcg_gen_movcond_i64(TCG_COND_GT, s64, s64, tt, tt, s64);
3344 tcg_temp_free_i64(tt);
3345 /* Sign extend the input to 64 bits; re-do the shift. */
3346 tcg_gen_ext_i32_i64(t64, reg);
3347 tcg_gen_shl_i64(s64, t64, s64);
3348 /* Clear all bits that are unchanged. */
3349 tcg_gen_xor_i64(t64, t64, s64);
3350 /* Ignore the bits below the sign bit. */
3351 tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1));
3352 /* If any bits remain set, we have overflow. */
3353 tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0);
3354 tcg_gen_extrl_i64_i32(QREG_CC_V, t64);
3355 tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
3356 }
3357 } else {
3358 tcg_gen_shli_i64(t64, t64, 32);
3359 if (logical) {
3360 tcg_gen_shr_i64(t64, t64, s64);
3361 } else {
3362 tcg_gen_sar_i64(t64, t64, s64);
3363 }
3364 tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
3365
3366 /* Note that C=0 if shift count is 0, and we get that for free. */
3367 tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
3368
3369 /* X = C, but only if the shift count was non-zero. */
3370 tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
3371 QREG_CC_C, QREG_CC_X);
3372 }
3373 gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
3374 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3375
3376 tcg_temp_free(s32);
3377 tcg_temp_free_i64(s64);
3378 tcg_temp_free_i64(t64);
3379
3380 /* Write back the result. */
3381 gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
3382 set_cc_op(s, CC_OP_FLAGS);
3383 }
3384
3385 DISAS_INSN(shift8_im)
3386 {
3387 shift_im(s, insn, OS_BYTE);
3388 }
3389
3390 DISAS_INSN(shift16_im)
3391 {
3392 shift_im(s, insn, OS_WORD);
3393 }
3394
3395 DISAS_INSN(shift_im)
3396 {
3397 shift_im(s, insn, OS_LONG);
3398 }
3399
3400 DISAS_INSN(shift8_reg)
3401 {
3402 shift_reg(s, insn, OS_BYTE);
3403 }
3404
3405 DISAS_INSN(shift16_reg)
3406 {
3407 shift_reg(s, insn, OS_WORD);
3408 }
3409
3410 DISAS_INSN(shift_reg)
3411 {
3412 shift_reg(s, insn, OS_LONG);
3413 }
3414
3415 DISAS_INSN(shift_mem)
3416 {
3417 int logical = insn & 8;
3418 int left = insn & 0x100;
3419 TCGv src;
3420 TCGv addr;
3421
3422 SRC_EA(env, src, OS_WORD, !logical, &addr);
3423 tcg_gen_movi_i32(QREG_CC_V, 0);
3424 if (left) {
3425 tcg_gen_shri_i32(QREG_CC_C, src, 15);
3426 tcg_gen_shli_i32(QREG_CC_N, src, 1);
3427
3428 /* Note that ColdFire always clears V,
3429 while M68000 sets if the most significant bit is changed at
3430 any time during the shift operation */
3431 if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
3432 src = gen_extend(src, OS_WORD, 1);
3433 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
3434 }
3435 } else {
3436 tcg_gen_mov_i32(QREG_CC_C, src);
3437 if (logical) {
3438 tcg_gen_shri_i32(QREG_CC_N, src, 1);
3439 } else {
3440 tcg_gen_sari_i32(QREG_CC_N, src, 1);
3441 }
3442 }
3443
3444 gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
3445 tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
3446 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
3447 tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
3448
3449 DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
3450 set_cc_op(s, CC_OP_FLAGS);
3451 }
3452
3453 static void rotate(TCGv reg, TCGv shift, int left, int size)
3454 {
3455 switch (size) {
3456 case 8:
3457 /* Replicate the 8-bit input so that a 32-bit rotate works. */
3458 tcg_gen_ext8u_i32(reg, reg);
3459 tcg_gen_muli_i32(reg, reg, 0x01010101);
3460 goto do_long;
3461 case 16:
3462 /* Replicate the 16-bit input so that a 32-bit rotate works. */
3463 tcg_gen_deposit_i32(reg, reg, reg, 16, 16);
3464 goto do_long;
3465 do_long:
3466 default:
3467 if (left) {
3468 tcg_gen_rotl_i32(reg, reg, shift);
3469 } else {
3470 tcg_gen_rotr_i32(reg, reg, shift);
3471 }
3472 }
3473
3474 /* compute flags */
3475
3476 switch (size) {
3477 case 8:
3478 tcg_gen_ext8s_i32(reg, reg);
3479 break;
3480 case 16:
3481 tcg_gen_ext16s_i32(reg, reg);
3482 break;
3483 default:
3484 break;
3485 }
3486
3487 /* QREG_CC_X is not affected */
3488
3489 tcg_gen_mov_i32(QREG_CC_N, reg);
3490 tcg_gen_mov_i32(QREG_CC_Z, reg);
3491
3492 if (left) {
3493 tcg_gen_andi_i32(QREG_CC_C, reg, 1);
3494 } else {
3495 tcg_gen_shri_i32(QREG_CC_C, reg, 31);
3496 }
3497
3498 tcg_gen_movi_i32(QREG_CC_V, 0); /* always cleared */
3499 }
3500
3501 static void rotate_x_flags(TCGv reg, TCGv X, int size)
3502 {
3503 switch (size) {
3504 case 8:
3505 tcg_gen_ext8s_i32(reg, reg);
3506 break;
3507 case 16:
3508 tcg_gen_ext16s_i32(reg, reg);
3509 break;
3510 default:
3511 break;
3512 }
3513 tcg_gen_mov_i32(QREG_CC_N, reg);
3514 tcg_gen_mov_i32(QREG_CC_Z, reg);
3515 tcg_gen_mov_i32(QREG_CC_X, X);
3516 tcg_gen_mov_i32(QREG_CC_C, X);
3517 tcg_gen_movi_i32(QREG_CC_V, 0);
3518 }
3519
3520 /* Result of rotate_x() is valid if 0 <= shift <= size */
3521 static TCGv rotate_x(TCGv reg, TCGv shift, int left, int size)
3522 {
3523 TCGv X, shl, shr, shx, sz, zero;
3524
3525 sz = tcg_const_i32(size);
3526
3527 shr = tcg_temp_new();
3528 shl = tcg_temp_new();
3529 shx = tcg_temp_new();
3530 if (left) {
3531 tcg_gen_mov_i32(shl, shift); /* shl = shift */
3532 tcg_gen_movi_i32(shr, size + 1);
3533 tcg_gen_sub_i32(shr, shr, shift); /* shr = size + 1 - shift */
3534 tcg_gen_subi_i32(shx, shift, 1); /* shx = shift - 1 */
3535 /* shx = shx < 0 ? size : shx; */
3536 zero = tcg_const_i32(0);
3537 tcg_gen_movcond_i32(TCG_COND_LT, shx, shx, zero, sz, shx);
3538 tcg_temp_free(zero);
3539 } else {
3540 tcg_gen_mov_i32(shr, shift); /* shr = shift */
3541 tcg_gen_movi_i32(shl, size + 1);
3542 tcg_gen_sub_i32(shl, shl, shift); /* shl = size + 1 - shift */
3543 tcg_gen_sub_i32(shx, sz, shift); /* shx = size - shift */
3544 }
3545
3546 /* reg = (reg << shl) | (reg >> shr) | (x << shx); */
3547
3548 tcg_gen_shl_i32(shl, reg, shl);
3549 tcg_gen_shr_i32(shr, reg, shr);
3550 tcg_gen_or_i32(reg, shl, shr);
3551 tcg_temp_free(shl);
3552 tcg_temp_free(shr);
3553 tcg_gen_shl_i32(shx, QREG_CC_X, shx);
3554 tcg_gen_or_i32(reg, reg, shx);
3555 tcg_temp_free(shx);
3556
3557 /* X = (reg >> size) & 1 */
3558
3559 X = tcg_temp_new();
3560 tcg_gen_shr_i32(X, reg, sz);
3561 tcg_gen_andi_i32(X, X, 1);
3562 tcg_temp_free(sz);
3563
3564 return X;
3565 }
3566
3567 /* Result of rotate32_x() is valid if 0 <= shift < 33 */
3568 static TCGv rotate32_x(TCGv reg, TCGv shift, int left)
3569 {
3570 TCGv_i64 t0, shift64;
3571 TCGv X, lo, hi, zero;
3572
3573 shift64 = tcg_temp_new_i64();
3574 tcg_gen_extu_i32_i64(shift64, shift);
3575
3576 t0 = tcg_temp_new_i64();
3577
3578 X = tcg_temp_new();
3579 lo = tcg_temp_new();
3580 hi = tcg_temp_new();
3581
3582 if (left) {
3583 /* create [reg:X:..] */
3584
3585 tcg_gen_shli_i32(lo, QREG_CC_X, 31);
3586 tcg_gen_concat_i32_i64(t0, lo, reg);
3587
3588 /* rotate */
3589
3590 tcg_gen_rotl_i64(t0, t0, shift64);
3591 tcg_temp_free_i64(shift64);
3592
3593 /* result is [reg:..:reg:X] */
3594
3595 tcg_gen_extr_i64_i32(lo, hi, t0);
3596 tcg_gen_andi_i32(X, lo, 1);
3597
3598 tcg_gen_shri_i32(lo, lo, 1);
3599 } else {
3600 /* create [..:X:reg] */
3601
3602 tcg_gen_concat_i32_i64(t0, reg, QREG_CC_X);
3603
3604 tcg_gen_rotr_i64(t0, t0, shift64);
3605 tcg_temp_free_i64(shift64);
3606
3607 /* result is value: [X:reg:..:reg] */
3608
3609 tcg_gen_extr_i64_i32(lo, hi, t0);
3610
3611 /* extract X */
3612
3613 tcg_gen_shri_i32(X, hi, 31);
3614
3615 /* extract result */
3616
3617 tcg_gen_shli_i32(hi, hi, 1);
3618 }
3619 tcg_temp_free_i64(t0);
3620 tcg_gen_or_i32(lo, lo, hi);
3621 tcg_temp_free(hi);
3622
3623 /* if shift == 0, register and X are not affected */
3624
3625 zero = tcg_const_i32(0);
3626 tcg_gen_movcond_i32(TCG_COND_EQ, X, shift, zero, QREG_CC_X, X);
3627 tcg_gen_movcond_i32(TCG_COND_EQ, reg, shift, zero, reg, lo);
3628 tcg_temp_free(zero);
3629 tcg_temp_free(lo);
3630
3631 return X;
3632 }
3633
3634 DISAS_INSN(rotate_im)
3635 {
3636 TCGv shift;
3637 int tmp;
3638 int left = (insn & 0x100);
3639
3640 tmp = (insn >> 9) & 7;
3641 if (tmp == 0) {
3642 tmp = 8;
3643 }
3644
3645 shift = tcg_const_i32(tmp);
3646 if (insn & 8) {
3647 rotate(DREG(insn, 0), shift, left, 32);
3648 } else {
3649 TCGv X = rotate32_x(DREG(insn, 0), shift, left);
3650 rotate_x_flags(DREG(insn, 0), X, 32);
3651 tcg_temp_free(X);
3652 }
3653 tcg_temp_free(shift);
3654
3655 set_cc_op(s, CC_OP_FLAGS);
3656 }
3657
3658 DISAS_INSN(rotate8_im)
3659 {
3660 int left = (insn & 0x100);
3661 TCGv reg;
3662 TCGv shift;
3663 int tmp;
3664
3665 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3666
3667 tmp = (insn >> 9) & 7;
3668 if (tmp == 0) {
3669 tmp = 8;
3670 }
3671
3672 shift = tcg_const_i32(tmp);
3673 if (insn & 8) {
3674 rotate(reg, shift, left, 8);
3675 } else {
3676 TCGv X = rotate_x(reg, shift, left, 8);
3677 rotate_x_flags(reg, X, 8);
3678 tcg_temp_free(X);
3679 }
3680 tcg_temp_free(shift);
3681 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3682 set_cc_op(s, CC_OP_FLAGS);
3683 }
3684
3685 DISAS_INSN(rotate16_im)
3686 {
3687 int left = (insn & 0x100);
3688 TCGv reg;
3689 TCGv shift;
3690 int tmp;
3691
3692 reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3693 tmp = (insn >> 9) & 7;
3694 if (tmp == 0) {
3695 tmp = 8;
3696 }
3697
3698 shift = tcg_const_i32(tmp);
3699 if (insn & 8) {
3700 rotate(reg, shift, left, 16);
3701 } else {
3702 TCGv X = rotate_x(reg, shift, left, 16);
3703 rotate_x_flags(reg, X, 16);
3704 tcg_temp_free(X);
3705 }
3706 tcg_temp_free(shift);
3707 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3708 set_cc_op(s, CC_OP_FLAGS);
3709 }
3710
3711 DISAS_INSN(rotate_reg)
3712 {
3713 TCGv reg;
3714 TCGv src;
3715 TCGv t0, t1;
3716 int left = (insn & 0x100);
3717
3718 reg = DREG(insn, 0);
3719 src = DREG(insn, 9);
3720 /* shift in [0..63] */
3721 t0 = tcg_temp_new();
3722 tcg_gen_andi_i32(t0, src, 63);
3723 t1 = tcg_temp_new_i32();
3724 if (insn & 8) {
3725 tcg_gen_andi_i32(t1, src, 31);
3726 rotate(reg, t1, left, 32);
3727 /* if shift == 0, clear C */
3728 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3729 t0, QREG_CC_V /* 0 */,
3730 QREG_CC_V /* 0 */, QREG_CC_C);
3731 } else {
3732 TCGv X;
3733 /* modulo 33 */
3734 tcg_gen_movi_i32(t1, 33);
3735 tcg_gen_remu_i32(t1, t0, t1);
3736 X = rotate32_x(DREG(insn, 0), t1, left);
3737 rotate_x_flags(DREG(insn, 0), X, 32);
3738 tcg_temp_free(X);
3739 }
3740 tcg_temp_free(t1);
3741 tcg_temp_free(t0);
3742 set_cc_op(s, CC_OP_FLAGS);
3743 }
3744
3745 DISAS_INSN(rotate8_reg)
3746 {
3747 TCGv reg;
3748 TCGv src;
3749 TCGv t0, t1;
3750 int left = (insn & 0x100);
3751
3752 reg = gen_extend(DREG(insn, 0), OS_BYTE, 0);
3753 src = DREG(insn, 9);
3754 /* shift in [0..63] */
3755 t0 = tcg_temp_new_i32();
3756 tcg_gen_andi_i32(t0, src, 63);
3757 t1 = tcg_temp_new_i32();
3758 if (insn & 8) {
3759 tcg_gen_andi_i32(t1, src, 7);
3760 rotate(reg, t1, left, 8);
3761 /* if shift == 0, clear C */
3762 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3763 t0, QREG_CC_V /* 0 */,
3764 QREG_CC_V /* 0 */, QREG_CC_C);
3765 } else {
3766 TCGv X;
3767 /* modulo 9 */
3768 tcg_gen_movi_i32(t1, 9);
3769 tcg_gen_remu_i32(t1, t0, t1);
3770 X = rotate_x(reg, t1, left, 8);
3771 rotate_x_flags(reg, X, 8);
3772 tcg_temp_free(X);
3773 }
3774 tcg_temp_free(t1);
3775 tcg_temp_free(t0);
3776 gen_partset_reg(OS_BYTE, DREG(insn, 0), reg);
3777 set_cc_op(s, CC_OP_FLAGS);
3778 }
3779
3780 DISAS_INSN(rotate16_reg)
3781 {
3782 TCGv reg;
3783 TCGv src;
3784 TCGv t0, t1;
3785 int left = (insn & 0x100);
3786
3787 reg = gen_extend(DREG(insn, 0), OS_WORD, 0);
3788 src = DREG(insn, 9);
3789 /* shift in [0..63] */
3790 t0 = tcg_temp_new_i32();
3791 tcg_gen_andi_i32(t0, src, 63);
3792 t1 = tcg_temp_new_i32();
3793 if (insn & 8) {
3794 tcg_gen_andi_i32(t1, src, 15);
3795 rotate(reg, t1, left, 16);
3796 /* if shift == 0, clear C */
3797 tcg_gen_movcond_i32(TCG_COND_EQ, QREG_CC_C,
3798 t0, QREG_CC_V /* 0 */,
3799 QREG_CC_V /* 0 */, QREG_CC_C);
3800 } else {
3801 TCGv X;
3802 /* modulo 17 */
3803 tcg_gen_movi_i32(t1, 17);
3804 tcg_gen_remu_i32(t1, t0, t1);
3805 X = rotate_x(reg, t1, left, 16);
3806 rotate_x_flags(reg, X, 16);
3807 tcg_temp_free(X);
3808 }
3809 tcg_temp_free(t1);
3810 tcg_temp_free(t0);
3811 gen_partset_reg(OS_WORD, DREG(insn, 0), reg);
3812 set_cc_op(s, CC_OP_FLAGS);
3813 }
3814
3815 DISAS_INSN(rotate_mem)
3816 {
3817 TCGv src;
3818 TCGv addr;
3819 TCGv shift;
3820 int left = (insn & 0x100);
3821
3822 SRC_EA(env, src, OS_WORD, 0, &addr);
3823
3824 shift = tcg_const_i32(1);
3825 if (insn & 0x0200) {
3826 rotate(src, shift, left, 16);
3827 } else {
3828 TCGv X = rotate_x(src, shift, left, 16);
3829 rotate_x_flags(src, X, 16);
3830 tcg_temp_free(X);
3831 }
3832 tcg_temp_free(shift);
3833 DEST_EA(env, insn, OS_WORD, src, &addr);
3834 set_cc_op(s, CC_OP_FLAGS);
3835 }
3836
3837 DISAS_INSN(bfext_reg)
3838 {
3839 int ext = read_im16(env, s);
3840 int is_sign = insn & 0x200;
3841 TCGv src = DREG(insn, 0);
3842 TCGv dst = DREG(ext, 12);
3843 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
3844 int ofs = extract32(ext, 6, 5); /* big bit-endian */
3845 int pos = 32 - ofs - len; /* little bit-endian */
3846 TCGv tmp = tcg_temp_new();
3847 TCGv shift;
3848
3849 /* In general, we're going to rotate the field so that it's at the
3850 top of the word and then right-shift by the compliment of the
3851 width to extend the field. */
3852 if (ext & 0x20) {
3853 /* Variable width. */
3854 if (ext & 0x800) {
3855 /* Variable offset. */
3856 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3857 tcg_gen_rotl_i32(tmp, src, tmp);
3858 } else {
3859 tcg_gen_rotli_i32(tmp, src, ofs);
3860 }
3861
3862 shift = tcg_temp_new();
3863 tcg_gen_neg_i32(shift, DREG(ext, 0));
3864 tcg_gen_andi_i32(shift, shift, 31);
3865 tcg_gen_sar_i32(QREG_CC_N, tmp, shift);
3866 if (is_sign) {
3867 tcg_gen_mov_i32(dst, QREG_CC_N);
3868 } else {
3869 tcg_gen_shr_i32(dst, tmp, shift);
3870 }
3871 tcg_temp_free(shift);
3872 } else {
3873 /* Immediate width. */
3874 if (ext & 0x800) {
3875 /* Variable offset */
3876 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3877 tcg_gen_rotl_i32(tmp, src, tmp);
3878 src = tmp;
3879 pos = 32 - len;
3880 } else {
3881 /* Immediate offset. If the field doesn't wrap around the
3882 end of the word, rely on (s)extract completely. */
3883 if (pos < 0) {
3884 tcg_gen_rotli_i32(tmp, src, ofs);
3885 src = tmp;
3886 pos = 32 - len;
3887 }
3888 }
3889
3890 tcg_gen_sextract_i32(QREG_CC_N, src, pos, len);
3891 if (is_sign) {
3892 tcg_gen_mov_i32(dst, QREG_CC_N);
3893 } else {
3894 tcg_gen_extract_i32(dst, src, pos, len);
3895 }
3896 }
3897
3898 tcg_temp_free(tmp);
3899 set_cc_op(s, CC_OP_LOGIC);
3900 }
3901
3902 DISAS_INSN(bfext_mem)
3903 {
3904 int ext = read_im16(env, s);
3905 int is_sign = insn & 0x200;
3906 TCGv dest = DREG(ext, 12);
3907 TCGv addr, len, ofs;
3908
3909 addr = gen_lea(env, s, insn, OS_UNSIZED);
3910 if (IS_NULL_QREG(addr)) {
3911 gen_addr_fault(s);
3912 return;
3913 }
3914
3915 if (ext & 0x20) {
3916 len = DREG(ext, 0);
3917 } else {
3918 len = tcg_const_i32(extract32(ext, 0, 5));
3919 }
3920 if (ext & 0x800) {
3921 ofs = DREG(ext, 6);
3922 } else {
3923 ofs = tcg_const_i32(extract32(ext, 6, 5));
3924 }
3925
3926 if (is_sign) {
3927 gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len);
3928 tcg_gen_mov_i32(QREG_CC_N, dest);
3929 } else {
3930 TCGv_i64 tmp = tcg_temp_new_i64();
3931 gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len);
3932 tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp);
3933 tcg_temp_free_i64(tmp);
3934 }
3935 set_cc_op(s, CC_OP_LOGIC);
3936
3937 if (!(ext & 0x20)) {
3938 tcg_temp_free(len);
3939 }
3940 if (!(ext & 0x800)) {
3941 tcg_temp_free(ofs);
3942 }
3943 }
3944
3945 DISAS_INSN(bfop_reg)
3946 {
3947 int ext = read_im16(env, s);
3948 TCGv src = DREG(insn, 0);
3949 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
3950 int ofs = extract32(ext, 6, 5); /* big bit-endian */
3951 TCGv mask, tofs, tlen;
3952
3953 TCGV_UNUSED(tofs);
3954 TCGV_UNUSED(tlen);
3955 if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
3956 tofs = tcg_temp_new();
3957 tlen = tcg_temp_new();
3958 }
3959
3960 if ((ext & 0x820) == 0) {
3961 /* Immediate width and offset. */
3962 uint32_t maski = 0x7fffffffu >> (len - 1);
3963 if (ofs + len <= 32) {
3964 tcg_gen_shli_i32(QREG_CC_N, src, ofs);
3965 } else {
3966 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
3967 }
3968 tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
3969 mask = tcg_const_i32(ror32(maski, ofs));
3970 if (!TCGV_IS_UNUSED(tofs)) {
3971 tcg_gen_movi_i32(tofs, ofs);
3972 tcg_gen_movi_i32(tlen, len);
3973 }
3974 } else {
3975 TCGv tmp = tcg_temp_new();
3976 if (ext & 0x20) {
3977 /* Variable width */
3978 tcg_gen_subi_i32(tmp, DREG(ext, 0), 1);
3979 tcg_gen_andi_i32(tmp, tmp, 31);
3980 mask = tcg_const_i32(0x7fffffffu);
3981 tcg_gen_shr_i32(mask, mask, tmp);
3982 if (!TCGV_IS_UNUSED(tlen)) {
3983 tcg_gen_addi_i32(tlen, tmp, 1);
3984 }
3985 } else {
3986 /* Immediate width */
3987 mask = tcg_const_i32(0x7fffffffu >> (len - 1));
3988 if (!TCGV_IS_UNUSED(tlen)) {
3989 tcg_gen_movi_i32(tlen, len);
3990 }
3991 }
3992 if (ext & 0x800) {
3993 /* Variable offset */
3994 tcg_gen_andi_i32(tmp, DREG(ext, 6), 31);
3995 tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
3996 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
3997 tcg_gen_rotr_i32(mask, mask, tmp);
3998 if (!TCGV_IS_UNUSED(tofs)) {
3999 tcg_gen_mov_i32(tofs, tmp);
4000 }
4001 } else {
4002 /* Immediate offset (and variable width) */
4003 tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
4004 tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
4005 tcg_gen_rotri_i32(mask, mask, ofs);
4006 if (!TCGV_IS_UNUSED(tofs)) {
4007 tcg_gen_movi_i32(tofs, ofs);
4008 }
4009 }
4010 tcg_temp_free(tmp);
4011 }
4012 set_cc_op(s, CC_OP_LOGIC);
4013
4014 switch (insn & 0x0f00) {
4015 case 0x0a00: /* bfchg */
4016 tcg_gen_eqv_i32(src, src, mask);
4017 break;
4018 case 0x0c00: /* bfclr */
4019 tcg_gen_and_i32(src, src, mask);
4020 break;
4021 case 0x0d00: /* bfffo */
4022 gen_helper_bfffo_reg(DREG(ext, 12), QREG_CC_N, tofs, tlen);
4023 tcg_temp_free(tlen);
4024 tcg_temp_free(tofs);
4025 break;
4026 case 0x0e00: /* bfset */
4027 tcg_gen_orc_i32(src, src, mask);
4028 break;
4029 case 0x0800: /* bftst */
4030 /* flags already set; no other work to do. */
4031 break;
4032 default:
4033 g_assert_not_reached();
4034 }
4035 tcg_temp_free(mask);
4036 }
4037
4038 DISAS_INSN(bfop_mem)
4039 {
4040 int ext = read_im16(env, s);
4041 TCGv addr, len, ofs;
4042 TCGv_i64 t64;
4043
4044 addr = gen_lea(env, s, insn, OS_UNSIZED);
4045 if (IS_NULL_QREG(addr)) {
4046 gen_addr_fault(s);
4047 return;
4048 }
4049
4050 if (ext & 0x20) {
4051 len = DREG(ext, 0);
4052 } else {
4053 len = tcg_const_i32(extract32(ext, 0, 5));
4054 }
4055 if (ext & 0x800) {
4056 ofs = DREG(ext, 6);
4057 } else {
4058 ofs = tcg_const_i32(extract32(ext, 6, 5));
4059 }
4060
4061 switch (insn & 0x0f00) {
4062 case 0x0a00: /* bfchg */
4063 gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4064 break;
4065 case 0x0c00: /* bfclr */
4066 gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4067 break;
4068 case 0x0d00: /* bfffo */
4069 t64 = tcg_temp_new_i64();
4070 gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len);
4071 tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64);
4072 tcg_temp_free_i64(t64);
4073 break;
4074 case 0x0e00: /* bfset */
4075 gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4076 break;
4077 case 0x0800: /* bftst */
4078 gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len);
4079 break;
4080 default:
4081 g_assert_not_reached();
4082 }
4083 set_cc_op(s, CC_OP_LOGIC);
4084
4085 if (!(ext & 0x20)) {
4086 tcg_temp_free(len);
4087 }
4088 if (!(ext & 0x800)) {
4089 tcg_temp_free(ofs);
4090 }
4091 }
4092
4093 DISAS_INSN(bfins_reg)
4094 {
4095 int ext = read_im16(env, s);
4096 TCGv dst = DREG(insn, 0);
4097 TCGv src = DREG(ext, 12);
4098 int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
4099 int ofs = extract32(ext, 6, 5); /* big bit-endian */
4100 int pos = 32 - ofs - len; /* little bit-endian */
4101 TCGv tmp;
4102
4103 tmp = tcg_temp_new();
4104
4105 if (ext & 0x20) {
4106 /* Variable width */
4107 tcg_gen_neg_i32(tmp, DREG(ext, 0));
4108 tcg_gen_andi_i32(tmp, tmp, 31);
4109 tcg_gen_shl_i32(QREG_CC_N, src, tmp);
4110 } else {
4111 /* Immediate width */
4112 tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
4113 }
4114 set_cc_op(s, CC_OP_LOGIC);
4115
4116 /* Immediate width and offset */
4117 if ((ext & 0x820) == 0) {
4118 /* Check for suitability for deposit. */
4119 if (pos >= 0) {
4120 tcg_gen_deposit_i32(dst, dst, src, pos, len);
4121 } else {
4122 uint32_t maski = -2U << (len - 1);
4123 uint32_t roti = (ofs + len) & 31;
4124 tcg_gen_andi_i32(tmp, src, ~maski);
4125 tcg_gen_rotri_i32(tmp, tmp, roti);
4126 tcg_gen_andi_i32(dst, dst, ror32(maski, roti));
4127 tcg_gen_or_i32(dst, dst, tmp);
4128 }
4129 } else {
4130 TCGv mask = tcg_temp_new();
4131 TCGv rot = tcg_temp_new();
4132
4133 if (ext & 0x20) {
4134 /* Variable width */
4135 tcg_gen_subi_i32(rot, DREG(ext, 0), 1);
4136 tcg_gen_andi_i32(rot, rot, 31);
4137 tcg_gen_movi_i32(mask, -2);
4138 tcg_gen_shl_i32(mask, mask, rot);
4139 tcg_gen_mov_i32(rot, DREG(ext, 0));
4140 tcg_gen_andc_i32(tmp, src, mask);
4141 } else {
4142 /* Immediate width (variable offset) */
4143 uint32_t maski = -2U << (len - 1);
4144 tcg_gen_andi_i32(tmp, src, ~maski);
4145 tcg_gen_movi_i32(mask, maski);
4146 tcg_gen_movi_i32(rot, len & 31);
4147 }
4148 if (ext & 0x800) {
4149 /* Variable offset */
4150 tcg_gen_add_i32(rot, rot, DREG(ext, 6));
4151 } else {
4152 /* Immediate offset (variable width) */
4153 tcg_gen_addi_i32(rot, rot, ofs);
4154 }
4155 tcg_gen_andi_i32(rot, rot, 31);
4156 tcg_gen_rotr_i32(mask, mask, rot);
4157 tcg_gen_rotr_i32(tmp, tmp, rot);
4158 tcg_gen_and_i32(dst, dst, mask);
4159 tcg_gen_or_i32(dst, dst, tmp);
4160
4161 tcg_temp_free(rot);
4162 tcg_temp_free(mask);
4163 }
4164 tcg_temp_free(tmp);
4165 }
4166
4167 DISAS_INSN(bfins_mem)
4168 {
4169 int ext = read_im16(env, s);
4170 TCGv src = DREG(ext, 12);
4171 TCGv addr, len, ofs;
4172
4173 addr = gen_lea(env, s, insn, OS_UNSIZED);
4174 if (IS_NULL_QREG(addr)) {
4175 gen_addr_fault(s);
4176 return;
4177 }
4178
4179 if (ext & 0x20) {
4180 len = DREG(ext, 0);
4181 } else {
4182 len = tcg_const_i32(extract32(ext, 0, 5));
4183 }
4184 if (ext & 0x800) {
4185 ofs = DREG(ext, 6);
4186 } else {
4187 ofs = tcg_const_i32(extract32(ext, 6, 5));
4188 }
4189
4190 gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len);
4191 set_cc_op(s, CC_OP_LOGIC);
4192
4193 if (!(ext & 0x20)) {
4194 tcg_temp_free(len);
4195 }
4196 if (!(ext & 0x800)) {
4197 tcg_temp_free(ofs);
4198 }
4199 }
4200
4201 DISAS_INSN(ff1)
4202 {
4203 TCGv reg;
4204 reg = DREG(insn, 0);
4205 gen_logic_cc(s, reg, OS_LONG);
4206 gen_helper_ff1(reg, reg);
4207 }
4208
4209 static TCGv gen_get_sr(DisasContext *s)
4210 {
4211 TCGv ccr;
4212 TCGv sr;
4213
4214 ccr = gen_get_ccr(s);
4215 sr = tcg_temp_new();
4216 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
4217 tcg_gen_or_i32(sr, sr, ccr);
4218 return sr;
4219 }
4220
4221 DISAS_INSN(strldsr)
4222 {
4223 uint16_t ext;
4224 uint32_t addr;
4225
4226 addr = s->pc - 2;
4227 ext = read_im16(env, s);
4228 if (ext != 0x46FC) {
4229 gen_exception(s, addr, EXCP_UNSUPPORTED);
4230 return;
4231 }
4232 ext = read_im16(env, s);
4233 if (IS_USER(s) || (ext & SR_S) == 0) {
4234 gen_exception(s, addr, EXCP_PRIVILEGE);
4235 return;
4236 }
4237 gen_push(s, gen_get_sr(s));
4238 gen_set_sr_im(s, ext, 0);
4239 }
4240
4241 DISAS_INSN(move_from_sr)
4242 {
4243 TCGv sr;
4244
4245 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
4246 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4247 return;
4248 }
4249 sr = gen_get_sr(s);
4250 DEST_EA(env, insn, OS_WORD, sr, NULL);
4251 }
4252
4253 DISAS_INSN(move_to_sr)
4254 {
4255 if (IS_USER(s)) {
4256 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4257 return;
4258 }
4259 gen_set_sr(env, s, insn, 0);
4260 gen_lookup_tb(s);
4261 }
4262
4263 DISAS_INSN(move_from_usp)
4264 {
4265 if (IS_USER(s)) {
4266 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4267 return;
4268 }
4269 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
4270 offsetof(CPUM68KState, sp[M68K_USP]));
4271 }
4272
4273 DISAS_INSN(move_to_usp)
4274 {
4275 if (IS_USER(s)) {
4276 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4277 return;
4278 }
4279 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
4280 offsetof(CPUM68KState, sp[M68K_USP]));
4281 }
4282
4283 DISAS_INSN(halt)
4284 {
4285 gen_exception(s, s->pc, EXCP_HALT_INSN);
4286 }
4287
4288 DISAS_INSN(stop)
4289 {
4290 uint16_t ext;
4291
4292 if (IS_USER(s)) {
4293 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4294 return;
4295 }
4296
4297 ext = read_im16(env, s);
4298
4299 gen_set_sr_im(s, ext, 0);
4300 tcg_gen_movi_i32(cpu_halted, 1);
4301 gen_exception(s, s->pc, EXCP_HLT);
4302 }
4303
4304 DISAS_INSN(rte)
4305 {
4306 if (IS_USER(s)) {
4307 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4308 return;
4309 }
4310 gen_exception(s, s->pc - 2, EXCP_RTE);
4311 }
4312
4313 DISAS_INSN(movec)
4314 {
4315 uint16_t ext;
4316 TCGv reg;
4317
4318 if (IS_USER(s)) {
4319 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4320 return;
4321 }
4322
4323 ext = read_im16(env, s);
4324
4325 if (ext & 0x8000) {
4326 reg = AREG(ext, 12);
4327 } else {
4328 reg = DREG(ext, 12);
4329 }
4330 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
4331 gen_lookup_tb(s);
4332 }
4333
4334 DISAS_INSN(intouch)
4335 {
4336 if (IS_USER(s)) {
4337 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4338 return;
4339 }
4340 /* ICache fetch. Implement as no-op. */
4341 }
4342
4343 DISAS_INSN(cpushl)
4344 {
4345 if (IS_USER(s)) {
4346 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4347 return;
4348 }
4349 /* Cache push/invalidate. Implement as no-op. */
4350 }
4351
4352 DISAS_INSN(wddata)
4353 {
4354 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4355 }
4356
4357 DISAS_INSN(wdebug)
4358 {
4359 M68kCPU *cpu = m68k_env_get_cpu(env);
4360
4361 if (IS_USER(s)) {
4362 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
4363 return;
4364 }
4365 /* TODO: Implement wdebug. */
4366 cpu_abort(CPU(cpu), "WDEBUG not implemented");
4367 }
4368
4369 DISAS_INSN(trap)
4370 {
4371 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
4372 }
4373
4374 static void gen_load_fcr(DisasContext *s, TCGv res, int reg)
4375 {
4376 switch (reg) {
4377 case M68K_FPIAR:
4378 tcg_gen_movi_i32(res, 0);
4379 break;
4380 case M68K_FPSR:
4381 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr));
4382 break;
4383 case M68K_FPCR:
4384 tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr));
4385 break;
4386 }
4387 }
4388
4389 static void gen_store_fcr(DisasContext *s, TCGv val, int reg)
4390 {
4391 switch (reg) {
4392 case M68K_FPIAR:
4393 break;
4394 case M68K_FPSR:
4395 tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr));
4396 break;
4397 case M68K_FPCR:
4398 gen_helper_set_fpcr(cpu_env, val);
4399 break;
4400 }
4401 }
4402
4403 static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
4404 {
4405 int index = IS_USER(s);
4406 TCGv tmp;
4407
4408 tmp = tcg_temp_new();
4409 gen_load_fcr(s, tmp, reg);
4410 tcg_gen_qemu_st32(tmp, addr, index);
4411 tcg_temp_free(tmp);
4412 }
4413
4414 static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
4415 {
4416 int index = IS_USER(s);
4417 TCGv tmp;
4418
4419 tmp = tcg_temp_new();
4420 tcg_gen_qemu_ld32u(tmp, addr, index);
4421 gen_store_fcr(s, tmp, reg);
4422 tcg_temp_free(tmp);
4423 }
4424
4425
4426 static void gen_op_fmove_fcr(CPUM68KState *env, DisasContext *s,
4427 uint32_t insn, uint32_t ext)
4428 {
4429 int mask = (ext >> 10) & 7;
4430 int is_write = (ext >> 13) & 1;
4431 int mode = extract32(insn, 3, 3);
4432 int i;
4433 TCGv addr, tmp;
4434
4435 switch (mode) {
4436 case 0: /* Dn */
4437 if (mask != M68K_FPIAR && mask != M68K_FPSR && mask != M68K_FPCR) {
4438 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4439 return;
4440 }
4441 if (is_write) {
4442 gen_load_fcr(s, DREG(insn, 0), mask);
4443 } else {
4444 gen_store_fcr(s, DREG(insn, 0), mask);
4445 }
4446 return;
4447 case 1: /* An, only with FPIAR */
4448 if (mask != M68K_FPIAR) {
4449 gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
4450 return;
4451 }
4452 if (is_write) {
4453 gen_load_fcr(s, AREG(insn, 0), mask);
4454 } else {
4455 gen_store_fcr(s, AREG(insn, 0), mask);
4456 }
4457 return;
4458 default:
4459 break;
4460 }
4461
4462 tmp = gen_lea(env, s, insn, OS_LONG);
4463 if (IS_NULL_QREG(tmp)) {
4464 gen_addr_fault(s);
4465 return;
4466 }
4467
4468 addr = tcg_temp_new();
4469 tcg_gen_mov_i32(addr, tmp);
4470
4471 /* mask:
4472 *
4473 * 0b100 Floating-Point Control Register
4474 * 0b010 Floating-Point Status Register
4475 * 0b001 Floating-Point Instruction Address Register
4476 *
4477 */
4478
4479 if (is_write && mode == 4) {
4480 for (i = 2; i >= 0; i--, mask >>= 1) {
4481 if (mask & 1) {
4482 gen_qemu_store_fcr(s, addr, 1 << i);
4483 if (mask != 1) {
4484 tcg_gen_subi_i32(addr, addr, opsize_bytes(OS_LONG));
4485 }
4486 }
4487 }
4488 tcg_gen_mov_i32(AREG(insn, 0), addr);
4489 } else {
4490 for (i = 0; i < 3; i++, mask >>= 1) {
4491 if (mask & 1) {
4492 if (is_write) {
4493 gen_qemu_store_fcr(s, addr, 1 << i);
4494 } else {
4495 gen_qemu_load_fcr(s, addr, 1 << i);
4496 }
4497 if (mask != 1 || mode == 3) {
4498 tcg_gen_addi_i32(addr, addr, opsize_bytes(OS_LONG));
4499 }
4500 }
4501 }
4502 if (mode == 3) {
4503 tcg_gen_mov_i32(AREG(insn, 0), addr);
4504 }
4505 }
4506 tcg_temp_free_i32(addr);
4507 }
4508
4509 static void gen_op_fmovem(CPUM68KState *env, DisasContext *s,
4510 uint32_t insn, uint32_t ext)
4511 {
4512 int opsize;
4513 TCGv addr, tmp;
4514 int mode = (ext >> 11) & 0x3;
4515 int is_load = ((ext & 0x2000) == 0);
4516
4517 if (m68k_feature(s->env, M68K_FEATURE_FPU)) {
4518 opsize = OS_EXTENDED;
4519 } else {
4520 opsize = OS_DOUBLE; /* FIXME */
4521 }
4522
4523 addr = gen_lea(env, s, insn, opsize);
4524 if (IS_NULL_QREG(addr)) {
4525 gen_addr_fault(s);
4526 return;
4527 }
4528
4529 tmp = tcg_temp_new();
4530 if (mode & 0x1) {
4531 /* Dynamic register list */
4532 tcg_gen_ext8u_i32(tmp, DREG(ext, 4));
4533 } else {
4534 /* Static register list */
4535 tcg_gen_movi_i32(tmp, ext & 0xff);
4536 }
4537
4538 if (!is_load && (mode & 2) == 0) {
4539 /* predecrement addressing mode
4540 * only available to store register to memory
4541 */
4542 if (opsize == OS_EXTENDED) {
4543 gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp);
4544 } else {
4545 gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp);
4546 }
4547 } else {
4548 /* postincrement addressing mode */
4549 if (opsize == OS_EXTENDED) {
4550 if (is_load) {
4551 gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp);
4552 } else {
4553 gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp);
4554 }
4555 } else {
4556 if (is_load) {
4557 gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp);
4558 } else {
4559 gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp);
4560 }
4561 }
4562 }
4563 if ((insn & 070) == 030 || (insn & 070) == 040) {
4564 tcg_gen_mov_i32(AREG(insn, 0), tmp);
4565 }
4566 tcg_temp_free(tmp);
4567 }
4568
4569 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
4570 immediately before the next FP instruction is executed. */
4571 DISAS_INSN(fpu)
4572 {
4573 uint16_t ext;
4574 int opmode;
4575 int opsize;
4576 TCGv_ptr cpu_src, cpu_dest;
4577
4578 ext = read_im16(env, s);
4579 opmode = ext & 0x7f;
4580 switch ((ext >> 13) & 7) {
4581 case 0:
4582 break;
4583 case 1:
4584 goto undef;
4585 case 2:
4586 if (insn == 0xf200 && (ext & 0xfc00) == 0x5c00) {
4587 /* fmovecr */
4588 TCGv rom_offset = tcg_const_i32(opmode);
4589 cpu_dest = gen_fp_ptr(REG(ext, 7));
4590 gen_helper_fconst(cpu_env, cpu_dest, rom_offset);
4591 tcg_temp_free_ptr(cpu_dest);
4592 tcg_temp_free(rom_offset);
4593 return;
4594 }
4595 break;
4596 case 3: /* fmove out */
4597 cpu_src = gen_fp_ptr(REG(ext, 7));
4598 opsize = ext_opsize(ext, 10);
4599 if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_STORE) == -1) {
4600 gen_addr_fault(s);
4601 }
4602 gen_helper_ftst(cpu_env, cpu_src);
4603 tcg_temp_free_ptr(cpu_src);
4604 return;
4605 case 4: /* fmove to control register. */
4606 case 5: /* fmove from control register. */
4607 gen_op_fmove_fcr(env, s, insn, ext);
4608 return;
4609 case 6: /* fmovem */
4610 case 7:
4611 if ((ext & 0x1000) == 0 && !m68k_feature(s->env, M68K_FEATURE_FPU)) {
4612 goto undef;
4613 }
4614 gen_op_fmovem(env, s, insn, ext);
4615 return;
4616 }
4617 if (ext & (1 << 14)) {
4618 /* Source effective address. */
4619 opsize = ext_opsize(ext, 10);
4620 cpu_src = gen_fp_result_ptr();
4621 if (gen_ea_fp(env, s, insn, opsize, cpu_src, EA_LOADS) == -1) {
4622 gen_addr_fault(s);
4623 return;
4624 }
4625 } else {
4626 /* Source register. */
4627 opsize = OS_EXTENDED;
4628 cpu_src = gen_fp_ptr(REG(ext, 10));
4629 }
4630 cpu_dest = gen_fp_ptr(REG(ext, 7));
4631 switch (opmode) {
4632 case 0: /* fmove */
4633 gen_fp_move(cpu_dest, cpu_src);
4634 break;
4635 case 0x40: /* fsmove */
4636 gen_helper_fsround(cpu_env, cpu_dest, cpu_src);
4637 break;
4638 case 0x44: /* fdmove */
4639 gen_helper_fdround(cpu_env, cpu_dest, cpu_src);
4640 break;
4641 case 1: /* fint */
4642 gen_helper_firound(cpu_env, cpu_dest, cpu_src);
4643 break;
4644 case 3: /* fintrz */
4645 gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src);
4646 break;
4647 case 4: /* fsqrt */
4648 gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src);
4649 break;
4650 case 0x41: /* fssqrt */
4651 gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src);
4652 break;
4653 case 0x45: /* fdsqrt */
4654 gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src);
4655 break;
4656 case 0x18: /* fabs */
4657 gen_helper_fabs(cpu_env, cpu_dest, cpu_src);
4658 break;
4659 case 0x58: /* fsabs */
4660 gen_helper_fsabs(cpu_env, cpu_dest, cpu_src);
4661 break;
4662 case 0x5c: /* fdabs */
4663 gen_helper_fdabs(cpu_env, cpu_dest, cpu_src);
4664 break;
4665 case 0x1a: /* fneg */
4666 gen_helper_fneg(cpu_env, cpu_dest, cpu_src);
4667 break;
4668 case 0x5a: /* fsneg */
4669 gen_helper_fsneg(cpu_env, cpu_dest, cpu_src);
4670 break;
4671 case 0x5e: /* fdneg */
4672 gen_helper_fdneg(cpu_env, cpu_dest, cpu_src);
4673 break;
4674 case 0x20: /* fdiv */
4675 gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4676 break;
4677 case 0x60: /* fsdiv */
4678 gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4679 break;
4680 case 0x64: /* fddiv */
4681 gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4682 break;
4683 case 0x22: /* fadd */
4684 gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
4685 break;
4686 case 0x62: /* fsadd */
4687 gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
4688 break;
4689 case 0x66: /* fdadd */
4690 gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest);
4691 break;
4692 case 0x23: /* fmul */
4693 gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4694 break;
4695 case 0x63: /* fsmul */
4696 gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4697 break;
4698 case 0x67: /* fdmul */
4699 gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4700 break;
4701 case 0x24: /* fsgldiv */
4702 gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest);
4703 break;
4704 case 0x27: /* fsglmul */
4705 gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest);
4706 break;
4707 case 0x28: /* fsub */
4708 gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
4709 break;
4710 case 0x68: /* fssub */
4711 gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest);
4712 break;
4713 case 0x6c: /* fdsub */
4714 gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest);
4715 break;
4716 case 0x38: /* fcmp */
4717 gen_helper_fcmp(cpu_env, cpu_src, cpu_dest);
4718 return;
4719 case 0x3a: /* ftst */
4720 gen_helper_ftst(cpu_env, cpu_src);
4721 return;
4722 default:
4723 goto undef;
4724 }
4725 tcg_temp_free_ptr(cpu_src);
4726 gen_helper_ftst(cpu_env, cpu_dest);
4727 tcg_temp_free_ptr(cpu_dest);
4728 return;
4729 undef:
4730 /* FIXME: Is this right for offset addressing modes? */
4731 s->pc -= 2;
4732 disas_undef_fpu(env, s, insn);
4733 }
4734
4735 static void gen_fcc_cond(DisasCompare *c, DisasContext *s, int cond)
4736 {
4737 TCGv fpsr;
4738
4739 c->g1 = 1;
4740 c->v2 = tcg_const_i32(0);
4741 c->g2 = 0;
4742 /* TODO: Raise BSUN exception. */
4743 fpsr = tcg_temp_new();
4744 gen_load_fcr(s, fpsr, M68K_FPSR);
4745 switch (cond) {
4746 case 0: /* False */
4747 case 16: /* Signaling False */
4748 c->v1 = c->v2;
4749 c->tcond = TCG_COND_NEVER;
4750 break;
4751 case 1: /* EQual Z */
4752 case 17: /* Signaling EQual Z */
4753 c->v1 = tcg_temp_new();
4754 c->g1 = 0;
4755 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4756 c->tcond = TCG_COND_NE;
4757 break;
4758 case 2: /* Ordered Greater Than !(A || Z || N) */
4759 case 18: /* Greater Than !(A || Z || N) */
4760 c->v1 = tcg_temp_new();
4761 c->g1 = 0;
4762 tcg_gen_andi_i32(c->v1, fpsr,
4763 FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4764 c->tcond = TCG_COND_EQ;
4765 break;
4766 case 3: /* Ordered Greater than or Equal Z || !(A || N) */
4767 case 19: /* Greater than or Equal Z || !(A || N) */
4768 c->v1 = tcg_temp_new();
4769 c->g1 = 0;
4770 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4771 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
4772 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
4773 tcg_gen_or_i32(c->v1, c->v1, fpsr);
4774 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4775 c->tcond = TCG_COND_NE;
4776 break;
4777 case 4: /* Ordered Less Than !(!N || A || Z); */
4778 case 20: /* Less Than !(!N || A || Z); */
4779 c->v1 = tcg_temp_new();
4780 c->g1 = 0;
4781 tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
4782 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
4783 c->tcond = TCG_COND_EQ;
4784 break;
4785 case 5: /* Ordered Less than or Equal Z || (N && !A) */
4786 case 21: /* Less than or Equal Z || (N && !A) */
4787 c->v1 = tcg_temp_new();
4788 c->g1 = 0;
4789 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4790 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
4791 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
4792 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_Z | FPSR_CC_N);
4793 c->tcond = TCG_COND_NE;
4794 break;
4795 case 6: /* Ordered Greater or Less than !(A || Z) */
4796 case 22: /* Greater or Less than !(A || Z) */
4797 c->v1 = tcg_temp_new();
4798 c->g1 = 0;
4799 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
4800 c->tcond = TCG_COND_EQ;
4801 break;
4802 case 7: /* Ordered !A */
4803 case 23: /* Greater, Less or Equal !A */
4804 c->v1 = tcg_temp_new();
4805 c->g1 = 0;
4806 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4807 c->tcond = TCG_COND_EQ;
4808 break;
4809 case 8: /* Unordered A */
4810 case 24: /* Not Greater, Less or Equal A */
4811 c->v1 = tcg_temp_new();
4812 c->g1 = 0;
4813 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
4814 c->tcond = TCG_COND_NE;
4815 break;
4816 case 9: /* Unordered or Equal A || Z */
4817 case 25: /* Not Greater or Less then A || Z */
4818 c->v1 = tcg_temp_new();
4819 c->g1 = 0;
4820 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
4821 c->tcond = TCG_COND_NE;
4822 break;
4823 case 10: /* Unordered or Greater Than A || !(N || Z)) */
4824 case 26: /* Not Less or Equal A || !(N || Z)) */
4825 c->v1 = tcg_temp_new();
4826 c->g1 = 0;
4827 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4828 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
4829 tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
4830 tcg_gen_or_i32(c->v1, c->v1, fpsr);
4831 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4832 c->tcond = TCG_COND_NE;
4833 break;
4834 case 11: /* Unordered or Greater or Equal A || Z || !N */
4835 case 27: /* Not Less Than A || Z || !N */
4836 c->v1 = tcg_temp_new();
4837 c->g1 = 0;
4838 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4839 tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
4840 c->tcond = TCG_COND_NE;
4841 break;
4842 case 12: /* Unordered or Less Than A || (N && !Z) */
4843 case 28: /* Not Greater than or Equal A || (N && !Z) */
4844 c->v1 = tcg_temp_new();
4845 c->g1 = 0;
4846 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4847 tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
4848 tcg_gen_andc_i32(c->v1, fpsr, c->v1);
4849 tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_A | FPSR_CC_N);
4850 c->tcond = TCG_COND_NE;
4851 break;
4852 case 13: /* Unordered or Less or Equal A || Z || N */
4853 case 29: /* Not Greater Than A || Z || N */
4854 c->v1 = tcg_temp_new();
4855 c->g1 = 0;
4856 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
4857 c->tcond = TCG_COND_NE;
4858 break;
4859 case 14: /* Not Equal !Z */
4860 case 30: /* Signaling Not Equal !Z */
4861 c->v1 = tcg_temp_new();
4862 c->g1 = 0;
4863 tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
4864 c->tcond = TCG_COND_EQ;
4865 break;
4866 case 15: /* True */
4867 case 31: /* Signaling True */
4868 c->v1 = c->v2;
4869 c->tcond = TCG_COND_ALWAYS;
4870 break;
4871 }
4872 tcg_temp_free(fpsr);
4873 }
4874
4875 static void gen_fjmpcc(DisasContext *s, int cond, TCGLabel *l1)
4876 {
4877 DisasCompare c;
4878
4879 gen_fcc_cond(&c, s, cond);
4880 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
4881 free_cond(&c);
4882 }
4883
4884 DISAS_INSN(fbcc)
4885 {
4886 uint32_t offset;
4887 uint32_t base;
4888 TCGLabel *l1;
4889
4890 base = s->pc;
4891 offset = (int16_t)read_im16(env, s);
4892 if (insn & (1 << 6)) {
4893 offset = (offset << 16) | read_im16(env, s);
4894 }
4895
4896 l1 = gen_new_label();
4897 update_cc_op(s);
4898 gen_fjmpcc(s, insn & 0x3f, l1);
4899 gen_jmp_tb(s, 0, s->pc);
4900 gen_set_label(l1);
4901 gen_jmp_tb(s, 1, base + offset);
4902 }
4903
4904 DISAS_INSN(fscc)
4905 {
4906 DisasCompare c;
4907 int cond;
4908 TCGv tmp;
4909 uint16_t ext;
4910
4911 ext = read_im16(env, s);
4912 cond = ext & 0x3f;
4913 gen_fcc_cond(&c, s, cond);
4914
4915 tmp = tcg_temp_new();
4916 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
4917 free_cond(&c);
4918
4919 tcg_gen_neg_i32(tmp, tmp);
4920 DEST_EA(env, insn, OS_BYTE, tmp, NULL);
4921 tcg_temp_free(tmp);
4922 }
4923
4924 static void QEMU_NORETURN disas_frestore(CPUM68KState *env,
4925 DisasContext *s, uint16_t insn);
4926 DISAS_INSN(frestore)
4927 {
4928 M68kCPU *cpu = m68k_env_get_cpu(env);
4929
4930 /* TODO: Implement frestore. */
4931 cpu_abort(CPU(cpu), "FRESTORE not implemented");
4932 }
4933
4934 static void QEMU_NORETURN disas_fsave(CPUM68KState *env,
4935 DisasContext *s, uint16_t insn);
4936 DISAS_INSN(fsave)
4937 {
4938 M68kCPU *cpu = m68k_env_get_cpu(env);
4939
4940 /* TODO: Implement fsave. */
4941 cpu_abort(CPU(cpu), "FSAVE not implemented");
4942 }
4943
4944 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
4945 {
4946 TCGv tmp = tcg_temp_new();
4947 if (s->env->macsr & MACSR_FI) {
4948 if (upper)
4949 tcg_gen_andi_i32(tmp, val, 0xffff0000);
4950 else
4951 tcg_gen_shli_i32(tmp, val, 16);
4952 } else if (s->env->macsr & MACSR_SU) {
4953 if (upper)
4954 tcg_gen_sari_i32(tmp, val, 16);
4955 else
4956 tcg_gen_ext16s_i32(tmp, val);
4957 } else {
4958 if (upper)
4959 tcg_gen_shri_i32(tmp, val, 16);
4960 else
4961 tcg_gen_ext16u_i32(tmp, val);
4962 }
4963 return tmp;
4964 }
4965
4966 static void gen_mac_clear_flags(void)
4967 {
4968 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
4969 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
4970 }
4971
4972 DISAS_INSN(mac)
4973 {
4974 TCGv rx;
4975 TCGv ry;
4976 uint16_t ext;
4977 int acc;
4978 TCGv tmp;
4979 TCGv addr;
4980 TCGv loadval;
4981 int dual;
4982 TCGv saved_flags;
4983
4984 if (!s->done_mac) {
4985 s->mactmp = tcg_temp_new_i64();
4986 s->done_mac = 1;
4987 }
4988
4989 ext = read_im16(env, s);
4990
4991 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
4992 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
4993 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
4994 disas_undef(env, s, insn);
4995 return;
4996 }
4997 if (insn & 0x30) {
4998 /* MAC with load. */
4999 tmp = gen_lea(env, s, insn, OS_LONG);
5000 addr = tcg_temp_new();
5001 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
5002 /* Load the value now to ensure correct exception behavior.
5003 Perform writeback after reading the MAC inputs. */
5004 loadval = gen_load(s, OS_LONG, addr, 0);
5005
5006 acc ^= 1;
5007 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
5008 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
5009 } else {
5010 loadval = addr = NULL_QREG;
5011 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5012 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5013 }
5014
5015 gen_mac_clear_flags();
5016 #if 0
5017 l1 = -1;
5018 /* Disabled because conditional branches clobber temporary vars. */
5019 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
5020 /* Skip the multiply if we know we will ignore it. */
5021 l1 = gen_new_label();
5022 tmp = tcg_temp_new();
5023 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
5024 gen_op_jmp_nz32(tmp, l1);
5025 }
5026 #endif
5027
5028 if ((ext & 0x0800) == 0) {
5029 /* Word. */
5030 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
5031 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
5032 }
5033 if (s->env->macsr & MACSR_FI) {
5034 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
5035 } else {
5036 if (s->env->macsr & MACSR_SU)
5037 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
5038 else
5039 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
5040 switch ((ext >> 9) & 3) {
5041 case 1:
5042 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
5043 break;
5044 case 3:
5045 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
5046 break;
5047 }
5048 }
5049
5050 if (dual) {
5051 /* Save the overflow flag from the multiply. */
5052 saved_flags = tcg_temp_new();
5053 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
5054 } else {
5055 saved_flags = NULL_QREG;
5056 }
5057
5058 #if 0
5059 /* Disabled because conditional branches clobber temporary vars. */
5060 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
5061 /* Skip the accumulate if the value is already saturated. */
5062 l1 = gen_new_label();
5063 tmp = tcg_temp_new();
5064 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5065 gen_op_jmp_nz32(tmp, l1);
5066 }
5067 #endif
5068
5069 if (insn & 0x100)
5070 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5071 else
5072 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5073
5074 if (s->env->macsr & MACSR_FI)
5075 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5076 else if (s->env->macsr & MACSR_SU)
5077 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5078 else
5079 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5080
5081 #if 0
5082 /* Disabled because conditional branches clobber temporary vars. */
5083 if (l1 != -1)
5084 gen_set_label(l1);
5085 #endif
5086
5087 if (dual) {
5088 /* Dual accumulate variant. */
5089 acc = (ext >> 2) & 3;
5090 /* Restore the overflow flag from the multiplier. */
5091 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
5092 #if 0
5093 /* Disabled because conditional branches clobber temporary vars. */
5094 if ((s->env->macsr & MACSR_OMC) != 0) {
5095 /* Skip the accumulate if the value is already saturated. */
5096 l1 = gen_new_label();
5097 tmp = tcg_temp_new();
5098 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
5099 gen_op_jmp_nz32(tmp, l1);
5100 }
5101 #endif
5102 if (ext & 2)
5103 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
5104 else
5105 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
5106 if (s->env->macsr & MACSR_FI)
5107 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
5108 else if (s->env->macsr & MACSR_SU)
5109 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
5110 else
5111 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
5112 #if 0
5113 /* Disabled because conditional branches clobber temporary vars. */
5114 if (l1 != -1)
5115 gen_set_label(l1);
5116 #endif
5117 }
5118 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
5119
5120 if (insn & 0x30) {
5121 TCGv rw;
5122 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
5123 tcg_gen_mov_i32(rw, loadval);
5124 /* FIXME: Should address writeback happen with the masked or
5125 unmasked value? */
5126 switch ((insn >> 3) & 7) {
5127 case 3: /* Post-increment. */
5128 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
5129 break;
5130 case 4: /* Pre-decrement. */
5131 tcg_gen_mov_i32(AREG(insn, 0), addr);
5132 }
5133 }
5134 }
5135
5136 DISAS_INSN(from_mac)
5137 {
5138 TCGv rx;
5139 TCGv_i64 acc;
5140 int accnum;
5141
5142 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5143 accnum = (insn >> 9) & 3;
5144 acc = MACREG(accnum);
5145 if (s->env->macsr & MACSR_FI) {
5146 gen_helper_get_macf(rx, cpu_env, acc);
5147 } else if ((s->env->macsr & MACSR_OMC) == 0) {
5148 tcg_gen_extrl_i64_i32(rx, acc);
5149 } else if (s->env->macsr & MACSR_SU) {
5150 gen_helper_get_macs(rx, acc);
5151 } else {
5152 gen_helper_get_macu(rx, acc);
5153 }
5154 if (insn & 0x40) {
5155 tcg_gen_movi_i64(acc, 0);
5156 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5157 }
5158 }
5159
5160 DISAS_INSN(move_mac)
5161 {
5162 /* FIXME: This can be done without a helper. */
5163 int src;
5164 TCGv dest;
5165 src = insn & 3;
5166 dest = tcg_const_i32((insn >> 9) & 3);
5167 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
5168 gen_mac_clear_flags();
5169 gen_helper_mac_set_flags(cpu_env, dest);
5170 }
5171
5172 DISAS_INSN(from_macsr)
5173 {
5174 TCGv reg;
5175
5176 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5177 tcg_gen_mov_i32(reg, QREG_MACSR);
5178 }
5179
5180 DISAS_INSN(from_mask)
5181 {
5182 TCGv reg;
5183 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5184 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
5185 }
5186
5187 DISAS_INSN(from_mext)
5188 {
5189 TCGv reg;
5190 TCGv acc;
5191 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
5192 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5193 if (s->env->macsr & MACSR_FI)
5194 gen_helper_get_mac_extf(reg, cpu_env, acc);
5195 else
5196 gen_helper_get_mac_exti(reg, cpu_env, acc);
5197 }
5198
5199 DISAS_INSN(macsr_to_ccr)
5200 {
5201 TCGv tmp = tcg_temp_new();
5202 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
5203 gen_helper_set_sr(cpu_env, tmp);
5204 tcg_temp_free(tmp);
5205 set_cc_op(s, CC_OP_FLAGS);
5206 }
5207
5208 DISAS_INSN(to_mac)
5209 {
5210 TCGv_i64 acc;
5211 TCGv val;
5212 int accnum;
5213 accnum = (insn >> 9) & 3;
5214 acc = MACREG(accnum);
5215 SRC_EA(env, val, OS_LONG, 0, NULL);
5216 if (s->env->macsr & MACSR_FI) {
5217 tcg_gen_ext_i32_i64(acc, val);
5218 tcg_gen_shli_i64(acc, acc, 8);
5219 } else if (s->env->macsr & MACSR_SU) {
5220 tcg_gen_ext_i32_i64(acc, val);
5221 } else {
5222 tcg_gen_extu_i32_i64(acc, val);
5223 }
5224 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
5225 gen_mac_clear_flags();
5226 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
5227 }
5228
5229 DISAS_INSN(to_macsr)
5230 {
5231 TCGv val;
5232 SRC_EA(env, val, OS_LONG, 0, NULL);
5233 gen_helper_set_macsr(cpu_env, val);
5234 gen_lookup_tb(s);
5235 }
5236
5237 DISAS_INSN(to_mask)
5238 {
5239 TCGv val;
5240 SRC_EA(env, val, OS_LONG, 0, NULL);
5241 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
5242 }
5243
5244 DISAS_INSN(to_mext)
5245 {
5246 TCGv val;
5247 TCGv acc;
5248 SRC_EA(env, val, OS_LONG, 0, NULL);
5249 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
5250 if (s->env->macsr & MACSR_FI)
5251 gen_helper_set_mac_extf(cpu_env, val, acc);
5252 else if (s->env->macsr & MACSR_SU)
5253 gen_helper_set_mac_exts(cpu_env, val, acc);
5254 else
5255 gen_helper_set_mac_extu(cpu_env, val, acc);
5256 }
5257
5258 static disas_proc opcode_table[65536];
5259
5260 static void
5261 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
5262 {
5263 int i;
5264 int from;
5265 int to;
5266
5267 /* Sanity check. All set bits must be included in the mask. */
5268 if (opcode & ~mask) {
5269 fprintf(stderr,
5270 "qemu internal error: bogus opcode definition %04x/%04x\n",
5271 opcode, mask);
5272 abort();
5273 }
5274 /* This could probably be cleverer. For now just optimize the case where
5275 the top bits are known. */
5276 /* Find the first zero bit in the mask. */
5277 i = 0x8000;
5278 while ((i & mask) != 0)
5279 i >>= 1;
5280 /* Iterate over all combinations of this and lower bits. */
5281 if (i == 0)
5282 i = 1;
5283 else
5284 i <<= 1;
5285 from = opcode & ~(i - 1);
5286 to = from + i;
5287 for (i = from; i < to; i++) {
5288 if ((i & mask) == opcode)
5289 opcode_table[i] = proc;
5290 }
5291 }
5292
5293 /* Register m68k opcode handlers. Order is important.
5294 Later insn override earlier ones. */
5295 void register_m68k_insns (CPUM68KState *env)
5296 {
5297 /* Build the opcode table only once to avoid
5298 multithreading issues. */
5299 if (opcode_table[0] != NULL) {
5300 return;
5301 }
5302
5303 /* use BASE() for instruction available
5304 * for CF_ISA_A and M68000.
5305 */
5306 #define BASE(name, opcode, mask) \
5307 register_opcode(disas_##name, 0x##opcode, 0x##mask)
5308 #define INSN(name, opcode, mask, feature) do { \
5309 if (m68k_feature(env, M68K_FEATURE_##feature)) \
5310 BASE(name, opcode, mask); \
5311 } while(0)
5312 BASE(undef, 0000, 0000);
5313 INSN(arith_im, 0080, fff8, CF_ISA_A);
5314 INSN(arith_im, 0000, ff00, M68000);
5315 INSN(undef, 00c0, ffc0, M68000);
5316 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
5317 BASE(bitop_reg, 0100, f1c0);
5318 BASE(bitop_reg, 0140, f1c0);
5319 BASE(bitop_reg, 0180, f1c0);
5320 BASE(bitop_reg, 01c0, f1c0);
5321 INSN(arith_im, 0280, fff8, CF_ISA_A);
5322 INSN(arith_im, 0200, ff00, M68000);
5323 INSN(undef, 02c0, ffc0, M68000);
5324 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
5325 INSN(arith_im, 0480, fff8, CF_ISA_A);
5326 INSN(arith_im, 0400, ff00, M68000);
5327 INSN(undef, 04c0, ffc0, M68000);
5328 INSN(arith_im, 0600, ff00, M68000);
5329 INSN(undef, 06c0, ffc0, M68000);
5330 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
5331 INSN(arith_im, 0680, fff8, CF_ISA_A);
5332 INSN(arith_im, 0c00, ff38, CF_ISA_A);
5333 INSN(arith_im, 0c00, ff00, M68000);
5334 BASE(bitop_im, 0800, ffc0);
5335 BASE(bitop_im, 0840, ffc0);
5336 BASE(bitop_im, 0880, ffc0);
5337 BASE(bitop_im, 08c0, ffc0);
5338 INSN(arith_im, 0a80, fff8, CF_ISA_A);
5339 INSN(arith_im, 0a00, ff00, M68000);
5340 INSN(cas, 0ac0, ffc0, CAS);
5341 INSN(cas, 0cc0, ffc0, CAS);
5342 INSN(cas, 0ec0, ffc0, CAS);
5343 INSN(cas2w, 0cfc, ffff, CAS);
5344 INSN(cas2l, 0efc, ffff, CAS);
5345 BASE(move, 1000, f000);
5346 BASE(move, 2000, f000);
5347 BASE(move, 3000, f000);
5348 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
5349 INSN(negx, 4080, fff8, CF_ISA_A);
5350 INSN(negx, 4000, ff00, M68000);
5351 INSN(undef, 40c0, ffc0, M68000);
5352 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
5353 INSN(move_from_sr, 40c0, ffc0, M68000);
5354 BASE(lea, 41c0, f1c0);
5355 BASE(clr, 4200, ff00);
5356 BASE(undef, 42c0, ffc0);
5357 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
5358 INSN(move_from_ccr, 42c0, ffc0, M68000);
5359 INSN(neg, 4480, fff8, CF_ISA_A);
5360 INSN(neg, 4400, ff00, M68000);
5361 INSN(undef, 44c0, ffc0, M68000);
5362 BASE(move_to_ccr, 44c0, ffc0);
5363 INSN(not, 4680, fff8, CF_ISA_A);
5364 INSN(not, 4600, ff00, M68000);
5365 INSN(undef, 46c0, ffc0, M68000);
5366 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
5367 INSN(nbcd, 4800, ffc0, M68000);
5368 INSN(linkl, 4808, fff8, M68000);
5369 BASE(pea, 4840, ffc0);
5370 BASE(swap, 4840, fff8);
5371 INSN(bkpt, 4848, fff8, BKPT);
5372 INSN(movem, 48d0, fbf8, CF_ISA_A);
5373 INSN(movem, 48e8, fbf8, CF_ISA_A);
5374 INSN(movem, 4880, fb80, M68000);
5375 BASE(ext, 4880, fff8);
5376 BASE(ext, 48c0, fff8);
5377 BASE(ext, 49c0, fff8);
5378 BASE(tst, 4a00, ff00);
5379 INSN(tas, 4ac0, ffc0, CF_ISA_B);
5380 INSN(tas, 4ac0, ffc0, M68000);
5381 INSN(halt, 4ac8, ffff, CF_ISA_A);
5382 INSN(pulse, 4acc, ffff, CF_ISA_A);
5383 BASE(illegal, 4afc, ffff);
5384 INSN(mull, 4c00, ffc0, CF_ISA_A);
5385 INSN(mull, 4c00, ffc0, LONG_MULDIV);
5386 INSN(divl, 4c40, ffc0, CF_ISA_A);
5387 INSN(divl, 4c40, ffc0, LONG_MULDIV);
5388 INSN(sats, 4c80, fff8, CF_ISA_B);
5389 BASE(trap, 4e40, fff0);
5390 BASE(link, 4e50, fff8);
5391 BASE(unlk, 4e58, fff8);
5392 INSN(move_to_usp, 4e60, fff8, USP);
5393 INSN(move_from_usp, 4e68, fff8, USP);
5394 BASE(nop, 4e71, ffff);
5395 BASE(stop, 4e72, ffff);
5396 BASE(rte, 4e73, ffff);
5397 INSN(rtd, 4e74, ffff, RTD);
5398 BASE(rts, 4e75, ffff);
5399 INSN(movec, 4e7b, ffff, CF_ISA_A);
5400 BASE(jump, 4e80, ffc0);
5401 BASE(jump, 4ec0, ffc0);
5402 INSN(addsubq, 5000, f080, M68000);
5403 BASE(addsubq, 5080, f0c0);
5404 INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */
5405 INSN(scc, 50c0, f0c0, M68000); /* Scc.B <EA> */
5406 INSN(dbcc, 50c8, f0f8, M68000);
5407 INSN(tpf, 51f8, fff8, CF_ISA_A);
5408
5409 /* Branch instructions. */
5410 BASE(branch, 6000, f000);
5411 /* Disable long branch instructions, then add back the ones we want. */
5412 BASE(undef, 60ff, f0ff); /* All long branches. */
5413 INSN(branch, 60ff, f0ff, CF_ISA_B);
5414 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
5415 INSN(branch, 60ff, ffff, BRAL);
5416 INSN(branch, 60ff, f0ff, BCCL);
5417
5418 BASE(moveq, 7000, f100);
5419 INSN(mvzs, 7100, f100, CF_ISA_B);
5420 BASE(or, 8000, f000);
5421 BASE(divw, 80c0, f0c0);
5422 INSN(sbcd_reg, 8100, f1f8, M68000);
5423 INSN(sbcd_mem, 8108, f1f8, M68000);
5424 BASE(addsub, 9000, f000);
5425 INSN(undef, 90c0, f0c0, CF_ISA_A);
5426 INSN(subx_reg, 9180, f1f8, CF_ISA_A);
5427 INSN(subx_reg, 9100, f138, M68000);
5428 INSN(subx_mem, 9108, f138, M68000);
5429 INSN(suba, 91c0, f1c0, CF_ISA_A);
5430 INSN(suba, 90c0, f0c0, M68000);
5431
5432 BASE(undef_mac, a000, f000);
5433 INSN(mac, a000, f100, CF_EMAC);
5434 INSN(from_mac, a180, f9b0, CF_EMAC);
5435 INSN(move_mac, a110, f9fc, CF_EMAC);
5436 INSN(from_macsr,a980, f9f0, CF_EMAC);
5437 INSN(from_mask, ad80, fff0, CF_EMAC);
5438 INSN(from_mext, ab80, fbf0, CF_EMAC);
5439 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
5440 INSN(to_mac, a100, f9c0, CF_EMAC);
5441 INSN(to_macsr, a900, ffc0, CF_EMAC);
5442 INSN(to_mext, ab00, fbc0, CF_EMAC);
5443 INSN(to_mask, ad00, ffc0, CF_EMAC);
5444
5445 INSN(mov3q, a140, f1c0, CF_ISA_B);
5446 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
5447 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
5448 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
5449 INSN(cmp, b080, f1c0, CF_ISA_A);
5450 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
5451 INSN(cmp, b000, f100, M68000);
5452 INSN(eor, b100, f100, M68000);
5453 INSN(cmpm, b108, f138, M68000);
5454 INSN(cmpa, b0c0, f0c0, M68000);
5455 INSN(eor, b180, f1c0, CF_ISA_A);
5456 BASE(and, c000, f000);
5457 INSN(exg_dd, c140, f1f8, M68000);
5458 INSN(exg_aa, c148, f1f8, M68000);
5459 INSN(exg_da, c188, f1f8, M68000);
5460 BASE(mulw, c0c0, f0c0);
5461 INSN(abcd_reg, c100, f1f8, M68000);
5462 INSN(abcd_mem, c108, f1f8, M68000);
5463 BASE(addsub, d000, f000);
5464 INSN(undef, d0c0, f0c0, CF_ISA_A);
5465 INSN(addx_reg, d180, f1f8, CF_ISA_A);
5466 INSN(addx_reg, d100, f138, M68000);
5467 INSN(addx_mem, d108, f138, M68000);
5468 INSN(adda, d1c0, f1c0, CF_ISA_A);
5469 INSN(adda, d0c0, f0c0, M68000);
5470 INSN(shift_im, e080, f0f0, CF_ISA_A);
5471 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
5472 INSN(shift8_im, e000, f0f0, M68000);
5473 INSN(shift16_im, e040, f0f0, M68000);
5474 INSN(shift_im, e080, f0f0, M68000);
5475 INSN(shift8_reg, e020, f0f0, M68000);
5476 INSN(shift16_reg, e060, f0f0, M68000);
5477 INSN(shift_reg, e0a0, f0f0, M68000);
5478 INSN(shift_mem, e0c0, fcc0, M68000);
5479 INSN(rotate_im, e090, f0f0, M68000);
5480 INSN(rotate8_im, e010, f0f0, M68000);
5481 INSN(rotate16_im, e050, f0f0, M68000);
5482 INSN(rotate_reg, e0b0, f0f0, M68000);
5483 INSN(rotate8_reg, e030, f0f0, M68000);
5484 INSN(rotate16_reg, e070, f0f0, M68000);
5485 INSN(rotate_mem, e4c0, fcc0, M68000);
5486 INSN(bfext_mem, e9c0, fdc0, BITFIELD); /* bfextu & bfexts */
5487 INSN(bfext_reg, e9c0, fdf8, BITFIELD);
5488 INSN(bfins_mem, efc0, ffc0, BITFIELD);
5489 INSN(bfins_reg, efc0, fff8, BITFIELD);
5490 INSN(bfop_mem, eac0, ffc0, BITFIELD); /* bfchg */
5491 INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
5492 INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
5493 INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
5494 INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
5495 INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
5496 INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
5497 INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
5498 INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */
5499 INSN(bfop_reg, e8c0, fff8, BITFIELD); /* bftst */
5500 BASE(undef_fpu, f000, f000);
5501 INSN(fpu, f200, ffc0, CF_FPU);
5502 INSN(fbcc, f280, ffc0, CF_FPU);
5503 INSN(frestore, f340, ffc0, CF_FPU);
5504 INSN(fsave, f300, ffc0, CF_FPU);
5505 INSN(fpu, f200, ffc0, FPU);
5506 INSN(fscc, f240, ffc0, FPU);
5507 INSN(fbcc, f280, ff80, FPU);
5508 INSN(frestore, f340, ffc0, FPU);
5509 INSN(fsave, f300, ffc0, FPU);
5510 INSN(intouch, f340, ffc0, CF_ISA_A);
5511 INSN(cpushl, f428, ff38, CF_ISA_A);
5512 INSN(wddata, fb00, ff00, CF_ISA_A);
5513 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
5514 #undef INSN
5515 }
5516
5517 /* ??? Some of this implementation is not exception safe. We should always
5518 write back the result to memory before setting the condition codes. */
5519 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
5520 {
5521 uint16_t insn = read_im16(env, s);
5522 opcode_table[insn](env, s, insn);
5523 do_writebacks(s);
5524 }
5525
5526 /* generate intermediate code for basic block 'tb'. */
5527 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
5528 {
5529 CPUM68KState *env = cs->env_ptr;
5530 DisasContext dc1, *dc = &dc1;
5531 target_ulong pc_start;
5532 int pc_offset;
5533 int num_insns;
5534 int max_insns;
5535
5536 /* generate intermediate code */
5537 pc_start = tb->pc;
5538
5539 dc->tb = tb;
5540
5541 dc->env = env;
5542 dc->is_jmp = DISAS_NEXT;
5543 dc->pc = pc_start;
5544 dc->cc_op = CC_OP_DYNAMIC;
5545 dc->cc_op_synced = 1;
5546 dc->singlestep_enabled = cs->singlestep_enabled;
5547 dc->user = (env->sr & SR_S) == 0;
5548 dc->done_mac = 0;
5549 dc->writeback_mask = 0;
5550 num_insns = 0;
5551 max_insns = tb_cflags(tb) & CF_COUNT_MASK;
5552 if (max_insns == 0) {
5553 max_insns = CF_COUNT_MASK;
5554 }
5555 if (max_insns > TCG_MAX_INSNS) {
5556 max_insns = TCG_MAX_INSNS;
5557 }
5558
5559 gen_tb_start(tb);
5560 do {
5561 pc_offset = dc->pc - pc_start;
5562 tcg_gen_insn_start(dc->pc, dc->cc_op);
5563 num_insns++;
5564
5565 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
5566 gen_exception(dc, dc->pc, EXCP_DEBUG);
5567 dc->is_jmp = DISAS_JUMP;
5568 /* The address covered by the breakpoint must be included in
5569 [tb->pc, tb->pc + tb->size) in order to for it to be
5570 properly cleared -- thus we increment the PC here so that
5571 the logic setting tb->size below does the right thing. */
5572 dc->pc += 2;
5573 break;
5574 }
5575
5576 if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
5577 gen_io_start();
5578 }
5579
5580 dc->insn_pc = dc->pc;
5581 disas_m68k_insn(env, dc);
5582 } while (!dc->is_jmp && !tcg_op_buf_full() &&
5583 !cs->singlestep_enabled &&
5584 !singlestep &&
5585 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
5586 num_insns < max_insns);
5587
5588 if (tb_cflags(tb) & CF_LAST_IO)
5589 gen_io_end();
5590 if (unlikely(cs->singlestep_enabled)) {
5591 /* Make sure the pc is updated, and raise a debug exception. */
5592 if (!dc->is_jmp) {
5593 update_cc_op(dc);
5594 tcg_gen_movi_i32(QREG_PC, dc->pc);
5595 }
5596 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
5597 } else {
5598 switch(dc->is_jmp) {
5599 case DISAS_NEXT:
5600 update_cc_op(dc);
5601 gen_jmp_tb(dc, 0, dc->pc);
5602 break;
5603 default:
5604 case DISAS_JUMP:
5605 case DISAS_UPDATE:
5606 update_cc_op(dc);
5607 /* indicate that the hash table must be used to find the next TB */
5608 tcg_gen_exit_tb(0);
5609 break;
5610 case DISAS_TB_JUMP:
5611 /* nothing more to generate */
5612 break;
5613 }
5614 }
5615 gen_tb_end(tb, num_insns);
5616
5617 #ifdef DEBUG_DISAS
5618 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
5619 && qemu_log_in_addr_range(pc_start)) {
5620 qemu_log_lock();
5621 qemu_log("----------------\n");
5622 qemu_log("IN: %s\n", lookup_symbol(pc_start));
5623 log_target_disas(cs, pc_start, dc->pc - pc_start);
5624 qemu_log("\n");
5625 qemu_log_unlock();
5626 }
5627 #endif
5628 tb->size = dc->pc - pc_start;
5629 tb->icount = num_insns;
5630 }
5631
5632 static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
5633 {
5634 floatx80 a = { .high = high, .low = low };
5635 union {
5636 float64 f64;
5637 double d;
5638 } u;
5639
5640 u.f64 = floatx80_to_float64(a, &env->fp_status);
5641 return u.d;
5642 }
5643
5644 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
5645 int flags)
5646 {
5647 M68kCPU *cpu = M68K_CPU(cs);
5648 CPUM68KState *env = &cpu->env;
5649 int i;
5650 uint16_t sr;
5651 for (i = 0; i < 8; i++) {
5652 cpu_fprintf(f, "D%d = %08x A%d = %08x "
5653 "F%d = %04x %016"PRIx64" (%12g)\n",
5654 i, env->dregs[i], i, env->aregs[i],
5655 i, env->fregs[i].l.upper, env->fregs[i].l.lower,
5656 floatx80_to_double(env, env->fregs[i].l.upper,
5657 env->fregs[i].l.lower));
5658 }
5659 cpu_fprintf (f, "PC = %08x ", env->pc);
5660 sr = env->sr | cpu_m68k_get_ccr(env);
5661 cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
5662 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
5663 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
5664 cpu_fprintf(f, "FPSR = %08x %c%c%c%c ", env->fpsr,
5665 (env->fpsr & FPSR_CC_A) ? 'A' : '-',
5666 (env->fpsr & FPSR_CC_I) ? 'I' : '-',
5667 (env->fpsr & FPSR_CC_Z) ? 'Z' : '-',
5668 (env->fpsr & FPSR_CC_N) ? 'N' : '-');
5669 cpu_fprintf(f, "\n "
5670 "FPCR = %04x ", env->fpcr);
5671 switch (env->fpcr & FPCR_PREC_MASK) {
5672 case FPCR_PREC_X:
5673 cpu_fprintf(f, "X ");
5674 break;
5675 case FPCR_PREC_S:
5676 cpu_fprintf(f, "S ");
5677 break;
5678 case FPCR_PREC_D:
5679 cpu_fprintf(f, "D ");
5680 break;
5681 }
5682 switch (env->fpcr & FPCR_RND_MASK) {
5683 case FPCR_RND_N:
5684 cpu_fprintf(f, "RN ");
5685 break;
5686 case FPCR_RND_Z:
5687 cpu_fprintf(f, "RZ ");
5688 break;
5689 case FPCR_RND_M:
5690 cpu_fprintf(f, "RM ");
5691 break;
5692 case FPCR_RND_P:
5693 cpu_fprintf(f, "RP ");
5694 break;
5695 }
5696 }
5697
5698 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
5699 target_ulong *data)
5700 {
5701 int cc_op = data[1];
5702 env->pc = data[0];
5703 if (cc_op != CC_OP_DYNAMIC) {
5704 env->cc_op = cc_op;
5705 }
5706 }
AR7 emulation for QEMU