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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / target / i386 / kvm.c
blob35143acc25db9cddb37da79313290f47f546da66
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "exec/ioport.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci/msix.h"
47 #include "migration/blocker.h"
48 #include "exec/memattrs.h"
49 #include "trace.h"
50
51 //#define DEBUG_KVM
52
53 #ifdef DEBUG_KVM
54 #define DPRINTF(fmt, ...) \
55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56 #else
57 #define DPRINTF(fmt, ...) \
58 do { } while (0)
59 #endif
60
61 #define MSR_KVM_WALL_CLOCK 0x11
62 #define MSR_KVM_SYSTEM_TIME 0x12
63
64 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66 #define MSR_BUF_SIZE 4096
67
68 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73 };
74
75 static bool has_msr_star;
76 static bool has_msr_hsave_pa;
77 static bool has_msr_tsc_aux;
78 static bool has_msr_tsc_adjust;
79 static bool has_msr_tsc_deadline;
80 static bool has_msr_feature_control;
81 static bool has_msr_misc_enable;
82 static bool has_msr_smbase;
83 static bool has_msr_bndcfgs;
84 static int lm_capable_kernel;
85 static bool has_msr_hv_hypercall;
86 static bool has_msr_hv_crash;
87 static bool has_msr_hv_reset;
88 static bool has_msr_hv_vpindex;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_xss;
94 static bool has_msr_spec_ctrl;
95
96 static uint32_t has_architectural_pmu_version;
97 static uint32_t num_architectural_pmu_gp_counters;
98 static uint32_t num_architectural_pmu_fixed_counters;
99
100 static int has_xsave;
101 static int has_xcrs;
102 static int has_pit_state2;
103
104 static bool has_msr_mcg_ext_ctl;
105
106 static struct kvm_cpuid2 *cpuid_cache;
107
108 int kvm_has_pit_state2(void)
109 {
110 return has_pit_state2;
111 }
112
113 bool kvm_has_smm(void)
114 {
115 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
116 }
117
118 bool kvm_has_adjust_clock_stable(void)
119 {
120 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
121
122 return (ret == KVM_CLOCK_TSC_STABLE);
123 }
124
125 bool kvm_allows_irq0_override(void)
126 {
127 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
128 }
129
130 static bool kvm_x2apic_api_set_flags(uint64_t flags)
131 {
132 KVMState *s = KVM_STATE(current_machine->accelerator);
133
134 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
135 }
136
137 #define MEMORIZE(fn, _result) \
138 ({ \
139 static bool _memorized; \
140 \
141 if (_memorized) { \
142 return _result; \
143 } \
144 _memorized = true; \
145 _result = fn; \
146 })
147
148 static bool has_x2apic_api;
149
150 bool kvm_has_x2apic_api(void)
151 {
152 return has_x2apic_api;
153 }
154
155 bool kvm_enable_x2apic(void)
156 {
157 return MEMORIZE(
158 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
159 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
160 has_x2apic_api);
161 }
162
163 static int kvm_get_tsc(CPUState *cs)
164 {
165 X86CPU *cpu = X86_CPU(cs);
166 CPUX86State *env = &cpu->env;
167 struct {
168 struct kvm_msrs info;
169 struct kvm_msr_entry entries[1];
170 } msr_data;
171 int ret;
172
173 if (env->tsc_valid) {
174 return 0;
175 }
176
177 msr_data.info.nmsrs = 1;
178 msr_data.entries[0].index = MSR_IA32_TSC;
179 env->tsc_valid = !runstate_is_running();
180
181 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
182 if (ret < 0) {
183 return ret;
184 }
185
186 assert(ret == 1);
187 env->tsc = msr_data.entries[0].data;
188 return 0;
189 }
190
191 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
192 {
193 kvm_get_tsc(cpu);
194 }
195
196 void kvm_synchronize_all_tsc(void)
197 {
198 CPUState *cpu;
199
200 if (kvm_enabled()) {
201 CPU_FOREACH(cpu) {
202 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
203 }
204 }
205 }
206
207 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
208 {
209 struct kvm_cpuid2 *cpuid;
210 int r, size;
211
212 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
213 cpuid = g_malloc0(size);
214 cpuid->nent = max;
215 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
216 if (r == 0 && cpuid->nent >= max) {
217 r = -E2BIG;
218 }
219 if (r < 0) {
220 if (r == -E2BIG) {
221 g_free(cpuid);
222 return NULL;
223 } else {
224 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
225 strerror(-r));
226 exit(1);
227 }
228 }
229 return cpuid;
230 }
231
232 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
233 * for all entries.
234 */
235 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
236 {
237 struct kvm_cpuid2 *cpuid;
238 int max = 1;
239
240 if (cpuid_cache != NULL) {
241 return cpuid_cache;
242 }
243 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
244 max *= 2;
245 }
246 cpuid_cache = cpuid;
247 return cpuid;
248 }
249
250 static const struct kvm_para_features {
251 int cap;
252 int feature;
253 } para_features[] = {
254 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
255 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
256 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
257 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
258 };
259
260 static int get_para_features(KVMState *s)
261 {
262 int i, features = 0;
263
264 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
265 if (kvm_check_extension(s, para_features[i].cap)) {
266 features |= (1 << para_features[i].feature);
267 }
268 }
269
270 return features;
271 }
272
273 static bool host_tsx_blacklisted(void)
274 {
275 int family, model, stepping;\
276 char vendor[CPUID_VENDOR_SZ + 1];
277
278 host_vendor_fms(vendor, &family, &model, &stepping);
279
280 /* Check if we are running on a Haswell host known to have broken TSX */
281 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
282 (family == 6) &&
283 ((model == 63 && stepping < 4) ||
284 model == 60 || model == 69 || model == 70);
285 }
286
287 /* Returns the value for a specific register on the cpuid entry
288 */
289 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
290 {
291 uint32_t ret = 0;
292 switch (reg) {
293 case R_EAX:
294 ret = entry->eax;
295 break;
296 case R_EBX:
297 ret = entry->ebx;
298 break;
299 case R_ECX:
300 ret = entry->ecx;
301 break;
302 case R_EDX:
303 ret = entry->edx;
304 break;
305 }
306 return ret;
307 }
308
309 /* Find matching entry for function/index on kvm_cpuid2 struct
310 */
311 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
312 uint32_t function,
313 uint32_t index)
314 {
315 int i;
316 for (i = 0; i < cpuid->nent; ++i) {
317 if (cpuid->entries[i].function == function &&
318 cpuid->entries[i].index == index) {
319 return &cpuid->entries[i];
320 }
321 }
322 /* not found: */
323 return NULL;
324 }
325
326 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
327 uint32_t index, int reg)
328 {
329 struct kvm_cpuid2 *cpuid;
330 uint32_t ret = 0;
331 uint32_t cpuid_1_edx;
332 bool found = false;
333
334 cpuid = get_supported_cpuid(s);
335
336 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
337 if (entry) {
338 found = true;
339 ret = cpuid_entry_get_reg(entry, reg);
340 }
341
342 /* Fixups for the data returned by KVM, below */
343
344 if (function == 1 && reg == R_EDX) {
345 /* KVM before 2.6.30 misreports the following features */
346 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
347 } else if (function == 1 && reg == R_ECX) {
348 /* We can set the hypervisor flag, even if KVM does not return it on
349 * GET_SUPPORTED_CPUID
350 */
351 ret |= CPUID_EXT_HYPERVISOR;
352 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
353 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
354 * and the irqchip is in the kernel.
355 */
356 if (kvm_irqchip_in_kernel() &&
357 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
358 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
359 }
360
361 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
362 * without the in-kernel irqchip
363 */
364 if (!kvm_irqchip_in_kernel()) {
365 ret &= ~CPUID_EXT_X2APIC;
366 }
367 } else if (function == 6 && reg == R_EAX) {
368 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
369 } else if (function == 7 && index == 0 && reg == R_EBX) {
370 if (host_tsx_blacklisted()) {
371 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
372 }
373 } else if (function == 0x80000001 && reg == R_EDX) {
374 /* On Intel, kvm returns cpuid according to the Intel spec,
375 * so add missing bits according to the AMD spec:
376 */
377 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
378 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
379 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
380 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
381 * be enabled without the in-kernel irqchip
382 */
383 if (!kvm_irqchip_in_kernel()) {
384 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
385 }
386 }
387
388 /* fallback for older kernels */
389 if ((function == KVM_CPUID_FEATURES) && !found) {
390 ret = get_para_features(s);
391 }
392
393 return ret;
394 }
395
396 typedef struct HWPoisonPage {
397 ram_addr_t ram_addr;
398 QLIST_ENTRY(HWPoisonPage) list;
399 } HWPoisonPage;
400
401 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
402 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
403
404 static void kvm_unpoison_all(void *param)
405 {
406 HWPoisonPage *page, *next_page;
407
408 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
409 QLIST_REMOVE(page, list);
410 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
411 g_free(page);
412 }
413 }
414
415 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
416 {
417 HWPoisonPage *page;
418
419 QLIST_FOREACH(page, &hwpoison_page_list, list) {
420 if (page->ram_addr == ram_addr) {
421 return;
422 }
423 }
424 page = g_new(HWPoisonPage, 1);
425 page->ram_addr = ram_addr;
426 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
427 }
428
429 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
430 int *max_banks)
431 {
432 int r;
433
434 r = kvm_check_extension(s, KVM_CAP_MCE);
435 if (r > 0) {
436 *max_banks = r;
437 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
438 }
439 return -ENOSYS;
440 }
441
442 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
443 {
444 CPUState *cs = CPU(cpu);
445 CPUX86State *env = &cpu->env;
446 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
447 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
448 uint64_t mcg_status = MCG_STATUS_MCIP;
449 int flags = 0;
450
451 if (code == BUS_MCEERR_AR) {
452 status |= MCI_STATUS_AR | 0x134;
453 mcg_status |= MCG_STATUS_EIPV;
454 } else {
455 status |= 0xc0;
456 mcg_status |= MCG_STATUS_RIPV;
457 }
458
459 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
460 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
461 * guest kernel back into env->mcg_ext_ctl.
462 */
463 cpu_synchronize_state(cs);
464 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
465 mcg_status |= MCG_STATUS_LMCE;
466 flags = 0;
467 }
468
469 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
470 (MCM_ADDR_PHYS << 6) | 0xc, flags);
471 }
472
473 static void hardware_memory_error(void)
474 {
475 fprintf(stderr, "Hardware memory error!\n");
476 exit(1);
477 }
478
479 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
480 {
481 X86CPU *cpu = X86_CPU(c);
482 CPUX86State *env = &cpu->env;
483 ram_addr_t ram_addr;
484 hwaddr paddr;
485
486 /* If we get an action required MCE, it has been injected by KVM
487 * while the VM was running. An action optional MCE instead should
488 * be coming from the main thread, which qemu_init_sigbus identifies
489 * as the "early kill" thread.
490 */
491 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
492
493 if ((env->mcg_cap & MCG_SER_P) && addr) {
494 ram_addr = qemu_ram_addr_from_host(addr);
495 if (ram_addr != RAM_ADDR_INVALID &&
496 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
497 kvm_hwpoison_page_add(ram_addr);
498 kvm_mce_inject(cpu, paddr, code);
499 return;
500 }
501
502 fprintf(stderr, "Hardware memory error for memory used by "
503 "QEMU itself instead of guest system!\n");
504 }
505
506 if (code == BUS_MCEERR_AR) {
507 hardware_memory_error();
508 }
509
510 /* Hope we are lucky for AO MCE */
511 }
512
513 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
514 {
515 CPUX86State *env = &cpu->env;
516
517 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
518 unsigned int bank, bank_num = env->mcg_cap & 0xff;
519 struct kvm_x86_mce mce;
520
521 env->exception_injected = -1;
522
523 /*
524 * There must be at least one bank in use if an MCE is pending.
525 * Find it and use its values for the event injection.
526 */
527 for (bank = 0; bank < bank_num; bank++) {
528 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
529 break;
530 }
531 }
532 assert(bank < bank_num);
533
534 mce.bank = bank;
535 mce.status = env->mce_banks[bank * 4 + 1];
536 mce.mcg_status = env->mcg_status;
537 mce.addr = env->mce_banks[bank * 4 + 2];
538 mce.misc = env->mce_banks[bank * 4 + 3];
539
540 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
541 }
542 return 0;
543 }
544
545 static void cpu_update_state(void *opaque, int running, RunState state)
546 {
547 CPUX86State *env = opaque;
548
549 if (running) {
550 env->tsc_valid = false;
551 }
552 }
553
554 unsigned long kvm_arch_vcpu_id(CPUState *cs)
555 {
556 X86CPU *cpu = X86_CPU(cs);
557 return cpu->apic_id;
558 }
559
560 #ifndef KVM_CPUID_SIGNATURE_NEXT
561 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
562 #endif
563
564 static bool hyperv_hypercall_available(X86CPU *cpu)
565 {
566 return cpu->hyperv_vapic ||
567 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
568 }
569
570 static bool hyperv_enabled(X86CPU *cpu)
571 {
572 CPUState *cs = CPU(cpu);
573 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
574 (hyperv_hypercall_available(cpu) ||
575 cpu->hyperv_time ||
576 cpu->hyperv_relaxed_timing ||
577 cpu->hyperv_crash ||
578 cpu->hyperv_reset ||
579 cpu->hyperv_vpindex ||
580 cpu->hyperv_runtime ||
581 cpu->hyperv_synic ||
582 cpu->hyperv_stimer);
583 }
584
585 static int kvm_arch_set_tsc_khz(CPUState *cs)
586 {
587 X86CPU *cpu = X86_CPU(cs);
588 CPUX86State *env = &cpu->env;
589 int r;
590
591 if (!env->tsc_khz) {
592 return 0;
593 }
594
595 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
596 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
597 -ENOTSUP;
598 if (r < 0) {
599 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
600 * TSC frequency doesn't match the one we want.
601 */
602 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
603 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
604 -ENOTSUP;
605 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
606 warn_report("TSC frequency mismatch between "
607 "VM (%" PRId64 " kHz) and host (%d kHz), "
608 "and TSC scaling unavailable",
609 env->tsc_khz, cur_freq);
610 return r;
611 }
612 }
613
614 return 0;
615 }
616
617 static bool tsc_is_stable_and_known(CPUX86State *env)
618 {
619 if (!env->tsc_khz) {
620 return false;
621 }
622 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
623 || env->user_tsc_khz;
624 }
625
626 static int hyperv_handle_properties(CPUState *cs)
627 {
628 X86CPU *cpu = X86_CPU(cs);
629 CPUX86State *env = &cpu->env;
630
631 if (cpu->hyperv_time &&
632 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
633 cpu->hyperv_time = false;
634 }
635
636 if (cpu->hyperv_relaxed_timing) {
637 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
638 }
639 if (cpu->hyperv_vapic) {
640 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
641 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
642 }
643 if (cpu->hyperv_time) {
644 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
645 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
646 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
647
648 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
649 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
650 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
651 }
652 }
653 if (cpu->hyperv_crash && has_msr_hv_crash) {
654 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
655 }
656 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
657 if (cpu->hyperv_reset && has_msr_hv_reset) {
658 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
659 }
660 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
661 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
662 }
663 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
664 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
665 }
666 if (cpu->hyperv_synic) {
667 if (!has_msr_hv_synic ||
668 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
669 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
670 return -ENOSYS;
671 }
672
673 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
674 }
675 if (cpu->hyperv_stimer) {
676 if (!has_msr_hv_stimer) {
677 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
678 return -ENOSYS;
679 }
680 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
681 }
682 return 0;
683 }
684
685 static Error *invtsc_mig_blocker;
686
687 #define KVM_MAX_CPUID_ENTRIES 100
688
689 int kvm_arch_init_vcpu(CPUState *cs)
690 {
691 struct {
692 struct kvm_cpuid2 cpuid;
693 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
694 } QEMU_PACKED cpuid_data;
695 X86CPU *cpu = X86_CPU(cs);
696 CPUX86State *env = &cpu->env;
697 uint32_t limit, i, j, cpuid_i;
698 uint32_t unused;
699 struct kvm_cpuid_entry2 *c;
700 uint32_t signature[3];
701 int kvm_base = KVM_CPUID_SIGNATURE;
702 int r;
703 Error *local_err = NULL;
704
705 memset(&cpuid_data, 0, sizeof(cpuid_data));
706
707 cpuid_i = 0;
708
709 r = kvm_arch_set_tsc_khz(cs);
710 if (r < 0) {
711 goto fail;
712 }
713
714 /* vcpu's TSC frequency is either specified by user, or following
715 * the value used by KVM if the former is not present. In the
716 * latter case, we query it from KVM and record in env->tsc_khz,
717 * so that vcpu's TSC frequency can be migrated later via this field.
718 */
719 if (!env->tsc_khz) {
720 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
721 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
722 -ENOTSUP;
723 if (r > 0) {
724 env->tsc_khz = r;
725 }
726 }
727
728 /* Paravirtualization CPUIDs */
729 if (hyperv_enabled(cpu)) {
730 c = &cpuid_data.entries[cpuid_i++];
731 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
732 if (!cpu->hyperv_vendor_id) {
733 memcpy(signature, "Microsoft Hv", 12);
734 } else {
735 size_t len = strlen(cpu->hyperv_vendor_id);
736
737 if (len > 12) {
738 error_report("hv-vendor-id truncated to 12 characters");
739 len = 12;
740 }
741 memset(signature, 0, 12);
742 memcpy(signature, cpu->hyperv_vendor_id, len);
743 }
744 c->eax = HV_CPUID_MIN;
745 c->ebx = signature[0];
746 c->ecx = signature[1];
747 c->edx = signature[2];
748
749 c = &cpuid_data.entries[cpuid_i++];
750 c->function = HV_CPUID_INTERFACE;
751 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
752 c->eax = signature[0];
753 c->ebx = 0;
754 c->ecx = 0;
755 c->edx = 0;
756
757 c = &cpuid_data.entries[cpuid_i++];
758 c->function = HV_CPUID_VERSION;
759 c->eax = 0x00001bbc;
760 c->ebx = 0x00060001;
761
762 c = &cpuid_data.entries[cpuid_i++];
763 c->function = HV_CPUID_FEATURES;
764 r = hyperv_handle_properties(cs);
765 if (r) {
766 return r;
767 }
768 c->eax = env->features[FEAT_HYPERV_EAX];
769 c->ebx = env->features[FEAT_HYPERV_EBX];
770 c->edx = env->features[FEAT_HYPERV_EDX];
771
772 c = &cpuid_data.entries[cpuid_i++];
773 c->function = HV_CPUID_ENLIGHTMENT_INFO;
774 if (cpu->hyperv_relaxed_timing) {
775 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
776 }
777 if (cpu->hyperv_vapic) {
778 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
779 }
780 c->ebx = cpu->hyperv_spinlock_attempts;
781
782 c = &cpuid_data.entries[cpuid_i++];
783 c->function = HV_CPUID_IMPLEMENT_LIMITS;
784
785 c->eax = cpu->hv_max_vps;
786 c->ebx = 0x40;
787
788 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
789 has_msr_hv_hypercall = true;
790 }
791
792 if (cpu->expose_kvm) {
793 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
794 c = &cpuid_data.entries[cpuid_i++];
795 c->function = KVM_CPUID_SIGNATURE | kvm_base;
796 c->eax = KVM_CPUID_FEATURES | kvm_base;
797 c->ebx = signature[0];
798 c->ecx = signature[1];
799 c->edx = signature[2];
800
801 c = &cpuid_data.entries[cpuid_i++];
802 c->function = KVM_CPUID_FEATURES | kvm_base;
803 c->eax = env->features[FEAT_KVM];
804 }
805
806 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
807
808 for (i = 0; i <= limit; i++) {
809 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
810 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
811 abort();
812 }
813 c = &cpuid_data.entries[cpuid_i++];
814 assert(cpuid_i < 100);
815
816 switch (i) {
817 case 2: {
818 /* Keep reading function 2 till all the input is received */
819 int times;
820
821 c->function = i;
822 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
823 KVM_CPUID_FLAG_STATE_READ_NEXT;
824 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
825 times = c->eax & 0xff;
826
827 for (j = 1; j < times; ++j) {
828 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
829 fprintf(stderr, "cpuid_data is full, no space for "
830 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
831 abort();
832 }
833 c = &cpuid_data.entries[cpuid_i++];
834 c->function = i;
835 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
836 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
837 }
838 break;
839 }
840 case 4:
841 case 0xb:
842 case 0xd:
843 for (j = 0; ; j++) {
844 if (i == 0xd && j == 64) {
845 break;
846 }
847 c->function = i;
848 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
849 c->index = j;
850 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
851
852 if (i == 4 && c->eax == 0) {
853 break;
854 }
855 if (i == 0xb && !(c->ecx & 0xff00)) {
856 break;
857 }
858 if (i == 0xd && c->eax == 0) {
859 continue;
860 }
861 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
862 fprintf(stderr, "cpuid_data is full, no space for "
863 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
864 abort();
865 }
866 c = &cpuid_data.entries[cpuid_i++];
867 }
868 break;
869 default:
870 c->function = i;
871 c->flags = 0;
872 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
873 break;
874 }
875 }
876
877 if (limit >= 0x0a) {
878 uint32_t eax, edx;
879
880 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
881
882 has_architectural_pmu_version = eax & 0xff;
883 if (has_architectural_pmu_version > 0) {
884 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
885
886 /* Shouldn't be more than 32, since that's the number of bits
887 * available in EBX to tell us _which_ counters are available.
888 * Play it safe.
889 */
890 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
891 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
892 }
893
894 if (has_architectural_pmu_version > 1) {
895 num_architectural_pmu_fixed_counters = edx & 0x1f;
896
897 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
898 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
899 }
900 }
901 }
902 }
903
904 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
905
906 for (i = 0x80000000; i <= limit; i++) {
907 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
908 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
909 abort();
910 }
911 c = &cpuid_data.entries[cpuid_i++];
912 assert(cpuid_i < 100);
913
914 c->function = i;
915 c->flags = 0;
916 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
917 }
918
919 /* Call Centaur's CPUID instructions they are supported. */
920 if (env->cpuid_xlevel2 > 0) {
921 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
922
923 for (i = 0xC0000000; i <= limit; i++) {
924 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
925 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
926 abort();
927 }
928 c = &cpuid_data.entries[cpuid_i++];
929
930 c->function = i;
931 c->flags = 0;
932 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
933 }
934 }
935
936 cpuid_data.cpuid.nent = cpuid_i;
937
938 if (((env->cpuid_version >> 8)&0xF) >= 6
939 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
940 (CPUID_MCE | CPUID_MCA)
941 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
942 uint64_t mcg_cap, unsupported_caps;
943 int banks;
944 int ret;
945
946 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
947 if (ret < 0) {
948 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
949 return ret;
950 }
951
952 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
953 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
954 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
955 return -ENOTSUP;
956 }
957
958 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
959 if (unsupported_caps) {
960 if (unsupported_caps & MCG_LMCE_P) {
961 error_report("kvm: LMCE not supported");
962 return -ENOTSUP;
963 }
964 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
965 unsupported_caps);
966 }
967
968 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
969 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
970 if (ret < 0) {
971 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
972 return ret;
973 }
974 }
975
976 qemu_add_vm_change_state_handler(cpu_update_state, env);
977
978 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
979 if (c) {
980 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
981 !!(c->ecx & CPUID_EXT_SMX);
982 }
983
984 if (env->mcg_cap & MCG_LMCE_P) {
985 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
986 }
987
988 if (!env->user_tsc_khz) {
989 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
990 invtsc_mig_blocker == NULL) {
991 /* for migration */
992 error_setg(&invtsc_mig_blocker,
993 "State blocked by non-migratable CPU device"
994 " (invtsc flag)");
995 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
996 if (local_err) {
997 error_report_err(local_err);
998 error_free(invtsc_mig_blocker);
999 goto fail;
1000 }
1001 /* for savevm */
1002 vmstate_x86_cpu.unmigratable = 1;
1003 }
1004 }
1005
1006 if (cpu->vmware_cpuid_freq
1007 /* Guests depend on 0x40000000 to detect this feature, so only expose
1008 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1009 && cpu->expose_kvm
1010 && kvm_base == KVM_CPUID_SIGNATURE
1011 /* TSC clock must be stable and known for this feature. */
1012 && tsc_is_stable_and_known(env)) {
1013
1014 c = &cpuid_data.entries[cpuid_i++];
1015 c->function = KVM_CPUID_SIGNATURE | 0x10;
1016 c->eax = env->tsc_khz;
1017 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1018 * APIC_BUS_CYCLE_NS */
1019 c->ebx = 1000000;
1020 c->ecx = c->edx = 0;
1021
1022 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1023 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1024 }
1025
1026 cpuid_data.cpuid.nent = cpuid_i;
1027
1028 cpuid_data.cpuid.padding = 0;
1029 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1030 if (r) {
1031 goto fail;
1032 }
1033
1034 if (has_xsave) {
1035 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1036 }
1037 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1038
1039 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1040 has_msr_tsc_aux = false;
1041 }
1042
1043 return 0;
1044
1045 fail:
1046 migrate_del_blocker(invtsc_mig_blocker);
1047 return r;
1048 }
1049
1050 void kvm_arch_reset_vcpu(X86CPU *cpu)
1051 {
1052 CPUX86State *env = &cpu->env;
1053
1054 env->xcr0 = 1;
1055 if (kvm_irqchip_in_kernel()) {
1056 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1057 KVM_MP_STATE_UNINITIALIZED;
1058 } else {
1059 env->mp_state = KVM_MP_STATE_RUNNABLE;
1060 }
1061
1062 if (cpu->hyperv_synic) {
1063 int i;
1064 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1065 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1066 }
1067 }
1068 }
1069
1070 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1071 {
1072 CPUX86State *env = &cpu->env;
1073
1074 /* APs get directly into wait-for-SIPI state. */
1075 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1076 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1077 }
1078 }
1079
1080 static int kvm_get_supported_msrs(KVMState *s)
1081 {
1082 static int kvm_supported_msrs;
1083 int ret = 0;
1084
1085 /* first time */
1086 if (kvm_supported_msrs == 0) {
1087 struct kvm_msr_list msr_list, *kvm_msr_list;
1088
1089 kvm_supported_msrs = -1;
1090
1091 /* Obtain MSR list from KVM. These are the MSRs that we must
1092 * save/restore */
1093 msr_list.nmsrs = 0;
1094 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1095 if (ret < 0 && ret != -E2BIG) {
1096 return ret;
1097 }
1098 /* Old kernel modules had a bug and could write beyond the provided
1099 memory. Allocate at least a safe amount of 1K. */
1100 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1101 msr_list.nmsrs *
1102 sizeof(msr_list.indices[0])));
1103
1104 kvm_msr_list->nmsrs = msr_list.nmsrs;
1105 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1106 if (ret >= 0) {
1107 int i;
1108
1109 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1110 switch (kvm_msr_list->indices[i]) {
1111 case MSR_STAR:
1112 has_msr_star = true;
1113 break;
1114 case MSR_VM_HSAVE_PA:
1115 has_msr_hsave_pa = true;
1116 break;
1117 case MSR_TSC_AUX:
1118 has_msr_tsc_aux = true;
1119 break;
1120 case MSR_TSC_ADJUST:
1121 has_msr_tsc_adjust = true;
1122 break;
1123 case MSR_IA32_TSCDEADLINE:
1124 has_msr_tsc_deadline = true;
1125 break;
1126 case MSR_IA32_SMBASE:
1127 has_msr_smbase = true;
1128 break;
1129 case MSR_IA32_MISC_ENABLE:
1130 has_msr_misc_enable = true;
1131 break;
1132 case MSR_IA32_BNDCFGS:
1133 has_msr_bndcfgs = true;
1134 break;
1135 case MSR_IA32_XSS:
1136 has_msr_xss = true;
1137 break;
1138 case HV_X64_MSR_CRASH_CTL:
1139 has_msr_hv_crash = true;
1140 break;
1141 case HV_X64_MSR_RESET:
1142 has_msr_hv_reset = true;
1143 break;
1144 case HV_X64_MSR_VP_INDEX:
1145 has_msr_hv_vpindex = true;
1146 break;
1147 case HV_X64_MSR_VP_RUNTIME:
1148 has_msr_hv_runtime = true;
1149 break;
1150 case HV_X64_MSR_SCONTROL:
1151 has_msr_hv_synic = true;
1152 break;
1153 case HV_X64_MSR_STIMER0_CONFIG:
1154 has_msr_hv_stimer = true;
1155 break;
1156 case HV_X64_MSR_TSC_FREQUENCY:
1157 has_msr_hv_frequencies = true;
1158 break;
1159 case MSR_IA32_SPEC_CTRL:
1160 has_msr_spec_ctrl = true;
1161 break;
1162 }
1163 }
1164 }
1165
1166 g_free(kvm_msr_list);
1167 }
1168
1169 return ret;
1170 }
1171
1172 static Notifier smram_machine_done;
1173 static KVMMemoryListener smram_listener;
1174 static AddressSpace smram_address_space;
1175 static MemoryRegion smram_as_root;
1176 static MemoryRegion smram_as_mem;
1177
1178 static void register_smram_listener(Notifier *n, void *unused)
1179 {
1180 MemoryRegion *smram =
1181 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1182
1183 /* Outer container... */
1184 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1185 memory_region_set_enabled(&smram_as_root, true);
1186
1187 /* ... with two regions inside: normal system memory with low
1188 * priority, and...
1189 */
1190 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1191 get_system_memory(), 0, ~0ull);
1192 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1193 memory_region_set_enabled(&smram_as_mem, true);
1194
1195 if (smram) {
1196 /* ... SMRAM with higher priority */
1197 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1198 memory_region_set_enabled(smram, true);
1199 }
1200
1201 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1202 kvm_memory_listener_register(kvm_state, &smram_listener,
1203 &smram_address_space, 1);
1204 }
1205
1206 int kvm_arch_init(MachineState *ms, KVMState *s)
1207 {
1208 uint64_t identity_base = 0xfffbc000;
1209 uint64_t shadow_mem;
1210 int ret;
1211 struct utsname utsname;
1212
1213 #ifdef KVM_CAP_XSAVE
1214 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1215 #endif
1216
1217 #ifdef KVM_CAP_XCRS
1218 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1219 #endif
1220
1221 #ifdef KVM_CAP_PIT_STATE2
1222 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1223 #endif
1224
1225 ret = kvm_get_supported_msrs(s);
1226 if (ret < 0) {
1227 return ret;
1228 }
1229
1230 uname(&utsname);
1231 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1232
1233 /*
1234 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1235 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1236 * Since these must be part of guest physical memory, we need to allocate
1237 * them, both by setting their start addresses in the kernel and by
1238 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1239 *
1240 * Older KVM versions may not support setting the identity map base. In
1241 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1242 * size.
1243 */
1244 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1245 /* Allows up to 16M BIOSes. */
1246 identity_base = 0xfeffc000;
1247
1248 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1249 if (ret < 0) {
1250 return ret;
1251 }
1252 }
1253
1254 /* Set TSS base one page after EPT identity map. */
1255 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1256 if (ret < 0) {
1257 return ret;
1258 }
1259
1260 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1261 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1262 if (ret < 0) {
1263 fprintf(stderr, "e820_add_entry() table is full\n");
1264 return ret;
1265 }
1266 qemu_register_reset(kvm_unpoison_all, NULL);
1267
1268 shadow_mem = machine_kvm_shadow_mem(ms);
1269 if (shadow_mem != -1) {
1270 shadow_mem /= 4096;
1271 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1272 if (ret < 0) {
1273 return ret;
1274 }
1275 }
1276
1277 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1278 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1279 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1280 smram_machine_done.notify = register_smram_listener;
1281 qemu_add_machine_init_done_notifier(&smram_machine_done);
1282 }
1283 return 0;
1284 }
1285
1286 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1287 {
1288 lhs->selector = rhs->selector;
1289 lhs->base = rhs->base;
1290 lhs->limit = rhs->limit;
1291 lhs->type = 3;
1292 lhs->present = 1;
1293 lhs->dpl = 3;
1294 lhs->db = 0;
1295 lhs->s = 1;
1296 lhs->l = 0;
1297 lhs->g = 0;
1298 lhs->avl = 0;
1299 lhs->unusable = 0;
1300 }
1301
1302 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1303 {
1304 unsigned flags = rhs->flags;
1305 lhs->selector = rhs->selector;
1306 lhs->base = rhs->base;
1307 lhs->limit = rhs->limit;
1308 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1309 lhs->present = (flags & DESC_P_MASK) != 0;
1310 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1311 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1312 lhs->s = (flags & DESC_S_MASK) != 0;
1313 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1314 lhs->g = (flags & DESC_G_MASK) != 0;
1315 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1316 lhs->unusable = !lhs->present;
1317 lhs->padding = 0;
1318 }
1319
1320 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1321 {
1322 lhs->selector = rhs->selector;
1323 lhs->base = rhs->base;
1324 lhs->limit = rhs->limit;
1325 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1326 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1327 (rhs->dpl << DESC_DPL_SHIFT) |
1328 (rhs->db << DESC_B_SHIFT) |
1329 (rhs->s * DESC_S_MASK) |
1330 (rhs->l << DESC_L_SHIFT) |
1331 (rhs->g * DESC_G_MASK) |
1332 (rhs->avl * DESC_AVL_MASK);
1333 }
1334
1335 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1336 {
1337 if (set) {
1338 *kvm_reg = *qemu_reg;
1339 } else {
1340 *qemu_reg = *kvm_reg;
1341 }
1342 }
1343
1344 static int kvm_getput_regs(X86CPU *cpu, int set)
1345 {
1346 CPUX86State *env = &cpu->env;
1347 struct kvm_regs regs;
1348 int ret = 0;
1349
1350 if (!set) {
1351 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1352 if (ret < 0) {
1353 return ret;
1354 }
1355 }
1356
1357 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1358 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1359 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1360 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1361 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1362 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1363 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1364 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1365 #ifdef TARGET_X86_64
1366 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1367 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1368 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1369 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1370 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1371 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1372 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1373 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1374 #endif
1375
1376 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1377 kvm_getput_reg(&regs.rip, &env->eip, set);
1378
1379 if (set) {
1380 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1381 }
1382
1383 return ret;
1384 }
1385
1386 static int kvm_put_fpu(X86CPU *cpu)
1387 {
1388 CPUX86State *env = &cpu->env;
1389 struct kvm_fpu fpu;
1390 int i;
1391
1392 memset(&fpu, 0, sizeof fpu);
1393 fpu.fsw = env->fpus & ~(7 << 11);
1394 fpu.fsw |= (env->fpstt & 7) << 11;
1395 fpu.fcw = env->fpuc;
1396 fpu.last_opcode = env->fpop;
1397 fpu.last_ip = env->fpip;
1398 fpu.last_dp = env->fpdp;
1399 for (i = 0; i < 8; ++i) {
1400 fpu.ftwx |= (!env->fptags[i]) << i;
1401 }
1402 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1403 for (i = 0; i < CPU_NB_REGS; i++) {
1404 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1405 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1406 }
1407 fpu.mxcsr = env->mxcsr;
1408
1409 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1410 }
1411
1412 #define XSAVE_FCW_FSW 0
1413 #define XSAVE_FTW_FOP 1
1414 #define XSAVE_CWD_RIP 2
1415 #define XSAVE_CWD_RDP 4
1416 #define XSAVE_MXCSR 6
1417 #define XSAVE_ST_SPACE 8
1418 #define XSAVE_XMM_SPACE 40
1419 #define XSAVE_XSTATE_BV 128
1420 #define XSAVE_YMMH_SPACE 144
1421 #define XSAVE_BNDREGS 240
1422 #define XSAVE_BNDCSR 256
1423 #define XSAVE_OPMASK 272
1424 #define XSAVE_ZMM_Hi256 288
1425 #define XSAVE_Hi16_ZMM 416
1426 #define XSAVE_PKRU 672
1427
1428 #define XSAVE_BYTE_OFFSET(word_offset) \
1429 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1430
1431 #define ASSERT_OFFSET(word_offset, field) \
1432 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1433 offsetof(X86XSaveArea, field))
1434
1435 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1436 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1437 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1438 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1439 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1440 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1441 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1442 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1443 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1444 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1445 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1446 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1447 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1448 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1449 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1450
1451 static int kvm_put_xsave(X86CPU *cpu)
1452 {
1453 CPUX86State *env = &cpu->env;
1454 X86XSaveArea *xsave = env->kvm_xsave_buf;
1455
1456 if (!has_xsave) {
1457 return kvm_put_fpu(cpu);
1458 }
1459 x86_cpu_xsave_all_areas(cpu, xsave);
1460
1461 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1462 }
1463
1464 static int kvm_put_xcrs(X86CPU *cpu)
1465 {
1466 CPUX86State *env = &cpu->env;
1467 struct kvm_xcrs xcrs = {};
1468
1469 if (!has_xcrs) {
1470 return 0;
1471 }
1472
1473 xcrs.nr_xcrs = 1;
1474 xcrs.flags = 0;
1475 xcrs.xcrs[0].xcr = 0;
1476 xcrs.xcrs[0].value = env->xcr0;
1477 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1478 }
1479
1480 static int kvm_put_sregs(X86CPU *cpu)
1481 {
1482 CPUX86State *env = &cpu->env;
1483 struct kvm_sregs sregs;
1484
1485 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1486 if (env->interrupt_injected >= 0) {
1487 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1488 (uint64_t)1 << (env->interrupt_injected % 64);
1489 }
1490
1491 if ((env->eflags & VM_MASK)) {
1492 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1493 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1494 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1495 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1496 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1497 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1498 } else {
1499 set_seg(&sregs.cs, &env->segs[R_CS]);
1500 set_seg(&sregs.ds, &env->segs[R_DS]);
1501 set_seg(&sregs.es, &env->segs[R_ES]);
1502 set_seg(&sregs.fs, &env->segs[R_FS]);
1503 set_seg(&sregs.gs, &env->segs[R_GS]);
1504 set_seg(&sregs.ss, &env->segs[R_SS]);
1505 }
1506
1507 set_seg(&sregs.tr, &env->tr);
1508 set_seg(&sregs.ldt, &env->ldt);
1509
1510 sregs.idt.limit = env->idt.limit;
1511 sregs.idt.base = env->idt.base;
1512 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1513 sregs.gdt.limit = env->gdt.limit;
1514 sregs.gdt.base = env->gdt.base;
1515 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1516
1517 sregs.cr0 = env->cr[0];
1518 sregs.cr2 = env->cr[2];
1519 sregs.cr3 = env->cr[3];
1520 sregs.cr4 = env->cr[4];
1521
1522 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1523 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1524
1525 sregs.efer = env->efer;
1526
1527 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1528 }
1529
1530 static void kvm_msr_buf_reset(X86CPU *cpu)
1531 {
1532 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1533 }
1534
1535 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1536 {
1537 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1538 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1539 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1540
1541 assert((void *)(entry + 1) <= limit);
1542
1543 entry->index = index;
1544 entry->reserved = 0;
1545 entry->data = value;
1546 msrs->nmsrs++;
1547 }
1548
1549 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1550 {
1551 kvm_msr_buf_reset(cpu);
1552 kvm_msr_entry_add(cpu, index, value);
1553
1554 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1555 }
1556
1557 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1558 {
1559 int ret;
1560
1561 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1562 assert(ret == 1);
1563 }
1564
1565 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1566 {
1567 CPUX86State *env = &cpu->env;
1568 int ret;
1569
1570 if (!has_msr_tsc_deadline) {
1571 return 0;
1572 }
1573
1574 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1575 if (ret < 0) {
1576 return ret;
1577 }
1578
1579 assert(ret == 1);
1580 return 0;
1581 }
1582
1583 /*
1584 * Provide a separate write service for the feature control MSR in order to
1585 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1586 * before writing any other state because forcibly leaving nested mode
1587 * invalidates the VCPU state.
1588 */
1589 static int kvm_put_msr_feature_control(X86CPU *cpu)
1590 {
1591 int ret;
1592
1593 if (!has_msr_feature_control) {
1594 return 0;
1595 }
1596
1597 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1598 cpu->env.msr_ia32_feature_control);
1599 if (ret < 0) {
1600 return ret;
1601 }
1602
1603 assert(ret == 1);
1604 return 0;
1605 }
1606
1607 static int kvm_put_msrs(X86CPU *cpu, int level)
1608 {
1609 CPUX86State *env = &cpu->env;
1610 int i;
1611 int ret;
1612
1613 kvm_msr_buf_reset(cpu);
1614
1615 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1616 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1617 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1618 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1619 if (has_msr_star) {
1620 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1621 }
1622 if (has_msr_hsave_pa) {
1623 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1624 }
1625 if (has_msr_tsc_aux) {
1626 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1627 }
1628 if (has_msr_tsc_adjust) {
1629 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1630 }
1631 if (has_msr_misc_enable) {
1632 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1633 env->msr_ia32_misc_enable);
1634 }
1635 if (has_msr_smbase) {
1636 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1637 }
1638 if (has_msr_bndcfgs) {
1639 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1640 }
1641 if (has_msr_xss) {
1642 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1643 }
1644 if (has_msr_spec_ctrl) {
1645 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1646 }
1647 #ifdef TARGET_X86_64
1648 if (lm_capable_kernel) {
1649 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1650 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1651 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1652 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1653 }
1654 #endif
1655
1656 /*
1657 * The following MSRs have side effects on the guest or are too heavy
1658 * for normal writeback. Limit them to reset or full state updates.
1659 */
1660 if (level >= KVM_PUT_RESET_STATE) {
1661 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1662 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1663 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1664 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1665 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1666 }
1667 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1668 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1669 }
1670 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1671 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1672 }
1673 if (has_architectural_pmu_version > 0) {
1674 if (has_architectural_pmu_version > 1) {
1675 /* Stop the counter. */
1676 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1677 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1678 }
1679
1680 /* Set the counter values. */
1681 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
1682 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1683 env->msr_fixed_counters[i]);
1684 }
1685 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
1686 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1687 env->msr_gp_counters[i]);
1688 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1689 env->msr_gp_evtsel[i]);
1690 }
1691 if (has_architectural_pmu_version > 1) {
1692 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1693 env->msr_global_status);
1694 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1695 env->msr_global_ovf_ctrl);
1696
1697 /* Now start the PMU. */
1698 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1699 env->msr_fixed_ctr_ctrl);
1700 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1701 env->msr_global_ctrl);
1702 }
1703 }
1704 /*
1705 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1706 * only sync them to KVM on the first cpu
1707 */
1708 if (current_cpu == first_cpu) {
1709 if (has_msr_hv_hypercall) {
1710 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1711 env->msr_hv_guest_os_id);
1712 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1713 env->msr_hv_hypercall);
1714 }
1715 if (cpu->hyperv_time) {
1716 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1717 env->msr_hv_tsc);
1718 }
1719 }
1720 if (cpu->hyperv_vapic) {
1721 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1722 env->msr_hv_vapic);
1723 }
1724 if (has_msr_hv_crash) {
1725 int j;
1726
1727 for (j = 0; j < HV_CRASH_PARAMS; j++)
1728 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1729 env->msr_hv_crash_params[j]);
1730
1731 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
1732 }
1733 if (has_msr_hv_runtime) {
1734 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1735 }
1736 if (cpu->hyperv_synic) {
1737 int j;
1738
1739 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1740
1741 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1742 env->msr_hv_synic_control);
1743 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1744 env->msr_hv_synic_evt_page);
1745 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1746 env->msr_hv_synic_msg_page);
1747
1748 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1749 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1750 env->msr_hv_synic_sint[j]);
1751 }
1752 }
1753 if (has_msr_hv_stimer) {
1754 int j;
1755
1756 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1757 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1758 env->msr_hv_stimer_config[j]);
1759 }
1760
1761 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1762 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1763 env->msr_hv_stimer_count[j]);
1764 }
1765 }
1766 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1767 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1768
1769 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1770 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1771 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1772 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1773 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1774 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1775 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1776 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1777 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1778 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1779 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1780 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1781 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1782 /* The CPU GPs if we write to a bit above the physical limit of
1783 * the host CPU (and KVM emulates that)
1784 */
1785 uint64_t mask = env->mtrr_var[i].mask;
1786 mask &= phys_mask;
1787
1788 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1789 env->mtrr_var[i].base);
1790 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1791 }
1792 }
1793
1794 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1795 * kvm_put_msr_feature_control. */
1796 }
1797 if (env->mcg_cap) {
1798 int i;
1799
1800 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1801 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1802 if (has_msr_mcg_ext_ctl) {
1803 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1804 }
1805 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1806 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1807 }
1808 }
1809
1810 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1811 if (ret < 0) {
1812 return ret;
1813 }
1814
1815 if (ret < cpu->kvm_msr_buf->nmsrs) {
1816 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1817 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1818 (uint32_t)e->index, (uint64_t)e->data);
1819 }
1820
1821 assert(ret == cpu->kvm_msr_buf->nmsrs);
1822 return 0;
1823 }
1824
1825
1826 static int kvm_get_fpu(X86CPU *cpu)
1827 {
1828 CPUX86State *env = &cpu->env;
1829 struct kvm_fpu fpu;
1830 int i, ret;
1831
1832 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1833 if (ret < 0) {
1834 return ret;
1835 }
1836
1837 env->fpstt = (fpu.fsw >> 11) & 7;
1838 env->fpus = fpu.fsw;
1839 env->fpuc = fpu.fcw;
1840 env->fpop = fpu.last_opcode;
1841 env->fpip = fpu.last_ip;
1842 env->fpdp = fpu.last_dp;
1843 for (i = 0; i < 8; ++i) {
1844 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1845 }
1846 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1847 for (i = 0; i < CPU_NB_REGS; i++) {
1848 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1849 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1850 }
1851 env->mxcsr = fpu.mxcsr;
1852
1853 return 0;
1854 }
1855
1856 static int kvm_get_xsave(X86CPU *cpu)
1857 {
1858 CPUX86State *env = &cpu->env;
1859 X86XSaveArea *xsave = env->kvm_xsave_buf;
1860 int ret;
1861
1862 if (!has_xsave) {
1863 return kvm_get_fpu(cpu);
1864 }
1865
1866 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1867 if (ret < 0) {
1868 return ret;
1869 }
1870 x86_cpu_xrstor_all_areas(cpu, xsave);
1871
1872 return 0;
1873 }
1874
1875 static int kvm_get_xcrs(X86CPU *cpu)
1876 {
1877 CPUX86State *env = &cpu->env;
1878 int i, ret;
1879 struct kvm_xcrs xcrs;
1880
1881 if (!has_xcrs) {
1882 return 0;
1883 }
1884
1885 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1886 if (ret < 0) {
1887 return ret;
1888 }
1889
1890 for (i = 0; i < xcrs.nr_xcrs; i++) {
1891 /* Only support xcr0 now */
1892 if (xcrs.xcrs[i].xcr == 0) {
1893 env->xcr0 = xcrs.xcrs[i].value;
1894 break;
1895 }
1896 }
1897 return 0;
1898 }
1899
1900 static int kvm_get_sregs(X86CPU *cpu)
1901 {
1902 CPUX86State *env = &cpu->env;
1903 struct kvm_sregs sregs;
1904 int bit, i, ret;
1905
1906 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1907 if (ret < 0) {
1908 return ret;
1909 }
1910
1911 /* There can only be one pending IRQ set in the bitmap at a time, so try
1912 to find it and save its number instead (-1 for none). */
1913 env->interrupt_injected = -1;
1914 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1915 if (sregs.interrupt_bitmap[i]) {
1916 bit = ctz64(sregs.interrupt_bitmap[i]);
1917 env->interrupt_injected = i * 64 + bit;
1918 break;
1919 }
1920 }
1921
1922 get_seg(&env->segs[R_CS], &sregs.cs);
1923 get_seg(&env->segs[R_DS], &sregs.ds);
1924 get_seg(&env->segs[R_ES], &sregs.es);
1925 get_seg(&env->segs[R_FS], &sregs.fs);
1926 get_seg(&env->segs[R_GS], &sregs.gs);
1927 get_seg(&env->segs[R_SS], &sregs.ss);
1928
1929 get_seg(&env->tr, &sregs.tr);
1930 get_seg(&env->ldt, &sregs.ldt);
1931
1932 env->idt.limit = sregs.idt.limit;
1933 env->idt.base = sregs.idt.base;
1934 env->gdt.limit = sregs.gdt.limit;
1935 env->gdt.base = sregs.gdt.base;
1936
1937 env->cr[0] = sregs.cr0;
1938 env->cr[2] = sregs.cr2;
1939 env->cr[3] = sregs.cr3;
1940 env->cr[4] = sregs.cr4;
1941
1942 env->efer = sregs.efer;
1943
1944 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1945 x86_update_hflags(env);
1946
1947 return 0;
1948 }
1949
1950 static int kvm_get_msrs(X86CPU *cpu)
1951 {
1952 CPUX86State *env = &cpu->env;
1953 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1954 int ret, i;
1955 uint64_t mtrr_top_bits;
1956
1957 kvm_msr_buf_reset(cpu);
1958
1959 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1960 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1961 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1962 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1963 if (has_msr_star) {
1964 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1965 }
1966 if (has_msr_hsave_pa) {
1967 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1968 }
1969 if (has_msr_tsc_aux) {
1970 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1971 }
1972 if (has_msr_tsc_adjust) {
1973 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
1974 }
1975 if (has_msr_tsc_deadline) {
1976 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
1977 }
1978 if (has_msr_misc_enable) {
1979 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
1980 }
1981 if (has_msr_smbase) {
1982 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
1983 }
1984 if (has_msr_feature_control) {
1985 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
1986 }
1987 if (has_msr_bndcfgs) {
1988 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
1989 }
1990 if (has_msr_xss) {
1991 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
1992 }
1993 if (has_msr_spec_ctrl) {
1994 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
1995 }
1996
1997
1998 if (!env->tsc_valid) {
1999 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2000 env->tsc_valid = !runstate_is_running();
2001 }
2002
2003 #ifdef TARGET_X86_64
2004 if (lm_capable_kernel) {
2005 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2006 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2007 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2008 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2009 }
2010 #endif
2011 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2012 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2013 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2014 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2015 }
2016 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2017 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2018 }
2019 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2020 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2021 }
2022 if (has_architectural_pmu_version > 0) {
2023 if (has_architectural_pmu_version > 1) {
2024 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2025 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2026 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2027 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2028 }
2029 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2030 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2031 }
2032 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2033 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2034 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2035 }
2036 }
2037
2038 if (env->mcg_cap) {
2039 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2040 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2041 if (has_msr_mcg_ext_ctl) {
2042 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2043 }
2044 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2045 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2046 }
2047 }
2048
2049 if (has_msr_hv_hypercall) {
2050 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2051 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2052 }
2053 if (cpu->hyperv_vapic) {
2054 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2055 }
2056 if (cpu->hyperv_time) {
2057 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2058 }
2059 if (has_msr_hv_crash) {
2060 int j;
2061
2062 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2063 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2064 }
2065 }
2066 if (has_msr_hv_runtime) {
2067 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2068 }
2069 if (cpu->hyperv_synic) {
2070 uint32_t msr;
2071
2072 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2073 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2074 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2075 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2076 kvm_msr_entry_add(cpu, msr, 0);
2077 }
2078 }
2079 if (has_msr_hv_stimer) {
2080 uint32_t msr;
2081
2082 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2083 msr++) {
2084 kvm_msr_entry_add(cpu, msr, 0);
2085 }
2086 }
2087 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2088 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2089 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2090 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2091 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2092 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2093 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2094 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2095 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2096 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2097 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2098 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2099 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2100 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2101 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2102 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2103 }
2104 }
2105
2106 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2107 if (ret < 0) {
2108 return ret;
2109 }
2110
2111 if (ret < cpu->kvm_msr_buf->nmsrs) {
2112 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2113 error_report("error: failed to get MSR 0x%" PRIx32,
2114 (uint32_t)e->index);
2115 }
2116
2117 assert(ret == cpu->kvm_msr_buf->nmsrs);
2118 /*
2119 * MTRR masks: Each mask consists of 5 parts
2120 * a 10..0: must be zero
2121 * b 11 : valid bit
2122 * c n-1.12: actual mask bits
2123 * d 51..n: reserved must be zero
2124 * e 63.52: reserved must be zero
2125 *
2126 * 'n' is the number of physical bits supported by the CPU and is
2127 * apparently always <= 52. We know our 'n' but don't know what
2128 * the destinations 'n' is; it might be smaller, in which case
2129 * it masks (c) on loading. It might be larger, in which case
2130 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2131 * we're migrating to.
2132 */
2133
2134 if (cpu->fill_mtrr_mask) {
2135 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2136 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2137 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2138 } else {
2139 mtrr_top_bits = 0;
2140 }
2141
2142 for (i = 0; i < ret; i++) {
2143 uint32_t index = msrs[i].index;
2144 switch (index) {
2145 case MSR_IA32_SYSENTER_CS:
2146 env->sysenter_cs = msrs[i].data;
2147 break;
2148 case MSR_IA32_SYSENTER_ESP:
2149 env->sysenter_esp = msrs[i].data;
2150 break;
2151 case MSR_IA32_SYSENTER_EIP:
2152 env->sysenter_eip = msrs[i].data;
2153 break;
2154 case MSR_PAT:
2155 env->pat = msrs[i].data;
2156 break;
2157 case MSR_STAR:
2158 env->star = msrs[i].data;
2159 break;
2160 #ifdef TARGET_X86_64
2161 case MSR_CSTAR:
2162 env->cstar = msrs[i].data;
2163 break;
2164 case MSR_KERNELGSBASE:
2165 env->kernelgsbase = msrs[i].data;
2166 break;
2167 case MSR_FMASK:
2168 env->fmask = msrs[i].data;
2169 break;
2170 case MSR_LSTAR:
2171 env->lstar = msrs[i].data;
2172 break;
2173 #endif
2174 case MSR_IA32_TSC:
2175 env->tsc = msrs[i].data;
2176 break;
2177 case MSR_TSC_AUX:
2178 env->tsc_aux = msrs[i].data;
2179 break;
2180 case MSR_TSC_ADJUST:
2181 env->tsc_adjust = msrs[i].data;
2182 break;
2183 case MSR_IA32_TSCDEADLINE:
2184 env->tsc_deadline = msrs[i].data;
2185 break;
2186 case MSR_VM_HSAVE_PA:
2187 env->vm_hsave = msrs[i].data;
2188 break;
2189 case MSR_KVM_SYSTEM_TIME:
2190 env->system_time_msr = msrs[i].data;
2191 break;
2192 case MSR_KVM_WALL_CLOCK:
2193 env->wall_clock_msr = msrs[i].data;
2194 break;
2195 case MSR_MCG_STATUS:
2196 env->mcg_status = msrs[i].data;
2197 break;
2198 case MSR_MCG_CTL:
2199 env->mcg_ctl = msrs[i].data;
2200 break;
2201 case MSR_MCG_EXT_CTL:
2202 env->mcg_ext_ctl = msrs[i].data;
2203 break;
2204 case MSR_IA32_MISC_ENABLE:
2205 env->msr_ia32_misc_enable = msrs[i].data;
2206 break;
2207 case MSR_IA32_SMBASE:
2208 env->smbase = msrs[i].data;
2209 break;
2210 case MSR_IA32_FEATURE_CONTROL:
2211 env->msr_ia32_feature_control = msrs[i].data;
2212 break;
2213 case MSR_IA32_BNDCFGS:
2214 env->msr_bndcfgs = msrs[i].data;
2215 break;
2216 case MSR_IA32_XSS:
2217 env->xss = msrs[i].data;
2218 break;
2219 default:
2220 if (msrs[i].index >= MSR_MC0_CTL &&
2221 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2222 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2223 }
2224 break;
2225 case MSR_KVM_ASYNC_PF_EN:
2226 env->async_pf_en_msr = msrs[i].data;
2227 break;
2228 case MSR_KVM_PV_EOI_EN:
2229 env->pv_eoi_en_msr = msrs[i].data;
2230 break;
2231 case MSR_KVM_STEAL_TIME:
2232 env->steal_time_msr = msrs[i].data;
2233 break;
2234 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2235 env->msr_fixed_ctr_ctrl = msrs[i].data;
2236 break;
2237 case MSR_CORE_PERF_GLOBAL_CTRL:
2238 env->msr_global_ctrl = msrs[i].data;
2239 break;
2240 case MSR_CORE_PERF_GLOBAL_STATUS:
2241 env->msr_global_status = msrs[i].data;
2242 break;
2243 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2244 env->msr_global_ovf_ctrl = msrs[i].data;
2245 break;
2246 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2247 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2248 break;
2249 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2250 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2251 break;
2252 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2253 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2254 break;
2255 case HV_X64_MSR_HYPERCALL:
2256 env->msr_hv_hypercall = msrs[i].data;
2257 break;
2258 case HV_X64_MSR_GUEST_OS_ID:
2259 env->msr_hv_guest_os_id = msrs[i].data;
2260 break;
2261 case HV_X64_MSR_APIC_ASSIST_PAGE:
2262 env->msr_hv_vapic = msrs[i].data;
2263 break;
2264 case HV_X64_MSR_REFERENCE_TSC:
2265 env->msr_hv_tsc = msrs[i].data;
2266 break;
2267 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2268 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2269 break;
2270 case HV_X64_MSR_VP_RUNTIME:
2271 env->msr_hv_runtime = msrs[i].data;
2272 break;
2273 case HV_X64_MSR_SCONTROL:
2274 env->msr_hv_synic_control = msrs[i].data;
2275 break;
2276 case HV_X64_MSR_SIEFP:
2277 env->msr_hv_synic_evt_page = msrs[i].data;
2278 break;
2279 case HV_X64_MSR_SIMP:
2280 env->msr_hv_synic_msg_page = msrs[i].data;
2281 break;
2282 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2283 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2284 break;
2285 case HV_X64_MSR_STIMER0_CONFIG:
2286 case HV_X64_MSR_STIMER1_CONFIG:
2287 case HV_X64_MSR_STIMER2_CONFIG:
2288 case HV_X64_MSR_STIMER3_CONFIG:
2289 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2290 msrs[i].data;
2291 break;
2292 case HV_X64_MSR_STIMER0_COUNT:
2293 case HV_X64_MSR_STIMER1_COUNT:
2294 case HV_X64_MSR_STIMER2_COUNT:
2295 case HV_X64_MSR_STIMER3_COUNT:
2296 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2297 msrs[i].data;
2298 break;
2299 case MSR_MTRRdefType:
2300 env->mtrr_deftype = msrs[i].data;
2301 break;
2302 case MSR_MTRRfix64K_00000:
2303 env->mtrr_fixed[0] = msrs[i].data;
2304 break;
2305 case MSR_MTRRfix16K_80000:
2306 env->mtrr_fixed[1] = msrs[i].data;
2307 break;
2308 case MSR_MTRRfix16K_A0000:
2309 env->mtrr_fixed[2] = msrs[i].data;
2310 break;
2311 case MSR_MTRRfix4K_C0000:
2312 env->mtrr_fixed[3] = msrs[i].data;
2313 break;
2314 case MSR_MTRRfix4K_C8000:
2315 env->mtrr_fixed[4] = msrs[i].data;
2316 break;
2317 case MSR_MTRRfix4K_D0000:
2318 env->mtrr_fixed[5] = msrs[i].data;
2319 break;
2320 case MSR_MTRRfix4K_D8000:
2321 env->mtrr_fixed[6] = msrs[i].data;
2322 break;
2323 case MSR_MTRRfix4K_E0000:
2324 env->mtrr_fixed[7] = msrs[i].data;
2325 break;
2326 case MSR_MTRRfix4K_E8000:
2327 env->mtrr_fixed[8] = msrs[i].data;
2328 break;
2329 case MSR_MTRRfix4K_F0000:
2330 env->mtrr_fixed[9] = msrs[i].data;
2331 break;
2332 case MSR_MTRRfix4K_F8000:
2333 env->mtrr_fixed[10] = msrs[i].data;
2334 break;
2335 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2336 if (index & 1) {
2337 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2338 mtrr_top_bits;
2339 } else {
2340 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2341 }
2342 break;
2343 case MSR_IA32_SPEC_CTRL:
2344 env->spec_ctrl = msrs[i].data;
2345 break;
2346 }
2347 }
2348
2349 return 0;
2350 }
2351
2352 static int kvm_put_mp_state(X86CPU *cpu)
2353 {
2354 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2355
2356 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2357 }
2358
2359 static int kvm_get_mp_state(X86CPU *cpu)
2360 {
2361 CPUState *cs = CPU(cpu);
2362 CPUX86State *env = &cpu->env;
2363 struct kvm_mp_state mp_state;
2364 int ret;
2365
2366 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2367 if (ret < 0) {
2368 return ret;
2369 }
2370 env->mp_state = mp_state.mp_state;
2371 if (kvm_irqchip_in_kernel()) {
2372 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2373 }
2374 return 0;
2375 }
2376
2377 static int kvm_get_apic(X86CPU *cpu)
2378 {
2379 DeviceState *apic = cpu->apic_state;
2380 struct kvm_lapic_state kapic;
2381 int ret;
2382
2383 if (apic && kvm_irqchip_in_kernel()) {
2384 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2385 if (ret < 0) {
2386 return ret;
2387 }
2388
2389 kvm_get_apic_state(apic, &kapic);
2390 }
2391 return 0;
2392 }
2393
2394 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2395 {
2396 CPUState *cs = CPU(cpu);
2397 CPUX86State *env = &cpu->env;
2398 struct kvm_vcpu_events events = {};
2399
2400 if (!kvm_has_vcpu_events()) {
2401 return 0;
2402 }
2403
2404 events.exception.injected = (env->exception_injected >= 0);
2405 events.exception.nr = env->exception_injected;
2406 events.exception.has_error_code = env->has_error_code;
2407 events.exception.error_code = env->error_code;
2408 events.exception.pad = 0;
2409
2410 events.interrupt.injected = (env->interrupt_injected >= 0);
2411 events.interrupt.nr = env->interrupt_injected;
2412 events.interrupt.soft = env->soft_interrupt;
2413
2414 events.nmi.injected = env->nmi_injected;
2415 events.nmi.pending = env->nmi_pending;
2416 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2417 events.nmi.pad = 0;
2418
2419 events.sipi_vector = env->sipi_vector;
2420 events.flags = 0;
2421
2422 if (has_msr_smbase) {
2423 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2424 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2425 if (kvm_irqchip_in_kernel()) {
2426 /* As soon as these are moved to the kernel, remove them
2427 * from cs->interrupt_request.
2428 */
2429 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2430 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2431 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2432 } else {
2433 /* Keep these in cs->interrupt_request. */
2434 events.smi.pending = 0;
2435 events.smi.latched_init = 0;
2436 }
2437 /* Stop SMI delivery on old machine types to avoid a reboot
2438 * on an inward migration of an old VM.
2439 */
2440 if (!cpu->kvm_no_smi_migration) {
2441 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2442 }
2443 }
2444
2445 if (level >= KVM_PUT_RESET_STATE) {
2446 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2447 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2448 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2449 }
2450 }
2451
2452 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2453 }
2454
2455 static int kvm_get_vcpu_events(X86CPU *cpu)
2456 {
2457 CPUX86State *env = &cpu->env;
2458 struct kvm_vcpu_events events;
2459 int ret;
2460
2461 if (!kvm_has_vcpu_events()) {
2462 return 0;
2463 }
2464
2465 memset(&events, 0, sizeof(events));
2466 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2467 if (ret < 0) {
2468 return ret;
2469 }
2470 env->exception_injected =
2471 events.exception.injected ? events.exception.nr : -1;
2472 env->has_error_code = events.exception.has_error_code;
2473 env->error_code = events.exception.error_code;
2474
2475 env->interrupt_injected =
2476 events.interrupt.injected ? events.interrupt.nr : -1;
2477 env->soft_interrupt = events.interrupt.soft;
2478
2479 env->nmi_injected = events.nmi.injected;
2480 env->nmi_pending = events.nmi.pending;
2481 if (events.nmi.masked) {
2482 env->hflags2 |= HF2_NMI_MASK;
2483 } else {
2484 env->hflags2 &= ~HF2_NMI_MASK;
2485 }
2486
2487 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2488 if (events.smi.smm) {
2489 env->hflags |= HF_SMM_MASK;
2490 } else {
2491 env->hflags &= ~HF_SMM_MASK;
2492 }
2493 if (events.smi.pending) {
2494 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2495 } else {
2496 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2497 }
2498 if (events.smi.smm_inside_nmi) {
2499 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2500 } else {
2501 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2502 }
2503 if (events.smi.latched_init) {
2504 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2505 } else {
2506 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2507 }
2508 }
2509
2510 env->sipi_vector = events.sipi_vector;
2511
2512 return 0;
2513 }
2514
2515 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2516 {
2517 CPUState *cs = CPU(cpu);
2518 CPUX86State *env = &cpu->env;
2519 int ret = 0;
2520 unsigned long reinject_trap = 0;
2521
2522 if (!kvm_has_vcpu_events()) {
2523 if (env->exception_injected == 1) {
2524 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2525 } else if (env->exception_injected == 3) {
2526 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2527 }
2528 env->exception_injected = -1;
2529 }
2530
2531 /*
2532 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2533 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2534 * by updating the debug state once again if single-stepping is on.
2535 * Another reason to call kvm_update_guest_debug here is a pending debug
2536 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2537 * reinject them via SET_GUEST_DEBUG.
2538 */
2539 if (reinject_trap ||
2540 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2541 ret = kvm_update_guest_debug(cs, reinject_trap);
2542 }
2543 return ret;
2544 }
2545
2546 static int kvm_put_debugregs(X86CPU *cpu)
2547 {
2548 CPUX86State *env = &cpu->env;
2549 struct kvm_debugregs dbgregs;
2550 int i;
2551
2552 if (!kvm_has_debugregs()) {
2553 return 0;
2554 }
2555
2556 for (i = 0; i < 4; i++) {
2557 dbgregs.db[i] = env->dr[i];
2558 }
2559 dbgregs.dr6 = env->dr[6];
2560 dbgregs.dr7 = env->dr[7];
2561 dbgregs.flags = 0;
2562
2563 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2564 }
2565
2566 static int kvm_get_debugregs(X86CPU *cpu)
2567 {
2568 CPUX86State *env = &cpu->env;
2569 struct kvm_debugregs dbgregs;
2570 int i, ret;
2571
2572 if (!kvm_has_debugregs()) {
2573 return 0;
2574 }
2575
2576 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2577 if (ret < 0) {
2578 return ret;
2579 }
2580 for (i = 0; i < 4; i++) {
2581 env->dr[i] = dbgregs.db[i];
2582 }
2583 env->dr[4] = env->dr[6] = dbgregs.dr6;
2584 env->dr[5] = env->dr[7] = dbgregs.dr7;
2585
2586 return 0;
2587 }
2588
2589 int kvm_arch_put_registers(CPUState *cpu, int level)
2590 {
2591 X86CPU *x86_cpu = X86_CPU(cpu);
2592 int ret;
2593
2594 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2595
2596 if (level >= KVM_PUT_RESET_STATE) {
2597 ret = kvm_put_msr_feature_control(x86_cpu);
2598 if (ret < 0) {
2599 return ret;
2600 }
2601 }
2602
2603 if (level == KVM_PUT_FULL_STATE) {
2604 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2605 * because TSC frequency mismatch shouldn't abort migration,
2606 * unless the user explicitly asked for a more strict TSC
2607 * setting (e.g. using an explicit "tsc-freq" option).
2608 */
2609 kvm_arch_set_tsc_khz(cpu);
2610 }
2611
2612 ret = kvm_getput_regs(x86_cpu, 1);
2613 if (ret < 0) {
2614 return ret;
2615 }
2616 ret = kvm_put_xsave(x86_cpu);
2617 if (ret < 0) {
2618 return ret;
2619 }
2620 ret = kvm_put_xcrs(x86_cpu);
2621 if (ret < 0) {
2622 return ret;
2623 }
2624 ret = kvm_put_sregs(x86_cpu);
2625 if (ret < 0) {
2626 return ret;
2627 }
2628 /* must be before kvm_put_msrs */
2629 ret = kvm_inject_mce_oldstyle(x86_cpu);
2630 if (ret < 0) {
2631 return ret;
2632 }
2633 ret = kvm_put_msrs(x86_cpu, level);
2634 if (ret < 0) {
2635 return ret;
2636 }
2637 ret = kvm_put_vcpu_events(x86_cpu, level);
2638 if (ret < 0) {
2639 return ret;
2640 }
2641 if (level >= KVM_PUT_RESET_STATE) {
2642 ret = kvm_put_mp_state(x86_cpu);
2643 if (ret < 0) {
2644 return ret;
2645 }
2646 }
2647
2648 ret = kvm_put_tscdeadline_msr(x86_cpu);
2649 if (ret < 0) {
2650 return ret;
2651 }
2652 ret = kvm_put_debugregs(x86_cpu);
2653 if (ret < 0) {
2654 return ret;
2655 }
2656 /* must be last */
2657 ret = kvm_guest_debug_workarounds(x86_cpu);
2658 if (ret < 0) {
2659 return ret;
2660 }
2661 return 0;
2662 }
2663
2664 int kvm_arch_get_registers(CPUState *cs)
2665 {
2666 X86CPU *cpu = X86_CPU(cs);
2667 int ret;
2668
2669 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2670
2671 ret = kvm_get_vcpu_events(cpu);
2672 if (ret < 0) {
2673 goto out;
2674 }
2675 /*
2676 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2677 * KVM_GET_REGS and KVM_GET_SREGS.
2678 */
2679 ret = kvm_get_mp_state(cpu);
2680 if (ret < 0) {
2681 goto out;
2682 }
2683 ret = kvm_getput_regs(cpu, 0);
2684 if (ret < 0) {
2685 goto out;
2686 }
2687 ret = kvm_get_xsave(cpu);
2688 if (ret < 0) {
2689 goto out;
2690 }
2691 ret = kvm_get_xcrs(cpu);
2692 if (ret < 0) {
2693 goto out;
2694 }
2695 ret = kvm_get_sregs(cpu);
2696 if (ret < 0) {
2697 goto out;
2698 }
2699 ret = kvm_get_msrs(cpu);
2700 if (ret < 0) {
2701 goto out;
2702 }
2703 ret = kvm_get_apic(cpu);
2704 if (ret < 0) {
2705 goto out;
2706 }
2707 ret = kvm_get_debugregs(cpu);
2708 if (ret < 0) {
2709 goto out;
2710 }
2711 ret = 0;
2712 out:
2713 cpu_sync_bndcs_hflags(&cpu->env);
2714 return ret;
2715 }
2716
2717 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2718 {
2719 X86CPU *x86_cpu = X86_CPU(cpu);
2720 CPUX86State *env = &x86_cpu->env;
2721 int ret;
2722
2723 /* Inject NMI */
2724 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2725 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2726 qemu_mutex_lock_iothread();
2727 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2728 qemu_mutex_unlock_iothread();
2729 DPRINTF("injected NMI\n");
2730 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2731 if (ret < 0) {
2732 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2733 strerror(-ret));
2734 }
2735 }
2736 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2737 qemu_mutex_lock_iothread();
2738 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2739 qemu_mutex_unlock_iothread();
2740 DPRINTF("injected SMI\n");
2741 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2742 if (ret < 0) {
2743 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2744 strerror(-ret));
2745 }
2746 }
2747 }
2748
2749 if (!kvm_pic_in_kernel()) {
2750 qemu_mutex_lock_iothread();
2751 }
2752
2753 /* Force the VCPU out of its inner loop to process any INIT requests
2754 * or (for userspace APIC, but it is cheap to combine the checks here)
2755 * pending TPR access reports.
2756 */
2757 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2758 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2759 !(env->hflags & HF_SMM_MASK)) {
2760 cpu->exit_request = 1;
2761 }
2762 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2763 cpu->exit_request = 1;
2764 }
2765 }
2766
2767 if (!kvm_pic_in_kernel()) {
2768 /* Try to inject an interrupt if the guest can accept it */
2769 if (run->ready_for_interrupt_injection &&
2770 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2771 (env->eflags & IF_MASK)) {
2772 int irq;
2773
2774 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2775 irq = cpu_get_pic_interrupt(env);
2776 if (irq >= 0) {
2777 struct kvm_interrupt intr;
2778
2779 intr.irq = irq;
2780 DPRINTF("injected interrupt %d\n", irq);
2781 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2782 if (ret < 0) {
2783 fprintf(stderr,
2784 "KVM: injection failed, interrupt lost (%s)\n",
2785 strerror(-ret));
2786 }
2787 }
2788 }
2789
2790 /* If we have an interrupt but the guest is not ready to receive an
2791 * interrupt, request an interrupt window exit. This will
2792 * cause a return to userspace as soon as the guest is ready to
2793 * receive interrupts. */
2794 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2795 run->request_interrupt_window = 1;
2796 } else {
2797 run->request_interrupt_window = 0;
2798 }
2799
2800 DPRINTF("setting tpr\n");
2801 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2802
2803 qemu_mutex_unlock_iothread();
2804 }
2805 }
2806
2807 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2808 {
2809 X86CPU *x86_cpu = X86_CPU(cpu);
2810 CPUX86State *env = &x86_cpu->env;
2811
2812 if (run->flags & KVM_RUN_X86_SMM) {
2813 env->hflags |= HF_SMM_MASK;
2814 } else {
2815 env->hflags &= ~HF_SMM_MASK;
2816 }
2817 if (run->if_flag) {
2818 env->eflags |= IF_MASK;
2819 } else {
2820 env->eflags &= ~IF_MASK;
2821 }
2822
2823 /* We need to protect the apic state against concurrent accesses from
2824 * different threads in case the userspace irqchip is used. */
2825 if (!kvm_irqchip_in_kernel()) {
2826 qemu_mutex_lock_iothread();
2827 }
2828 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2829 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2830 if (!kvm_irqchip_in_kernel()) {
2831 qemu_mutex_unlock_iothread();
2832 }
2833 return cpu_get_mem_attrs(env);
2834 }
2835
2836 int kvm_arch_process_async_events(CPUState *cs)
2837 {
2838 X86CPU *cpu = X86_CPU(cs);
2839 CPUX86State *env = &cpu->env;
2840
2841 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2842 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2843 assert(env->mcg_cap);
2844
2845 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2846
2847 kvm_cpu_synchronize_state(cs);
2848
2849 if (env->exception_injected == EXCP08_DBLE) {
2850 /* this means triple fault */
2851 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
2852 cs->exit_request = 1;
2853 return 0;
2854 }
2855 env->exception_injected = EXCP12_MCHK;
2856 env->has_error_code = 0;
2857
2858 cs->halted = 0;
2859 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2860 env->mp_state = KVM_MP_STATE_RUNNABLE;
2861 }
2862 }
2863
2864 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2865 !(env->hflags & HF_SMM_MASK)) {
2866 kvm_cpu_synchronize_state(cs);
2867 do_cpu_init(cpu);
2868 }
2869
2870 if (kvm_irqchip_in_kernel()) {
2871 return 0;
2872 }
2873
2874 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2875 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2876 apic_poll_irq(cpu->apic_state);
2877 }
2878 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2879 (env->eflags & IF_MASK)) ||
2880 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2881 cs->halted = 0;
2882 }
2883 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2884 kvm_cpu_synchronize_state(cs);
2885 do_cpu_sipi(cpu);
2886 }
2887 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2888 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2889 kvm_cpu_synchronize_state(cs);
2890 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2891 env->tpr_access_type);
2892 }
2893
2894 return cs->halted;
2895 }
2896
2897 static int kvm_handle_halt(X86CPU *cpu)
2898 {
2899 CPUState *cs = CPU(cpu);
2900 CPUX86State *env = &cpu->env;
2901
2902 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2903 (env->eflags & IF_MASK)) &&
2904 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2905 cs->halted = 1;
2906 return EXCP_HLT;
2907 }
2908
2909 return 0;
2910 }
2911
2912 static int kvm_handle_tpr_access(X86CPU *cpu)
2913 {
2914 CPUState *cs = CPU(cpu);
2915 struct kvm_run *run = cs->kvm_run;
2916
2917 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2918 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2919 : TPR_ACCESS_READ);
2920 return 1;
2921 }
2922
2923 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2924 {
2925 static const uint8_t int3 = 0xcc;
2926
2927 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2928 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2929 return -EINVAL;
2930 }
2931 return 0;
2932 }
2933
2934 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2935 {
2936 uint8_t int3;
2937
2938 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2939 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2940 return -EINVAL;
2941 }
2942 return 0;
2943 }
2944
2945 static struct {
2946 target_ulong addr;
2947 int len;
2948 int type;
2949 } hw_breakpoint[4];
2950
2951 static int nb_hw_breakpoint;
2952
2953 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2954 {
2955 int n;
2956
2957 for (n = 0; n < nb_hw_breakpoint; n++) {
2958 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2959 (hw_breakpoint[n].len == len || len == -1)) {
2960 return n;
2961 }
2962 }
2963 return -1;
2964 }
2965
2966 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2967 target_ulong len, int type)
2968 {
2969 switch (type) {
2970 case GDB_BREAKPOINT_HW:
2971 len = 1;
2972 break;
2973 case GDB_WATCHPOINT_WRITE:
2974 case GDB_WATCHPOINT_ACCESS:
2975 switch (len) {
2976 case 1:
2977 break;
2978 case 2:
2979 case 4:
2980 case 8:
2981 if (addr & (len - 1)) {
2982 return -EINVAL;
2983 }
2984 break;
2985 default:
2986 return -EINVAL;
2987 }
2988 break;
2989 default:
2990 return -ENOSYS;
2991 }
2992
2993 if (nb_hw_breakpoint == 4) {
2994 return -ENOBUFS;
2995 }
2996 if (find_hw_breakpoint(addr, len, type) >= 0) {
2997 return -EEXIST;
2998 }
2999 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3000 hw_breakpoint[nb_hw_breakpoint].len = len;
3001 hw_breakpoint[nb_hw_breakpoint].type = type;
3002 nb_hw_breakpoint++;
3003
3004 return 0;
3005 }
3006
3007 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3008 target_ulong len, int type)
3009 {
3010 int n;
3011
3012 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3013 if (n < 0) {
3014 return -ENOENT;
3015 }
3016 nb_hw_breakpoint--;
3017 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3018
3019 return 0;
3020 }
3021
3022 void kvm_arch_remove_all_hw_breakpoints(void)
3023 {
3024 nb_hw_breakpoint = 0;
3025 }
3026
3027 static CPUWatchpoint hw_watchpoint;
3028
3029 static int kvm_handle_debug(X86CPU *cpu,
3030 struct kvm_debug_exit_arch *arch_info)
3031 {
3032 CPUState *cs = CPU(cpu);
3033 CPUX86State *env = &cpu->env;
3034 int ret = 0;
3035 int n;
3036
3037 if (arch_info->exception == 1) {
3038 if (arch_info->dr6 & (1 << 14)) {
3039 if (cs->singlestep_enabled) {
3040 ret = EXCP_DEBUG;
3041 }
3042 } else {
3043 for (n = 0; n < 4; n++) {
3044 if (arch_info->dr6 & (1 << n)) {
3045 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3046 case 0x0:
3047 ret = EXCP_DEBUG;
3048 break;
3049 case 0x1:
3050 ret = EXCP_DEBUG;
3051 cs->watchpoint_hit = &hw_watchpoint;
3052 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3053 hw_watchpoint.flags = BP_MEM_WRITE;
3054 break;
3055 case 0x3:
3056 ret = EXCP_DEBUG;
3057 cs->watchpoint_hit = &hw_watchpoint;
3058 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3059 hw_watchpoint.flags = BP_MEM_ACCESS;
3060 break;
3061 }
3062 }
3063 }
3064 }
3065 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3066 ret = EXCP_DEBUG;
3067 }
3068 if (ret == 0) {
3069 cpu_synchronize_state(cs);
3070 assert(env->exception_injected == -1);
3071
3072 /* pass to guest */
3073 env->exception_injected = arch_info->exception;
3074 env->has_error_code = 0;
3075 }
3076
3077 return ret;
3078 }
3079
3080 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3081 {
3082 const uint8_t type_code[] = {
3083 [GDB_BREAKPOINT_HW] = 0x0,
3084 [GDB_WATCHPOINT_WRITE] = 0x1,
3085 [GDB_WATCHPOINT_ACCESS] = 0x3
3086 };
3087 const uint8_t len_code[] = {
3088 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3089 };
3090 int n;
3091
3092 if (kvm_sw_breakpoints_active(cpu)) {
3093 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3094 }
3095 if (nb_hw_breakpoint > 0) {
3096 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3097 dbg->arch.debugreg[7] = 0x0600;
3098 for (n = 0; n < nb_hw_breakpoint; n++) {
3099 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3100 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3101 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3102 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3103 }
3104 }
3105 }
3106
3107 static bool host_supports_vmx(void)
3108 {
3109 uint32_t ecx, unused;
3110
3111 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3112 return ecx & CPUID_EXT_VMX;
3113 }
3114
3115 #define VMX_INVALID_GUEST_STATE 0x80000021
3116
3117 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3118 {
3119 X86CPU *cpu = X86_CPU(cs);
3120 uint64_t code;
3121 int ret;
3122
3123 switch (run->exit_reason) {
3124 case KVM_EXIT_HLT:
3125 DPRINTF("handle_hlt\n");
3126 qemu_mutex_lock_iothread();
3127 ret = kvm_handle_halt(cpu);
3128 qemu_mutex_unlock_iothread();
3129 break;
3130 case KVM_EXIT_SET_TPR:
3131 ret = 0;
3132 break;
3133 case KVM_EXIT_TPR_ACCESS:
3134 qemu_mutex_lock_iothread();
3135 ret = kvm_handle_tpr_access(cpu);
3136 qemu_mutex_unlock_iothread();
3137 break;
3138 case KVM_EXIT_FAIL_ENTRY:
3139 code = run->fail_entry.hardware_entry_failure_reason;
3140 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3141 code);
3142 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3143 fprintf(stderr,
3144 "\nIf you're running a guest on an Intel machine without "
3145 "unrestricted mode\n"
3146 "support, the failure can be most likely due to the guest "
3147 "entering an invalid\n"
3148 "state for Intel VT. For example, the guest maybe running "
3149 "in big real mode\n"
3150 "which is not supported on less recent Intel processors."
3151 "\n\n");
3152 }
3153 ret = -1;
3154 break;
3155 case KVM_EXIT_EXCEPTION:
3156 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3157 run->ex.exception, run->ex.error_code);
3158 ret = -1;
3159 break;
3160 case KVM_EXIT_DEBUG:
3161 DPRINTF("kvm_exit_debug\n");
3162 qemu_mutex_lock_iothread();
3163 ret = kvm_handle_debug(cpu, &run->debug.arch);
3164 qemu_mutex_unlock_iothread();
3165 break;
3166 case KVM_EXIT_HYPERV:
3167 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3168 break;
3169 case KVM_EXIT_IOAPIC_EOI:
3170 ioapic_eoi_broadcast(run->eoi.vector);
3171 ret = 0;
3172 break;
3173 default:
3174 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3175 ret = -1;
3176 break;
3177 }
3178
3179 return ret;
3180 }
3181
3182 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3183 {
3184 X86CPU *cpu = X86_CPU(cs);
3185 CPUX86State *env = &cpu->env;
3186
3187 kvm_cpu_synchronize_state(cs);
3188 return !(env->cr[0] & CR0_PE_MASK) ||
3189 ((env->segs[R_CS].selector & 3) != 3);
3190 }
3191
3192 void kvm_arch_init_irq_routing(KVMState *s)
3193 {
3194 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3195 /* If kernel can't do irq routing, interrupt source
3196 * override 0->2 cannot be set up as required by HPET.
3197 * So we have to disable it.
3198 */
3199 no_hpet = 1;
3200 }
3201 /* We know at this point that we're using the in-kernel
3202 * irqchip, so we can use irqfds, and on x86 we know
3203 * we can use msi via irqfd and GSI routing.
3204 */
3205 kvm_msi_via_irqfd_allowed = true;
3206 kvm_gsi_routing_allowed = true;
3207
3208 if (kvm_irqchip_is_split()) {
3209 int i;
3210
3211 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3212 MSI routes for signaling interrupts to the local apics. */
3213 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3214 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3215 error_report("Could not enable split IRQ mode.");
3216 exit(1);
3217 }
3218 }
3219 }
3220 }
3221
3222 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3223 {
3224 int ret;
3225 if (machine_kernel_irqchip_split(ms)) {
3226 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3227 if (ret) {
3228 error_report("Could not enable split irqchip mode: %s",
3229 strerror(-ret));
3230 exit(1);
3231 } else {
3232 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3233 kvm_split_irqchip = true;
3234 return 1;
3235 }
3236 } else {
3237 return 0;
3238 }
3239 }
3240
3241 /* Classic KVM device assignment interface. Will remain x86 only. */
3242 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3243 uint32_t flags, uint32_t *dev_id)
3244 {
3245 struct kvm_assigned_pci_dev dev_data = {
3246 .segnr = dev_addr->domain,
3247 .busnr = dev_addr->bus,
3248 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3249 .flags = flags,
3250 };
3251 int ret;
3252
3253 dev_data.assigned_dev_id =
3254 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3255
3256 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3257 if (ret < 0) {
3258 return ret;
3259 }
3260
3261 *dev_id = dev_data.assigned_dev_id;
3262
3263 return 0;
3264 }
3265
3266 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3267 {
3268 struct kvm_assigned_pci_dev dev_data = {
3269 .assigned_dev_id = dev_id,
3270 };
3271
3272 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3273 }
3274
3275 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3276 uint32_t irq_type, uint32_t guest_irq)
3277 {
3278 struct kvm_assigned_irq assigned_irq = {
3279 .assigned_dev_id = dev_id,
3280 .guest_irq = guest_irq,
3281 .flags = irq_type,
3282 };
3283
3284 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3285 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3286 } else {
3287 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3288 }
3289 }
3290
3291 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3292 uint32_t guest_irq)
3293 {
3294 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3295 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3296
3297 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3298 }
3299
3300 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3301 {
3302 struct kvm_assigned_pci_dev dev_data = {
3303 .assigned_dev_id = dev_id,
3304 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3305 };
3306
3307 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3308 }
3309
3310 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3311 uint32_t type)
3312 {
3313 struct kvm_assigned_irq assigned_irq = {
3314 .assigned_dev_id = dev_id,
3315 .flags = type,
3316 };
3317
3318 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3319 }
3320
3321 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3322 {
3323 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3324 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3325 }
3326
3327 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3328 {
3329 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3330 KVM_DEV_IRQ_GUEST_MSI, virq);
3331 }
3332
3333 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3334 {
3335 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3336 KVM_DEV_IRQ_HOST_MSI);
3337 }
3338
3339 bool kvm_device_msix_supported(KVMState *s)
3340 {
3341 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3342 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3343 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3344 }
3345
3346 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3347 uint32_t nr_vectors)
3348 {
3349 struct kvm_assigned_msix_nr msix_nr = {
3350 .assigned_dev_id = dev_id,
3351 .entry_nr = nr_vectors,
3352 };
3353
3354 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3355 }
3356
3357 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3358 int virq)
3359 {
3360 struct kvm_assigned_msix_entry msix_entry = {
3361 .assigned_dev_id = dev_id,
3362 .gsi = virq,
3363 .entry = vector,
3364 };
3365
3366 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3367 }
3368
3369 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3370 {
3371 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3372 KVM_DEV_IRQ_GUEST_MSIX, 0);
3373 }
3374
3375 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3376 {
3377 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3378 KVM_DEV_IRQ_HOST_MSIX);
3379 }
3380
3381 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3382 uint64_t address, uint32_t data, PCIDevice *dev)
3383 {
3384 X86IOMMUState *iommu = x86_iommu_get_default();
3385
3386 if (iommu) {
3387 int ret;
3388 MSIMessage src, dst;
3389 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3390
3391 src.address = route->u.msi.address_hi;
3392 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3393 src.address |= route->u.msi.address_lo;
3394 src.data = route->u.msi.data;
3395
3396 ret = class->int_remap(iommu, &src, &dst, dev ? \
3397 pci_requester_id(dev) : \
3398 X86_IOMMU_SID_INVALID);
3399 if (ret) {
3400 trace_kvm_x86_fixup_msi_error(route->gsi);
3401 return 1;
3402 }
3403
3404 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3405 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3406 route->u.msi.data = dst.data;
3407 }
3408
3409 return 0;
3410 }
3411
3412 typedef struct MSIRouteEntry MSIRouteEntry;
3413
3414 struct MSIRouteEntry {
3415 PCIDevice *dev; /* Device pointer */
3416 int vector; /* MSI/MSIX vector index */
3417 int virq; /* Virtual IRQ index */
3418 QLIST_ENTRY(MSIRouteEntry) list;
3419 };
3420
3421 /* List of used GSI routes */
3422 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3423 QLIST_HEAD_INITIALIZER(msi_route_list);
3424
3425 static void kvm_update_msi_routes_all(void *private, bool global,
3426 uint32_t index, uint32_t mask)
3427 {
3428 int cnt = 0;
3429 MSIRouteEntry *entry;
3430 MSIMessage msg;
3431 PCIDevice *dev;
3432
3433 /* TODO: explicit route update */
3434 QLIST_FOREACH(entry, &msi_route_list, list) {
3435 cnt++;
3436 dev = entry->dev;
3437 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3438 continue;
3439 }
3440 msg = pci_get_msi_message(dev, entry->vector);
3441 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3442 }
3443 kvm_irqchip_commit_routes(kvm_state);
3444 trace_kvm_x86_update_msi_routes(cnt);
3445 }
3446
3447 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3448 int vector, PCIDevice *dev)
3449 {
3450 static bool notify_list_inited = false;
3451 MSIRouteEntry *entry;
3452
3453 if (!dev) {
3454 /* These are (possibly) IOAPIC routes only used for split
3455 * kernel irqchip mode, while what we are housekeeping are
3456 * PCI devices only. */
3457 return 0;
3458 }
3459
3460 entry = g_new0(MSIRouteEntry, 1);
3461 entry->dev = dev;
3462 entry->vector = vector;
3463 entry->virq = route->gsi;
3464 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3465
3466 trace_kvm_x86_add_msi_route(route->gsi);
3467
3468 if (!notify_list_inited) {
3469 /* For the first time we do add route, add ourselves into
3470 * IOMMU's IEC notify list if needed. */
3471 X86IOMMUState *iommu = x86_iommu_get_default();
3472 if (iommu) {
3473 x86_iommu_iec_register_notifier(iommu,
3474 kvm_update_msi_routes_all,
3475 NULL);
3476 }
3477 notify_list_inited = true;
3478 }
3479 return 0;
3480 }
3481
3482 int kvm_arch_release_virq_post(int virq)
3483 {
3484 MSIRouteEntry *entry, *next;
3485 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3486 if (entry->virq == virq) {
3487 trace_kvm_x86_remove_msi_route(virq);
3488 QLIST_REMOVE(entry, list);
3489 g_free(entry);
3490 break;
3491 }
3492 }
3493 return 0;
3494 }
3495
3496 int kvm_arch_msi_data_to_gsi(uint32_t data)
3497 {
3498 abort();
3499 }
AR7 emulation for QEMU