target-microblaze/op_helper.c

   1 /*
   2  *  Microblaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23 #include "qemu/host-utils.h"
  24 #include "exec/cpu_ldst.h"
  25
  26 #define D(x)
  27
  28 #if !defined(CONFIG_USER_ONLY)
  29
  30 /* Try to fill the TLB and return an exception if error. If retaddr is
  31  * NULL, it means that the function was called in C code (i.e. not
  32  * from generated code or from helper.c)
  33  */
  34 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  35               uintptr_t retaddr)
  36 {
  37     int ret;
  38
  39     ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
  40     if (unlikely(ret)) {
  41         if (retaddr) {
  42             /* now we have a real cpu fault */
  43             cpu_restore_state(cs, retaddr);
  44         }
  45         cpu_loop_exit(cs);
  46     }
  47 }
  48 #endif
  49
  50 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
  51 {
  52     int test = ctrl & STREAM_TEST;
  53     int atomic = ctrl & STREAM_ATOMIC;
  54     int control = ctrl & STREAM_CONTROL;
  55     int nonblock = ctrl & STREAM_NONBLOCK;
  56     int exception = ctrl & STREAM_EXCEPTION;
  57
  58     qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
  59              id, data,
  60              test ? "t" : "",
  61              nonblock ? "n" : "",
  62              exception ? "e" : "",
  63              control ? "c" : "",
  64              atomic ? "a" : "");
  65 }
  66
  67 uint32_t helper_get(uint32_t id, uint32_t ctrl)
  68 {
  69     int test = ctrl & STREAM_TEST;
  70     int atomic = ctrl & STREAM_ATOMIC;
  71     int control = ctrl & STREAM_CONTROL;
  72     int nonblock = ctrl & STREAM_NONBLOCK;
  73     int exception = ctrl & STREAM_EXCEPTION;
  74
  75     qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
  76              id,
  77              test ? "t" : "",
  78              nonblock ? "n" : "",
  79              exception ? "e" : "",
  80              control ? "c" : "",
  81              atomic ? "a" : "");
  82     return 0xdead0000 | id;
  83 }
  84
  85 void helper_raise_exception(CPUMBState *env, uint32_t index)
  86 {
  87     CPUState *cs = CPU(mb_env_get_cpu(env));
  88
  89     cs->exception_index = index;
  90     cpu_loop_exit(cs);
  91 }
  92
  93 void helper_debug(CPUMBState *env)
  94 {
  95     int i;
  96
  97     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
  98     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
  99              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
 100              env->debug, env->imm, env->iflags);
 101     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
 102              env->btaken, env->btarget,
 103              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
 104              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
 105              (env->sregs[SR_MSR] & MSR_EIP),
 106              (env->sregs[SR_MSR] & MSR_IE));
 107     for (i = 0; i < 32; i++) {
 108         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
 109         if ((i + 1) % 4 == 0)
 110             qemu_log("\n");
 111     }
 112     qemu_log("\n\n");
 113 }
 114
 115 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
 116 {
 117     uint32_t cout = 0;
 118
 119     if ((b == ~0) && cin)
 120         cout = 1;
 121     else if ((~0 - a) < (b + cin))
 122         cout = 1;
 123     return cout;
 124 }
 125
 126 uint32_t helper_cmp(uint32_t a, uint32_t b)
 127 {
 128     uint32_t t;
 129
 130     t = b + ~a + 1;
 131     if ((b & 0x80000000) ^ (a & 0x80000000))
 132         t = (t & 0x7fffffff) | (b & 0x80000000);
 133     return t;
 134 }
 135
 136 uint32_t helper_cmpu(uint32_t a, uint32_t b)
 137 {
 138     uint32_t t;
 139
 140     t = b + ~a + 1;
 141     if ((b & 0x80000000) ^ (a & 0x80000000))
 142         t = (t & 0x7fffffff) | (a & 0x80000000);
 143     return t;
 144 }
 145
 146 uint32_t helper_clz(uint32_t t0)
 147 {
 148     return clz32(t0);
 149 }
 150
 151 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
 152 {
 153     return compute_carry(a, b, cf);
 154 }
 155
 156 static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
 157 {
 158     if (b == 0) {
 159         env->sregs[SR_MSR] |= MSR_DZ;
 160
 161         if ((env->sregs[SR_MSR] & MSR_EE)
 162             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
 163             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
 164             helper_raise_exception(env, EXCP_HW_EXCP);
 165         }
 166         return 0;
 167     }
 168     env->sregs[SR_MSR] &= ~MSR_DZ;
 169     return 1;
 170 }
 171
 172 uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
 173 {
 174     if (!div_prepare(env, a, b)) {
 175         return 0;
 176     }
 177     return (int32_t)a / (int32_t)b;
 178 }
 179
 180 uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
 181 {
 182     if (!div_prepare(env, a, b)) {
 183         return 0;
 184     }
 185     return a / b;
 186 }
 187
 188 /* raise FPU exception.  */
 189 static void raise_fpu_exception(CPUMBState *env)
 190 {
 191     env->sregs[SR_ESR] = ESR_EC_FPU;
 192     helper_raise_exception(env, EXCP_HW_EXCP);
 193 }
 194
 195 static void update_fpu_flags(CPUMBState *env, int flags)
 196 {
 197     int raise = 0;
 198
 199     if (flags & float_flag_invalid) {
 200         env->sregs[SR_FSR] |= FSR_IO;
 201         raise = 1;
 202     }
 203     if (flags & float_flag_divbyzero) {
 204         env->sregs[SR_FSR] |= FSR_DZ;
 205         raise = 1;
 206     }
 207     if (flags & float_flag_overflow) {
 208         env->sregs[SR_FSR] |= FSR_OF;
 209         raise = 1;
 210     }
 211     if (flags & float_flag_underflow) {
 212         env->sregs[SR_FSR] |= FSR_UF;
 213         raise = 1;
 214     }
 215     if (raise
 216         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
 217         && (env->sregs[SR_MSR] & MSR_EE)) {
 218         raise_fpu_exception(env);
 219     }
 220 }
 221
 222 uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
 223 {
 224     CPU_FloatU fd, fa, fb;
 225     int flags;
 226
 227     set_float_exception_flags(0, &env->fp_status);
 228     fa.l = a;
 229     fb.l = b;
 230     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
 231
 232     flags = get_float_exception_flags(&env->fp_status);
 233     update_fpu_flags(env, flags);
 234     return fd.l;
 235 }
 236
 237 uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
 238 {
 239     CPU_FloatU fd, fa, fb;
 240     int flags;
 241
 242     set_float_exception_flags(0, &env->fp_status);
 243     fa.l = a;
 244     fb.l = b;
 245     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
 246     flags = get_float_exception_flags(&env->fp_status);
 247     update_fpu_flags(env, flags);
 248     return fd.l;
 249 }
 250
 251 uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
 252 {
 253     CPU_FloatU fd, fa, fb;
 254     int flags;
 255
 256     set_float_exception_flags(0, &env->fp_status);
 257     fa.l = a;
 258     fb.l = b;
 259     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
 260     flags = get_float_exception_flags(&env->fp_status);
 261     update_fpu_flags(env, flags);
 262
 263     return fd.l;
 264 }
 265
 266 uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
 267 {
 268     CPU_FloatU fd, fa, fb;
 269     int flags;
 270
 271     set_float_exception_flags(0, &env->fp_status);
 272     fa.l = a;
 273     fb.l = b;
 274     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
 275     flags = get_float_exception_flags(&env->fp_status);
 276     update_fpu_flags(env, flags);
 277
 278     return fd.l;
 279 }
 280
 281 uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
 282 {
 283     CPU_FloatU fa, fb;
 284     uint32_t r = 0;
 285
 286     fa.l = a;
 287     fb.l = b;
 288
 289     if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
 290         update_fpu_flags(env, float_flag_invalid);
 291         r = 1;
 292     }
 293
 294     if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
 295         r = 1;
 296     }
 297
 298     return r;
 299 }
 300
 301 uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
 302 {
 303     CPU_FloatU fa, fb;
 304     int r;
 305     int flags;
 306
 307     set_float_exception_flags(0, &env->fp_status);
 308     fa.l = a;
 309     fb.l = b;
 310     r = float32_lt(fb.f, fa.f, &env->fp_status);
 311     flags = get_float_exception_flags(&env->fp_status);
 312     update_fpu_flags(env, flags & float_flag_invalid);
 313
 314     return r;
 315 }
 316
 317 uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
 318 {
 319     CPU_FloatU fa, fb;
 320     int flags;
 321     int r;
 322
 323     set_float_exception_flags(0, &env->fp_status);
 324     fa.l = a;
 325     fb.l = b;
 326     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 327     flags = get_float_exception_flags(&env->fp_status);
 328     update_fpu_flags(env, flags & float_flag_invalid);
 329
 330     return r;
 331 }
 332
 333 uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
 334 {
 335     CPU_FloatU fa, fb;
 336     int flags;
 337     int r;
 338
 339     fa.l = a;
 340     fb.l = b;
 341     set_float_exception_flags(0, &env->fp_status);
 342     r = float32_le(fa.f, fb.f, &env->fp_status);
 343     flags = get_float_exception_flags(&env->fp_status);
 344     update_fpu_flags(env, flags & float_flag_invalid);
 345
 346
 347     return r;
 348 }
 349
 350 uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
 351 {
 352     CPU_FloatU fa, fb;
 353     int flags, r;
 354
 355     fa.l = a;
 356     fb.l = b;
 357     set_float_exception_flags(0, &env->fp_status);
 358     r = float32_lt(fa.f, fb.f, &env->fp_status);
 359     flags = get_float_exception_flags(&env->fp_status);
 360     update_fpu_flags(env, flags & float_flag_invalid);
 361     return r;
 362 }
 363
 364 uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
 365 {
 366     CPU_FloatU fa, fb;
 367     int flags, r;
 368
 369     fa.l = a;
 370     fb.l = b;
 371     set_float_exception_flags(0, &env->fp_status);
 372     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 373     flags = get_float_exception_flags(&env->fp_status);
 374     update_fpu_flags(env, flags & float_flag_invalid);
 375
 376     return r;
 377 }
 378
 379 uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
 380 {
 381     CPU_FloatU fa, fb;
 382     int flags, r;
 383
 384     fa.l = a;
 385     fb.l = b;
 386     set_float_exception_flags(0, &env->fp_status);
 387     r = !float32_lt(fa.f, fb.f, &env->fp_status);
 388     flags = get_float_exception_flags(&env->fp_status);
 389     update_fpu_flags(env, flags & float_flag_invalid);
 390
 391     return r;
 392 }
 393
 394 uint32_t helper_flt(CPUMBState *env, uint32_t a)
 395 {
 396     CPU_FloatU fd, fa;
 397
 398     fa.l = a;
 399     fd.f = int32_to_float32(fa.l, &env->fp_status);
 400     return fd.l;
 401 }
 402
 403 uint32_t helper_fint(CPUMBState *env, uint32_t a)
 404 {
 405     CPU_FloatU fa;
 406     uint32_t r;
 407     int flags;
 408
 409     set_float_exception_flags(0, &env->fp_status);
 410     fa.l = a;
 411     r = float32_to_int32(fa.f, &env->fp_status);
 412     flags = get_float_exception_flags(&env->fp_status);
 413     update_fpu_flags(env, flags);
 414
 415     return r;
 416 }
 417
 418 uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
 419 {
 420     CPU_FloatU fd, fa;
 421     int flags;
 422
 423     set_float_exception_flags(0, &env->fp_status);
 424     fa.l = a;
 425     fd.l = float32_sqrt(fa.f, &env->fp_status);
 426     flags = get_float_exception_flags(&env->fp_status);
 427     update_fpu_flags(env, flags);
 428
 429     return fd.l;
 430 }
 431
 432 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
 433 {
 434     unsigned int i;
 435     uint32_t mask = 0xff000000;
 436
 437     for (i = 0; i < 4; i++) {
 438         if ((a & mask) == (b & mask))
 439             return i + 1;
 440         mask >>= 8;
 441     }
 442     return 0;
 443 }
 444
 445 void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
 446                      uint32_t mask)
 447 {
 448     if (addr & mask) {
 449             qemu_log_mask(CPU_LOG_INT,
 450                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
 451                           addr, mask, wr, dr);
 452             env->sregs[SR_EAR] = addr;
 453             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
 454                                  | (dr & 31) << 5;
 455             if (mask == 3) {
 456                 env->sregs[SR_ESR] |= 1 << 11;
 457             }
 458             if (!(env->sregs[SR_MSR] & MSR_EE)) {
 459                 return;
 460             }
 461             helper_raise_exception(env, EXCP_HW_EXCP);
 462     }
 463 }
 464
 465 void helper_stackprot(CPUMBState *env, uint32_t addr)
 466 {
 467     if (addr < env->slr || addr > env->shr) {
 468         qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
 469                       addr, env->slr, env->shr);
 470         env->sregs[SR_EAR] = addr;
 471         env->sregs[SR_ESR] = ESR_EC_STACKPROT;
 472         helper_raise_exception(env, EXCP_HW_EXCP);
 473     }
 474 }
 475
 476 #if !defined(CONFIG_USER_ONLY)
 477 /* Writes/reads to the MMU's special regs end up here.  */
 478 uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
 479 {
 480     return mmu_read(env, rn);
 481 }
 482
 483 void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
 484 {
 485     mmu_write(env, rn, v);
 486 }
 487
 488 void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
 489                               bool is_write, bool is_exec, int is_asi,
 490                               unsigned size)
 491 {
 492     MicroBlazeCPU *cpu;
 493     CPUMBState *env;
 494
 495     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
 496              addr, is_write ? 1 : 0, is_exec ? 1 : 0);
 497     if (cs == NULL) {
 498         return;
 499     }
 500     cpu = MICROBLAZE_CPU(cs);
 501     env = &cpu->env;
 502     if (!(env->sregs[SR_MSR] & MSR_EE)) {
 503         return;
 504     }
 505
 506     env->sregs[SR_EAR] = addr;
 507     if (is_exec) {
 508         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
 509             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
 510             helper_raise_exception(env, EXCP_HW_EXCP);
 511         }
 512     } else {
 513         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
 514             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
 515             helper_raise_exception(env, EXCP_HW_EXCP);
 516         }
 517     }
 518 }
 519 #endif