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block: m25p80: Add Quad Page Program 4byte
[qemu/ar7.git] / hw / block / m25p80.c
blob4ad67ac58855020768febceae8a169e04e5685e7
1 /*
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command
3 * set. Known devices table current as of Jun/2012 and taken from linux.
4 * See drivers/mtd/devices/m25p80.c.
5 *
6 * Copyright (C) 2011 Edgar E. Iglesias <edgar.iglesias@gmail.com>
7 * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Copyright (C) 2012 PetaLogix
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 or
13 * (at your option) a later version of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
22 */
23
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/block-backend.h"
27 #include "sysemu/blockdev.h"
28 #include "hw/ssi/ssi.h"
29 #include "qemu/bitops.h"
30 #include "qemu/log.h"
31 #include "qemu/error-report.h"
32 #include "qapi/error.h"
33
34 #ifndef M25P80_ERR_DEBUG
35 #define M25P80_ERR_DEBUG 0
36 #endif
37
38 #define DB_PRINT_L(level, ...) do { \
39 if (M25P80_ERR_DEBUG > (level)) { \
40 fprintf(stderr, ": %s: ", __func__); \
41 fprintf(stderr, ## __VA_ARGS__); \
42 } \
43 } while (0);
44
45 /* Fields for FlashPartInfo->flags */
46
47 /* erase capabilities */
48 #define ER_4K 1
49 #define ER_32K 2
50 /* set to allow the page program command to write 0s back to 1. Useful for
51 * modelling EEPROM with SPI flash command set
52 */
53 #define EEPROM 0x100
54
55 /* 16 MiB max in 3 byte address mode */
56 #define MAX_3BYTES_SIZE 0x1000000
57
58 #define SPI_NOR_MAX_ID_LEN 6
59
60 typedef struct FlashPartInfo {
61 const char *part_name;
62 /*
63 * This array stores the ID bytes.
64 * The first three bytes are the JEDIC ID.
65 * JEDEC ID zero means "no ID" (mostly older chips).
66 */
67 uint8_t id[SPI_NOR_MAX_ID_LEN];
68 uint8_t id_len;
69 /* there is confusion between manufacturers as to what a sector is. In this
70 * device model, a "sector" is the size that is erased by the ERASE_SECTOR
71 * command (opcode 0xd8).
72 */
73 uint32_t sector_size;
74 uint32_t n_sectors;
75 uint32_t page_size;
76 uint16_t flags;
77 } FlashPartInfo;
78
79 /* adapted from linux */
80 /* Used when the "_ext_id" is two bytes at most */
81 #define INFO(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
82 .part_name = _part_name,\
83 .id = {\
84 ((_jedec_id) >> 16) & 0xff,\
85 ((_jedec_id) >> 8) & 0xff,\
86 (_jedec_id) & 0xff,\
87 ((_ext_id) >> 8) & 0xff,\
88 (_ext_id) & 0xff,\
89 },\
90 .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),\
91 .sector_size = (_sector_size),\
92 .n_sectors = (_n_sectors),\
93 .page_size = 256,\
94 .flags = (_flags),
95
96 #define INFO6(_part_name, _jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
97 .part_name = _part_name,\
98 .id = {\
99 ((_jedec_id) >> 16) & 0xff,\
100 ((_jedec_id) >> 8) & 0xff,\
101 (_jedec_id) & 0xff,\
102 ((_ext_id) >> 16) & 0xff,\
103 ((_ext_id) >> 8) & 0xff,\
104 (_ext_id) & 0xff,\
105 },\
106 .id_len = 6,\
107 .sector_size = (_sector_size),\
108 .n_sectors = (_n_sectors),\
109 .page_size = 256,\
110 .flags = (_flags),\
111
112 #define JEDEC_NUMONYX 0x20
113 #define JEDEC_WINBOND 0xEF
114 #define JEDEC_SPANSION 0x01
115
116 /* Numonyx (Micron) Configuration register macros */
117 #define VCFG_DUMMY 0x1
118 #define VCFG_WRAP_SEQUENTIAL 0x2
119 #define NVCFG_XIP_MODE_DISABLED (7 << 9)
120 #define NVCFG_XIP_MODE_MASK (7 << 9)
121 #define VCFG_XIP_MODE_ENABLED (1 << 3)
122 #define CFG_DUMMY_CLK_LEN 4
123 #define NVCFG_DUMMY_CLK_POS 12
124 #define VCFG_DUMMY_CLK_POS 4
125 #define EVCFG_OUT_DRIVER_STRENGHT_DEF 7
126 #define EVCFG_VPP_ACCELERATOR (1 << 3)
127 #define EVCFG_RESET_HOLD_ENABLED (1 << 4)
128 #define NVCFG_DUAL_IO_MASK (1 << 2)
129 #define EVCFG_DUAL_IO_ENABLED (1 << 6)
130 #define NVCFG_QUAD_IO_MASK (1 << 3)
131 #define EVCFG_QUAD_IO_ENABLED (1 << 7)
132 #define NVCFG_4BYTE_ADDR_MASK (1 << 0)
133 #define NVCFG_LOWER_SEGMENT_MASK (1 << 1)
134
135 /* Numonyx (Micron) Flag Status Register macros */
136 #define FSR_4BYTE_ADDR_MODE_ENABLED 0x1
137 #define FSR_FLASH_READY (1 << 7)
138
139 /* Spansion configuration registers macros. */
140 #define SPANSION_QUAD_CFG_POS 0
141 #define SPANSION_QUAD_CFG_LEN 1
142 #define SPANSION_DUMMY_CLK_POS 0
143 #define SPANSION_DUMMY_CLK_LEN 4
144 #define SPANSION_ADDR_LEN_POS 7
145 #define SPANSION_ADDR_LEN_LEN 1
146
147 /*
148 * Spansion read mode command length in bytes,
149 * the mode is currently not supported.
150 */
151
152 #define SPANSION_CONTINUOUS_READ_MODE_CMD_LEN 1
153 #define WINBOND_CONTINUOUS_READ_MODE_CMD_LEN 1
154
155 static const FlashPartInfo known_devices[] = {
156 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
157 { INFO("at25fs010", 0x1f6601, 0, 32 << 10, 4, ER_4K) },
158 { INFO("at25fs040", 0x1f6604, 0, 64 << 10, 8, ER_4K) },
159
160 { INFO("at25df041a", 0x1f4401, 0, 64 << 10, 8, ER_4K) },
161 { INFO("at25df321a", 0x1f4701, 0, 64 << 10, 64, ER_4K) },
162 { INFO("at25df641", 0x1f4800, 0, 64 << 10, 128, ER_4K) },
163
164 { INFO("at26f004", 0x1f0400, 0, 64 << 10, 8, ER_4K) },
165 { INFO("at26df081a", 0x1f4501, 0, 64 << 10, 16, ER_4K) },
166 { INFO("at26df161a", 0x1f4601, 0, 64 << 10, 32, ER_4K) },
167 { INFO("at26df321", 0x1f4700, 0, 64 << 10, 64, ER_4K) },
168
169 { INFO("at45db081d", 0x1f2500, 0, 64 << 10, 16, ER_4K) },
170
171 /* Atmel EEPROMS - it is assumed, that don't care bit in command
172 * is set to 0. Block protection is not supported.
173 */
174 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },
175 { INFO("at25256a-nonjedec", 0x0, 0, 1, 262144, EEPROM) },
176
177 /* EON -- en25xxx */
178 { INFO("en25f32", 0x1c3116, 0, 64 << 10, 64, ER_4K) },
179 { INFO("en25p32", 0x1c2016, 0, 64 << 10, 64, 0) },
180 { INFO("en25q32b", 0x1c3016, 0, 64 << 10, 64, 0) },
181 { INFO("en25p64", 0x1c2017, 0, 64 << 10, 128, 0) },
182 { INFO("en25q64", 0x1c3017, 0, 64 << 10, 128, ER_4K) },
183
184 /* GigaDevice */
185 { INFO("gd25q32", 0xc84016, 0, 64 << 10, 64, ER_4K) },
186 { INFO("gd25q64", 0xc84017, 0, 64 << 10, 128, ER_4K) },
187
188 /* Intel/Numonyx -- xxxs33b */
189 { INFO("160s33b", 0x898911, 0, 64 << 10, 32, 0) },
190 { INFO("320s33b", 0x898912, 0, 64 << 10, 64, 0) },
191 { INFO("640s33b", 0x898913, 0, 64 << 10, 128, 0) },
192 { INFO("n25q064", 0x20ba17, 0, 64 << 10, 128, 0) },
193
194 /* Macronix */
195 { INFO("mx25l2005a", 0xc22012, 0, 64 << 10, 4, ER_4K) },
196 { INFO("mx25l4005a", 0xc22013, 0, 64 << 10, 8, ER_4K) },
197 { INFO("mx25l8005", 0xc22014, 0, 64 << 10, 16, 0) },
198 { INFO("mx25l1606e", 0xc22015, 0, 64 << 10, 32, ER_4K) },
199 { INFO("mx25l3205d", 0xc22016, 0, 64 << 10, 64, 0) },
200 { INFO("mx25l6405d", 0xc22017, 0, 64 << 10, 128, 0) },
201 { INFO("mx25l12805d", 0xc22018, 0, 64 << 10, 256, 0) },
202 { INFO("mx25l12855e", 0xc22618, 0, 64 << 10, 256, 0) },
203 { INFO("mx25l25635e", 0xc22019, 0, 64 << 10, 512, 0) },
204 { INFO("mx25l25655e", 0xc22619, 0, 64 << 10, 512, 0) },
205 { INFO("mx66u51235f", 0xc2253a, 0, 64 << 10, 1024, ER_4K | ER_32K) },
206 { INFO("mx66u1g45g", 0xc2253b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
207 { INFO("mx66l1g45g", 0xc2201b, 0, 64 << 10, 2048, ER_4K | ER_32K) },
208
209 /* Micron */
210 { INFO("n25q032a11", 0x20bb16, 0, 64 << 10, 64, ER_4K) },
211 { INFO("n25q032a13", 0x20ba16, 0, 64 << 10, 64, ER_4K) },
212 { INFO("n25q064a11", 0x20bb17, 0, 64 << 10, 128, ER_4K) },
213 { INFO("n25q064a13", 0x20ba17, 0, 64 << 10, 128, ER_4K) },
214 { INFO("n25q128a11", 0x20bb18, 0, 64 << 10, 256, ER_4K) },
215 { INFO("n25q128a13", 0x20ba18, 0, 64 << 10, 256, ER_4K) },
216 { INFO("n25q256a11", 0x20bb19, 0, 64 << 10, 512, ER_4K) },
217 { INFO("n25q256a13", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
218 { INFO("n25q128", 0x20ba18, 0, 64 << 10, 256, 0) },
219 { INFO("n25q256a", 0x20ba19, 0, 64 << 10, 512, ER_4K) },
220 { INFO("n25q512a", 0x20ba20, 0, 64 << 10, 1024, ER_4K) },
221 { INFO("mt25ql01g", 0x20ba21, 0, 64 << 10, 2048, ER_4K) },
222 { INFO("mt25qu01g", 0x20bb21, 0, 64 << 10, 2048, ER_4K) },
223
224 /* Spansion -- single (large) sector size only, at least
225 * for the chips listed here (without boot sectors).
226 */
227 { INFO("s25sl032p", 0x010215, 0x4d00, 64 << 10, 64, ER_4K) },
228 { INFO("s25sl064p", 0x010216, 0x4d00, 64 << 10, 128, ER_4K) },
229 { INFO("s25fl256s0", 0x010219, 0x4d00, 256 << 10, 128, 0) },
230 { INFO("s25fl256s1", 0x010219, 0x4d01, 64 << 10, 512, 0) },
231 { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 << 10, 256, 0) },
232 { INFO6("s70fl01gs", 0x010221, 0x4d0080, 256 << 10, 512, 0) },
233 { INFO("s25sl12800", 0x012018, 0x0300, 256 << 10, 64, 0) },
234 { INFO("s25sl12801", 0x012018, 0x0301, 64 << 10, 256, 0) },
235 { INFO("s25fl129p0", 0x012018, 0x4d00, 256 << 10, 64, 0) },
236 { INFO("s25fl129p1", 0x012018, 0x4d01, 64 << 10, 256, 0) },
237 { INFO("s25sl004a", 0x010212, 0, 64 << 10, 8, 0) },
238 { INFO("s25sl008a", 0x010213, 0, 64 << 10, 16, 0) },
239 { INFO("s25sl016a", 0x010214, 0, 64 << 10, 32, 0) },
240 { INFO("s25sl032a", 0x010215, 0, 64 << 10, 64, 0) },
241 { INFO("s25sl064a", 0x010216, 0, 64 << 10, 128, 0) },
242 { INFO("s25fl016k", 0xef4015, 0, 64 << 10, 32, ER_4K | ER_32K) },
243 { INFO("s25fl064k", 0xef4017, 0, 64 << 10, 128, ER_4K | ER_32K) },
244
245 /* Spansion -- boot sectors support */
246 { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 << 10, 256, 0) },
247 { INFO6("s70fs01gs", 0x010221, 0x4d0081, 256 << 10, 512, 0) },
248
249 /* SST -- large erase sizes are "overlays", "sectors" are 4<< 10 */
250 { INFO("sst25vf040b", 0xbf258d, 0, 64 << 10, 8, ER_4K) },
251 { INFO("sst25vf080b", 0xbf258e, 0, 64 << 10, 16, ER_4K) },
252 { INFO("sst25vf016b", 0xbf2541, 0, 64 << 10, 32, ER_4K) },
253 { INFO("sst25vf032b", 0xbf254a, 0, 64 << 10, 64, ER_4K) },
254 { INFO("sst25wf512", 0xbf2501, 0, 64 << 10, 1, ER_4K) },
255 { INFO("sst25wf010", 0xbf2502, 0, 64 << 10, 2, ER_4K) },
256 { INFO("sst25wf020", 0xbf2503, 0, 64 << 10, 4, ER_4K) },
257 { INFO("sst25wf040", 0xbf2504, 0, 64 << 10, 8, ER_4K) },
258 { INFO("sst25wf080", 0xbf2505, 0, 64 << 10, 16, ER_4K) },
259
260 /* ST Microelectronics -- newer production may have feature updates */
261 { INFO("m25p05", 0x202010, 0, 32 << 10, 2, 0) },
262 { INFO("m25p10", 0x202011, 0, 32 << 10, 4, 0) },
263 { INFO("m25p20", 0x202012, 0, 64 << 10, 4, 0) },
264 { INFO("m25p40", 0x202013, 0, 64 << 10, 8, 0) },
265 { INFO("m25p80", 0x202014, 0, 64 << 10, 16, 0) },
266 { INFO("m25p16", 0x202015, 0, 64 << 10, 32, 0) },
267 { INFO("m25p32", 0x202016, 0, 64 << 10, 64, 0) },
268 { INFO("m25p64", 0x202017, 0, 64 << 10, 128, 0) },
269 { INFO("m25p128", 0x202018, 0, 256 << 10, 64, 0) },
270 { INFO("n25q032", 0x20ba16, 0, 64 << 10, 64, 0) },
271
272 { INFO("m45pe10", 0x204011, 0, 64 << 10, 2, 0) },
273 { INFO("m45pe80", 0x204014, 0, 64 << 10, 16, 0) },
274 { INFO("m45pe16", 0x204015, 0, 64 << 10, 32, 0) },
275
276 { INFO("m25pe20", 0x208012, 0, 64 << 10, 4, 0) },
277 { INFO("m25pe80", 0x208014, 0, 64 << 10, 16, 0) },
278 { INFO("m25pe16", 0x208015, 0, 64 << 10, 32, ER_4K) },
279
280 { INFO("m25px32", 0x207116, 0, 64 << 10, 64, ER_4K) },
281 { INFO("m25px32-s0", 0x207316, 0, 64 << 10, 64, ER_4K) },
282 { INFO("m25px32-s1", 0x206316, 0, 64 << 10, 64, ER_4K) },
283 { INFO("m25px64", 0x207117, 0, 64 << 10, 128, 0) },
284
285 /* Winbond -- w25x "blocks" are 64k, "sectors" are 4KiB */
286 { INFO("w25x10", 0xef3011, 0, 64 << 10, 2, ER_4K) },
287 { INFO("w25x20", 0xef3012, 0, 64 << 10, 4, ER_4K) },
288 { INFO("w25x40", 0xef3013, 0, 64 << 10, 8, ER_4K) },
289 { INFO("w25x80", 0xef3014, 0, 64 << 10, 16, ER_4K) },
290 { INFO("w25x16", 0xef3015, 0, 64 << 10, 32, ER_4K) },
291 { INFO("w25x32", 0xef3016, 0, 64 << 10, 64, ER_4K) },
292 { INFO("w25q32", 0xef4016, 0, 64 << 10, 64, ER_4K) },
293 { INFO("w25q32dw", 0xef6016, 0, 64 << 10, 64, ER_4K) },
294 { INFO("w25x64", 0xef3017, 0, 64 << 10, 128, ER_4K) },
295 { INFO("w25q64", 0xef4017, 0, 64 << 10, 128, ER_4K) },
296 { INFO("w25q80", 0xef5014, 0, 64 << 10, 16, ER_4K) },
297 { INFO("w25q80bl", 0xef4014, 0, 64 << 10, 16, ER_4K) },
298 { INFO("w25q256", 0xef4019, 0, 64 << 10, 512, ER_4K) },
299 };
300
301 typedef enum {
302 NOP = 0,
303 WRSR = 0x1,
304 WRDI = 0x4,
305 RDSR = 0x5,
306 WREN = 0x6,
307 JEDEC_READ = 0x9f,
308 BULK_ERASE = 0xc7,
309 READ_FSR = 0x70,
310 RDCR = 0x15,
311
312 READ = 0x03,
313 READ4 = 0x13,
314 FAST_READ = 0x0b,
315 FAST_READ4 = 0x0c,
316 DOR = 0x3b,
317 DOR4 = 0x3c,
318 QOR = 0x6b,
319 QOR4 = 0x6c,
320 DIOR = 0xbb,
321 DIOR4 = 0xbc,
322 QIOR = 0xeb,
323 QIOR4 = 0xec,
324
325 PP = 0x02,
326 PP4 = 0x12,
327 PP4_4 = 0x3e,
328 DPP = 0xa2,
329 QPP = 0x32,
330 QPP_4 = 0x34,
331
332 ERASE_4K = 0x20,
333 ERASE4_4K = 0x21,
334 ERASE_32K = 0x52,
335 ERASE4_32K = 0x5c,
336 ERASE_SECTOR = 0xd8,
337 ERASE4_SECTOR = 0xdc,
338
339 EN_4BYTE_ADDR = 0xB7,
340 EX_4BYTE_ADDR = 0xE9,
341
342 EXTEND_ADDR_READ = 0xC8,
343 EXTEND_ADDR_WRITE = 0xC5,
344
345 RESET_ENABLE = 0x66,
346 RESET_MEMORY = 0x99,
347
348 /*
349 * Micron: 0x35 - enable QPI
350 * Spansion: 0x35 - read control register
351 */
352 RDCR_EQIO = 0x35,
353 RSTQIO = 0xf5,
354
355 RNVCR = 0xB5,
356 WNVCR = 0xB1,
357
358 RVCR = 0x85,
359 WVCR = 0x81,
360
361 REVCR = 0x65,
362 WEVCR = 0x61,
363 } FlashCMD;
364
365 typedef enum {
366 STATE_IDLE,
367 STATE_PAGE_PROGRAM,
368 STATE_READ,
369 STATE_COLLECTING_DATA,
370 STATE_COLLECTING_VAR_LEN_DATA,
371 STATE_READING_DATA,
372 } CMDState;
373
374 typedef enum {
375 MAN_SPANSION,
376 MAN_MACRONIX,
377 MAN_NUMONYX,
378 MAN_WINBOND,
379 MAN_GENERIC,
380 } Manufacturer;
381
382 #define M25P80_INTERNAL_DATA_BUFFER_SZ 16
383
384 typedef struct Flash {
385 SSISlave parent_obj;
386
387 BlockBackend *blk;
388
389 uint8_t *storage;
390 uint32_t size;
391 int page_size;
392
393 uint8_t state;
394 uint8_t data[M25P80_INTERNAL_DATA_BUFFER_SZ];
395 uint32_t len;
396 uint32_t pos;
397 uint8_t needed_bytes;
398 uint8_t cmd_in_progress;
399 uint32_t cur_addr;
400 uint32_t nonvolatile_cfg;
401 /* Configuration register for Macronix */
402 uint32_t volatile_cfg;
403 uint32_t enh_volatile_cfg;
404 /* Spansion cfg registers. */
405 uint8_t spansion_cr1nv;
406 uint8_t spansion_cr2nv;
407 uint8_t spansion_cr3nv;
408 uint8_t spansion_cr4nv;
409 uint8_t spansion_cr1v;
410 uint8_t spansion_cr2v;
411 uint8_t spansion_cr3v;
412 uint8_t spansion_cr4v;
413 bool write_enable;
414 bool four_bytes_address_mode;
415 bool reset_enable;
416 bool quad_enable;
417 uint8_t ear;
418
419 int64_t dirty_page;
420
421 const FlashPartInfo *pi;
422
423 } Flash;
424
425 typedef struct M25P80Class {
426 SSISlaveClass parent_class;
427 FlashPartInfo *pi;
428 } M25P80Class;
429
430 #define TYPE_M25P80 "m25p80-generic"
431 #define M25P80(obj) \
432 OBJECT_CHECK(Flash, (obj), TYPE_M25P80)
433 #define M25P80_CLASS(klass) \
434 OBJECT_CLASS_CHECK(M25P80Class, (klass), TYPE_M25P80)
435 #define M25P80_GET_CLASS(obj) \
436 OBJECT_GET_CLASS(M25P80Class, (obj), TYPE_M25P80)
437
438 static inline Manufacturer get_man(Flash *s)
439 {
440 switch (s->pi->id[0]) {
441 case 0x20:
442 return MAN_NUMONYX;
443 case 0xEF:
444 return MAN_WINBOND;
445 case 0x01:
446 return MAN_SPANSION;
447 case 0xC2:
448 return MAN_MACRONIX;
449 default:
450 return MAN_GENERIC;
451 }
452 }
453
454 static void blk_sync_complete(void *opaque, int ret)
455 {
456 QEMUIOVector *iov = opaque;
457
458 qemu_iovec_destroy(iov);
459 g_free(iov);
460
461 /* do nothing. Masters do not directly interact with the backing store,
462 * only the working copy so no mutexing required.
463 */
464 }
465
466 static void flash_sync_page(Flash *s, int page)
467 {
468 QEMUIOVector *iov;
469
470 if (!s->blk || blk_is_read_only(s->blk)) {
471 return;
472 }
473
474 iov = g_new(QEMUIOVector, 1);
475 qemu_iovec_init(iov, 1);
476 qemu_iovec_add(iov, s->storage + page * s->pi->page_size,
477 s->pi->page_size);
478 blk_aio_pwritev(s->blk, page * s->pi->page_size, iov, 0,
479 blk_sync_complete, iov);
480 }
481
482 static inline void flash_sync_area(Flash *s, int64_t off, int64_t len)
483 {
484 QEMUIOVector *iov;
485
486 if (!s->blk || blk_is_read_only(s->blk)) {
487 return;
488 }
489
490 assert(!(len % BDRV_SECTOR_SIZE));
491 iov = g_new(QEMUIOVector, 1);
492 qemu_iovec_init(iov, 1);
493 qemu_iovec_add(iov, s->storage + off, len);
494 blk_aio_pwritev(s->blk, off, iov, 0, blk_sync_complete, iov);
495 }
496
497 static void flash_erase(Flash *s, int offset, FlashCMD cmd)
498 {
499 uint32_t len;
500 uint8_t capa_to_assert = 0;
501
502 switch (cmd) {
503 case ERASE_4K:
504 case ERASE4_4K:
505 len = 4 << 10;
506 capa_to_assert = ER_4K;
507 break;
508 case ERASE_32K:
509 case ERASE4_32K:
510 len = 32 << 10;
511 capa_to_assert = ER_32K;
512 break;
513 case ERASE_SECTOR:
514 case ERASE4_SECTOR:
515 len = s->pi->sector_size;
516 break;
517 case BULK_ERASE:
518 len = s->size;
519 break;
520 default:
521 abort();
522 }
523
524 DB_PRINT_L(0, "offset = %#x, len = %d\n", offset, len);
525 if ((s->pi->flags & capa_to_assert) != capa_to_assert) {
526 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: %d erase size not supported by"
527 " device\n", len);
528 }
529
530 if (!s->write_enable) {
531 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: erase with write protect!\n");
532 return;
533 }
534 memset(s->storage + offset, 0xff, len);
535 flash_sync_area(s, offset, len);
536 }
537
538 static inline void flash_sync_dirty(Flash *s, int64_t newpage)
539 {
540 if (s->dirty_page >= 0 && s->dirty_page != newpage) {
541 flash_sync_page(s, s->dirty_page);
542 s->dirty_page = newpage;
543 }
544 }
545
546 static inline
547 void flash_write8(Flash *s, uint32_t addr, uint8_t data)
548 {
549 uint32_t page = addr / s->pi->page_size;
550 uint8_t prev = s->storage[s->cur_addr];
551
552 if (!s->write_enable) {
553 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
554 }
555
556 if ((prev ^ data) & data) {
557 DB_PRINT_L(1, "programming zero to one! addr=%" PRIx32 " %" PRIx8
558 " -> %" PRIx8 "\n", addr, prev, data);
559 }
560
561 if (s->pi->flags & EEPROM) {
562 s->storage[s->cur_addr] = data;
563 } else {
564 s->storage[s->cur_addr] &= data;
565 }
566
567 flash_sync_dirty(s, page);
568 s->dirty_page = page;
569 }
570
571 static inline int get_addr_length(Flash *s)
572 {
573 /* check if eeprom is in use */
574 if (s->pi->flags == EEPROM) {
575 return 2;
576 }
577
578 switch (s->cmd_in_progress) {
579 case PP4:
580 case PP4_4:
581 case QPP_4:
582 case READ4:
583 case QIOR4:
584 case ERASE4_4K:
585 case ERASE4_32K:
586 case ERASE4_SECTOR:
587 case FAST_READ4:
588 case DOR4:
589 case QOR4:
590 case DIOR4:
591 return 4;
592 default:
593 return s->four_bytes_address_mode ? 4 : 3;
594 }
595 }
596
597 static void complete_collecting_data(Flash *s)
598 {
599 int i, n;
600
601 n = get_addr_length(s);
602 s->cur_addr = (n == 3 ? s->ear : 0);
603 for (i = 0; i < n; ++i) {
604 s->cur_addr <<= 8;
605 s->cur_addr |= s->data[i];
606 }
607
608 s->cur_addr &= s->size - 1;
609
610 s->state = STATE_IDLE;
611
612 switch (s->cmd_in_progress) {
613 case DPP:
614 case QPP:
615 case QPP_4:
616 case PP:
617 case PP4:
618 case PP4_4:
619 s->state = STATE_PAGE_PROGRAM;
620 break;
621 case READ:
622 case READ4:
623 case FAST_READ:
624 case FAST_READ4:
625 case DOR:
626 case DOR4:
627 case QOR:
628 case QOR4:
629 case DIOR:
630 case DIOR4:
631 case QIOR:
632 case QIOR4:
633 s->state = STATE_READ;
634 break;
635 case ERASE_4K:
636 case ERASE4_4K:
637 case ERASE_32K:
638 case ERASE4_32K:
639 case ERASE_SECTOR:
640 case ERASE4_SECTOR:
641 flash_erase(s, s->cur_addr, s->cmd_in_progress);
642 break;
643 case WRSR:
644 switch (get_man(s)) {
645 case MAN_SPANSION:
646 s->quad_enable = !!(s->data[1] & 0x02);
647 break;
648 case MAN_MACRONIX:
649 s->quad_enable = extract32(s->data[0], 6, 1);
650 if (s->len > 1) {
651 s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
652 }
653 break;
654 default:
655 break;
656 }
657 if (s->write_enable) {
658 s->write_enable = false;
659 }
660 break;
661 case EXTEND_ADDR_WRITE:
662 s->ear = s->data[0];
663 break;
664 case WNVCR:
665 s->nonvolatile_cfg = s->data[0] | (s->data[1] << 8);
666 break;
667 case WVCR:
668 s->volatile_cfg = s->data[0];
669 break;
670 case WEVCR:
671 s->enh_volatile_cfg = s->data[0];
672 break;
673 default:
674 break;
675 }
676 }
677
678 static void reset_memory(Flash *s)
679 {
680 s->cmd_in_progress = NOP;
681 s->cur_addr = 0;
682 s->ear = 0;
683 s->four_bytes_address_mode = false;
684 s->len = 0;
685 s->needed_bytes = 0;
686 s->pos = 0;
687 s->state = STATE_IDLE;
688 s->write_enable = false;
689 s->reset_enable = false;
690 s->quad_enable = false;
691
692 switch (get_man(s)) {
693 case MAN_NUMONYX:
694 s->volatile_cfg = 0;
695 s->volatile_cfg |= VCFG_DUMMY;
696 s->volatile_cfg |= VCFG_WRAP_SEQUENTIAL;
697 if ((s->nonvolatile_cfg & NVCFG_XIP_MODE_MASK)
698 != NVCFG_XIP_MODE_DISABLED) {
699 s->volatile_cfg |= VCFG_XIP_MODE_ENABLED;
700 }
701 s->volatile_cfg |= deposit32(s->volatile_cfg,
702 VCFG_DUMMY_CLK_POS,
703 CFG_DUMMY_CLK_LEN,
704 extract32(s->nonvolatile_cfg,
705 NVCFG_DUMMY_CLK_POS,
706 CFG_DUMMY_CLK_LEN)
707 );
708
709 s->enh_volatile_cfg = 0;
710 s->enh_volatile_cfg |= EVCFG_OUT_DRIVER_STRENGHT_DEF;
711 s->enh_volatile_cfg |= EVCFG_VPP_ACCELERATOR;
712 s->enh_volatile_cfg |= EVCFG_RESET_HOLD_ENABLED;
713 if (s->nonvolatile_cfg & NVCFG_DUAL_IO_MASK) {
714 s->enh_volatile_cfg |= EVCFG_DUAL_IO_ENABLED;
715 }
716 if (s->nonvolatile_cfg & NVCFG_QUAD_IO_MASK) {
717 s->enh_volatile_cfg |= EVCFG_QUAD_IO_ENABLED;
718 }
719 if (!(s->nonvolatile_cfg & NVCFG_4BYTE_ADDR_MASK)) {
720 s->four_bytes_address_mode = true;
721 }
722 if (!(s->nonvolatile_cfg & NVCFG_LOWER_SEGMENT_MASK)) {
723 s->ear = s->size / MAX_3BYTES_SIZE - 1;
724 }
725 break;
726 case MAN_MACRONIX:
727 s->volatile_cfg = 0x7;
728 break;
729 case MAN_SPANSION:
730 s->spansion_cr1v = s->spansion_cr1nv;
731 s->spansion_cr2v = s->spansion_cr2nv;
732 s->spansion_cr3v = s->spansion_cr3nv;
733 s->spansion_cr4v = s->spansion_cr4nv;
734 s->quad_enable = extract32(s->spansion_cr1v,
735 SPANSION_QUAD_CFG_POS,
736 SPANSION_QUAD_CFG_LEN
737 );
738 s->four_bytes_address_mode = extract32(s->spansion_cr2v,
739 SPANSION_ADDR_LEN_POS,
740 SPANSION_ADDR_LEN_LEN
741 );
742 break;
743 default:
744 break;
745 }
746
747 DB_PRINT_L(0, "Reset done.\n");
748 }
749
750 static void decode_fast_read_cmd(Flash *s)
751 {
752 s->needed_bytes = get_addr_length(s);
753 switch (get_man(s)) {
754 /* Dummy cycles - modeled with bytes writes instead of bits */
755 case MAN_WINBOND:
756 s->needed_bytes += 8;
757 break;
758 case MAN_NUMONYX:
759 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
760 break;
761 case MAN_MACRONIX:
762 if (extract32(s->volatile_cfg, 6, 2) == 1) {
763 s->needed_bytes += 6;
764 } else {
765 s->needed_bytes += 8;
766 }
767 break;
768 case MAN_SPANSION:
769 s->needed_bytes += extract32(s->spansion_cr2v,
770 SPANSION_DUMMY_CLK_POS,
771 SPANSION_DUMMY_CLK_LEN
772 );
773 break;
774 default:
775 break;
776 }
777 s->pos = 0;
778 s->len = 0;
779 s->state = STATE_COLLECTING_DATA;
780 }
781
782 static void decode_dio_read_cmd(Flash *s)
783 {
784 s->needed_bytes = get_addr_length(s);
785 /* Dummy cycles modeled with bytes writes instead of bits */
786 switch (get_man(s)) {
787 case MAN_WINBOND:
788 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
789 break;
790 case MAN_SPANSION:
791 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
792 s->needed_bytes += extract32(s->spansion_cr2v,
793 SPANSION_DUMMY_CLK_POS,
794 SPANSION_DUMMY_CLK_LEN
795 );
796 break;
797 case MAN_NUMONYX:
798 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
799 break;
800 case MAN_MACRONIX:
801 switch (extract32(s->volatile_cfg, 6, 2)) {
802 case 1:
803 s->needed_bytes += 6;
804 break;
805 case 2:
806 s->needed_bytes += 8;
807 break;
808 default:
809 s->needed_bytes += 4;
810 break;
811 }
812 break;
813 default:
814 break;
815 }
816 s->pos = 0;
817 s->len = 0;
818 s->state = STATE_COLLECTING_DATA;
819 }
820
821 static void decode_qio_read_cmd(Flash *s)
822 {
823 s->needed_bytes = get_addr_length(s);
824 /* Dummy cycles modeled with bytes writes instead of bits */
825 switch (get_man(s)) {
826 case MAN_WINBOND:
827 s->needed_bytes += WINBOND_CONTINUOUS_READ_MODE_CMD_LEN;
828 s->needed_bytes += 4;
829 break;
830 case MAN_SPANSION:
831 s->needed_bytes += SPANSION_CONTINUOUS_READ_MODE_CMD_LEN;
832 s->needed_bytes += extract32(s->spansion_cr2v,
833 SPANSION_DUMMY_CLK_POS,
834 SPANSION_DUMMY_CLK_LEN
835 );
836 break;
837 case MAN_NUMONYX:
838 s->needed_bytes += extract32(s->volatile_cfg, 4, 4);
839 break;
840 case MAN_MACRONIX:
841 switch (extract32(s->volatile_cfg, 6, 2)) {
842 case 1:
843 s->needed_bytes += 4;
844 break;
845 case 2:
846 s->needed_bytes += 8;
847 break;
848 default:
849 s->needed_bytes += 6;
850 break;
851 }
852 break;
853 default:
854 break;
855 }
856 s->pos = 0;
857 s->len = 0;
858 s->state = STATE_COLLECTING_DATA;
859 }
860
861 static void decode_new_cmd(Flash *s, uint32_t value)
862 {
863 s->cmd_in_progress = value;
864 int i;
865 DB_PRINT_L(0, "decoded new command:%x\n", value);
866
867 if (value != RESET_MEMORY) {
868 s->reset_enable = false;
869 }
870
871 switch (value) {
872
873 case ERASE_4K:
874 case ERASE4_4K:
875 case ERASE_32K:
876 case ERASE4_32K:
877 case ERASE_SECTOR:
878 case ERASE4_SECTOR:
879 case READ:
880 case READ4:
881 case DPP:
882 case QPP:
883 case QPP_4:
884 case PP:
885 case PP4:
886 case PP4_4:
887 s->needed_bytes = get_addr_length(s);
888 s->pos = 0;
889 s->len = 0;
890 s->state = STATE_COLLECTING_DATA;
891 break;
892
893 case FAST_READ:
894 case FAST_READ4:
895 case DOR:
896 case DOR4:
897 case QOR:
898 case QOR4:
899 decode_fast_read_cmd(s);
900 break;
901
902 case DIOR:
903 case DIOR4:
904 decode_dio_read_cmd(s);
905 break;
906
907 case QIOR:
908 case QIOR4:
909 decode_qio_read_cmd(s);
910 break;
911
912 case WRSR:
913 if (s->write_enable) {
914 switch (get_man(s)) {
915 case MAN_SPANSION:
916 s->needed_bytes = 2;
917 s->state = STATE_COLLECTING_DATA;
918 break;
919 case MAN_MACRONIX:
920 s->needed_bytes = 2;
921 s->state = STATE_COLLECTING_VAR_LEN_DATA;
922 break;
923 default:
924 s->needed_bytes = 1;
925 s->state = STATE_COLLECTING_DATA;
926 }
927 s->pos = 0;
928 }
929 break;
930
931 case WRDI:
932 s->write_enable = false;
933 break;
934 case WREN:
935 s->write_enable = true;
936 break;
937
938 case RDSR:
939 s->data[0] = (!!s->write_enable) << 1;
940 if (get_man(s) == MAN_MACRONIX) {
941 s->data[0] |= (!!s->quad_enable) << 6;
942 }
943 s->pos = 0;
944 s->len = 1;
945 s->state = STATE_READING_DATA;
946 break;
947
948 case READ_FSR:
949 s->data[0] = FSR_FLASH_READY;
950 if (s->four_bytes_address_mode) {
951 s->data[0] |= FSR_4BYTE_ADDR_MODE_ENABLED;
952 }
953 s->pos = 0;
954 s->len = 1;
955 s->state = STATE_READING_DATA;
956 break;
957
958 case JEDEC_READ:
959 DB_PRINT_L(0, "populated jedec code\n");
960 for (i = 0; i < s->pi->id_len; i++) {
961 s->data[i] = s->pi->id[i];
962 }
963
964 s->len = s->pi->id_len;
965 s->pos = 0;
966 s->state = STATE_READING_DATA;
967 break;
968
969 case RDCR:
970 s->data[0] = s->volatile_cfg & 0xFF;
971 s->data[0] |= (!!s->four_bytes_address_mode) << 5;
972 s->pos = 0;
973 s->len = 1;
974 s->state = STATE_READING_DATA;
975 break;
976
977 case BULK_ERASE:
978 if (s->write_enable) {
979 DB_PRINT_L(0, "chip erase\n");
980 flash_erase(s, 0, BULK_ERASE);
981 } else {
982 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: chip erase with write "
983 "protect!\n");
984 }
985 break;
986 case NOP:
987 break;
988 case EN_4BYTE_ADDR:
989 s->four_bytes_address_mode = true;
990 break;
991 case EX_4BYTE_ADDR:
992 s->four_bytes_address_mode = false;
993 break;
994 case EXTEND_ADDR_READ:
995 s->data[0] = s->ear;
996 s->pos = 0;
997 s->len = 1;
998 s->state = STATE_READING_DATA;
999 break;
1000 case EXTEND_ADDR_WRITE:
1001 if (s->write_enable) {
1002 s->needed_bytes = 1;
1003 s->pos = 0;
1004 s->len = 0;
1005 s->state = STATE_COLLECTING_DATA;
1006 }
1007 break;
1008 case RNVCR:
1009 s->data[0] = s->nonvolatile_cfg & 0xFF;
1010 s->data[1] = (s->nonvolatile_cfg >> 8) & 0xFF;
1011 s->pos = 0;
1012 s->len = 2;
1013 s->state = STATE_READING_DATA;
1014 break;
1015 case WNVCR:
1016 if (s->write_enable && get_man(s) == MAN_NUMONYX) {
1017 s->needed_bytes = 2;
1018 s->pos = 0;
1019 s->len = 0;
1020 s->state = STATE_COLLECTING_DATA;
1021 }
1022 break;
1023 case RVCR:
1024 s->data[0] = s->volatile_cfg & 0xFF;
1025 s->pos = 0;
1026 s->len = 1;
1027 s->state = STATE_READING_DATA;
1028 break;
1029 case WVCR:
1030 if (s->write_enable) {
1031 s->needed_bytes = 1;
1032 s->pos = 0;
1033 s->len = 0;
1034 s->state = STATE_COLLECTING_DATA;
1035 }
1036 break;
1037 case REVCR:
1038 s->data[0] = s->enh_volatile_cfg & 0xFF;
1039 s->pos = 0;
1040 s->len = 1;
1041 s->state = STATE_READING_DATA;
1042 break;
1043 case WEVCR:
1044 if (s->write_enable) {
1045 s->needed_bytes = 1;
1046 s->pos = 0;
1047 s->len = 0;
1048 s->state = STATE_COLLECTING_DATA;
1049 }
1050 break;
1051 case RESET_ENABLE:
1052 s->reset_enable = true;
1053 break;
1054 case RESET_MEMORY:
1055 if (s->reset_enable) {
1056 reset_memory(s);
1057 }
1058 break;
1059 case RDCR_EQIO:
1060 switch (get_man(s)) {
1061 case MAN_SPANSION:
1062 s->data[0] = (!!s->quad_enable) << 1;
1063 s->pos = 0;
1064 s->len = 1;
1065 s->state = STATE_READING_DATA;
1066 break;
1067 case MAN_MACRONIX:
1068 s->quad_enable = true;
1069 break;
1070 default:
1071 break;
1072 }
1073 break;
1074 case RSTQIO:
1075 s->quad_enable = false;
1076 break;
1077 default:
1078 qemu_log_mask(LOG_GUEST_ERROR, "M25P80: Unknown cmd %x\n", value);
1079 break;
1080 }
1081 }
1082
1083 static int m25p80_cs(SSISlave *ss, bool select)
1084 {
1085 Flash *s = M25P80(ss);
1086
1087 if (select) {
1088 if (s->state == STATE_COLLECTING_VAR_LEN_DATA) {
1089 complete_collecting_data(s);
1090 }
1091 s->len = 0;
1092 s->pos = 0;
1093 s->state = STATE_IDLE;
1094 flash_sync_dirty(s, -1);
1095 }
1096
1097 DB_PRINT_L(0, "%sselect\n", select ? "de" : "");
1098
1099 return 0;
1100 }
1101
1102 static uint32_t m25p80_transfer8(SSISlave *ss, uint32_t tx)
1103 {
1104 Flash *s = M25P80(ss);
1105 uint32_t r = 0;
1106
1107 switch (s->state) {
1108
1109 case STATE_PAGE_PROGRAM:
1110 DB_PRINT_L(1, "page program cur_addr=%#" PRIx32 " data=%" PRIx8 "\n",
1111 s->cur_addr, (uint8_t)tx);
1112 flash_write8(s, s->cur_addr, (uint8_t)tx);
1113 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1114 break;
1115
1116 case STATE_READ:
1117 r = s->storage[s->cur_addr];
1118 DB_PRINT_L(1, "READ 0x%" PRIx32 "=%" PRIx8 "\n", s->cur_addr,
1119 (uint8_t)r);
1120 s->cur_addr = (s->cur_addr + 1) & (s->size - 1);
1121 break;
1122
1123 case STATE_COLLECTING_DATA:
1124 case STATE_COLLECTING_VAR_LEN_DATA:
1125
1126 if (s->len >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1127 qemu_log_mask(LOG_GUEST_ERROR,
1128 "M25P80: Write overrun internal data buffer. "
1129 "SPI controller (QEMU emulator or guest driver) "
1130 "is misbehaving\n");
1131 s->len = s->pos = 0;
1132 s->state = STATE_IDLE;
1133 break;
1134 }
1135
1136 s->data[s->len] = (uint8_t)tx;
1137 s->len++;
1138
1139 if (s->len == s->needed_bytes) {
1140 complete_collecting_data(s);
1141 }
1142 break;
1143
1144 case STATE_READING_DATA:
1145
1146 if (s->pos >= M25P80_INTERNAL_DATA_BUFFER_SZ) {
1147 qemu_log_mask(LOG_GUEST_ERROR,
1148 "M25P80: Read overrun internal data buffer. "
1149 "SPI controller (QEMU emulator or guest driver) "
1150 "is misbehaving\n");
1151 s->len = s->pos = 0;
1152 s->state = STATE_IDLE;
1153 break;
1154 }
1155
1156 r = s->data[s->pos];
1157 s->pos++;
1158 if (s->pos == s->len) {
1159 s->pos = 0;
1160 s->state = STATE_IDLE;
1161 }
1162 break;
1163
1164 default:
1165 case STATE_IDLE:
1166 decode_new_cmd(s, (uint8_t)tx);
1167 break;
1168 }
1169
1170 return r;
1171 }
1172
1173 static void m25p80_realize(SSISlave *ss, Error **errp)
1174 {
1175 Flash *s = M25P80(ss);
1176 M25P80Class *mc = M25P80_GET_CLASS(s);
1177
1178 s->pi = mc->pi;
1179
1180 s->size = s->pi->sector_size * s->pi->n_sectors;
1181 s->dirty_page = -1;
1182
1183 if (s->blk) {
1184 DB_PRINT_L(0, "Binding to IF_MTD drive\n");
1185 s->storage = blk_blockalign(s->blk, s->size);
1186
1187 if (blk_pread(s->blk, 0, s->storage, s->size) != s->size) {
1188 error_setg(errp, "failed to read the initial flash content");
1189 return;
1190 }
1191 } else {
1192 DB_PRINT_L(0, "No BDRV - binding to RAM\n");
1193 s->storage = blk_blockalign(NULL, s->size);
1194 memset(s->storage, 0xFF, s->size);
1195 }
1196 }
1197
1198 static void m25p80_reset(DeviceState *d)
1199 {
1200 Flash *s = M25P80(d);
1201
1202 reset_memory(s);
1203 }
1204
1205 static void m25p80_pre_save(void *opaque)
1206 {
1207 flash_sync_dirty((Flash *)opaque, -1);
1208 }
1209
1210 static Property m25p80_properties[] = {
1211 /* This is default value for Micron flash */
1212 DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF),
1213 DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0),
1214 DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8),
1215 DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2),
1216 DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10),
1217 DEFINE_PROP_DRIVE("drive", Flash, blk),
1218 DEFINE_PROP_END_OF_LIST(),
1219 };
1220
1221 static const VMStateDescription vmstate_m25p80 = {
1222 .name = "m25p80",
1223 .version_id = 0,
1224 .minimum_version_id = 0,
1225 .pre_save = m25p80_pre_save,
1226 .fields = (VMStateField[]) {
1227 VMSTATE_UINT8(state, Flash),
1228 VMSTATE_UINT8_ARRAY(data, Flash, M25P80_INTERNAL_DATA_BUFFER_SZ),
1229 VMSTATE_UINT32(len, Flash),
1230 VMSTATE_UINT32(pos, Flash),
1231 VMSTATE_UINT8(needed_bytes, Flash),
1232 VMSTATE_UINT8(cmd_in_progress, Flash),
1233 VMSTATE_UINT32(cur_addr, Flash),
1234 VMSTATE_BOOL(write_enable, Flash),
1235 VMSTATE_BOOL(reset_enable, Flash),
1236 VMSTATE_UINT8(ear, Flash),
1237 VMSTATE_BOOL(four_bytes_address_mode, Flash),
1238 VMSTATE_UINT32(nonvolatile_cfg, Flash),
1239 VMSTATE_UINT32(volatile_cfg, Flash),
1240 VMSTATE_UINT32(enh_volatile_cfg, Flash),
1241 VMSTATE_BOOL(quad_enable, Flash),
1242 VMSTATE_UINT8(spansion_cr1nv, Flash),
1243 VMSTATE_UINT8(spansion_cr2nv, Flash),
1244 VMSTATE_UINT8(spansion_cr3nv, Flash),
1245 VMSTATE_UINT8(spansion_cr4nv, Flash),
1246 VMSTATE_END_OF_LIST()
1247 }
1248 };
1249
1250 static void m25p80_class_init(ObjectClass *klass, void *data)
1251 {
1252 DeviceClass *dc = DEVICE_CLASS(klass);
1253 SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
1254 M25P80Class *mc = M25P80_CLASS(klass);
1255
1256 k->realize = m25p80_realize;
1257 k->transfer = m25p80_transfer8;
1258 k->set_cs = m25p80_cs;
1259 k->cs_polarity = SSI_CS_LOW;
1260 dc->vmsd = &vmstate_m25p80;
1261 dc->props = m25p80_properties;
1262 dc->reset = m25p80_reset;
1263 mc->pi = data;
1264 }
1265
1266 static const TypeInfo m25p80_info = {
1267 .name = TYPE_M25P80,
1268 .parent = TYPE_SSI_SLAVE,
1269 .instance_size = sizeof(Flash),
1270 .class_size = sizeof(M25P80Class),
1271 .abstract = true,
1272 };
1273
1274 static void m25p80_register_types(void)
1275 {
1276 int i;
1277
1278 type_register_static(&m25p80_info);
1279 for (i = 0; i < ARRAY_SIZE(known_devices); ++i) {
1280 TypeInfo ti = {
1281 .name = known_devices[i].part_name,
1282 .parent = TYPE_M25P80,
1283 .class_init = m25p80_class_init,
1284 .class_data = (void *)&known_devices[i],
1285 };
1286 type_register(&ti);
1287 }
1288 }
1289
1290 type_init(m25p80_register_types)
AR7 emulation for QEMU