2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/i386/pc.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "hw/isa/isa.h"
30 #include "hw/sysbus.h"
31 #include "qemu/range.h"
32 #include "hw/xen/xen.h"
33 #include "hw/pci-host/pam.h"
34 #include "sysemu/sysemu.h"
35 #include "hw/i386/ioapic.h"
36 #include "qapi/visitor.h"
39 * I440FX chipset data sheet.
40 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
43 #define I440FX_PCI_HOST_BRIDGE(obj) \
44 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
46 typedef struct I440FXState
{
47 PCIHostState parent_obj
;
49 uint64_t pci_hole64_size
;
50 uint32_t short_root_bus
;
53 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
54 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
55 #define XEN_PIIX_NUM_PIRQS 128ULL
56 #define PIIX_PIRQC 0x60
59 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
60 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
62 #define RCR_IOPORT 0xcf9
64 typedef struct PIIX3State
{
68 * bitmap to track pic levels.
69 * The pic level is the logical OR of all the PCI irqs mapped to it
70 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
72 * PIRQ is mapped to PIC pins, we track it by
73 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
74 * pic_irq * PIIX_NUM_PIRQS + pirq
76 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
77 #error "unable to encode pic state in 64bit in pic_levels."
83 /* This member isn't used. Just for save/load compatibility */
84 int32_t pci_irq_levels_vmstate
[PIIX_NUM_PIRQS
];
86 /* Reset Control Register contents */
89 /* IO memory region for Reset Control Register (RCR_IOPORT) */
93 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
94 #define PIIX3_PCI_DEVICE(obj) \
95 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
97 #define I440FX_PCI_DEVICE(obj) \
98 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
100 struct PCII440FXState
{
102 PCIDevice parent_obj
;
105 MemoryRegion
*system_memory
;
106 MemoryRegion
*pci_address_space
;
107 MemoryRegion
*ram_memory
;
108 PAMMemoryRegion pam_regions
[13];
109 MemoryRegion smram_region
;
110 MemoryRegion smram
, low_smram
;
114 #define I440FX_PAM 0x59
115 #define I440FX_PAM_SIZE 7
116 #define I440FX_SMRAM 0x72
118 /* Older coreboot versions (4.0 and older) read a config register that doesn't
119 * exist in real hardware, to get the RAM size from QEMU.
121 #define I440FX_COREBOOT_RAM_SIZE 0x57
123 static void piix3_set_irq(void *opaque
, int pirq
, int level
);
124 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pci_intx
);
125 static void piix3_write_config_xen(PCIDevice
*dev
,
126 uint32_t address
, uint32_t val
, int len
);
128 /* return the global irq number corresponding to a given device irq
129 pin. We could also use the bus number to have a more precise
131 static int pci_slot_get_pirq(PCIDevice
*pci_dev
, int pci_intx
)
134 slot_addend
= (pci_dev
->devfn
>> 3) - 1;
135 return (pci_intx
+ slot_addend
) & 3;
138 static void i440fx_update_memory_mappings(PCII440FXState
*d
)
141 PCIDevice
*pd
= PCI_DEVICE(d
);
143 memory_region_transaction_begin();
144 for (i
= 0; i
< 13; i
++) {
145 pam_update(&d
->pam_regions
[i
], i
,
146 pd
->config
[I440FX_PAM
+ ((i
+ 1) / 2)]);
148 memory_region_set_enabled(&d
->smram_region
,
149 !(pd
->config
[I440FX_SMRAM
] & SMRAM_D_OPEN
));
150 memory_region_set_enabled(&d
->smram
,
151 pd
->config
[I440FX_SMRAM
] & SMRAM_G_SMRAME
);
152 memory_region_transaction_commit();
156 static void i440fx_write_config(PCIDevice
*dev
,
157 uint32_t address
, uint32_t val
, int len
)
159 PCII440FXState
*d
= I440FX_PCI_DEVICE(dev
);
161 /* XXX: implement SMRAM.D_LOCK */
162 pci_default_write_config(dev
, address
, val
, len
);
163 if (ranges_overlap(address
, len
, I440FX_PAM
, I440FX_PAM_SIZE
) ||
164 range_covers_byte(address
, len
, I440FX_SMRAM
)) {
165 i440fx_update_memory_mappings(d
);
169 static int i440fx_load_old(QEMUFile
* f
, void *opaque
, int version_id
)
171 PCII440FXState
*d
= opaque
;
172 PCIDevice
*pd
= PCI_DEVICE(d
);
176 ret
= pci_device_load(pd
, f
);
179 i440fx_update_memory_mappings(d
);
180 qemu_get_8s(f
, &smm_enabled
);
182 if (version_id
== 2) {
183 for (i
= 0; i
< PIIX_NUM_PIRQS
; i
++) {
184 qemu_get_be32(f
); /* dummy load for compatibility */
191 static int i440fx_post_load(void *opaque
, int version_id
)
193 PCII440FXState
*d
= opaque
;
195 i440fx_update_memory_mappings(d
);
199 static const VMStateDescription vmstate_i440fx
= {
202 .minimum_version_id
= 3,
203 .minimum_version_id_old
= 1,
204 .load_state_old
= i440fx_load_old
,
205 .post_load
= i440fx_post_load
,
206 .fields
= (VMStateField
[]) {
207 VMSTATE_PCI_DEVICE(parent_obj
, PCII440FXState
),
208 /* Used to be smm_enabled, which was basically always zero because
209 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
212 VMSTATE_END_OF_LIST()
216 static void i440fx_pcihost_get_pci_hole_start(Object
*obj
, Visitor
*v
,
217 void *opaque
, const char *name
,
220 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
221 uint32_t value
= s
->pci_info
.w32
.begin
;
223 visit_type_uint32(v
, &value
, name
, errp
);
226 static void i440fx_pcihost_get_pci_hole_end(Object
*obj
, Visitor
*v
,
227 void *opaque
, const char *name
,
230 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(obj
);
231 uint32_t value
= s
->pci_info
.w32
.end
;
233 visit_type_uint32(v
, &value
, name
, errp
);
236 static void i440fx_pcihost_get_pci_hole64_start(Object
*obj
, Visitor
*v
,
237 void *opaque
, const char *name
,
240 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
243 pci_bus_get_w64_range(h
->bus
, &w64
);
245 visit_type_uint64(v
, &w64
.begin
, name
, errp
);
248 static void i440fx_pcihost_get_pci_hole64_end(Object
*obj
, Visitor
*v
,
249 void *opaque
, const char *name
,
252 PCIHostState
*h
= PCI_HOST_BRIDGE(obj
);
255 pci_bus_get_w64_range(h
->bus
, &w64
);
257 visit_type_uint64(v
, &w64
.end
, name
, errp
);
260 static void i440fx_pcihost_initfn(Object
*obj
)
262 PCIHostState
*s
= PCI_HOST_BRIDGE(obj
);
263 I440FXState
*d
= I440FX_PCI_HOST_BRIDGE(obj
);
265 memory_region_init_io(&s
->conf_mem
, obj
, &pci_host_conf_le_ops
, s
,
267 memory_region_init_io(&s
->data_mem
, obj
, &pci_host_data_le_ops
, s
,
270 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_START
, "int",
271 i440fx_pcihost_get_pci_hole_start
,
272 NULL
, NULL
, NULL
, NULL
);
274 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE_END
, "int",
275 i440fx_pcihost_get_pci_hole_end
,
276 NULL
, NULL
, NULL
, NULL
);
278 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_START
, "int",
279 i440fx_pcihost_get_pci_hole64_start
,
280 NULL
, NULL
, NULL
, NULL
);
282 object_property_add(obj
, PCI_HOST_PROP_PCI_HOLE64_END
, "int",
283 i440fx_pcihost_get_pci_hole64_end
,
284 NULL
, NULL
, NULL
, NULL
);
286 d
->pci_info
.w32
.end
= IO_APIC_DEFAULT_ADDRESS
;
289 static void i440fx_pcihost_realize(DeviceState
*dev
, Error
**errp
)
291 PCIHostState
*s
= PCI_HOST_BRIDGE(dev
);
292 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
294 sysbus_add_io(sbd
, 0xcf8, &s
->conf_mem
);
295 sysbus_init_ioports(sbd
, 0xcf8, 4);
297 sysbus_add_io(sbd
, 0xcfc, &s
->data_mem
);
298 sysbus_init_ioports(sbd
, 0xcfc, 4);
301 static void i440fx_realize(PCIDevice
*dev
, Error
**errp
)
303 dev
->config
[I440FX_SMRAM
] = 0x02;
306 PCIBus
*i440fx_init(const char *host_type
, const char *pci_type
,
307 PCII440FXState
**pi440fx_state
,
309 ISABus
**isa_bus
, qemu_irq
*pic
,
310 MemoryRegion
*address_space_mem
,
311 MemoryRegion
*address_space_io
,
313 ram_addr_t below_4g_mem_size
,
314 ram_addr_t above_4g_mem_size
,
315 MemoryRegion
*pci_address_space
,
316 MemoryRegion
*ram_memory
)
327 dev
= qdev_create(NULL
, host_type
);
328 s
= PCI_HOST_BRIDGE(dev
);
329 b
= pci_bus_new(dev
, NULL
, pci_address_space
,
330 address_space_io
, 0, TYPE_PCI_BUS
);
332 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev
), NULL
);
333 qdev_init_nofail(dev
);
335 d
= pci_create_simple(b
, 0, pci_type
);
336 *pi440fx_state
= I440FX_PCI_DEVICE(d
);
338 f
->system_memory
= address_space_mem
;
339 f
->pci_address_space
= pci_address_space
;
340 f
->ram_memory
= ram_memory
;
342 i440fx
= I440FX_PCI_HOST_BRIDGE(dev
);
343 i440fx
->pci_info
.w32
.begin
= below_4g_mem_size
;
345 /* setup pci memory mapping */
346 pc_pci_as_mapping_init(OBJECT(f
), f
->system_memory
,
347 f
->pci_address_space
);
349 /* if *disabled* show SMRAM to all CPUs */
350 memory_region_init_alias(&f
->smram_region
, OBJECT(d
), "smram-region",
351 f
->pci_address_space
, 0xa0000, 0x20000);
352 memory_region_add_subregion_overlap(f
->system_memory
, 0xa0000,
353 &f
->smram_region
, 1);
354 memory_region_set_enabled(&f
->smram_region
, true);
356 /* smram, as seen by SMM CPUs */
357 memory_region_init(&f
->smram
, OBJECT(d
), "smram", 1ull << 32);
358 memory_region_set_enabled(&f
->smram
, true);
359 memory_region_init_alias(&f
->low_smram
, OBJECT(d
), "smram-low",
360 f
->ram_memory
, 0xa0000, 0x20000);
361 memory_region_set_enabled(&f
->low_smram
, true);
362 memory_region_add_subregion(&f
->smram
, 0xa0000, &f
->low_smram
);
363 object_property_add_const_link(qdev_get_machine(), "smram",
364 OBJECT(&f
->smram
), &error_abort
);
366 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
367 &f
->pam_regions
[0], PAM_BIOS_BASE
, PAM_BIOS_SIZE
);
368 for (i
= 0; i
< 12; ++i
) {
369 init_pam(dev
, f
->ram_memory
, f
->system_memory
, f
->pci_address_space
,
370 &f
->pam_regions
[i
+1], PAM_EXPAN_BASE
+ i
* PAM_EXPAN_SIZE
,
374 /* Xen supports additional interrupt routes from the PCI devices to
375 * the IOAPIC: the four pins of each PCI device on the bus are also
376 * connected to the IOAPIC directly.
377 * These additional routes can be discovered through ACPI. */
379 PCIDevice
*pci_dev
= pci_create_simple_multifunction(b
,
380 -1, true, "PIIX3-xen");
381 piix3
= PIIX3_PCI_DEVICE(pci_dev
);
382 pci_bus_irqs(b
, xen_piix3_set_irq
, xen_pci_slot_get_pirq
,
383 piix3
, XEN_PIIX_NUM_PIRQS
);
385 PCIDevice
*pci_dev
= pci_create_simple_multifunction(b
,
387 piix3
= PIIX3_PCI_DEVICE(pci_dev
);
388 pci_bus_irqs(b
, piix3_set_irq
, pci_slot_get_pirq
, piix3
,
390 pci_bus_set_route_irq_fn(b
, piix3_route_intx_pin_to_irq
);
393 *isa_bus
= ISA_BUS(qdev_get_child_bus(DEVICE(piix3
), "isa.0"));
395 *piix3_devfn
= piix3
->dev
.devfn
;
397 ram_size
= ram_size
/ 8 / 1024 / 1024;
398 if (ram_size
> 255) {
401 d
->config
[I440FX_COREBOOT_RAM_SIZE
] = ram_size
;
403 i440fx_update_memory_mappings(f
);
408 PCIBus
*find_i440fx(void)
410 PCIHostState
*s
= OBJECT_CHECK(PCIHostState
,
411 object_resolve_path("/machine/i440fx", NULL
),
412 TYPE_PCI_HOST_BRIDGE
);
413 return s
? s
->bus
: NULL
;
416 /* PIIX3 PCI to ISA bridge */
417 static void piix3_set_irq_pic(PIIX3State
*piix3
, int pic_irq
)
419 qemu_set_irq(piix3
->pic
[pic_irq
],
420 !!(piix3
->pic_levels
&
421 (((1ULL << PIIX_NUM_PIRQS
) - 1) <<
422 (pic_irq
* PIIX_NUM_PIRQS
))));
425 static void piix3_set_irq_level_internal(PIIX3State
*piix3
, int pirq
, int level
)
430 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
431 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
435 mask
= 1ULL << ((pic_irq
* PIIX_NUM_PIRQS
) + pirq
);
436 piix3
->pic_levels
&= ~mask
;
437 piix3
->pic_levels
|= mask
* !!level
;
440 static void piix3_set_irq_level(PIIX3State
*piix3
, int pirq
, int level
)
444 pic_irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pirq
];
445 if (pic_irq
>= PIIX_NUM_PIC_IRQS
) {
449 piix3_set_irq_level_internal(piix3
, pirq
, level
);
451 piix3_set_irq_pic(piix3
, pic_irq
);
454 static void piix3_set_irq(void *opaque
, int pirq
, int level
)
456 PIIX3State
*piix3
= opaque
;
457 piix3_set_irq_level(piix3
, pirq
, level
);
460 static PCIINTxRoute
piix3_route_intx_pin_to_irq(void *opaque
, int pin
)
462 PIIX3State
*piix3
= opaque
;
463 int irq
= piix3
->dev
.config
[PIIX_PIRQC
+ pin
];
466 if (irq
< PIIX_NUM_PIC_IRQS
) {
467 route
.mode
= PCI_INTX_ENABLED
;
470 route
.mode
= PCI_INTX_DISABLED
;
476 /* irq routing is changed. so rebuild bitmap */
477 static void piix3_update_irq_levels(PIIX3State
*piix3
)
481 piix3
->pic_levels
= 0;
482 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
483 piix3_set_irq_level(piix3
, pirq
,
484 pci_bus_get_irq_level(piix3
->dev
.bus
, pirq
));
488 static void piix3_write_config(PCIDevice
*dev
,
489 uint32_t address
, uint32_t val
, int len
)
491 pci_default_write_config(dev
, address
, val
, len
);
492 if (ranges_overlap(address
, len
, PIIX_PIRQC
, 4)) {
493 PIIX3State
*piix3
= PIIX3_PCI_DEVICE(dev
);
496 pci_bus_fire_intx_routing_notifier(piix3
->dev
.bus
);
497 piix3_update_irq_levels(piix3
);
498 for (pic_irq
= 0; pic_irq
< PIIX_NUM_PIC_IRQS
; pic_irq
++) {
499 piix3_set_irq_pic(piix3
, pic_irq
);
504 static void piix3_write_config_xen(PCIDevice
*dev
,
505 uint32_t address
, uint32_t val
, int len
)
507 xen_piix_pci_write_config_client(address
, val
, len
);
508 piix3_write_config(dev
, address
, val
, len
);
511 static void piix3_reset(void *opaque
)
513 PIIX3State
*d
= opaque
;
514 uint8_t *pci_conf
= d
->dev
.config
;
516 pci_conf
[0x04] = 0x07; /* master, memory and I/O */
517 pci_conf
[0x05] = 0x00;
518 pci_conf
[0x06] = 0x00;
519 pci_conf
[0x07] = 0x02; /* PCI_status_devsel_medium */
520 pci_conf
[0x4c] = 0x4d;
521 pci_conf
[0x4e] = 0x03;
522 pci_conf
[0x4f] = 0x00;
523 pci_conf
[0x60] = 0x80;
524 pci_conf
[0x61] = 0x80;
525 pci_conf
[0x62] = 0x80;
526 pci_conf
[0x63] = 0x80;
527 pci_conf
[0x69] = 0x02;
528 pci_conf
[0x70] = 0x80;
529 pci_conf
[0x76] = 0x0c;
530 pci_conf
[0x77] = 0x0c;
531 pci_conf
[0x78] = 0x02;
532 pci_conf
[0x79] = 0x00;
533 pci_conf
[0x80] = 0x00;
534 pci_conf
[0x82] = 0x00;
535 pci_conf
[0xa0] = 0x08;
536 pci_conf
[0xa2] = 0x00;
537 pci_conf
[0xa3] = 0x00;
538 pci_conf
[0xa4] = 0x00;
539 pci_conf
[0xa5] = 0x00;
540 pci_conf
[0xa6] = 0x00;
541 pci_conf
[0xa7] = 0x00;
542 pci_conf
[0xa8] = 0x0f;
543 pci_conf
[0xaa] = 0x00;
544 pci_conf
[0xab] = 0x00;
545 pci_conf
[0xac] = 0x00;
546 pci_conf
[0xae] = 0x00;
552 static int piix3_post_load(void *opaque
, int version_id
)
554 PIIX3State
*piix3
= opaque
;
557 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
558 * might bring the system to a different state than the saved one;
559 * for example, the interrupt could be masked but the i8259 would
560 * not know that yet and would trigger an interrupt in the CPU.
562 * Here, we update irq levels without raising the interrupt.
563 * Interrupt state will be deserialized separately through the i8259.
565 piix3
->pic_levels
= 0;
566 for (pirq
= 0; pirq
< PIIX_NUM_PIRQS
; pirq
++) {
567 piix3_set_irq_level_internal(piix3
, pirq
,
568 pci_bus_get_irq_level(piix3
->dev
.bus
, pirq
));
573 static void piix3_pre_save(void *opaque
)
576 PIIX3State
*piix3
= opaque
;
578 for (i
= 0; i
< ARRAY_SIZE(piix3
->pci_irq_levels_vmstate
); i
++) {
579 piix3
->pci_irq_levels_vmstate
[i
] =
580 pci_bus_get_irq_level(piix3
->dev
.bus
, i
);
584 static bool piix3_rcr_needed(void *opaque
)
586 PIIX3State
*piix3
= opaque
;
588 return (piix3
->rcr
!= 0);
591 static const VMStateDescription vmstate_piix3_rcr
= {
594 .minimum_version_id
= 1,
595 .needed
= piix3_rcr_needed
,
596 .fields
= (VMStateField
[]) {
597 VMSTATE_UINT8(rcr
, PIIX3State
),
598 VMSTATE_END_OF_LIST()
602 static const VMStateDescription vmstate_piix3
= {
605 .minimum_version_id
= 2,
606 .post_load
= piix3_post_load
,
607 .pre_save
= piix3_pre_save
,
608 .fields
= (VMStateField
[]) {
609 VMSTATE_PCI_DEVICE(dev
, PIIX3State
),
610 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate
, PIIX3State
,
612 VMSTATE_END_OF_LIST()
614 .subsections
= (const VMStateDescription
*[]) {
621 static void rcr_write(void *opaque
, hwaddr addr
, uint64_t val
, unsigned len
)
623 PIIX3State
*d
= opaque
;
626 qemu_system_reset_request();
629 d
->rcr
= val
& 2; /* keep System Reset type only */
632 static uint64_t rcr_read(void *opaque
, hwaddr addr
, unsigned len
)
634 PIIX3State
*d
= opaque
;
639 static const MemoryRegionOps rcr_ops
= {
642 .endianness
= DEVICE_LITTLE_ENDIAN
645 static void piix3_realize(PCIDevice
*dev
, Error
**errp
)
647 PIIX3State
*d
= PIIX3_PCI_DEVICE(dev
);
649 isa_bus_new(DEVICE(d
), get_system_memory(),
650 pci_address_space_io(dev
));
652 memory_region_init_io(&d
->rcr_mem
, OBJECT(dev
), &rcr_ops
, d
,
653 "piix3-reset-control", 1);
654 memory_region_add_subregion_overlap(pci_address_space_io(dev
), RCR_IOPORT
,
657 qemu_register_reset(piix3_reset
, d
);
660 static void pci_piix3_class_init(ObjectClass
*klass
, void *data
)
662 DeviceClass
*dc
= DEVICE_CLASS(klass
);
663 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
665 dc
->desc
= "ISA bridge";
666 dc
->vmsd
= &vmstate_piix3
;
667 dc
->hotpluggable
= false;
668 k
->realize
= piix3_realize
;
669 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
670 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
671 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_0
;
672 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
674 * Reason: part of PIIX3 southbridge, needs to be wired up by
675 * pc_piix.c's pc_init1()
677 dc
->cannot_instantiate_with_device_add_yet
= true;
680 static const TypeInfo piix3_pci_type_info
= {
681 .name
= TYPE_PIIX3_PCI_DEVICE
,
682 .parent
= TYPE_PCI_DEVICE
,
683 .instance_size
= sizeof(PIIX3State
),
685 .class_init
= pci_piix3_class_init
,
688 static void piix3_class_init(ObjectClass
*klass
, void *data
)
690 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
692 k
->config_write
= piix3_write_config
;
695 static const TypeInfo piix3_info
= {
697 .parent
= TYPE_PIIX3_PCI_DEVICE
,
698 .class_init
= piix3_class_init
,
701 static void piix3_xen_class_init(ObjectClass
*klass
, void *data
)
703 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
705 k
->config_write
= piix3_write_config_xen
;
708 static const TypeInfo piix3_xen_info
= {
710 .parent
= TYPE_PIIX3_PCI_DEVICE
,
711 .class_init
= piix3_xen_class_init
,
714 static void i440fx_class_init(ObjectClass
*klass
, void *data
)
716 DeviceClass
*dc
= DEVICE_CLASS(klass
);
717 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
719 k
->realize
= i440fx_realize
;
720 k
->config_write
= i440fx_write_config
;
721 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
722 k
->device_id
= PCI_DEVICE_ID_INTEL_82441
;
724 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
725 dc
->desc
= "Host bridge";
726 dc
->vmsd
= &vmstate_i440fx
;
728 * PCI-facing part of the host bridge, not usable without the
729 * host-facing part, which can't be device_add'ed, yet.
731 dc
->cannot_instantiate_with_device_add_yet
= true;
732 dc
->hotpluggable
= false;
735 static const TypeInfo i440fx_info
= {
736 .name
= TYPE_I440FX_PCI_DEVICE
,
737 .parent
= TYPE_PCI_DEVICE
,
738 .instance_size
= sizeof(PCII440FXState
),
739 .class_init
= i440fx_class_init
,
742 /* IGD Passthrough Host Bridge. */
748 /* Here we just expose minimal host bridge offset subset. */
749 static const IGDHostInfo igd_host_bridge_infos
[] = {
750 {0x08, 2}, /* revision id */
751 {0x2c, 2}, /* sybsystem vendor id */
752 {0x2e, 2}, /* sybsystem id */
753 {0x50, 2}, /* SNB: processor graphics control register */
754 {0x52, 2}, /* processor graphics control register */
755 {0xa4, 4}, /* SNB: graphics base of stolen memory */
756 {0xa8, 4}, /* SNB: base of GTT stolen memory */
759 static int host_pci_config_read(int pos
, int len
, uint32_t val
)
763 ssize_t size
= sizeof(path
);
764 /* Access real host bridge. */
765 int rc
= snprintf(path
, size
, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
766 0, 0, 0, 0, "config");
768 if (rc
>= size
|| rc
< 0) {
772 config_fd
= open(path
, O_RDWR
);
777 if (lseek(config_fd
, pos
, SEEK_SET
) != pos
) {
781 rc
= read(config_fd
, (uint8_t *)&val
, len
);
782 } while (rc
< 0 && (errno
== EINTR
|| errno
== EAGAIN
));
790 static int igd_pt_i440fx_initfn(struct PCIDevice
*pci_dev
)
796 num
= ARRAY_SIZE(igd_host_bridge_infos
);
797 for (i
= 0; i
< num
; i
++) {
798 pos
= igd_host_bridge_infos
[i
].offset
;
799 len
= igd_host_bridge_infos
[i
].len
;
800 rc
= host_pci_config_read(pos
, len
, val
);
804 pci_default_write_config(pci_dev
, pos
, val
, len
);
810 static void igd_passthrough_i440fx_class_init(ObjectClass
*klass
, void *data
)
812 DeviceClass
*dc
= DEVICE_CLASS(klass
);
813 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
815 k
->init
= igd_pt_i440fx_initfn
;
816 dc
->desc
= "IGD Passthrough Host bridge";
819 static const TypeInfo igd_passthrough_i440fx_info
= {
820 .name
= TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
,
821 .parent
= TYPE_I440FX_PCI_DEVICE
,
822 .instance_size
= sizeof(PCII440FXState
),
823 .class_init
= igd_passthrough_i440fx_class_init
,
826 static const char *i440fx_pcihost_root_bus_path(PCIHostState
*host_bridge
,
829 I440FXState
*s
= I440FX_PCI_HOST_BRIDGE(host_bridge
);
831 /* For backwards compat with old device paths */
832 if (s
->short_root_bus
) {
838 static Property i440fx_props
[] = {
839 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE
, I440FXState
,
840 pci_hole64_size
, DEFAULT_PCI_HOLE64_SIZE
),
841 DEFINE_PROP_UINT32("short_root_bus", I440FXState
, short_root_bus
, 0),
842 DEFINE_PROP_END_OF_LIST(),
845 static void i440fx_pcihost_class_init(ObjectClass
*klass
, void *data
)
847 DeviceClass
*dc
= DEVICE_CLASS(klass
);
848 PCIHostBridgeClass
*hc
= PCI_HOST_BRIDGE_CLASS(klass
);
850 hc
->root_bus_path
= i440fx_pcihost_root_bus_path
;
851 dc
->realize
= i440fx_pcihost_realize
;
853 dc
->props
= i440fx_props
;
856 static const TypeInfo i440fx_pcihost_info
= {
857 .name
= TYPE_I440FX_PCI_HOST_BRIDGE
,
858 .parent
= TYPE_PCI_HOST_BRIDGE
,
859 .instance_size
= sizeof(I440FXState
),
860 .instance_init
= i440fx_pcihost_initfn
,
861 .class_init
= i440fx_pcihost_class_init
,
864 static void i440fx_register_types(void)
866 type_register_static(&i440fx_info
);
867 type_register_static(&igd_passthrough_i440fx_info
);
868 type_register_static(&piix3_pci_type_info
);
869 type_register_static(&piix3_info
);
870 type_register_static(&piix3_xen_info
);
871 type_register_static(&i440fx_pcihost_info
);
874 type_init(i440fx_register_types
)