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pci_register_bar: cleanup
[qemu/ar7.git] / hw / pci / pci.c
blob8c2f6ed6058c1cc0658ce6598315429fd77267c0
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_bridge.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pci_host.h"
30 #include "monitor/monitor.h"
31 #include "net/net.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/loader.h"
34 #include "qemu/error-report.h"
35 #include "qemu/range.h"
36 #include "qmp-commands.h"
37 #include "trace.h"
38 #include "hw/pci/msi.h"
39 #include "hw/pci/msix.h"
40 #include "exec/address-spaces.h"
41 #include "hw/hotplug.h"
42 #include "hw/boards.h"
43 #include "qemu/cutils.h"
44
45 //#define DEBUG_PCI
46 #ifdef DEBUG_PCI
47 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
48 #else
49 # define PCI_DPRINTF(format, ...) do { } while (0)
50 #endif
51
52 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
53 static char *pcibus_get_dev_path(DeviceState *dev);
54 static char *pcibus_get_fw_dev_path(DeviceState *dev);
55 static void pcibus_reset(BusState *qbus);
56
57 static Property pci_props[] = {
58 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
59 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
60 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
61 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
62 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
63 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
64 QEMU_PCI_CAP_SERR_BITNR, true),
65 DEFINE_PROP_END_OF_LIST()
66 };
67
68 static const VMStateDescription vmstate_pcibus = {
69 .name = "PCIBUS",
70 .version_id = 1,
71 .minimum_version_id = 1,
72 .fields = (VMStateField[]) {
73 VMSTATE_INT32_EQUAL(nirq, PCIBus),
74 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
75 nirq, 0, vmstate_info_int32,
76 int32_t),
77 VMSTATE_END_OF_LIST()
78 }
79 };
80
81 static void pci_init_bus_master(PCIDevice *pci_dev)
82 {
83 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
84
85 memory_region_init_alias(&pci_dev->bus_master_enable_region,
86 OBJECT(pci_dev), "bus master",
87 dma_as->root, 0, memory_region_size(dma_as->root));
88 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
89 address_space_init(&pci_dev->bus_master_as,
90 &pci_dev->bus_master_enable_region, pci_dev->name);
91 }
92
93 static void pcibus_machine_done(Notifier *notifier, void *data)
94 {
95 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
96 int i;
97
98 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
99 if (bus->devices[i]) {
100 pci_init_bus_master(bus->devices[i]);
101 }
102 }
103 }
104
105 static void pci_bus_realize(BusState *qbus, Error **errp)
106 {
107 PCIBus *bus = PCI_BUS(qbus);
108
109 bus->machine_done.notify = pcibus_machine_done;
110 qemu_add_machine_init_done_notifier(&bus->machine_done);
111
112 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
113 }
114
115 static void pci_bus_unrealize(BusState *qbus, Error **errp)
116 {
117 PCIBus *bus = PCI_BUS(qbus);
118
119 qemu_remove_machine_init_done_notifier(&bus->machine_done);
120
121 vmstate_unregister(NULL, &vmstate_pcibus, bus);
122 }
123
124 static bool pcibus_is_root(PCIBus *bus)
125 {
126 return !bus->parent_dev;
127 }
128
129 static int pcibus_num(PCIBus *bus)
130 {
131 if (pcibus_is_root(bus)) {
132 return 0; /* pci host bridge */
133 }
134 return bus->parent_dev->config[PCI_SECONDARY_BUS];
135 }
136
137 static uint16_t pcibus_numa_node(PCIBus *bus)
138 {
139 return NUMA_NODE_UNASSIGNED;
140 }
141
142 static void pci_bus_class_init(ObjectClass *klass, void *data)
143 {
144 BusClass *k = BUS_CLASS(klass);
145 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
146
147 k->print_dev = pcibus_dev_print;
148 k->get_dev_path = pcibus_get_dev_path;
149 k->get_fw_dev_path = pcibus_get_fw_dev_path;
150 k->realize = pci_bus_realize;
151 k->unrealize = pci_bus_unrealize;
152 k->reset = pcibus_reset;
153
154 pbc->is_root = pcibus_is_root;
155 pbc->bus_num = pcibus_num;
156 pbc->numa_node = pcibus_numa_node;
157 }
158
159 static const TypeInfo pci_bus_info = {
160 .name = TYPE_PCI_BUS,
161 .parent = TYPE_BUS,
162 .instance_size = sizeof(PCIBus),
163 .class_size = sizeof(PCIBusClass),
164 .class_init = pci_bus_class_init,
165 };
166
167 static const TypeInfo pcie_bus_info = {
168 .name = TYPE_PCIE_BUS,
169 .parent = TYPE_PCI_BUS,
170 };
171
172 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
173 static void pci_update_mappings(PCIDevice *d);
174 static void pci_irq_handler(void *opaque, int irq_num, int level);
175 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
176 static void pci_del_option_rom(PCIDevice *pdev);
177
178 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
179 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
180
181 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
182
183 int pci_bar(PCIDevice *d, int reg)
184 {
185 uint8_t type;
186
187 if (reg != PCI_ROM_SLOT)
188 return PCI_BASE_ADDRESS_0 + reg * 4;
189
190 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
191 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
192 }
193
194 static inline int pci_irq_state(PCIDevice *d, int irq_num)
195 {
196 return (d->irq_state >> irq_num) & 0x1;
197 }
198
199 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
200 {
201 d->irq_state &= ~(0x1 << irq_num);
202 d->irq_state |= level << irq_num;
203 }
204
205 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
206 {
207 PCIBus *bus;
208 for (;;) {
209 bus = pci_dev->bus;
210 irq_num = bus->map_irq(pci_dev, irq_num);
211 if (bus->set_irq)
212 break;
213 pci_dev = bus->parent_dev;
214 }
215 bus->irq_count[irq_num] += change;
216 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
217 }
218
219 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
220 {
221 assert(irq_num >= 0);
222 assert(irq_num < bus->nirq);
223 return !!bus->irq_count[irq_num];
224 }
225
226 /* Update interrupt status bit in config space on interrupt
227 * state change. */
228 static void pci_update_irq_status(PCIDevice *dev)
229 {
230 if (dev->irq_state) {
231 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
232 } else {
233 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
234 }
235 }
236
237 void pci_device_deassert_intx(PCIDevice *dev)
238 {
239 int i;
240 for (i = 0; i < PCI_NUM_PINS; ++i) {
241 pci_irq_handler(dev, i, 0);
242 }
243 }
244
245 static void pci_do_device_reset(PCIDevice *dev)
246 {
247 int r;
248
249 pci_device_deassert_intx(dev);
250 assert(dev->irq_state == 0);
251
252 /* Clear all writable bits */
253 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
254 pci_get_word(dev->wmask + PCI_COMMAND) |
255 pci_get_word(dev->w1cmask + PCI_COMMAND));
256 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
257 pci_get_word(dev->wmask + PCI_STATUS) |
258 pci_get_word(dev->w1cmask + PCI_STATUS));
259 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
260 dev->config[PCI_INTERRUPT_LINE] = 0x0;
261 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
262 PCIIORegion *region = &dev->io_regions[r];
263 if (!region->size) {
264 continue;
265 }
266
267 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
268 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
269 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
270 } else {
271 pci_set_long(dev->config + pci_bar(dev, r), region->type);
272 }
273 }
274 pci_update_mappings(dev);
275
276 msi_reset(dev);
277 msix_reset(dev);
278 }
279
280 /*
281 * This function is called on #RST and FLR.
282 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
283 */
284 void pci_device_reset(PCIDevice *dev)
285 {
286 qdev_reset_all(&dev->qdev);
287 pci_do_device_reset(dev);
288 }
289
290 /*
291 * Trigger pci bus reset under a given bus.
292 * Called via qbus_reset_all on RST# assert, after the devices
293 * have been reset qdev_reset_all-ed already.
294 */
295 static void pcibus_reset(BusState *qbus)
296 {
297 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
298 int i;
299
300 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
301 if (bus->devices[i]) {
302 pci_do_device_reset(bus->devices[i]);
303 }
304 }
305
306 for (i = 0; i < bus->nirq; i++) {
307 assert(bus->irq_count[i] == 0);
308 }
309 }
310
311 static void pci_host_bus_register(DeviceState *host)
312 {
313 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
314
315 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
316 }
317
318 PCIBus *pci_find_primary_bus(void)
319 {
320 PCIBus *primary_bus = NULL;
321 PCIHostState *host;
322
323 QLIST_FOREACH(host, &pci_host_bridges, next) {
324 if (primary_bus) {
325 /* We have multiple root buses, refuse to select a primary */
326 return NULL;
327 }
328 primary_bus = host->bus;
329 }
330
331 return primary_bus;
332 }
333
334 PCIBus *pci_device_root_bus(const PCIDevice *d)
335 {
336 PCIBus *bus = d->bus;
337
338 while (!pci_bus_is_root(bus)) {
339 d = bus->parent_dev;
340 assert(d != NULL);
341
342 bus = d->bus;
343 }
344
345 return bus;
346 }
347
348 const char *pci_root_bus_path(PCIDevice *dev)
349 {
350 PCIBus *rootbus = pci_device_root_bus(dev);
351 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
352 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
353
354 assert(host_bridge->bus == rootbus);
355
356 if (hc->root_bus_path) {
357 return (*hc->root_bus_path)(host_bridge, rootbus);
358 }
359
360 return rootbus->qbus.name;
361 }
362
363 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
364 MemoryRegion *address_space_mem,
365 MemoryRegion *address_space_io,
366 uint8_t devfn_min)
367 {
368 assert(PCI_FUNC(devfn_min) == 0);
369 bus->devfn_min = devfn_min;
370 bus->address_space_mem = address_space_mem;
371 bus->address_space_io = address_space_io;
372
373 /* host bridge */
374 QLIST_INIT(&bus->child);
375
376 pci_host_bus_register(parent);
377 }
378
379 bool pci_bus_is_express(PCIBus *bus)
380 {
381 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
382 }
383
384 bool pci_bus_is_root(PCIBus *bus)
385 {
386 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
387 }
388
389 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
390 const char *name,
391 MemoryRegion *address_space_mem,
392 MemoryRegion *address_space_io,
393 uint8_t devfn_min, const char *typename)
394 {
395 qbus_create_inplace(bus, bus_size, typename, parent, name);
396 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
397 }
398
399 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
400 MemoryRegion *address_space_mem,
401 MemoryRegion *address_space_io,
402 uint8_t devfn_min, const char *typename)
403 {
404 PCIBus *bus;
405
406 bus = PCI_BUS(qbus_create(typename, parent, name));
407 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
408 return bus;
409 }
410
411 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
412 void *irq_opaque, int nirq)
413 {
414 bus->set_irq = set_irq;
415 bus->map_irq = map_irq;
416 bus->irq_opaque = irq_opaque;
417 bus->nirq = nirq;
418 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
419 }
420
421 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
422 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
423 void *irq_opaque,
424 MemoryRegion *address_space_mem,
425 MemoryRegion *address_space_io,
426 uint8_t devfn_min, int nirq, const char *typename)
427 {
428 PCIBus *bus;
429
430 bus = pci_bus_new(parent, name, address_space_mem,
431 address_space_io, devfn_min, typename);
432 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
433 return bus;
434 }
435
436 int pci_bus_num(PCIBus *s)
437 {
438 return PCI_BUS_GET_CLASS(s)->bus_num(s);
439 }
440
441 int pci_bus_numa_node(PCIBus *bus)
442 {
443 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
444 }
445
446 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
447 {
448 PCIDevice *s = container_of(pv, PCIDevice, config);
449 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
450 uint8_t *config;
451 int i;
452
453 assert(size == pci_config_size(s));
454 config = g_malloc(size);
455
456 qemu_get_buffer(f, config, size);
457 for (i = 0; i < size; ++i) {
458 if ((config[i] ^ s->config[i]) &
459 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
460 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
461 "cmask: %x wmask: %x w1cmask:%x", __func__,
462 i, config[i], s->config[i],
463 s->cmask[i], s->wmask[i], s->w1cmask[i]);
464 g_free(config);
465 return -EINVAL;
466 }
467 }
468 memcpy(s->config, config, size);
469
470 pci_update_mappings(s);
471 if (pc->is_bridge) {
472 PCIBridge *b = PCI_BRIDGE(s);
473 pci_bridge_update_mappings(b);
474 }
475
476 memory_region_set_enabled(&s->bus_master_enable_region,
477 pci_get_word(s->config + PCI_COMMAND)
478 & PCI_COMMAND_MASTER);
479
480 g_free(config);
481 return 0;
482 }
483
484 /* just put buffer */
485 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
486 {
487 const uint8_t **v = pv;
488 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
489 qemu_put_buffer(f, *v, size);
490 }
491
492 static VMStateInfo vmstate_info_pci_config = {
493 .name = "pci config",
494 .get = get_pci_config_device,
495 .put = put_pci_config_device,
496 };
497
498 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
499 {
500 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
501 uint32_t irq_state[PCI_NUM_PINS];
502 int i;
503 for (i = 0; i < PCI_NUM_PINS; ++i) {
504 irq_state[i] = qemu_get_be32(f);
505 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
506 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
507 irq_state[i]);
508 return -EINVAL;
509 }
510 }
511
512 for (i = 0; i < PCI_NUM_PINS; ++i) {
513 pci_set_irq_state(s, i, irq_state[i]);
514 }
515
516 return 0;
517 }
518
519 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
520 {
521 int i;
522 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
523
524 for (i = 0; i < PCI_NUM_PINS; ++i) {
525 qemu_put_be32(f, pci_irq_state(s, i));
526 }
527 }
528
529 static VMStateInfo vmstate_info_pci_irq_state = {
530 .name = "pci irq state",
531 .get = get_pci_irq_state,
532 .put = put_pci_irq_state,
533 };
534
535 const VMStateDescription vmstate_pci_device = {
536 .name = "PCIDevice",
537 .version_id = 2,
538 .minimum_version_id = 1,
539 .fields = (VMStateField[]) {
540 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
541 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
542 vmstate_info_pci_config,
543 PCI_CONFIG_SPACE_SIZE),
544 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
545 vmstate_info_pci_irq_state,
546 PCI_NUM_PINS * sizeof(int32_t)),
547 VMSTATE_END_OF_LIST()
548 }
549 };
550
551 const VMStateDescription vmstate_pcie_device = {
552 .name = "PCIEDevice",
553 .version_id = 2,
554 .minimum_version_id = 1,
555 .fields = (VMStateField[]) {
556 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
557 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
558 vmstate_info_pci_config,
559 PCIE_CONFIG_SPACE_SIZE),
560 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
561 vmstate_info_pci_irq_state,
562 PCI_NUM_PINS * sizeof(int32_t)),
563 VMSTATE_END_OF_LIST()
564 }
565 };
566
567 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
568 {
569 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
570 }
571
572 void pci_device_save(PCIDevice *s, QEMUFile *f)
573 {
574 /* Clear interrupt status bit: it is implicit
575 * in irq_state which we are saving.
576 * This makes us compatible with old devices
577 * which never set or clear this bit. */
578 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
579 vmstate_save_state(f, pci_get_vmstate(s), s, NULL);
580 /* Restore the interrupt status bit. */
581 pci_update_irq_status(s);
582 }
583
584 int pci_device_load(PCIDevice *s, QEMUFile *f)
585 {
586 int ret;
587 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
588 /* Restore the interrupt status bit. */
589 pci_update_irq_status(s);
590 return ret;
591 }
592
593 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
594 {
595 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
596 pci_default_sub_vendor_id);
597 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
598 pci_default_sub_device_id);
599 }
600
601 /*
602 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
603 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
604 */
605 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
606 unsigned int *slotp, unsigned int *funcp)
607 {
608 const char *p;
609 char *e;
610 unsigned long val;
611 unsigned long dom = 0, bus = 0;
612 unsigned int slot = 0;
613 unsigned int func = 0;
614
615 p = addr;
616 val = strtoul(p, &e, 16);
617 if (e == p)
618 return -1;
619 if (*e == ':') {
620 bus = val;
621 p = e + 1;
622 val = strtoul(p, &e, 16);
623 if (e == p)
624 return -1;
625 if (*e == ':') {
626 dom = bus;
627 bus = val;
628 p = e + 1;
629 val = strtoul(p, &e, 16);
630 if (e == p)
631 return -1;
632 }
633 }
634
635 slot = val;
636
637 if (funcp != NULL) {
638 if (*e != '.')
639 return -1;
640
641 p = e + 1;
642 val = strtoul(p, &e, 16);
643 if (e == p)
644 return -1;
645
646 func = val;
647 }
648
649 /* if funcp == NULL func is 0 */
650 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
651 return -1;
652
653 if (*e)
654 return -1;
655
656 *domp = dom;
657 *busp = bus;
658 *slotp = slot;
659 if (funcp != NULL)
660 *funcp = func;
661 return 0;
662 }
663
664 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
665 const char *devaddr)
666 {
667 int dom, bus;
668 unsigned slot;
669
670 if (!root) {
671 fprintf(stderr, "No primary PCI bus\n");
672 return NULL;
673 }
674
675 assert(!root->parent_dev);
676
677 if (!devaddr) {
678 *devfnp = -1;
679 return pci_find_bus_nr(root, 0);
680 }
681
682 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
683 return NULL;
684 }
685
686 if (dom != 0) {
687 fprintf(stderr, "No support for non-zero PCI domains\n");
688 return NULL;
689 }
690
691 *devfnp = PCI_DEVFN(slot, 0);
692 return pci_find_bus_nr(root, bus);
693 }
694
695 static void pci_init_cmask(PCIDevice *dev)
696 {
697 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
698 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
699 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
700 dev->cmask[PCI_REVISION_ID] = 0xff;
701 dev->cmask[PCI_CLASS_PROG] = 0xff;
702 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
703 dev->cmask[PCI_HEADER_TYPE] = 0xff;
704 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
705 }
706
707 static void pci_init_wmask(PCIDevice *dev)
708 {
709 int config_size = pci_config_size(dev);
710
711 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
712 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
713 pci_set_word(dev->wmask + PCI_COMMAND,
714 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
715 PCI_COMMAND_INTX_DISABLE);
716 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
717 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
718 }
719
720 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
721 config_size - PCI_CONFIG_HEADER_SIZE);
722 }
723
724 static void pci_init_w1cmask(PCIDevice *dev)
725 {
726 /*
727 * Note: It's okay to set w1cmask even for readonly bits as
728 * long as their value is hardwired to 0.
729 */
730 pci_set_word(dev->w1cmask + PCI_STATUS,
731 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
732 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
733 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
734 }
735
736 static void pci_init_mask_bridge(PCIDevice *d)
737 {
738 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
739 PCI_SEC_LETENCY_TIMER */
740 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
741
742 /* base and limit */
743 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
744 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
745 pci_set_word(d->wmask + PCI_MEMORY_BASE,
746 PCI_MEMORY_RANGE_MASK & 0xffff);
747 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
748 PCI_MEMORY_RANGE_MASK & 0xffff);
749 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
750 PCI_PREF_RANGE_MASK & 0xffff);
751 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
752 PCI_PREF_RANGE_MASK & 0xffff);
753
754 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
755 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
756
757 /* Supported memory and i/o types */
758 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
759 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
760 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
761 PCI_PREF_RANGE_TYPE_64);
762 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
763 PCI_PREF_RANGE_TYPE_64);
764
765 /*
766 * TODO: Bridges default to 10-bit VGA decoding but we currently only
767 * implement 16-bit decoding (no alias support).
768 */
769 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
770 PCI_BRIDGE_CTL_PARITY |
771 PCI_BRIDGE_CTL_SERR |
772 PCI_BRIDGE_CTL_ISA |
773 PCI_BRIDGE_CTL_VGA |
774 PCI_BRIDGE_CTL_VGA_16BIT |
775 PCI_BRIDGE_CTL_MASTER_ABORT |
776 PCI_BRIDGE_CTL_BUS_RESET |
777 PCI_BRIDGE_CTL_FAST_BACK |
778 PCI_BRIDGE_CTL_DISCARD |
779 PCI_BRIDGE_CTL_SEC_DISCARD |
780 PCI_BRIDGE_CTL_DISCARD_SERR);
781 /* Below does not do anything as we never set this bit, put here for
782 * completeness. */
783 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
784 PCI_BRIDGE_CTL_DISCARD_STATUS);
785 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
786 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
787 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
788 PCI_PREF_RANGE_TYPE_MASK);
789 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
790 PCI_PREF_RANGE_TYPE_MASK);
791 }
792
793 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
794 {
795 uint8_t slot = PCI_SLOT(dev->devfn);
796 uint8_t func;
797
798 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
799 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
800 }
801
802 /*
803 * multifunction bit is interpreted in two ways as follows.
804 * - all functions must set the bit to 1.
805 * Example: Intel X53
806 * - function 0 must set the bit, but the rest function (> 0)
807 * is allowed to leave the bit to 0.
808 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
809 *
810 * So OS (at least Linux) checks the bit of only function 0,
811 * and doesn't see the bit of function > 0.
812 *
813 * The below check allows both interpretation.
814 */
815 if (PCI_FUNC(dev->devfn)) {
816 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
817 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
818 /* function 0 should set multifunction bit */
819 error_setg(errp, "PCI: single function device can't be populated "
820 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
821 return;
822 }
823 return;
824 }
825
826 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
827 return;
828 }
829 /* function 0 indicates single function, so function > 0 must be NULL */
830 for (func = 1; func < PCI_FUNC_MAX; ++func) {
831 if (bus->devices[PCI_DEVFN(slot, func)]) {
832 error_setg(errp, "PCI: %x.0 indicates single function, "
833 "but %x.%x is already populated.",
834 slot, slot, func);
835 return;
836 }
837 }
838 }
839
840 static void pci_config_alloc(PCIDevice *pci_dev)
841 {
842 int config_size = pci_config_size(pci_dev);
843
844 pci_dev->config = g_malloc0(config_size);
845 pci_dev->cmask = g_malloc0(config_size);
846 pci_dev->wmask = g_malloc0(config_size);
847 pci_dev->w1cmask = g_malloc0(config_size);
848 pci_dev->used = g_malloc0(config_size);
849 }
850
851 static void pci_config_free(PCIDevice *pci_dev)
852 {
853 g_free(pci_dev->config);
854 g_free(pci_dev->cmask);
855 g_free(pci_dev->wmask);
856 g_free(pci_dev->w1cmask);
857 g_free(pci_dev->used);
858 }
859
860 static void do_pci_unregister_device(PCIDevice *pci_dev)
861 {
862 pci_dev->bus->devices[pci_dev->devfn] = NULL;
863 pci_config_free(pci_dev);
864
865 address_space_destroy(&pci_dev->bus_master_as);
866 }
867
868 /* Extract PCIReqIDCache into BDF format */
869 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
870 {
871 uint8_t bus_n;
872 uint16_t result;
873
874 switch (cache->type) {
875 case PCI_REQ_ID_BDF:
876 result = pci_get_bdf(cache->dev);
877 break;
878 case PCI_REQ_ID_SECONDARY_BUS:
879 bus_n = pci_bus_num(cache->dev->bus);
880 result = PCI_BUILD_BDF(bus_n, 0);
881 break;
882 default:
883 error_printf("Invalid PCI requester ID cache type: %d\n",
884 cache->type);
885 exit(1);
886 break;
887 }
888
889 return result;
890 }
891
892 /* Parse bridges up to the root complex and return requester ID
893 * cache for specific device. For full PCIe topology, the cache
894 * result would be exactly the same as getting BDF of the device.
895 * However, several tricks are required when system mixed up with
896 * legacy PCI devices and PCIe-to-PCI bridges.
897 *
898 * Here we cache the proxy device (and type) not requester ID since
899 * bus number might change from time to time.
900 */
901 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
902 {
903 PCIDevice *parent;
904 PCIReqIDCache cache = {
905 .dev = dev,
906 .type = PCI_REQ_ID_BDF,
907 };
908
909 while (!pci_bus_is_root(dev->bus)) {
910 /* We are under PCI/PCIe bridges */
911 parent = dev->bus->parent_dev;
912 if (pci_is_express(parent)) {
913 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
914 /* When we pass through PCIe-to-PCI/PCIX bridges, we
915 * override the requester ID using secondary bus
916 * number of parent bridge with zeroed devfn
917 * (pcie-to-pci bridge spec chap 2.3). */
918 cache.type = PCI_REQ_ID_SECONDARY_BUS;
919 cache.dev = dev;
920 }
921 } else {
922 /* Legacy PCI, override requester ID with the bridge's
923 * BDF upstream. When the root complex connects to
924 * legacy PCI devices (including buses), it can only
925 * obtain requester ID info from directly attached
926 * devices. If devices are attached under bridges, only
927 * the requester ID of the bridge that is directly
928 * attached to the root complex can be recognized. */
929 cache.type = PCI_REQ_ID_BDF;
930 cache.dev = parent;
931 }
932 dev = parent;
933 }
934
935 return cache;
936 }
937
938 uint16_t pci_requester_id(PCIDevice *dev)
939 {
940 return pci_req_id_cache_extract(&dev->requester_id_cache);
941 }
942
943 /* -1 for devfn means auto assign */
944 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
945 const char *name, int devfn,
946 Error **errp)
947 {
948 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
949 PCIConfigReadFunc *config_read = pc->config_read;
950 PCIConfigWriteFunc *config_write = pc->config_write;
951 Error *local_err = NULL;
952 DeviceState *dev = DEVICE(pci_dev);
953
954 pci_dev->bus = bus;
955 /* Only pci bridges can be attached to extra PCI root buses */
956 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
957 error_setg(errp,
958 "PCI: Only PCI/PCIe bridges can be plugged into %s",
959 bus->parent_dev->name);
960 return NULL;
961 }
962
963 if (devfn < 0) {
964 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
965 devfn += PCI_FUNC_MAX) {
966 if (!bus->devices[devfn])
967 goto found;
968 }
969 error_setg(errp, "PCI: no slot/function available for %s, all in use",
970 name);
971 return NULL;
972 found: ;
973 } else if (bus->devices[devfn]) {
974 error_setg(errp, "PCI: slot %d function %d not available for %s,"
975 " in use by %s",
976 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
977 bus->devices[devfn]->name);
978 return NULL;
979 } else if (dev->hotplugged &&
980 pci_get_function_0(pci_dev)) {
981 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
982 " new func %s cannot be exposed to guest.",
983 PCI_SLOT(devfn),
984 bus->devices[PCI_DEVFN(PCI_SLOT(devfn), 0)]->name,
985 name);
986
987 return NULL;
988 }
989
990 pci_dev->devfn = devfn;
991 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
992
993 if (qdev_hotplug) {
994 pci_init_bus_master(pci_dev);
995 }
996 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
997 pci_dev->irq_state = 0;
998 pci_config_alloc(pci_dev);
999
1000 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1001 pci_config_set_device_id(pci_dev->config, pc->device_id);
1002 pci_config_set_revision(pci_dev->config, pc->revision);
1003 pci_config_set_class(pci_dev->config, pc->class_id);
1004
1005 if (!pc->is_bridge) {
1006 if (pc->subsystem_vendor_id || pc->subsystem_id) {
1007 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1008 pc->subsystem_vendor_id);
1009 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1010 pc->subsystem_id);
1011 } else {
1012 pci_set_default_subsystem_id(pci_dev);
1013 }
1014 } else {
1015 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1016 assert(!pc->subsystem_vendor_id);
1017 assert(!pc->subsystem_id);
1018 }
1019 pci_init_cmask(pci_dev);
1020 pci_init_wmask(pci_dev);
1021 pci_init_w1cmask(pci_dev);
1022 if (pc->is_bridge) {
1023 pci_init_mask_bridge(pci_dev);
1024 }
1025 pci_init_multifunction(bus, pci_dev, &local_err);
1026 if (local_err) {
1027 error_propagate(errp, local_err);
1028 do_pci_unregister_device(pci_dev);
1029 return NULL;
1030 }
1031
1032 if (!config_read)
1033 config_read = pci_default_read_config;
1034 if (!config_write)
1035 config_write = pci_default_write_config;
1036 pci_dev->config_read = config_read;
1037 pci_dev->config_write = config_write;
1038 bus->devices[devfn] = pci_dev;
1039 pci_dev->version_id = 2; /* Current pci device vmstate version */
1040 return pci_dev;
1041 }
1042
1043 static void pci_unregister_io_regions(PCIDevice *pci_dev)
1044 {
1045 PCIIORegion *r;
1046 int i;
1047
1048 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1049 r = &pci_dev->io_regions[i];
1050 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1051 continue;
1052 memory_region_del_subregion(r->address_space, r->memory);
1053 }
1054
1055 pci_unregister_vga(pci_dev);
1056 }
1057
1058 static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
1059 {
1060 PCIDevice *pci_dev = PCI_DEVICE(dev);
1061 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1062
1063 pci_unregister_io_regions(pci_dev);
1064 pci_del_option_rom(pci_dev);
1065
1066 if (pc->exit) {
1067 pc->exit(pci_dev);
1068 }
1069
1070 do_pci_unregister_device(pci_dev);
1071 }
1072
1073 void pci_register_bar(PCIDevice *pci_dev, int region_num,
1074 uint8_t type, MemoryRegion *memory)
1075 {
1076 PCIIORegion *r;
1077 uint32_t addr; /* offset in pci config space */
1078 uint64_t wmask;
1079 pcibus_t size = memory_region_size(memory);
1080
1081 assert(region_num >= 0);
1082 assert(region_num < PCI_NUM_REGIONS);
1083 if (size & (size-1)) {
1084 fprintf(stderr, "ERROR: PCI region size must be pow2 "
1085 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
1086 exit(1);
1087 }
1088
1089 r = &pci_dev->io_regions[region_num];
1090 r->addr = PCI_BAR_UNMAPPED;
1091 r->size = size;
1092 r->type = type;
1093 r->memory = memory;
1094 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1095 ? pci_dev->bus->address_space_io
1096 : pci_dev->bus->address_space_mem;
1097
1098 wmask = ~(size - 1);
1099 if (region_num == PCI_ROM_SLOT) {
1100 /* ROM enable bit is writable */
1101 wmask |= PCI_ROM_ADDRESS_ENABLE;
1102 }
1103
1104 addr = pci_bar(pci_dev, region_num);
1105 pci_set_long(pci_dev->config + addr, type);
1106
1107 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1108 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1109 pci_set_quad(pci_dev->wmask + addr, wmask);
1110 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1111 } else {
1112 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1113 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1114 }
1115 }
1116
1117 static void pci_update_vga(PCIDevice *pci_dev)
1118 {
1119 uint16_t cmd;
1120
1121 if (!pci_dev->has_vga) {
1122 return;
1123 }
1124
1125 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1126
1127 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1128 cmd & PCI_COMMAND_MEMORY);
1129 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1130 cmd & PCI_COMMAND_IO);
1131 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1132 cmd & PCI_COMMAND_IO);
1133 }
1134
1135 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1136 MemoryRegion *io_lo, MemoryRegion *io_hi)
1137 {
1138 assert(!pci_dev->has_vga);
1139
1140 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1141 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1142 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
1143 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1144
1145 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1146 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1147 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1148 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1149
1150 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1151 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1152 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1153 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1154 pci_dev->has_vga = true;
1155
1156 pci_update_vga(pci_dev);
1157 }
1158
1159 void pci_unregister_vga(PCIDevice *pci_dev)
1160 {
1161 if (!pci_dev->has_vga) {
1162 return;
1163 }
1164
1165 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1166 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1167 memory_region_del_subregion(pci_dev->bus->address_space_io,
1168 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1169 memory_region_del_subregion(pci_dev->bus->address_space_io,
1170 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1171 pci_dev->has_vga = false;
1172 }
1173
1174 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1175 {
1176 return pci_dev->io_regions[region_num].addr;
1177 }
1178
1179 static pcibus_t pci_bar_address(PCIDevice *d,
1180 int reg, uint8_t type, pcibus_t size)
1181 {
1182 pcibus_t new_addr, last_addr;
1183 int bar = pci_bar(d, reg);
1184 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1185 Object *machine = qdev_get_machine();
1186 ObjectClass *oc = object_get_class(machine);
1187 MachineClass *mc = MACHINE_CLASS(oc);
1188 bool allow_0_address = mc->pci_allow_0_address;
1189
1190 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1191 if (!(cmd & PCI_COMMAND_IO)) {
1192 return PCI_BAR_UNMAPPED;
1193 }
1194 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1195 last_addr = new_addr + size - 1;
1196 /* Check if 32 bit BAR wraps around explicitly.
1197 * TODO: make priorities correct and remove this work around.
1198 */
1199 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1200 (!allow_0_address && new_addr == 0)) {
1201 return PCI_BAR_UNMAPPED;
1202 }
1203 return new_addr;
1204 }
1205
1206 if (!(cmd & PCI_COMMAND_MEMORY)) {
1207 return PCI_BAR_UNMAPPED;
1208 }
1209 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1210 new_addr = pci_get_quad(d->config + bar);
1211 } else {
1212 new_addr = pci_get_long(d->config + bar);
1213 }
1214 /* the ROM slot has a specific enable bit */
1215 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1216 return PCI_BAR_UNMAPPED;
1217 }
1218 new_addr &= ~(size - 1);
1219 last_addr = new_addr + size - 1;
1220 /* NOTE: we do not support wrapping */
1221 /* XXX: as we cannot support really dynamic
1222 mappings, we handle specific values as invalid
1223 mappings. */
1224 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1225 (!allow_0_address && new_addr == 0)) {
1226 return PCI_BAR_UNMAPPED;
1227 }
1228
1229 /* Now pcibus_t is 64bit.
1230 * Check if 32 bit BAR wraps around explicitly.
1231 * Without this, PC ide doesn't work well.
1232 * TODO: remove this work around.
1233 */
1234 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1235 return PCI_BAR_UNMAPPED;
1236 }
1237
1238 /*
1239 * OS is allowed to set BAR beyond its addressable
1240 * bits. For example, 32 bit OS can set 64bit bar
1241 * to >4G. Check it. TODO: we might need to support
1242 * it in the future for e.g. PAE.
1243 */
1244 if (last_addr >= HWADDR_MAX) {
1245 return PCI_BAR_UNMAPPED;
1246 }
1247
1248 return new_addr;
1249 }
1250
1251 static void pci_update_mappings(PCIDevice *d)
1252 {
1253 PCIIORegion *r;
1254 int i;
1255 pcibus_t new_addr;
1256
1257 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1258 r = &d->io_regions[i];
1259
1260 /* this region isn't registered */
1261 if (!r->size)
1262 continue;
1263
1264 new_addr = pci_bar_address(d, i, r->type, r->size);
1265
1266 /* This bar isn't changed */
1267 if (new_addr == r->addr)
1268 continue;
1269
1270 /* now do the real mapping */
1271 if (r->addr != PCI_BAR_UNMAPPED) {
1272 trace_pci_update_mappings_del(d, pci_bus_num(d->bus),
1273 PCI_SLOT(d->devfn),
1274 PCI_FUNC(d->devfn),
1275 i, r->addr, r->size);
1276 memory_region_del_subregion(r->address_space, r->memory);
1277 }
1278 r->addr = new_addr;
1279 if (r->addr != PCI_BAR_UNMAPPED) {
1280 trace_pci_update_mappings_add(d, pci_bus_num(d->bus),
1281 PCI_SLOT(d->devfn),
1282 PCI_FUNC(d->devfn),
1283 i, r->addr, r->size);
1284 memory_region_add_subregion_overlap(r->address_space,
1285 r->addr, r->memory, 1);
1286 }
1287 }
1288
1289 pci_update_vga(d);
1290 }
1291
1292 static inline int pci_irq_disabled(PCIDevice *d)
1293 {
1294 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1295 }
1296
1297 /* Called after interrupt disabled field update in config space,
1298 * assert/deassert interrupts if necessary.
1299 * Gets original interrupt disable bit value (before update). */
1300 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1301 {
1302 int i, disabled = pci_irq_disabled(d);
1303 if (disabled == was_irq_disabled)
1304 return;
1305 for (i = 0; i < PCI_NUM_PINS; ++i) {
1306 int state = pci_irq_state(d, i);
1307 pci_change_irq_level(d, i, disabled ? -state : state);
1308 }
1309 }
1310
1311 uint32_t pci_default_read_config(PCIDevice *d,
1312 uint32_t address, int len)
1313 {
1314 uint32_t val = 0;
1315
1316 memcpy(&val, d->config + address, len);
1317 return le32_to_cpu(val);
1318 }
1319
1320 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1321 {
1322 int i, was_irq_disabled = pci_irq_disabled(d);
1323 uint32_t val = val_in;
1324
1325 for (i = 0; i < l; val >>= 8, ++i) {
1326 uint8_t wmask = d->wmask[addr + i];
1327 uint8_t w1cmask = d->w1cmask[addr + i];
1328 assert(!(wmask & w1cmask));
1329 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1330 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1331 }
1332 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1333 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1334 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1335 range_covers_byte(addr, l, PCI_COMMAND))
1336 pci_update_mappings(d);
1337
1338 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1339 pci_update_irq_disabled(d, was_irq_disabled);
1340 memory_region_set_enabled(&d->bus_master_enable_region,
1341 pci_get_word(d->config + PCI_COMMAND)
1342 & PCI_COMMAND_MASTER);
1343 }
1344
1345 msi_write_config(d, addr, val_in, l);
1346 msix_write_config(d, addr, val_in, l);
1347 }
1348
1349 /***********************************************************/
1350 /* generic PCI irq support */
1351
1352 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1353 static void pci_irq_handler(void *opaque, int irq_num, int level)
1354 {
1355 PCIDevice *pci_dev = opaque;
1356 int change;
1357
1358 change = level - pci_irq_state(pci_dev, irq_num);
1359 if (!change)
1360 return;
1361
1362 pci_set_irq_state(pci_dev, irq_num, level);
1363 pci_update_irq_status(pci_dev);
1364 if (pci_irq_disabled(pci_dev))
1365 return;
1366 pci_change_irq_level(pci_dev, irq_num, change);
1367 }
1368
1369 static inline int pci_intx(PCIDevice *pci_dev)
1370 {
1371 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1372 }
1373
1374 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1375 {
1376 int intx = pci_intx(pci_dev);
1377
1378 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1379 }
1380
1381 void pci_set_irq(PCIDevice *pci_dev, int level)
1382 {
1383 int intx = pci_intx(pci_dev);
1384 pci_irq_handler(pci_dev, intx, level);
1385 }
1386
1387 /* Special hooks used by device assignment */
1388 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1389 {
1390 assert(pci_bus_is_root(bus));
1391 bus->route_intx_to_irq = route_intx_to_irq;
1392 }
1393
1394 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1395 {
1396 PCIBus *bus;
1397
1398 do {
1399 bus = dev->bus;
1400 pin = bus->map_irq(dev, pin);
1401 dev = bus->parent_dev;
1402 } while (dev);
1403
1404 if (!bus->route_intx_to_irq) {
1405 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1406 object_get_typename(OBJECT(bus->qbus.parent)));
1407 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1408 }
1409
1410 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1411 }
1412
1413 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1414 {
1415 return old->mode != new->mode || old->irq != new->irq;
1416 }
1417
1418 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1419 {
1420 PCIDevice *dev;
1421 PCIBus *sec;
1422 int i;
1423
1424 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1425 dev = bus->devices[i];
1426 if (dev && dev->intx_routing_notifier) {
1427 dev->intx_routing_notifier(dev);
1428 }
1429 }
1430
1431 QLIST_FOREACH(sec, &bus->child, sibling) {
1432 pci_bus_fire_intx_routing_notifier(sec);
1433 }
1434 }
1435
1436 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1437 PCIINTxRoutingNotifier notifier)
1438 {
1439 dev->intx_routing_notifier = notifier;
1440 }
1441
1442 /*
1443 * PCI-to-PCI bridge specification
1444 * 9.1: Interrupt routing. Table 9-1
1445 *
1446 * the PCI Express Base Specification, Revision 2.1
1447 * 2.2.8.1: INTx interrutp signaling - Rules
1448 * the Implementation Note
1449 * Table 2-20
1450 */
1451 /*
1452 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1453 * 0-origin unlike PCI interrupt pin register.
1454 */
1455 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1456 {
1457 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1458 }
1459
1460 /***********************************************************/
1461 /* monitor info on PCI */
1462
1463 typedef struct {
1464 uint16_t class;
1465 const char *desc;
1466 const char *fw_name;
1467 uint16_t fw_ign_bits;
1468 } pci_class_desc;
1469
1470 static const pci_class_desc pci_class_descriptions[] =
1471 {
1472 { 0x0001, "VGA controller", "display"},
1473 { 0x0100, "SCSI controller", "scsi"},
1474 { 0x0101, "IDE controller", "ide"},
1475 { 0x0102, "Floppy controller", "fdc"},
1476 { 0x0103, "IPI controller", "ipi"},
1477 { 0x0104, "RAID controller", "raid"},
1478 { 0x0106, "SATA controller"},
1479 { 0x0107, "SAS controller"},
1480 { 0x0180, "Storage controller"},
1481 { 0x0200, "Ethernet controller", "ethernet"},
1482 { 0x0201, "Token Ring controller", "token-ring"},
1483 { 0x0202, "FDDI controller", "fddi"},
1484 { 0x0203, "ATM controller", "atm"},
1485 { 0x0280, "Network controller"},
1486 { 0x0300, "VGA controller", "display", 0x00ff},
1487 { 0x0301, "XGA controller"},
1488 { 0x0302, "3D controller"},
1489 { 0x0380, "Display controller"},
1490 { 0x0400, "Video controller", "video"},
1491 { 0x0401, "Audio controller", "sound"},
1492 { 0x0402, "Phone"},
1493 { 0x0403, "Audio controller", "sound"},
1494 { 0x0480, "Multimedia controller"},
1495 { 0x0500, "RAM controller", "memory"},
1496 { 0x0501, "Flash controller", "flash"},
1497 { 0x0580, "Memory controller"},
1498 { 0x0600, "Host bridge", "host"},
1499 { 0x0601, "ISA bridge", "isa"},
1500 { 0x0602, "EISA bridge", "eisa"},
1501 { 0x0603, "MC bridge", "mca"},
1502 { 0x0604, "PCI bridge", "pci-bridge"},
1503 { 0x0605, "PCMCIA bridge", "pcmcia"},
1504 { 0x0606, "NUBUS bridge", "nubus"},
1505 { 0x0607, "CARDBUS bridge", "cardbus"},
1506 { 0x0608, "RACEWAY bridge"},
1507 { 0x0680, "Bridge"},
1508 { 0x0700, "Serial port", "serial"},
1509 { 0x0701, "Parallel port", "parallel"},
1510 { 0x0800, "Interrupt controller", "interrupt-controller"},
1511 { 0x0801, "DMA controller", "dma-controller"},
1512 { 0x0802, "Timer", "timer"},
1513 { 0x0803, "RTC", "rtc"},
1514 { 0x0900, "Keyboard", "keyboard"},
1515 { 0x0901, "Pen", "pen"},
1516 { 0x0902, "Mouse", "mouse"},
1517 { 0x0A00, "Dock station", "dock", 0x00ff},
1518 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1519 { 0x0c00, "Fireware contorller", "fireware"},
1520 { 0x0c01, "Access bus controller", "access-bus"},
1521 { 0x0c02, "SSA controller", "ssa"},
1522 { 0x0c03, "USB controller", "usb"},
1523 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1524 { 0x0c05, "SMBus"},
1525 { 0, NULL}
1526 };
1527
1528 static void pci_for_each_device_under_bus(PCIBus *bus,
1529 void (*fn)(PCIBus *b, PCIDevice *d,
1530 void *opaque),
1531 void *opaque)
1532 {
1533 PCIDevice *d;
1534 int devfn;
1535
1536 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1537 d = bus->devices[devfn];
1538 if (d) {
1539 fn(bus, d, opaque);
1540 }
1541 }
1542 }
1543
1544 void pci_for_each_device(PCIBus *bus, int bus_num,
1545 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1546 void *opaque)
1547 {
1548 bus = pci_find_bus_nr(bus, bus_num);
1549
1550 if (bus) {
1551 pci_for_each_device_under_bus(bus, fn, opaque);
1552 }
1553 }
1554
1555 static const pci_class_desc *get_class_desc(int class)
1556 {
1557 const pci_class_desc *desc;
1558
1559 desc = pci_class_descriptions;
1560 while (desc->desc && class != desc->class) {
1561 desc++;
1562 }
1563
1564 return desc;
1565 }
1566
1567 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1568
1569 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1570 {
1571 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1572 int i;
1573
1574 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1575 const PCIIORegion *r = &dev->io_regions[i];
1576 PciMemoryRegionList *region;
1577
1578 if (!r->size) {
1579 continue;
1580 }
1581
1582 region = g_malloc0(sizeof(*region));
1583 region->value = g_malloc0(sizeof(*region->value));
1584
1585 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1586 region->value->type = g_strdup("io");
1587 } else {
1588 region->value->type = g_strdup("memory");
1589 region->value->has_prefetch = true;
1590 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1591 region->value->has_mem_type_64 = true;
1592 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1593 }
1594
1595 region->value->bar = i;
1596 region->value->address = r->addr;
1597 region->value->size = r->size;
1598
1599 /* XXX: waiting for the qapi to support GSList */
1600 if (!cur_item) {
1601 head = cur_item = region;
1602 } else {
1603 cur_item->next = region;
1604 cur_item = region;
1605 }
1606 }
1607
1608 return head;
1609 }
1610
1611 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1612 int bus_num)
1613 {
1614 PciBridgeInfo *info;
1615 PciMemoryRange *range;
1616
1617 info = g_new0(PciBridgeInfo, 1);
1618
1619 info->bus = g_new0(PciBusInfo, 1);
1620 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1621 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1622 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1623
1624 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1625 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1626 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1627
1628 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1629 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1630 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1631
1632 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1633 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1634 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1635
1636 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1637 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1638 if (child_bus) {
1639 info->has_devices = true;
1640 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1641 }
1642 }
1643
1644 return info;
1645 }
1646
1647 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1648 int bus_num)
1649 {
1650 const pci_class_desc *desc;
1651 PciDeviceInfo *info;
1652 uint8_t type;
1653 int class;
1654
1655 info = g_new0(PciDeviceInfo, 1);
1656 info->bus = bus_num;
1657 info->slot = PCI_SLOT(dev->devfn);
1658 info->function = PCI_FUNC(dev->devfn);
1659
1660 info->class_info = g_new0(PciDeviceClass, 1);
1661 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1662 info->class_info->q_class = class;
1663 desc = get_class_desc(class);
1664 if (desc->desc) {
1665 info->class_info->has_desc = true;
1666 info->class_info->desc = g_strdup(desc->desc);
1667 }
1668
1669 info->id = g_new0(PciDeviceId, 1);
1670 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1671 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1672 info->regions = qmp_query_pci_regions(dev);
1673 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1674
1675 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1676 info->has_irq = true;
1677 info->irq = dev->config[PCI_INTERRUPT_LINE];
1678 }
1679
1680 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1681 if (type == PCI_HEADER_TYPE_BRIDGE) {
1682 info->has_pci_bridge = true;
1683 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1684 }
1685
1686 return info;
1687 }
1688
1689 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1690 {
1691 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1692 PCIDevice *dev;
1693 int devfn;
1694
1695 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1696 dev = bus->devices[devfn];
1697 if (dev) {
1698 info = g_malloc0(sizeof(*info));
1699 info->value = qmp_query_pci_device(dev, bus, bus_num);
1700
1701 /* XXX: waiting for the qapi to support GSList */
1702 if (!cur_item) {
1703 head = cur_item = info;
1704 } else {
1705 cur_item->next = info;
1706 cur_item = info;
1707 }
1708 }
1709 }
1710
1711 return head;
1712 }
1713
1714 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1715 {
1716 PciInfo *info = NULL;
1717
1718 bus = pci_find_bus_nr(bus, bus_num);
1719 if (bus) {
1720 info = g_malloc0(sizeof(*info));
1721 info->bus = bus_num;
1722 info->devices = qmp_query_pci_devices(bus, bus_num);
1723 }
1724
1725 return info;
1726 }
1727
1728 PciInfoList *qmp_query_pci(Error **errp)
1729 {
1730 PciInfoList *info, *head = NULL, *cur_item = NULL;
1731 PCIHostState *host_bridge;
1732
1733 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1734 info = g_malloc0(sizeof(*info));
1735 info->value = qmp_query_pci_bus(host_bridge->bus,
1736 pci_bus_num(host_bridge->bus));
1737
1738 /* XXX: waiting for the qapi to support GSList */
1739 if (!cur_item) {
1740 head = cur_item = info;
1741 } else {
1742 cur_item->next = info;
1743 cur_item = info;
1744 }
1745 }
1746
1747 return head;
1748 }
1749
1750 static const char * const pci_nic_models[] = {
1751 "ne2k_pci",
1752 "i82551",
1753 "i82557b",
1754 "i82559er",
1755 "rtl8139",
1756 "e1000",
1757 "pcnet",
1758 "virtio",
1759 NULL
1760 };
1761
1762 static const char * const pci_nic_names[] = {
1763 "ne2k_pci",
1764 "i82551",
1765 "i82557b",
1766 "i82559er",
1767 "rtl8139",
1768 "e1000",
1769 "pcnet",
1770 "virtio-net-pci",
1771 NULL
1772 };
1773
1774 /* Initialize a PCI NIC. */
1775 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1776 const char *default_model,
1777 const char *default_devaddr)
1778 {
1779 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1780 Error *err = NULL;
1781 PCIBus *bus;
1782 PCIDevice *pci_dev;
1783 DeviceState *dev;
1784 int devfn;
1785 int i;
1786
1787 if (qemu_show_nic_models(nd->model, pci_nic_models)) {
1788 exit(0);
1789 }
1790
1791 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1792 if (i < 0) {
1793 exit(1);
1794 }
1795
1796 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1797 if (!bus) {
1798 error_report("Invalid PCI device address %s for device %s",
1799 devaddr, pci_nic_names[i]);
1800 exit(1);
1801 }
1802
1803 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1804 dev = &pci_dev->qdev;
1805 qdev_set_nic_properties(dev, nd);
1806
1807 object_property_set_bool(OBJECT(dev), true, "realized", &err);
1808 if (err) {
1809 error_report_err(err);
1810 object_unparent(OBJECT(dev));
1811 exit(1);
1812 }
1813
1814 return pci_dev;
1815 }
1816
1817 PCIDevice *pci_vga_init(PCIBus *bus)
1818 {
1819 switch (vga_interface_type) {
1820 case VGA_CIRRUS:
1821 return pci_create_simple(bus, -1, "cirrus-vga");
1822 case VGA_QXL:
1823 return pci_create_simple(bus, -1, "qxl-vga");
1824 case VGA_STD:
1825 return pci_create_simple(bus, -1, "VGA");
1826 case VGA_VMWARE:
1827 return pci_create_simple(bus, -1, "vmware-svga");
1828 case VGA_VIRTIO:
1829 return pci_create_simple(bus, -1, "virtio-vga");
1830 case VGA_NONE:
1831 default: /* Other non-PCI types. Checking for unsupported types is already
1832 done in vl.c. */
1833 return NULL;
1834 }
1835 }
1836
1837 /* Whether a given bus number is in range of the secondary
1838 * bus of the given bridge device. */
1839 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1840 {
1841 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1842 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1843 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1844 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1845 }
1846
1847 /* Whether a given bus number is in a range of a root bus */
1848 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1849 {
1850 int i;
1851
1852 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1853 PCIDevice *dev = bus->devices[i];
1854
1855 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1856 if (pci_secondary_bus_in_range(dev, bus_num)) {
1857 return true;
1858 }
1859 }
1860 }
1861
1862 return false;
1863 }
1864
1865 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1866 {
1867 PCIBus *sec;
1868
1869 if (!bus) {
1870 return NULL;
1871 }
1872
1873 if (pci_bus_num(bus) == bus_num) {
1874 return bus;
1875 }
1876
1877 /* Consider all bus numbers in range for the host pci bridge. */
1878 if (!pci_bus_is_root(bus) &&
1879 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1880 return NULL;
1881 }
1882
1883 /* try child bus */
1884 for (; bus; bus = sec) {
1885 QLIST_FOREACH(sec, &bus->child, sibling) {
1886 if (pci_bus_num(sec) == bus_num) {
1887 return sec;
1888 }
1889 /* PXB buses assumed to be children of bus 0 */
1890 if (pci_bus_is_root(sec)) {
1891 if (pci_root_bus_in_range(sec, bus_num)) {
1892 break;
1893 }
1894 } else {
1895 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1896 break;
1897 }
1898 }
1899 }
1900 }
1901
1902 return NULL;
1903 }
1904
1905 void pci_for_each_bus_depth_first(PCIBus *bus,
1906 void *(*begin)(PCIBus *bus, void *parent_state),
1907 void (*end)(PCIBus *bus, void *state),
1908 void *parent_state)
1909 {
1910 PCIBus *sec;
1911 void *state;
1912
1913 if (!bus) {
1914 return;
1915 }
1916
1917 if (begin) {
1918 state = begin(bus, parent_state);
1919 } else {
1920 state = parent_state;
1921 }
1922
1923 QLIST_FOREACH(sec, &bus->child, sibling) {
1924 pci_for_each_bus_depth_first(sec, begin, end, state);
1925 }
1926
1927 if (end) {
1928 end(bus, state);
1929 }
1930 }
1931
1932
1933 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1934 {
1935 bus = pci_find_bus_nr(bus, bus_num);
1936
1937 if (!bus)
1938 return NULL;
1939
1940 return bus->devices[devfn];
1941 }
1942
1943 static void pci_qdev_realize(DeviceState *qdev, Error **errp)
1944 {
1945 PCIDevice *pci_dev = (PCIDevice *)qdev;
1946 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1947 Error *local_err = NULL;
1948 PCIBus *bus;
1949 bool is_default_rom;
1950
1951 /* initialize cap_present for pci_is_express() and pci_config_size() */
1952 if (pc->is_express) {
1953 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1954 }
1955
1956 bus = PCI_BUS(qdev_get_parent_bus(qdev));
1957 pci_dev = do_pci_register_device(pci_dev, bus,
1958 object_get_typename(OBJECT(qdev)),
1959 pci_dev->devfn, errp);
1960 if (pci_dev == NULL)
1961 return;
1962
1963 if (pc->realize) {
1964 pc->realize(pci_dev, &local_err);
1965 if (local_err) {
1966 error_propagate(errp, local_err);
1967 do_pci_unregister_device(pci_dev);
1968 return;
1969 }
1970 }
1971
1972 /* rom loading */
1973 is_default_rom = false;
1974 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1975 pci_dev->romfile = g_strdup(pc->romfile);
1976 is_default_rom = true;
1977 }
1978
1979 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
1980 if (local_err) {
1981 error_propagate(errp, local_err);
1982 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
1983 return;
1984 }
1985 }
1986
1987 static void pci_default_realize(PCIDevice *dev, Error **errp)
1988 {
1989 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1990
1991 if (pc->init) {
1992 if (pc->init(dev) < 0) {
1993 error_setg(errp, "Device initialization failed");
1994 return;
1995 }
1996 }
1997 }
1998
1999 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2000 const char *name)
2001 {
2002 DeviceState *dev;
2003
2004 dev = qdev_create(&bus->qbus, name);
2005 qdev_prop_set_int32(dev, "addr", devfn);
2006 qdev_prop_set_bit(dev, "multifunction", multifunction);
2007 return PCI_DEVICE(dev);
2008 }
2009
2010 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2011 bool multifunction,
2012 const char *name)
2013 {
2014 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
2015 qdev_init_nofail(&dev->qdev);
2016 return dev;
2017 }
2018
2019 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2020 {
2021 return pci_create_multifunction(bus, devfn, false, name);
2022 }
2023
2024 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2025 {
2026 return pci_create_simple_multifunction(bus, devfn, false, name);
2027 }
2028
2029 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2030 {
2031 int offset = PCI_CONFIG_HEADER_SIZE;
2032 int i;
2033 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2034 if (pdev->used[i])
2035 offset = i + 1;
2036 else if (i - offset + 1 == size)
2037 return offset;
2038 }
2039 return 0;
2040 }
2041
2042 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2043 uint8_t *prev_p)
2044 {
2045 uint8_t next, prev;
2046
2047 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2048 return 0;
2049
2050 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2051 prev = next + PCI_CAP_LIST_NEXT)
2052 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2053 break;
2054
2055 if (prev_p)
2056 *prev_p = prev;
2057 return next;
2058 }
2059
2060 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2061 {
2062 uint8_t next, prev, found = 0;
2063
2064 if (!(pdev->used[offset])) {
2065 return 0;
2066 }
2067
2068 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2069
2070 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2071 prev = next + PCI_CAP_LIST_NEXT) {
2072 if (next <= offset && next > found) {
2073 found = next;
2074 }
2075 }
2076 return found;
2077 }
2078
2079 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2080 This is needed for an option rom which is used for more than one device. */
2081 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2082 {
2083 uint16_t vendor_id;
2084 uint16_t device_id;
2085 uint16_t rom_vendor_id;
2086 uint16_t rom_device_id;
2087 uint16_t rom_magic;
2088 uint16_t pcir_offset;
2089 uint8_t checksum;
2090
2091 /* Words in rom data are little endian (like in PCI configuration),
2092 so they can be read / written with pci_get_word / pci_set_word. */
2093
2094 /* Only a valid rom will be patched. */
2095 rom_magic = pci_get_word(ptr);
2096 if (rom_magic != 0xaa55) {
2097 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2098 return;
2099 }
2100 pcir_offset = pci_get_word(ptr + 0x18);
2101 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2102 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2103 return;
2104 }
2105
2106 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2107 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2108 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2109 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2110
2111 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2112 vendor_id, device_id, rom_vendor_id, rom_device_id);
2113
2114 checksum = ptr[6];
2115
2116 if (vendor_id != rom_vendor_id) {
2117 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2118 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2119 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2120 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2121 ptr[6] = checksum;
2122 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2123 }
2124
2125 if (device_id != rom_device_id) {
2126 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2127 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2128 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2129 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2130 ptr[6] = checksum;
2131 pci_set_word(ptr + pcir_offset + 6, device_id);
2132 }
2133 }
2134
2135 /* Add an option rom for the device */
2136 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2137 Error **errp)
2138 {
2139 int size;
2140 char *path;
2141 void *ptr;
2142 char name[32];
2143 const VMStateDescription *vmsd;
2144
2145 if (!pdev->romfile)
2146 return;
2147 if (strlen(pdev->romfile) == 0)
2148 return;
2149
2150 if (!pdev->rom_bar) {
2151 /*
2152 * Load rom via fw_cfg instead of creating a rom bar,
2153 * for 0.11 compatibility.
2154 */
2155 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2156
2157 /*
2158 * Hot-plugged devices can't use the option ROM
2159 * if the rom bar is disabled.
2160 */
2161 if (DEVICE(pdev)->hotplugged) {
2162 error_setg(errp, "Hot-plugged device without ROM bar"
2163 " can't have an option ROM");
2164 return;
2165 }
2166
2167 if (class == 0x0300) {
2168 rom_add_vga(pdev->romfile);
2169 } else {
2170 rom_add_option(pdev->romfile, -1);
2171 }
2172 return;
2173 }
2174
2175 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2176 if (path == NULL) {
2177 path = g_strdup(pdev->romfile);
2178 }
2179
2180 size = get_image_size(path);
2181 if (size < 0) {
2182 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2183 g_free(path);
2184 return;
2185 } else if (size == 0) {
2186 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2187 g_free(path);
2188 return;
2189 }
2190 size = pow2ceil(size);
2191
2192 vmsd = qdev_get_vmsd(DEVICE(pdev));
2193
2194 if (vmsd) {
2195 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2196 } else {
2197 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2198 }
2199 pdev->has_rom = true;
2200 memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
2201 vmstate_register_ram(&pdev->rom, &pdev->qdev);
2202 ptr = memory_region_get_ram_ptr(&pdev->rom);
2203 load_image(path, ptr);
2204 g_free(path);
2205
2206 if (is_default_rom) {
2207 /* Only the default rom images will be patched (if needed). */
2208 pci_patch_ids(pdev, ptr, size);
2209 }
2210
2211 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2212 }
2213
2214 static void pci_del_option_rom(PCIDevice *pdev)
2215 {
2216 if (!pdev->has_rom)
2217 return;
2218
2219 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2220 pdev->has_rom = false;
2221 }
2222
2223 /*
2224 * if offset = 0,
2225 * Find and reserve space and add capability to the linked list
2226 * in pci config space
2227 */
2228 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2229 uint8_t offset, uint8_t size)
2230 {
2231 int ret;
2232 Error *local_err = NULL;
2233
2234 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
2235 if (local_err) {
2236 assert(ret < 0);
2237 error_report_err(local_err);
2238 } else {
2239 /* success implies a positive offset in config space */
2240 assert(ret > 0);
2241 }
2242 return ret;
2243 }
2244
2245 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
2246 uint8_t offset, uint8_t size,
2247 Error **errp)
2248 {
2249 uint8_t *config;
2250 int i, overlapping_cap;
2251
2252 if (!offset) {
2253 offset = pci_find_space(pdev, size);
2254 /* out of PCI config space is programming error */
2255 assert(offset);
2256 } else {
2257 /* Verify that capabilities don't overlap. Note: device assignment
2258 * depends on this check to verify that the device is not broken.
2259 * Should never trigger for emulated devices, but it's helpful
2260 * for debugging these. */
2261 for (i = offset; i < offset + size; i++) {
2262 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2263 if (overlapping_cap) {
2264 error_setg(errp, "%s:%02x:%02x.%x "
2265 "Attempt to add PCI capability %x at offset "
2266 "%x overlaps existing capability %x at offset %x",
2267 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2268 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2269 cap_id, offset, overlapping_cap, i);
2270 return -EINVAL;
2271 }
2272 }
2273 }
2274
2275 config = pdev->config + offset;
2276 config[PCI_CAP_LIST_ID] = cap_id;
2277 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2278 pdev->config[PCI_CAPABILITY_LIST] = offset;
2279 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2280 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2281 /* Make capability read-only by default */
2282 memset(pdev->wmask + offset, 0, size);
2283 /* Check capability by default */
2284 memset(pdev->cmask + offset, 0xFF, size);
2285 return offset;
2286 }
2287
2288 /* Unlink capability from the pci config space. */
2289 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2290 {
2291 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2292 if (!offset)
2293 return;
2294 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2295 /* Make capability writable again */
2296 memset(pdev->wmask + offset, 0xff, size);
2297 memset(pdev->w1cmask + offset, 0, size);
2298 /* Clear cmask as device-specific registers can't be checked */
2299 memset(pdev->cmask + offset, 0, size);
2300 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2301
2302 if (!pdev->config[PCI_CAPABILITY_LIST])
2303 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2304 }
2305
2306 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2307 {
2308 return pci_find_capability_list(pdev, cap_id, NULL);
2309 }
2310
2311 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2312 {
2313 PCIDevice *d = (PCIDevice *)dev;
2314 const pci_class_desc *desc;
2315 char ctxt[64];
2316 PCIIORegion *r;
2317 int i, class;
2318
2319 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2320 desc = pci_class_descriptions;
2321 while (desc->desc && class != desc->class)
2322 desc++;
2323 if (desc->desc) {
2324 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2325 } else {
2326 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2327 }
2328
2329 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2330 "pci id %04x:%04x (sub %04x:%04x)\n",
2331 indent, "", ctxt, pci_bus_num(d->bus),
2332 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2333 pci_get_word(d->config + PCI_VENDOR_ID),
2334 pci_get_word(d->config + PCI_DEVICE_ID),
2335 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2336 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2337 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2338 r = &d->io_regions[i];
2339 if (!r->size)
2340 continue;
2341 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2342 " [0x%"FMT_PCIBUS"]\n",
2343 indent, "",
2344 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2345 r->addr, r->addr + r->size - 1);
2346 }
2347 }
2348
2349 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2350 {
2351 PCIDevice *d = (PCIDevice *)dev;
2352 const char *name = NULL;
2353 const pci_class_desc *desc = pci_class_descriptions;
2354 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2355
2356 while (desc->desc &&
2357 (class & ~desc->fw_ign_bits) !=
2358 (desc->class & ~desc->fw_ign_bits)) {
2359 desc++;
2360 }
2361
2362 if (desc->desc) {
2363 name = desc->fw_name;
2364 }
2365
2366 if (name) {
2367 pstrcpy(buf, len, name);
2368 } else {
2369 snprintf(buf, len, "pci%04x,%04x",
2370 pci_get_word(d->config + PCI_VENDOR_ID),
2371 pci_get_word(d->config + PCI_DEVICE_ID));
2372 }
2373
2374 return buf;
2375 }
2376
2377 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2378 {
2379 PCIDevice *d = (PCIDevice *)dev;
2380 char path[50], name[33];
2381 int off;
2382
2383 off = snprintf(path, sizeof(path), "%s@%x",
2384 pci_dev_fw_name(dev, name, sizeof name),
2385 PCI_SLOT(d->devfn));
2386 if (PCI_FUNC(d->devfn))
2387 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2388 return g_strdup(path);
2389 }
2390
2391 static char *pcibus_get_dev_path(DeviceState *dev)
2392 {
2393 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2394 PCIDevice *t;
2395 int slot_depth;
2396 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2397 * 00 is added here to make this format compatible with
2398 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2399 * Slot.Function list specifies the slot and function numbers for all
2400 * devices on the path from root to the specific device. */
2401 const char *root_bus_path;
2402 int root_bus_len;
2403 char slot[] = ":SS.F";
2404 int slot_len = sizeof slot - 1 /* For '\0' */;
2405 int path_len;
2406 char *path, *p;
2407 int s;
2408
2409 root_bus_path = pci_root_bus_path(d);
2410 root_bus_len = strlen(root_bus_path);
2411
2412 /* Calculate # of slots on path between device and root. */;
2413 slot_depth = 0;
2414 for (t = d; t; t = t->bus->parent_dev) {
2415 ++slot_depth;
2416 }
2417
2418 path_len = root_bus_len + slot_len * slot_depth;
2419
2420 /* Allocate memory, fill in the terminating null byte. */
2421 path = g_malloc(path_len + 1 /* For '\0' */);
2422 path[path_len] = '\0';
2423
2424 memcpy(path, root_bus_path, root_bus_len);
2425
2426 /* Fill in slot numbers. We walk up from device to root, so need to print
2427 * them in the reverse order, last to first. */
2428 p = path + path_len;
2429 for (t = d; t; t = t->bus->parent_dev) {
2430 p -= slot_len;
2431 s = snprintf(slot, sizeof slot, ":%02x.%x",
2432 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2433 assert(s == slot_len);
2434 memcpy(p, slot, slot_len);
2435 }
2436
2437 return path;
2438 }
2439
2440 static int pci_qdev_find_recursive(PCIBus *bus,
2441 const char *id, PCIDevice **pdev)
2442 {
2443 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2444 if (!qdev) {
2445 return -ENODEV;
2446 }
2447
2448 /* roughly check if given qdev is pci device */
2449 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2450 *pdev = PCI_DEVICE(qdev);
2451 return 0;
2452 }
2453 return -EINVAL;
2454 }
2455
2456 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2457 {
2458 PCIHostState *host_bridge;
2459 int rc = -ENODEV;
2460
2461 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2462 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2463 if (!tmp) {
2464 rc = 0;
2465 break;
2466 }
2467 if (tmp != -ENODEV) {
2468 rc = tmp;
2469 }
2470 }
2471
2472 return rc;
2473 }
2474
2475 MemoryRegion *pci_address_space(PCIDevice *dev)
2476 {
2477 return dev->bus->address_space_mem;
2478 }
2479
2480 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2481 {
2482 return dev->bus->address_space_io;
2483 }
2484
2485 static void pci_device_class_init(ObjectClass *klass, void *data)
2486 {
2487 DeviceClass *k = DEVICE_CLASS(klass);
2488 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
2489
2490 k->realize = pci_qdev_realize;
2491 k->unrealize = pci_qdev_unrealize;
2492 k->bus_type = TYPE_PCI_BUS;
2493 k->props = pci_props;
2494 pc->realize = pci_default_realize;
2495 }
2496
2497 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2498 {
2499 PCIBus *bus = PCI_BUS(dev->bus);
2500 PCIBus *iommu_bus = bus;
2501
2502 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2503 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus);
2504 }
2505 if (iommu_bus && iommu_bus->iommu_fn) {
2506 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
2507 }
2508 return &address_space_memory;
2509 }
2510
2511 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2512 {
2513 bus->iommu_fn = fn;
2514 bus->iommu_opaque = opaque;
2515 }
2516
2517 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2518 {
2519 Range *range = opaque;
2520 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2521 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2522 int i;
2523
2524 if (!(cmd & PCI_COMMAND_MEMORY)) {
2525 return;
2526 }
2527
2528 if (pc->is_bridge) {
2529 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2530 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2531
2532 base = MAX(base, 0x1ULL << 32);
2533
2534 if (limit >= base) {
2535 Range pref_range;
2536 pref_range.begin = base;
2537 pref_range.end = limit + 1;
2538 range_extend(range, &pref_range);
2539 }
2540 }
2541 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2542 PCIIORegion *r = &dev->io_regions[i];
2543 Range region_range;
2544
2545 if (!r->size ||
2546 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2547 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2548 continue;
2549 }
2550 region_range.begin = pci_bar_address(dev, i, r->type, r->size);
2551 region_range.end = region_range.begin + r->size;
2552
2553 if (region_range.begin == PCI_BAR_UNMAPPED) {
2554 continue;
2555 }
2556
2557 region_range.begin = MAX(region_range.begin, 0x1ULL << 32);
2558
2559 if (region_range.end - 1 >= region_range.begin) {
2560 range_extend(range, &region_range);
2561 }
2562 }
2563 }
2564
2565 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2566 {
2567 range->begin = range->end = 0;
2568 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2569 }
2570
2571 static bool pcie_has_upstream_port(PCIDevice *dev)
2572 {
2573 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus);
2574
2575 /* Device associated with an upstream port.
2576 * As there are several types of these, it's easier to check the
2577 * parent device: upstream ports are always connected to
2578 * root or downstream ports.
2579 */
2580 return parent_dev &&
2581 pci_is_express(parent_dev) &&
2582 parent_dev->exp.exp_cap &&
2583 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2584 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2585 }
2586
2587 PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2588 {
2589 if(pcie_has_upstream_port(pci_dev)) {
2590 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2591 return pci_dev->bus->devices[0];
2592 } else {
2593 /* Other bus types might support multiple devices at slots 0-31 */
2594 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2595 }
2596 }
2597
2598 static const TypeInfo pci_device_type_info = {
2599 .name = TYPE_PCI_DEVICE,
2600 .parent = TYPE_DEVICE,
2601 .instance_size = sizeof(PCIDevice),
2602 .abstract = true,
2603 .class_size = sizeof(PCIDeviceClass),
2604 .class_init = pci_device_class_init,
2605 };
2606
2607 static void pci_register_types(void)
2608 {
2609 type_register_static(&pci_bus_info);
2610 type_register_static(&pcie_bus_info);
2611 type_register_static(&pci_device_type_info);
2612 }
2613
2614 type_init(pci_register_types)
AR7 emulation for QEMU