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util/mmap-alloc: check parameter before using
[qemu/ar7.git] / linux-user / main.c
blobdb4eb682a2fe82425e24232eae771b2b7b0bae08
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu-version.h"
21 #include <sys/syscall.h>
22 #include <sys/resource.h>
23
24 #include "qapi/error.h"
25 #include "qemu.h"
26 #include "qemu/path.h"
27 #include "qemu/config-file.h"
28 #include "qemu/cutils.h"
29 #include "qemu/help_option.h"
30 #include "cpu.h"
31 #include "exec/exec-all.h"
32 #include "tcg.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
35 #include "elf.h"
36 #include "exec/log.h"
37 #include "trace/control.h"
38 #include "glib-compat.h"
39
40 char *exec_path;
41
42 int singlestep;
43 static const char *filename;
44 static const char *argv0;
45 static int gdbstub_port;
46 static envlist_t *envlist;
47 static const char *cpu_model;
48 unsigned long mmap_min_addr;
49 unsigned long guest_base;
50 int have_guest_base;
51
52 #define EXCP_DUMP(env, fmt, ...) \
53 do { \
54 CPUState *cs = ENV_GET_CPU(env); \
55 fprintf(stderr, fmt , ## __VA_ARGS__); \
56 cpu_dump_state(cs, stderr, fprintf, 0); \
57 if (qemu_log_separate()) { \
58 qemu_log(fmt, ## __VA_ARGS__); \
59 log_cpu_state(cs, 0); \
60 } \
61 } while (0)
62
63 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
64 /*
65 * When running 32-on-64 we should make sure we can fit all of the possible
66 * guest address space into a contiguous chunk of virtual host memory.
67 *
68 * This way we will never overlap with our own libraries or binaries or stack
69 * or anything else that QEMU maps.
70 */
71 # ifdef TARGET_MIPS
72 /* MIPS only supports 31 bits of virtual address space for user space */
73 unsigned long reserved_va = 0x77000000;
74 # else
75 unsigned long reserved_va = 0xf7000000;
76 # endif
77 #else
78 unsigned long reserved_va;
79 #endif
80
81 static void usage(int exitcode);
82
83 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
84 const char *qemu_uname_release;
85
86 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
87 we allocate a bigger stack. Need a better solution, for example
88 by remapping the process stack directly at the right place */
89 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
90
91 void gemu_log(const char *fmt, ...)
92 {
93 va_list ap;
94
95 va_start(ap, fmt);
96 vfprintf(stderr, fmt, ap);
97 va_end(ap);
98 }
99
100 #if defined(TARGET_I386)
101 int cpu_get_pic_interrupt(CPUX86State *env)
102 {
103 return -1;
104 }
105 #endif
106
107 /***********************************************************/
108 /* Helper routines for implementing atomic operations. */
109
110 /* Make sure everything is in a consistent state for calling fork(). */
111 void fork_start(void)
112 {
113 cpu_list_lock();
114 qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
115 mmap_fork_start();
116 }
117
118 void fork_end(int child)
119 {
120 mmap_fork_end(child);
121 if (child) {
122 CPUState *cpu, *next_cpu;
123 /* Child processes created by fork() only have a single thread.
124 Discard information about the parent threads. */
125 CPU_FOREACH_SAFE(cpu, next_cpu) {
126 if (cpu != thread_cpu) {
127 QTAILQ_REMOVE(&cpus, cpu, node);
128 }
129 }
130 qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock);
131 qemu_init_cpu_list();
132 gdbserver_fork(thread_cpu);
133 } else {
134 qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
135 cpu_list_unlock();
136 }
137 }
138
139 #ifdef TARGET_I386
140 /***********************************************************/
141 /* CPUX86 core interface */
142
143 uint64_t cpu_get_tsc(CPUX86State *env)
144 {
145 return cpu_get_host_ticks();
146 }
147
148 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
149 int flags)
150 {
151 unsigned int e1, e2;
152 uint32_t *p;
153 e1 = (addr << 16) | (limit & 0xffff);
154 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
155 e2 |= flags;
156 p = ptr;
157 p[0] = tswap32(e1);
158 p[1] = tswap32(e2);
159 }
160
161 static uint64_t *idt_table;
162 #ifdef TARGET_X86_64
163 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
164 uint64_t addr, unsigned int sel)
165 {
166 uint32_t *p, e1, e2;
167 e1 = (addr & 0xffff) | (sel << 16);
168 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
169 p = ptr;
170 p[0] = tswap32(e1);
171 p[1] = tswap32(e2);
172 p[2] = tswap32(addr >> 32);
173 p[3] = 0;
174 }
175 /* only dpl matters as we do only user space emulation */
176 static void set_idt(int n, unsigned int dpl)
177 {
178 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
179 }
180 #else
181 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
182 uint32_t addr, unsigned int sel)
183 {
184 uint32_t *p, e1, e2;
185 e1 = (addr & 0xffff) | (sel << 16);
186 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
187 p = ptr;
188 p[0] = tswap32(e1);
189 p[1] = tswap32(e2);
190 }
191
192 /* only dpl matters as we do only user space emulation */
193 static void set_idt(int n, unsigned int dpl)
194 {
195 set_gate(idt_table + n, 0, dpl, 0, 0);
196 }
197 #endif
198
199 void cpu_loop(CPUX86State *env)
200 {
201 CPUState *cs = CPU(x86_env_get_cpu(env));
202 int trapnr;
203 abi_ulong pc;
204 abi_ulong ret;
205 target_siginfo_t info;
206
207 for(;;) {
208 cpu_exec_start(cs);
209 trapnr = cpu_exec(cs);
210 cpu_exec_end(cs);
211 process_queued_cpu_work(cs);
212
213 switch(trapnr) {
214 case 0x80:
215 /* linux syscall from int $0x80 */
216 ret = do_syscall(env,
217 env->regs[R_EAX],
218 env->regs[R_EBX],
219 env->regs[R_ECX],
220 env->regs[R_EDX],
221 env->regs[R_ESI],
222 env->regs[R_EDI],
223 env->regs[R_EBP],
224 0, 0);
225 if (ret == -TARGET_ERESTARTSYS) {
226 env->eip -= 2;
227 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
228 env->regs[R_EAX] = ret;
229 }
230 break;
231 #ifndef TARGET_ABI32
232 case EXCP_SYSCALL:
233 /* linux syscall from syscall instruction */
234 ret = do_syscall(env,
235 env->regs[R_EAX],
236 env->regs[R_EDI],
237 env->regs[R_ESI],
238 env->regs[R_EDX],
239 env->regs[10],
240 env->regs[8],
241 env->regs[9],
242 0, 0);
243 if (ret == -TARGET_ERESTARTSYS) {
244 env->eip -= 2;
245 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
246 env->regs[R_EAX] = ret;
247 }
248 break;
249 #endif
250 case EXCP0B_NOSEG:
251 case EXCP0C_STACK:
252 info.si_signo = TARGET_SIGBUS;
253 info.si_errno = 0;
254 info.si_code = TARGET_SI_KERNEL;
255 info._sifields._sigfault._addr = 0;
256 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
257 break;
258 case EXCP0D_GPF:
259 /* XXX: potential problem if ABI32 */
260 #ifndef TARGET_X86_64
261 if (env->eflags & VM_MASK) {
262 handle_vm86_fault(env);
263 } else
264 #endif
265 {
266 info.si_signo = TARGET_SIGSEGV;
267 info.si_errno = 0;
268 info.si_code = TARGET_SI_KERNEL;
269 info._sifields._sigfault._addr = 0;
270 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
271 }
272 break;
273 case EXCP0E_PAGE:
274 info.si_signo = TARGET_SIGSEGV;
275 info.si_errno = 0;
276 if (!(env->error_code & 1))
277 info.si_code = TARGET_SEGV_MAPERR;
278 else
279 info.si_code = TARGET_SEGV_ACCERR;
280 info._sifields._sigfault._addr = env->cr[2];
281 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
282 break;
283 case EXCP00_DIVZ:
284 #ifndef TARGET_X86_64
285 if (env->eflags & VM_MASK) {
286 handle_vm86_trap(env, trapnr);
287 } else
288 #endif
289 {
290 /* division by zero */
291 info.si_signo = TARGET_SIGFPE;
292 info.si_errno = 0;
293 info.si_code = TARGET_FPE_INTDIV;
294 info._sifields._sigfault._addr = env->eip;
295 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
296 }
297 break;
298 case EXCP01_DB:
299 case EXCP03_INT3:
300 #ifndef TARGET_X86_64
301 if (env->eflags & VM_MASK) {
302 handle_vm86_trap(env, trapnr);
303 } else
304 #endif
305 {
306 info.si_signo = TARGET_SIGTRAP;
307 info.si_errno = 0;
308 if (trapnr == EXCP01_DB) {
309 info.si_code = TARGET_TRAP_BRKPT;
310 info._sifields._sigfault._addr = env->eip;
311 } else {
312 info.si_code = TARGET_SI_KERNEL;
313 info._sifields._sigfault._addr = 0;
314 }
315 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
316 }
317 break;
318 case EXCP04_INTO:
319 case EXCP05_BOUND:
320 #ifndef TARGET_X86_64
321 if (env->eflags & VM_MASK) {
322 handle_vm86_trap(env, trapnr);
323 } else
324 #endif
325 {
326 info.si_signo = TARGET_SIGSEGV;
327 info.si_errno = 0;
328 info.si_code = TARGET_SI_KERNEL;
329 info._sifields._sigfault._addr = 0;
330 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
331 }
332 break;
333 case EXCP06_ILLOP:
334 info.si_signo = TARGET_SIGILL;
335 info.si_errno = 0;
336 info.si_code = TARGET_ILL_ILLOPN;
337 info._sifields._sigfault._addr = env->eip;
338 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
339 break;
340 case EXCP_INTERRUPT:
341 /* just indicate that signals should be handled asap */
342 break;
343 case EXCP_DEBUG:
344 {
345 int sig;
346
347 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
348 if (sig)
349 {
350 info.si_signo = sig;
351 info.si_errno = 0;
352 info.si_code = TARGET_TRAP_BRKPT;
353 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
354 }
355 }
356 break;
357 case EXCP_ATOMIC:
358 cpu_exec_step_atomic(cs);
359 break;
360 default:
361 pc = env->segs[R_CS].base + env->eip;
362 EXCP_DUMP(env, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
363 (long)pc, trapnr);
364 abort();
365 }
366 process_pending_signals(env);
367 }
368 }
369 #endif
370
371 #ifdef TARGET_ARM
372
373 #define get_user_code_u32(x, gaddr, env) \
374 ({ abi_long __r = get_user_u32((x), (gaddr)); \
375 if (!__r && bswap_code(arm_sctlr_b(env))) { \
376 (x) = bswap32(x); \
377 } \
378 __r; \
379 })
380
381 #define get_user_code_u16(x, gaddr, env) \
382 ({ abi_long __r = get_user_u16((x), (gaddr)); \
383 if (!__r && bswap_code(arm_sctlr_b(env))) { \
384 (x) = bswap16(x); \
385 } \
386 __r; \
387 })
388
389 #define get_user_data_u32(x, gaddr, env) \
390 ({ abi_long __r = get_user_u32((x), (gaddr)); \
391 if (!__r && arm_cpu_bswap_data(env)) { \
392 (x) = bswap32(x); \
393 } \
394 __r; \
395 })
396
397 #define get_user_data_u16(x, gaddr, env) \
398 ({ abi_long __r = get_user_u16((x), (gaddr)); \
399 if (!__r && arm_cpu_bswap_data(env)) { \
400 (x) = bswap16(x); \
401 } \
402 __r; \
403 })
404
405 #define put_user_data_u32(x, gaddr, env) \
406 ({ typeof(x) __x = (x); \
407 if (arm_cpu_bswap_data(env)) { \
408 __x = bswap32(__x); \
409 } \
410 put_user_u32(__x, (gaddr)); \
411 })
412
413 #define put_user_data_u16(x, gaddr, env) \
414 ({ typeof(x) __x = (x); \
415 if (arm_cpu_bswap_data(env)) { \
416 __x = bswap16(__x); \
417 } \
418 put_user_u16(__x, (gaddr)); \
419 })
420
421 #ifdef TARGET_ABI32
422 /* Commpage handling -- there is no commpage for AArch64 */
423
424 /*
425 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
426 * Input:
427 * r0 = pointer to oldval
428 * r1 = pointer to newval
429 * r2 = pointer to target value
430 *
431 * Output:
432 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
433 * C set if *ptr was changed, clear if no exchange happened
434 *
435 * Note segv's in kernel helpers are a bit tricky, we can set the
436 * data address sensibly but the PC address is just the entry point.
437 */
438 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
439 {
440 uint64_t oldval, newval, val;
441 uint32_t addr, cpsr;
442 target_siginfo_t info;
443
444 /* Based on the 32 bit code in do_kernel_trap */
445
446 /* XXX: This only works between threads, not between processes.
447 It's probably possible to implement this with native host
448 operations. However things like ldrex/strex are much harder so
449 there's not much point trying. */
450 start_exclusive();
451 cpsr = cpsr_read(env);
452 addr = env->regs[2];
453
454 if (get_user_u64(oldval, env->regs[0])) {
455 env->exception.vaddress = env->regs[0];
456 goto segv;
457 };
458
459 if (get_user_u64(newval, env->regs[1])) {
460 env->exception.vaddress = env->regs[1];
461 goto segv;
462 };
463
464 if (get_user_u64(val, addr)) {
465 env->exception.vaddress = addr;
466 goto segv;
467 }
468
469 if (val == oldval) {
470 val = newval;
471
472 if (put_user_u64(val, addr)) {
473 env->exception.vaddress = addr;
474 goto segv;
475 };
476
477 env->regs[0] = 0;
478 cpsr |= CPSR_C;
479 } else {
480 env->regs[0] = -1;
481 cpsr &= ~CPSR_C;
482 }
483 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
484 end_exclusive();
485 return;
486
487 segv:
488 end_exclusive();
489 /* We get the PC of the entry address - which is as good as anything,
490 on a real kernel what you get depends on which mode it uses. */
491 info.si_signo = TARGET_SIGSEGV;
492 info.si_errno = 0;
493 /* XXX: check env->error_code */
494 info.si_code = TARGET_SEGV_MAPERR;
495 info._sifields._sigfault._addr = env->exception.vaddress;
496 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
497 }
498
499 /* Handle a jump to the kernel code page. */
500 static int
501 do_kernel_trap(CPUARMState *env)
502 {
503 uint32_t addr;
504 uint32_t cpsr;
505 uint32_t val;
506
507 switch (env->regs[15]) {
508 case 0xffff0fa0: /* __kernel_memory_barrier */
509 /* ??? No-op. Will need to do better for SMP. */
510 break;
511 case 0xffff0fc0: /* __kernel_cmpxchg */
512 /* XXX: This only works between threads, not between processes.
513 It's probably possible to implement this with native host
514 operations. However things like ldrex/strex are much harder so
515 there's not much point trying. */
516 start_exclusive();
517 cpsr = cpsr_read(env);
518 addr = env->regs[2];
519 /* FIXME: This should SEGV if the access fails. */
520 if (get_user_u32(val, addr))
521 val = ~env->regs[0];
522 if (val == env->regs[0]) {
523 val = env->regs[1];
524 /* FIXME: Check for segfaults. */
525 put_user_u32(val, addr);
526 env->regs[0] = 0;
527 cpsr |= CPSR_C;
528 } else {
529 env->regs[0] = -1;
530 cpsr &= ~CPSR_C;
531 }
532 cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
533 end_exclusive();
534 break;
535 case 0xffff0fe0: /* __kernel_get_tls */
536 env->regs[0] = cpu_get_tls(env);
537 break;
538 case 0xffff0f60: /* __kernel_cmpxchg64 */
539 arm_kernel_cmpxchg64_helper(env);
540 break;
541
542 default:
543 return 1;
544 }
545 /* Jump back to the caller. */
546 addr = env->regs[14];
547 if (addr & 1) {
548 env->thumb = 1;
549 addr &= ~1;
550 }
551 env->regs[15] = addr;
552
553 return 0;
554 }
555
556 void cpu_loop(CPUARMState *env)
557 {
558 CPUState *cs = CPU(arm_env_get_cpu(env));
559 int trapnr;
560 unsigned int n, insn;
561 target_siginfo_t info;
562 uint32_t addr;
563 abi_ulong ret;
564
565 for(;;) {
566 cpu_exec_start(cs);
567 trapnr = cpu_exec(cs);
568 cpu_exec_end(cs);
569 process_queued_cpu_work(cs);
570
571 switch(trapnr) {
572 case EXCP_UDEF:
573 {
574 TaskState *ts = cs->opaque;
575 uint32_t opcode;
576 int rc;
577
578 /* we handle the FPU emulation here, as Linux */
579 /* we get the opcode */
580 /* FIXME - what to do if get_user() fails? */
581 get_user_code_u32(opcode, env->regs[15], env);
582
583 rc = EmulateAll(opcode, &ts->fpa, env);
584 if (rc == 0) { /* illegal instruction */
585 info.si_signo = TARGET_SIGILL;
586 info.si_errno = 0;
587 info.si_code = TARGET_ILL_ILLOPN;
588 info._sifields._sigfault._addr = env->regs[15];
589 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
590 } else if (rc < 0) { /* FP exception */
591 int arm_fpe=0;
592
593 /* translate softfloat flags to FPSR flags */
594 if (-rc & float_flag_invalid)
595 arm_fpe |= BIT_IOC;
596 if (-rc & float_flag_divbyzero)
597 arm_fpe |= BIT_DZC;
598 if (-rc & float_flag_overflow)
599 arm_fpe |= BIT_OFC;
600 if (-rc & float_flag_underflow)
601 arm_fpe |= BIT_UFC;
602 if (-rc & float_flag_inexact)
603 arm_fpe |= BIT_IXC;
604
605 FPSR fpsr = ts->fpa.fpsr;
606 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
607
608 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
609 info.si_signo = TARGET_SIGFPE;
610 info.si_errno = 0;
611
612 /* ordered by priority, least first */
613 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
614 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
615 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
616 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
617 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
618
619 info._sifields._sigfault._addr = env->regs[15];
620 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
621 } else {
622 env->regs[15] += 4;
623 }
624
625 /* accumulate unenabled exceptions */
626 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
627 fpsr |= BIT_IXC;
628 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
629 fpsr |= BIT_UFC;
630 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
631 fpsr |= BIT_OFC;
632 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
633 fpsr |= BIT_DZC;
634 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
635 fpsr |= BIT_IOC;
636 ts->fpa.fpsr=fpsr;
637 } else { /* everything OK */
638 /* increment PC */
639 env->regs[15] += 4;
640 }
641 }
642 break;
643 case EXCP_SWI:
644 case EXCP_BKPT:
645 {
646 env->eabi = 1;
647 /* system call */
648 if (trapnr == EXCP_BKPT) {
649 if (env->thumb) {
650 /* FIXME - what to do if get_user() fails? */
651 get_user_code_u16(insn, env->regs[15], env);
652 n = insn & 0xff;
653 env->regs[15] += 2;
654 } else {
655 /* FIXME - what to do if get_user() fails? */
656 get_user_code_u32(insn, env->regs[15], env);
657 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
658 env->regs[15] += 4;
659 }
660 } else {
661 if (env->thumb) {
662 /* FIXME - what to do if get_user() fails? */
663 get_user_code_u16(insn, env->regs[15] - 2, env);
664 n = insn & 0xff;
665 } else {
666 /* FIXME - what to do if get_user() fails? */
667 get_user_code_u32(insn, env->regs[15] - 4, env);
668 n = insn & 0xffffff;
669 }
670 }
671
672 if (n == ARM_NR_cacheflush) {
673 /* nop */
674 } else if (n == ARM_NR_semihosting
675 || n == ARM_NR_thumb_semihosting) {
676 env->regs[0] = do_arm_semihosting (env);
677 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
678 /* linux syscall */
679 if (env->thumb || n == 0) {
680 n = env->regs[7];
681 } else {
682 n -= ARM_SYSCALL_BASE;
683 env->eabi = 0;
684 }
685 if ( n > ARM_NR_BASE) {
686 switch (n) {
687 case ARM_NR_cacheflush:
688 /* nop */
689 break;
690 case ARM_NR_set_tls:
691 cpu_set_tls(env, env->regs[0]);
692 env->regs[0] = 0;
693 break;
694 case ARM_NR_breakpoint:
695 env->regs[15] -= env->thumb ? 2 : 4;
696 goto excp_debug;
697 default:
698 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
699 n);
700 env->regs[0] = -TARGET_ENOSYS;
701 break;
702 }
703 } else {
704 ret = do_syscall(env,
705 n,
706 env->regs[0],
707 env->regs[1],
708 env->regs[2],
709 env->regs[3],
710 env->regs[4],
711 env->regs[5],
712 0, 0);
713 if (ret == -TARGET_ERESTARTSYS) {
714 env->regs[15] -= env->thumb ? 2 : 4;
715 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
716 env->regs[0] = ret;
717 }
718 }
719 } else {
720 goto error;
721 }
722 }
723 break;
724 case EXCP_SEMIHOST:
725 env->regs[0] = do_arm_semihosting(env);
726 break;
727 case EXCP_INTERRUPT:
728 /* just indicate that signals should be handled asap */
729 break;
730 case EXCP_PREFETCH_ABORT:
731 case EXCP_DATA_ABORT:
732 addr = env->exception.vaddress;
733 {
734 info.si_signo = TARGET_SIGSEGV;
735 info.si_errno = 0;
736 /* XXX: check env->error_code */
737 info.si_code = TARGET_SEGV_MAPERR;
738 info._sifields._sigfault._addr = addr;
739 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
740 }
741 break;
742 case EXCP_DEBUG:
743 excp_debug:
744 {
745 int sig;
746
747 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
748 if (sig)
749 {
750 info.si_signo = sig;
751 info.si_errno = 0;
752 info.si_code = TARGET_TRAP_BRKPT;
753 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
754 }
755 }
756 break;
757 case EXCP_KERNEL_TRAP:
758 if (do_kernel_trap(env))
759 goto error;
760 break;
761 case EXCP_YIELD:
762 /* nothing to do here for user-mode, just resume guest code */
763 break;
764 case EXCP_ATOMIC:
765 cpu_exec_step_atomic(cs);
766 break;
767 default:
768 error:
769 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
770 abort();
771 }
772 process_pending_signals(env);
773 }
774 }
775
776 #else
777
778 /* AArch64 main loop */
779 void cpu_loop(CPUARMState *env)
780 {
781 CPUState *cs = CPU(arm_env_get_cpu(env));
782 int trapnr, sig;
783 abi_long ret;
784 target_siginfo_t info;
785
786 for (;;) {
787 cpu_exec_start(cs);
788 trapnr = cpu_exec(cs);
789 cpu_exec_end(cs);
790 process_queued_cpu_work(cs);
791
792 switch (trapnr) {
793 case EXCP_SWI:
794 ret = do_syscall(env,
795 env->xregs[8],
796 env->xregs[0],
797 env->xregs[1],
798 env->xregs[2],
799 env->xregs[3],
800 env->xregs[4],
801 env->xregs[5],
802 0, 0);
803 if (ret == -TARGET_ERESTARTSYS) {
804 env->pc -= 4;
805 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
806 env->xregs[0] = ret;
807 }
808 break;
809 case EXCP_INTERRUPT:
810 /* just indicate that signals should be handled asap */
811 break;
812 case EXCP_UDEF:
813 info.si_signo = TARGET_SIGILL;
814 info.si_errno = 0;
815 info.si_code = TARGET_ILL_ILLOPN;
816 info._sifields._sigfault._addr = env->pc;
817 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
818 break;
819 case EXCP_PREFETCH_ABORT:
820 case EXCP_DATA_ABORT:
821 info.si_signo = TARGET_SIGSEGV;
822 info.si_errno = 0;
823 /* XXX: check env->error_code */
824 info.si_code = TARGET_SEGV_MAPERR;
825 info._sifields._sigfault._addr = env->exception.vaddress;
826 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
827 break;
828 case EXCP_DEBUG:
829 case EXCP_BKPT:
830 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
831 if (sig) {
832 info.si_signo = sig;
833 info.si_errno = 0;
834 info.si_code = TARGET_TRAP_BRKPT;
835 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
836 }
837 break;
838 case EXCP_SEMIHOST:
839 env->xregs[0] = do_arm_semihosting(env);
840 break;
841 case EXCP_YIELD:
842 /* nothing to do here for user-mode, just resume guest code */
843 break;
844 case EXCP_ATOMIC:
845 cpu_exec_step_atomic(cs);
846 break;
847 default:
848 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
849 abort();
850 }
851 process_pending_signals(env);
852 /* Exception return on AArch64 always clears the exclusive monitor,
853 * so any return to running guest code implies this.
854 */
855 env->exclusive_addr = -1;
856 }
857 }
858 #endif /* ndef TARGET_ABI32 */
859
860 #endif
861
862 #ifdef TARGET_UNICORE32
863
864 void cpu_loop(CPUUniCore32State *env)
865 {
866 CPUState *cs = CPU(uc32_env_get_cpu(env));
867 int trapnr;
868 unsigned int n, insn;
869 target_siginfo_t info;
870
871 for (;;) {
872 cpu_exec_start(cs);
873 trapnr = cpu_exec(cs);
874 cpu_exec_end(cs);
875 process_queued_cpu_work(cs);
876
877 switch (trapnr) {
878 case UC32_EXCP_PRIV:
879 {
880 /* system call */
881 get_user_u32(insn, env->regs[31] - 4);
882 n = insn & 0xffffff;
883
884 if (n >= UC32_SYSCALL_BASE) {
885 /* linux syscall */
886 n -= UC32_SYSCALL_BASE;
887 if (n == UC32_SYSCALL_NR_set_tls) {
888 cpu_set_tls(env, env->regs[0]);
889 env->regs[0] = 0;
890 } else {
891 abi_long ret = do_syscall(env,
892 n,
893 env->regs[0],
894 env->regs[1],
895 env->regs[2],
896 env->regs[3],
897 env->regs[4],
898 env->regs[5],
899 0, 0);
900 if (ret == -TARGET_ERESTARTSYS) {
901 env->regs[31] -= 4;
902 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
903 env->regs[0] = ret;
904 }
905 }
906 } else {
907 goto error;
908 }
909 }
910 break;
911 case UC32_EXCP_DTRAP:
912 case UC32_EXCP_ITRAP:
913 info.si_signo = TARGET_SIGSEGV;
914 info.si_errno = 0;
915 /* XXX: check env->error_code */
916 info.si_code = TARGET_SEGV_MAPERR;
917 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
918 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
919 break;
920 case EXCP_INTERRUPT:
921 /* just indicate that signals should be handled asap */
922 break;
923 case EXCP_DEBUG:
924 {
925 int sig;
926
927 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
928 if (sig) {
929 info.si_signo = sig;
930 info.si_errno = 0;
931 info.si_code = TARGET_TRAP_BRKPT;
932 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
933 }
934 }
935 break;
936 case EXCP_ATOMIC:
937 cpu_exec_step_atomic(cs);
938 break;
939 default:
940 goto error;
941 }
942 process_pending_signals(env);
943 }
944
945 error:
946 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
947 abort();
948 }
949 #endif
950
951 #ifdef TARGET_SPARC
952 #define SPARC64_STACK_BIAS 2047
953
954 //#define DEBUG_WIN
955
956 /* WARNING: dealing with register windows _is_ complicated. More info
957 can be found at http://www.sics.se/~psm/sparcstack.html */
958 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
959 {
960 index = (index + cwp * 16) % (16 * env->nwindows);
961 /* wrap handling : if cwp is on the last window, then we use the
962 registers 'after' the end */
963 if (index < 8 && env->cwp == env->nwindows - 1)
964 index += 16 * env->nwindows;
965 return index;
966 }
967
968 /* save the register window 'cwp1' */
969 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
970 {
971 unsigned int i;
972 abi_ulong sp_ptr;
973
974 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
975 #ifdef TARGET_SPARC64
976 if (sp_ptr & 3)
977 sp_ptr += SPARC64_STACK_BIAS;
978 #endif
979 #if defined(DEBUG_WIN)
980 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
981 sp_ptr, cwp1);
982 #endif
983 for(i = 0; i < 16; i++) {
984 /* FIXME - what to do if put_user() fails? */
985 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
986 sp_ptr += sizeof(abi_ulong);
987 }
988 }
989
990 static void save_window(CPUSPARCState *env)
991 {
992 #ifndef TARGET_SPARC64
993 unsigned int new_wim;
994 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
995 ((1LL << env->nwindows) - 1);
996 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
997 env->wim = new_wim;
998 #else
999 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1000 env->cansave++;
1001 env->canrestore--;
1002 #endif
1003 }
1004
1005 static void restore_window(CPUSPARCState *env)
1006 {
1007 #ifndef TARGET_SPARC64
1008 unsigned int new_wim;
1009 #endif
1010 unsigned int i, cwp1;
1011 abi_ulong sp_ptr;
1012
1013 #ifndef TARGET_SPARC64
1014 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1015 ((1LL << env->nwindows) - 1);
1016 #endif
1017
1018 /* restore the invalid window */
1019 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1020 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1021 #ifdef TARGET_SPARC64
1022 if (sp_ptr & 3)
1023 sp_ptr += SPARC64_STACK_BIAS;
1024 #endif
1025 #if defined(DEBUG_WIN)
1026 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1027 sp_ptr, cwp1);
1028 #endif
1029 for(i = 0; i < 16; i++) {
1030 /* FIXME - what to do if get_user() fails? */
1031 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1032 sp_ptr += sizeof(abi_ulong);
1033 }
1034 #ifdef TARGET_SPARC64
1035 env->canrestore++;
1036 if (env->cleanwin < env->nwindows - 1)
1037 env->cleanwin++;
1038 env->cansave--;
1039 #else
1040 env->wim = new_wim;
1041 #endif
1042 }
1043
1044 static void flush_windows(CPUSPARCState *env)
1045 {
1046 int offset, cwp1;
1047
1048 offset = 1;
1049 for(;;) {
1050 /* if restore would invoke restore_window(), then we can stop */
1051 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1052 #ifndef TARGET_SPARC64
1053 if (env->wim & (1 << cwp1))
1054 break;
1055 #else
1056 if (env->canrestore == 0)
1057 break;
1058 env->cansave++;
1059 env->canrestore--;
1060 #endif
1061 save_window_offset(env, cwp1);
1062 offset++;
1063 }
1064 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1065 #ifndef TARGET_SPARC64
1066 /* set wim so that restore will reload the registers */
1067 env->wim = 1 << cwp1;
1068 #endif
1069 #if defined(DEBUG_WIN)
1070 printf("flush_windows: nb=%d\n", offset - 1);
1071 #endif
1072 }
1073
1074 void cpu_loop (CPUSPARCState *env)
1075 {
1076 CPUState *cs = CPU(sparc_env_get_cpu(env));
1077 int trapnr;
1078 abi_long ret;
1079 target_siginfo_t info;
1080
1081 while (1) {
1082 cpu_exec_start(cs);
1083 trapnr = cpu_exec(cs);
1084 cpu_exec_end(cs);
1085 process_queued_cpu_work(cs);
1086
1087 /* Compute PSR before exposing state. */
1088 if (env->cc_op != CC_OP_FLAGS) {
1089 cpu_get_psr(env);
1090 }
1091
1092 switch (trapnr) {
1093 #ifndef TARGET_SPARC64
1094 case 0x88:
1095 case 0x90:
1096 #else
1097 case 0x110:
1098 case 0x16d:
1099 #endif
1100 ret = do_syscall (env, env->gregs[1],
1101 env->regwptr[0], env->regwptr[1],
1102 env->regwptr[2], env->regwptr[3],
1103 env->regwptr[4], env->regwptr[5],
1104 0, 0);
1105 if (ret == -TARGET_ERESTARTSYS || ret == -TARGET_QEMU_ESIGRETURN) {
1106 break;
1107 }
1108 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1109 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1110 env->xcc |= PSR_CARRY;
1111 #else
1112 env->psr |= PSR_CARRY;
1113 #endif
1114 ret = -ret;
1115 } else {
1116 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1117 env->xcc &= ~PSR_CARRY;
1118 #else
1119 env->psr &= ~PSR_CARRY;
1120 #endif
1121 }
1122 env->regwptr[0] = ret;
1123 /* next instruction */
1124 env->pc = env->npc;
1125 env->npc = env->npc + 4;
1126 break;
1127 case 0x83: /* flush windows */
1128 #ifdef TARGET_ABI32
1129 case 0x103:
1130 #endif
1131 flush_windows(env);
1132 /* next instruction */
1133 env->pc = env->npc;
1134 env->npc = env->npc + 4;
1135 break;
1136 #ifndef TARGET_SPARC64
1137 case TT_WIN_OVF: /* window overflow */
1138 save_window(env);
1139 break;
1140 case TT_WIN_UNF: /* window underflow */
1141 restore_window(env);
1142 break;
1143 case TT_TFAULT:
1144 case TT_DFAULT:
1145 {
1146 info.si_signo = TARGET_SIGSEGV;
1147 info.si_errno = 0;
1148 /* XXX: check env->error_code */
1149 info.si_code = TARGET_SEGV_MAPERR;
1150 info._sifields._sigfault._addr = env->mmuregs[4];
1151 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1152 }
1153 break;
1154 #else
1155 case TT_SPILL: /* window overflow */
1156 save_window(env);
1157 break;
1158 case TT_FILL: /* window underflow */
1159 restore_window(env);
1160 break;
1161 case TT_TFAULT:
1162 case TT_DFAULT:
1163 {
1164 info.si_signo = TARGET_SIGSEGV;
1165 info.si_errno = 0;
1166 /* XXX: check env->error_code */
1167 info.si_code = TARGET_SEGV_MAPERR;
1168 if (trapnr == TT_DFAULT)
1169 info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
1170 else
1171 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1172 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1173 }
1174 break;
1175 #ifndef TARGET_ABI32
1176 case 0x16e:
1177 flush_windows(env);
1178 sparc64_get_context(env);
1179 break;
1180 case 0x16f:
1181 flush_windows(env);
1182 sparc64_set_context(env);
1183 break;
1184 #endif
1185 #endif
1186 case EXCP_INTERRUPT:
1187 /* just indicate that signals should be handled asap */
1188 break;
1189 case TT_ILL_INSN:
1190 {
1191 info.si_signo = TARGET_SIGILL;
1192 info.si_errno = 0;
1193 info.si_code = TARGET_ILL_ILLOPC;
1194 info._sifields._sigfault._addr = env->pc;
1195 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1196 }
1197 break;
1198 case EXCP_DEBUG:
1199 {
1200 int sig;
1201
1202 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1203 if (sig)
1204 {
1205 info.si_signo = sig;
1206 info.si_errno = 0;
1207 info.si_code = TARGET_TRAP_BRKPT;
1208 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1209 }
1210 }
1211 break;
1212 case EXCP_ATOMIC:
1213 cpu_exec_step_atomic(cs);
1214 break;
1215 default:
1216 printf ("Unhandled trap: 0x%x\n", trapnr);
1217 cpu_dump_state(cs, stderr, fprintf, 0);
1218 exit(EXIT_FAILURE);
1219 }
1220 process_pending_signals (env);
1221 }
1222 }
1223
1224 #endif
1225
1226 #ifdef TARGET_PPC
1227 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1228 {
1229 return cpu_get_host_ticks();
1230 }
1231
1232 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1233 {
1234 return cpu_ppc_get_tb(env);
1235 }
1236
1237 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1238 {
1239 return cpu_ppc_get_tb(env) >> 32;
1240 }
1241
1242 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1243 {
1244 return cpu_ppc_get_tb(env);
1245 }
1246
1247 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1248 {
1249 return cpu_ppc_get_tb(env) >> 32;
1250 }
1251
1252 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1253 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1254
1255 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1256 {
1257 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1258 }
1259
1260 /* XXX: to be fixed */
1261 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1262 {
1263 return -1;
1264 }
1265
1266 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1267 {
1268 return -1;
1269 }
1270
1271 static int do_store_exclusive(CPUPPCState *env)
1272 {
1273 target_ulong addr;
1274 target_ulong page_addr;
1275 target_ulong val, val2 __attribute__((unused)) = 0;
1276 int flags;
1277 int segv = 0;
1278
1279 addr = env->reserve_ea;
1280 page_addr = addr & TARGET_PAGE_MASK;
1281 start_exclusive();
1282 mmap_lock();
1283 flags = page_get_flags(page_addr);
1284 if ((flags & PAGE_READ) == 0) {
1285 segv = 1;
1286 } else {
1287 int reg = env->reserve_info & 0x1f;
1288 int size = env->reserve_info >> 5;
1289 int stored = 0;
1290
1291 if (addr == env->reserve_addr) {
1292 switch (size) {
1293 case 1: segv = get_user_u8(val, addr); break;
1294 case 2: segv = get_user_u16(val, addr); break;
1295 case 4: segv = get_user_u32(val, addr); break;
1296 #if defined(TARGET_PPC64)
1297 case 8: segv = get_user_u64(val, addr); break;
1298 case 16: {
1299 segv = get_user_u64(val, addr);
1300 if (!segv) {
1301 segv = get_user_u64(val2, addr + 8);
1302 }
1303 break;
1304 }
1305 #endif
1306 default: abort();
1307 }
1308 if (!segv && val == env->reserve_val) {
1309 val = env->gpr[reg];
1310 switch (size) {
1311 case 1: segv = put_user_u8(val, addr); break;
1312 case 2: segv = put_user_u16(val, addr); break;
1313 case 4: segv = put_user_u32(val, addr); break;
1314 #if defined(TARGET_PPC64)
1315 case 8: segv = put_user_u64(val, addr); break;
1316 case 16: {
1317 if (val2 == env->reserve_val2) {
1318 if (msr_le) {
1319 val2 = val;
1320 val = env->gpr[reg+1];
1321 } else {
1322 val2 = env->gpr[reg+1];
1323 }
1324 segv = put_user_u64(val, addr);
1325 if (!segv) {
1326 segv = put_user_u64(val2, addr + 8);
1327 }
1328 }
1329 break;
1330 }
1331 #endif
1332 default: abort();
1333 }
1334 if (!segv) {
1335 stored = 1;
1336 }
1337 }
1338 }
1339 env->crf[0] = (stored << 1) | xer_so;
1340 env->reserve_addr = (target_ulong)-1;
1341 }
1342 if (!segv) {
1343 env->nip += 4;
1344 }
1345 mmap_unlock();
1346 end_exclusive();
1347 return segv;
1348 }
1349
1350 void cpu_loop(CPUPPCState *env)
1351 {
1352 CPUState *cs = CPU(ppc_env_get_cpu(env));
1353 target_siginfo_t info;
1354 int trapnr;
1355 target_ulong ret;
1356
1357 for(;;) {
1358 cpu_exec_start(cs);
1359 trapnr = cpu_exec(cs);
1360 cpu_exec_end(cs);
1361 process_queued_cpu_work(cs);
1362
1363 switch(trapnr) {
1364 case POWERPC_EXCP_NONE:
1365 /* Just go on */
1366 break;
1367 case POWERPC_EXCP_CRITICAL: /* Critical input */
1368 cpu_abort(cs, "Critical interrupt while in user mode. "
1369 "Aborting\n");
1370 break;
1371 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1372 cpu_abort(cs, "Machine check exception while in user mode. "
1373 "Aborting\n");
1374 break;
1375 case POWERPC_EXCP_DSI: /* Data storage exception */
1376 /* XXX: check this. Seems bugged */
1377 switch (env->error_code & 0xFF000000) {
1378 case 0x40000000:
1379 case 0x42000000:
1380 info.si_signo = TARGET_SIGSEGV;
1381 info.si_errno = 0;
1382 info.si_code = TARGET_SEGV_MAPERR;
1383 break;
1384 case 0x04000000:
1385 info.si_signo = TARGET_SIGILL;
1386 info.si_errno = 0;
1387 info.si_code = TARGET_ILL_ILLADR;
1388 break;
1389 case 0x08000000:
1390 info.si_signo = TARGET_SIGSEGV;
1391 info.si_errno = 0;
1392 info.si_code = TARGET_SEGV_ACCERR;
1393 break;
1394 default:
1395 /* Let's send a regular segfault... */
1396 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1397 env->error_code);
1398 info.si_signo = TARGET_SIGSEGV;
1399 info.si_errno = 0;
1400 info.si_code = TARGET_SEGV_MAPERR;
1401 break;
1402 }
1403 info._sifields._sigfault._addr = env->nip;
1404 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1405 break;
1406 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1407 /* XXX: check this */
1408 switch (env->error_code & 0xFF000000) {
1409 case 0x40000000:
1410 info.si_signo = TARGET_SIGSEGV;
1411 info.si_errno = 0;
1412 info.si_code = TARGET_SEGV_MAPERR;
1413 break;
1414 case 0x10000000:
1415 case 0x08000000:
1416 info.si_signo = TARGET_SIGSEGV;
1417 info.si_errno = 0;
1418 info.si_code = TARGET_SEGV_ACCERR;
1419 break;
1420 default:
1421 /* Let's send a regular segfault... */
1422 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1423 env->error_code);
1424 info.si_signo = TARGET_SIGSEGV;
1425 info.si_errno = 0;
1426 info.si_code = TARGET_SEGV_MAPERR;
1427 break;
1428 }
1429 info._sifields._sigfault._addr = env->nip - 4;
1430 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1431 break;
1432 case POWERPC_EXCP_EXTERNAL: /* External input */
1433 cpu_abort(cs, "External interrupt while in user mode. "
1434 "Aborting\n");
1435 break;
1436 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1437 /* XXX: check this */
1438 info.si_signo = TARGET_SIGBUS;
1439 info.si_errno = 0;
1440 info.si_code = TARGET_BUS_ADRALN;
1441 info._sifields._sigfault._addr = env->nip;
1442 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1443 break;
1444 case POWERPC_EXCP_PROGRAM: /* Program exception */
1445 case POWERPC_EXCP_HV_EMU: /* HV emulation */
1446 /* XXX: check this */
1447 switch (env->error_code & ~0xF) {
1448 case POWERPC_EXCP_FP:
1449 info.si_signo = TARGET_SIGFPE;
1450 info.si_errno = 0;
1451 switch (env->error_code & 0xF) {
1452 case POWERPC_EXCP_FP_OX:
1453 info.si_code = TARGET_FPE_FLTOVF;
1454 break;
1455 case POWERPC_EXCP_FP_UX:
1456 info.si_code = TARGET_FPE_FLTUND;
1457 break;
1458 case POWERPC_EXCP_FP_ZX:
1459 case POWERPC_EXCP_FP_VXZDZ:
1460 info.si_code = TARGET_FPE_FLTDIV;
1461 break;
1462 case POWERPC_EXCP_FP_XX:
1463 info.si_code = TARGET_FPE_FLTRES;
1464 break;
1465 case POWERPC_EXCP_FP_VXSOFT:
1466 info.si_code = TARGET_FPE_FLTINV;
1467 break;
1468 case POWERPC_EXCP_FP_VXSNAN:
1469 case POWERPC_EXCP_FP_VXISI:
1470 case POWERPC_EXCP_FP_VXIDI:
1471 case POWERPC_EXCP_FP_VXIMZ:
1472 case POWERPC_EXCP_FP_VXVC:
1473 case POWERPC_EXCP_FP_VXSQRT:
1474 case POWERPC_EXCP_FP_VXCVI:
1475 info.si_code = TARGET_FPE_FLTSUB;
1476 break;
1477 default:
1478 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1479 env->error_code);
1480 break;
1481 }
1482 break;
1483 case POWERPC_EXCP_INVAL:
1484 info.si_signo = TARGET_SIGILL;
1485 info.si_errno = 0;
1486 switch (env->error_code & 0xF) {
1487 case POWERPC_EXCP_INVAL_INVAL:
1488 info.si_code = TARGET_ILL_ILLOPC;
1489 break;
1490 case POWERPC_EXCP_INVAL_LSWX:
1491 info.si_code = TARGET_ILL_ILLOPN;
1492 break;
1493 case POWERPC_EXCP_INVAL_SPR:
1494 info.si_code = TARGET_ILL_PRVREG;
1495 break;
1496 case POWERPC_EXCP_INVAL_FP:
1497 info.si_code = TARGET_ILL_COPROC;
1498 break;
1499 default:
1500 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1501 env->error_code & 0xF);
1502 info.si_code = TARGET_ILL_ILLADR;
1503 break;
1504 }
1505 break;
1506 case POWERPC_EXCP_PRIV:
1507 info.si_signo = TARGET_SIGILL;
1508 info.si_errno = 0;
1509 switch (env->error_code & 0xF) {
1510 case POWERPC_EXCP_PRIV_OPC:
1511 info.si_code = TARGET_ILL_PRVOPC;
1512 break;
1513 case POWERPC_EXCP_PRIV_REG:
1514 info.si_code = TARGET_ILL_PRVREG;
1515 break;
1516 default:
1517 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1518 env->error_code & 0xF);
1519 info.si_code = TARGET_ILL_PRVOPC;
1520 break;
1521 }
1522 break;
1523 case POWERPC_EXCP_TRAP:
1524 cpu_abort(cs, "Tried to call a TRAP\n");
1525 break;
1526 default:
1527 /* Should not happen ! */
1528 cpu_abort(cs, "Unknown program exception (%02x)\n",
1529 env->error_code);
1530 break;
1531 }
1532 info._sifields._sigfault._addr = env->nip;
1533 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1534 break;
1535 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1536 info.si_signo = TARGET_SIGILL;
1537 info.si_errno = 0;
1538 info.si_code = TARGET_ILL_COPROC;
1539 info._sifields._sigfault._addr = env->nip;
1540 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1541 break;
1542 case POWERPC_EXCP_SYSCALL: /* System call exception */
1543 cpu_abort(cs, "Syscall exception while in user mode. "
1544 "Aborting\n");
1545 break;
1546 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1547 info.si_signo = TARGET_SIGILL;
1548 info.si_errno = 0;
1549 info.si_code = TARGET_ILL_COPROC;
1550 info._sifields._sigfault._addr = env->nip;
1551 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1552 break;
1553 case POWERPC_EXCP_DECR: /* Decrementer exception */
1554 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1555 "Aborting\n");
1556 break;
1557 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1558 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1559 "Aborting\n");
1560 break;
1561 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1562 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1563 "Aborting\n");
1564 break;
1565 case POWERPC_EXCP_DTLB: /* Data TLB error */
1566 cpu_abort(cs, "Data TLB exception while in user mode. "
1567 "Aborting\n");
1568 break;
1569 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1570 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1571 "Aborting\n");
1572 break;
1573 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1574 info.si_signo = TARGET_SIGILL;
1575 info.si_errno = 0;
1576 info.si_code = TARGET_ILL_COPROC;
1577 info._sifields._sigfault._addr = env->nip;
1578 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1579 break;
1580 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1581 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1582 break;
1583 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1584 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1585 break;
1586 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1587 cpu_abort(cs, "Performance monitor exception not handled\n");
1588 break;
1589 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1590 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1591 "Aborting\n");
1592 break;
1593 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1594 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1595 "Aborting\n");
1596 break;
1597 case POWERPC_EXCP_RESET: /* System reset exception */
1598 cpu_abort(cs, "Reset interrupt while in user mode. "
1599 "Aborting\n");
1600 break;
1601 case POWERPC_EXCP_DSEG: /* Data segment exception */
1602 cpu_abort(cs, "Data segment exception while in user mode. "
1603 "Aborting\n");
1604 break;
1605 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1606 cpu_abort(cs, "Instruction segment exception "
1607 "while in user mode. Aborting\n");
1608 break;
1609 /* PowerPC 64 with hypervisor mode support */
1610 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1611 cpu_abort(cs, "Hypervisor decrementer interrupt "
1612 "while in user mode. Aborting\n");
1613 break;
1614 case POWERPC_EXCP_TRACE: /* Trace exception */
1615 /* Nothing to do:
1616 * we use this exception to emulate step-by-step execution mode.
1617 */
1618 break;
1619 /* PowerPC 64 with hypervisor mode support */
1620 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1621 cpu_abort(cs, "Hypervisor data storage exception "
1622 "while in user mode. Aborting\n");
1623 break;
1624 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1625 cpu_abort(cs, "Hypervisor instruction storage exception "
1626 "while in user mode. Aborting\n");
1627 break;
1628 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1629 cpu_abort(cs, "Hypervisor data segment exception "
1630 "while in user mode. Aborting\n");
1631 break;
1632 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1633 cpu_abort(cs, "Hypervisor instruction segment exception "
1634 "while in user mode. Aborting\n");
1635 break;
1636 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1637 info.si_signo = TARGET_SIGILL;
1638 info.si_errno = 0;
1639 info.si_code = TARGET_ILL_COPROC;
1640 info._sifields._sigfault._addr = env->nip;
1641 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1642 break;
1643 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1644 cpu_abort(cs, "Programmable interval timer interrupt "
1645 "while in user mode. Aborting\n");
1646 break;
1647 case POWERPC_EXCP_IO: /* IO error exception */
1648 cpu_abort(cs, "IO error exception while in user mode. "
1649 "Aborting\n");
1650 break;
1651 case POWERPC_EXCP_RUNM: /* Run mode exception */
1652 cpu_abort(cs, "Run mode exception while in user mode. "
1653 "Aborting\n");
1654 break;
1655 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1656 cpu_abort(cs, "Emulation trap exception not handled\n");
1657 break;
1658 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1659 cpu_abort(cs, "Instruction fetch TLB exception "
1660 "while in user-mode. Aborting");
1661 break;
1662 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1663 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1664 "Aborting");
1665 break;
1666 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1667 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1668 "Aborting");
1669 break;
1670 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1671 cpu_abort(cs, "Floating-point assist exception not handled\n");
1672 break;
1673 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1674 cpu_abort(cs, "Instruction address breakpoint exception "
1675 "not handled\n");
1676 break;
1677 case POWERPC_EXCP_SMI: /* System management interrupt */
1678 cpu_abort(cs, "System management interrupt while in user mode. "
1679 "Aborting\n");
1680 break;
1681 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1682 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1683 "Aborting\n");
1684 break;
1685 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1686 cpu_abort(cs, "Performance monitor exception not handled\n");
1687 break;
1688 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1689 cpu_abort(cs, "Vector assist exception not handled\n");
1690 break;
1691 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1692 cpu_abort(cs, "Soft patch exception not handled\n");
1693 break;
1694 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1695 cpu_abort(cs, "Maintenance exception while in user mode. "
1696 "Aborting\n");
1697 break;
1698 case POWERPC_EXCP_STOP: /* stop translation */
1699 /* We did invalidate the instruction cache. Go on */
1700 break;
1701 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1702 /* We just stopped because of a branch. Go on */
1703 break;
1704 case POWERPC_EXCP_SYSCALL_USER:
1705 /* system call in user-mode emulation */
1706 /* WARNING:
1707 * PPC ABI uses overflow flag in cr0 to signal an error
1708 * in syscalls.
1709 */
1710 env->crf[0] &= ~0x1;
1711 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1712 env->gpr[5], env->gpr[6], env->gpr[7],
1713 env->gpr[8], 0, 0);
1714 if (ret == -TARGET_ERESTARTSYS) {
1715 break;
1716 }
1717 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1718 /* Returning from a successful sigreturn syscall.
1719 Avoid corrupting register state. */
1720 break;
1721 }
1722 env->nip += 4;
1723 if (ret > (target_ulong)(-515)) {
1724 env->crf[0] |= 0x1;
1725 ret = -ret;
1726 }
1727 env->gpr[3] = ret;
1728 break;
1729 case POWERPC_EXCP_STCX:
1730 if (do_store_exclusive(env)) {
1731 info.si_signo = TARGET_SIGSEGV;
1732 info.si_errno = 0;
1733 info.si_code = TARGET_SEGV_MAPERR;
1734 info._sifields._sigfault._addr = env->nip;
1735 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1736 }
1737 break;
1738 case EXCP_DEBUG:
1739 {
1740 int sig;
1741
1742 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1743 if (sig) {
1744 info.si_signo = sig;
1745 info.si_errno = 0;
1746 info.si_code = TARGET_TRAP_BRKPT;
1747 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
1748 }
1749 }
1750 break;
1751 case EXCP_INTERRUPT:
1752 /* just indicate that signals should be handled asap */
1753 break;
1754 case EXCP_ATOMIC:
1755 cpu_exec_step_atomic(cs);
1756 break;
1757 default:
1758 cpu_abort(cs, "Unknown exception 0x%x. Aborting\n", trapnr);
1759 break;
1760 }
1761 process_pending_signals(env);
1762 }
1763 }
1764 #endif
1765
1766 #ifdef TARGET_MIPS
1767
1768 # ifdef TARGET_ABI_MIPSO32
1769 # define MIPS_SYS(name, args) args,
1770 static const uint8_t mips_syscall_args[] = {
1771 MIPS_SYS(sys_syscall , 8) /* 4000 */
1772 MIPS_SYS(sys_exit , 1)
1773 MIPS_SYS(sys_fork , 0)
1774 MIPS_SYS(sys_read , 3)
1775 MIPS_SYS(sys_write , 3)
1776 MIPS_SYS(sys_open , 3) /* 4005 */
1777 MIPS_SYS(sys_close , 1)
1778 MIPS_SYS(sys_waitpid , 3)
1779 MIPS_SYS(sys_creat , 2)
1780 MIPS_SYS(sys_link , 2)
1781 MIPS_SYS(sys_unlink , 1) /* 4010 */
1782 MIPS_SYS(sys_execve , 0)
1783 MIPS_SYS(sys_chdir , 1)
1784 MIPS_SYS(sys_time , 1)
1785 MIPS_SYS(sys_mknod , 3)
1786 MIPS_SYS(sys_chmod , 2) /* 4015 */
1787 MIPS_SYS(sys_lchown , 3)
1788 MIPS_SYS(sys_ni_syscall , 0)
1789 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1790 MIPS_SYS(sys_lseek , 3)
1791 MIPS_SYS(sys_getpid , 0) /* 4020 */
1792 MIPS_SYS(sys_mount , 5)
1793 MIPS_SYS(sys_umount , 1)
1794 MIPS_SYS(sys_setuid , 1)
1795 MIPS_SYS(sys_getuid , 0)
1796 MIPS_SYS(sys_stime , 1) /* 4025 */
1797 MIPS_SYS(sys_ptrace , 4)
1798 MIPS_SYS(sys_alarm , 1)
1799 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1800 MIPS_SYS(sys_pause , 0)
1801 MIPS_SYS(sys_utime , 2) /* 4030 */
1802 MIPS_SYS(sys_ni_syscall , 0)
1803 MIPS_SYS(sys_ni_syscall , 0)
1804 MIPS_SYS(sys_access , 2)
1805 MIPS_SYS(sys_nice , 1)
1806 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
1807 MIPS_SYS(sys_sync , 0)
1808 MIPS_SYS(sys_kill , 2)
1809 MIPS_SYS(sys_rename , 2)
1810 MIPS_SYS(sys_mkdir , 2)
1811 MIPS_SYS(sys_rmdir , 1) /* 4040 */
1812 MIPS_SYS(sys_dup , 1)
1813 MIPS_SYS(sys_pipe , 0)
1814 MIPS_SYS(sys_times , 1)
1815 MIPS_SYS(sys_ni_syscall , 0)
1816 MIPS_SYS(sys_brk , 1) /* 4045 */
1817 MIPS_SYS(sys_setgid , 1)
1818 MIPS_SYS(sys_getgid , 0)
1819 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
1820 MIPS_SYS(sys_geteuid , 0)
1821 MIPS_SYS(sys_getegid , 0) /* 4050 */
1822 MIPS_SYS(sys_acct , 0)
1823 MIPS_SYS(sys_umount2 , 2)
1824 MIPS_SYS(sys_ni_syscall , 0)
1825 MIPS_SYS(sys_ioctl , 3)
1826 MIPS_SYS(sys_fcntl , 3) /* 4055 */
1827 MIPS_SYS(sys_ni_syscall , 2)
1828 MIPS_SYS(sys_setpgid , 2)
1829 MIPS_SYS(sys_ni_syscall , 0)
1830 MIPS_SYS(sys_olduname , 1)
1831 MIPS_SYS(sys_umask , 1) /* 4060 */
1832 MIPS_SYS(sys_chroot , 1)
1833 MIPS_SYS(sys_ustat , 2)
1834 MIPS_SYS(sys_dup2 , 2)
1835 MIPS_SYS(sys_getppid , 0)
1836 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
1837 MIPS_SYS(sys_setsid , 0)
1838 MIPS_SYS(sys_sigaction , 3)
1839 MIPS_SYS(sys_sgetmask , 0)
1840 MIPS_SYS(sys_ssetmask , 1)
1841 MIPS_SYS(sys_setreuid , 2) /* 4070 */
1842 MIPS_SYS(sys_setregid , 2)
1843 MIPS_SYS(sys_sigsuspend , 0)
1844 MIPS_SYS(sys_sigpending , 1)
1845 MIPS_SYS(sys_sethostname , 2)
1846 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
1847 MIPS_SYS(sys_getrlimit , 2)
1848 MIPS_SYS(sys_getrusage , 2)
1849 MIPS_SYS(sys_gettimeofday, 2)
1850 MIPS_SYS(sys_settimeofday, 2)
1851 MIPS_SYS(sys_getgroups , 2) /* 4080 */
1852 MIPS_SYS(sys_setgroups , 2)
1853 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
1854 MIPS_SYS(sys_symlink , 2)
1855 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
1856 MIPS_SYS(sys_readlink , 3) /* 4085 */
1857 MIPS_SYS(sys_uselib , 1)
1858 MIPS_SYS(sys_swapon , 2)
1859 MIPS_SYS(sys_reboot , 3)
1860 MIPS_SYS(old_readdir , 3)
1861 MIPS_SYS(old_mmap , 6) /* 4090 */
1862 MIPS_SYS(sys_munmap , 2)
1863 MIPS_SYS(sys_truncate , 2)
1864 MIPS_SYS(sys_ftruncate , 2)
1865 MIPS_SYS(sys_fchmod , 2)
1866 MIPS_SYS(sys_fchown , 3) /* 4095 */
1867 MIPS_SYS(sys_getpriority , 2)
1868 MIPS_SYS(sys_setpriority , 3)
1869 MIPS_SYS(sys_ni_syscall , 0)
1870 MIPS_SYS(sys_statfs , 2)
1871 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
1872 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
1873 MIPS_SYS(sys_socketcall , 2)
1874 MIPS_SYS(sys_syslog , 3)
1875 MIPS_SYS(sys_setitimer , 3)
1876 MIPS_SYS(sys_getitimer , 2) /* 4105 */
1877 MIPS_SYS(sys_newstat , 2)
1878 MIPS_SYS(sys_newlstat , 2)
1879 MIPS_SYS(sys_newfstat , 2)
1880 MIPS_SYS(sys_uname , 1)
1881 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
1882 MIPS_SYS(sys_vhangup , 0)
1883 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
1884 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
1885 MIPS_SYS(sys_wait4 , 4)
1886 MIPS_SYS(sys_swapoff , 1) /* 4115 */
1887 MIPS_SYS(sys_sysinfo , 1)
1888 MIPS_SYS(sys_ipc , 6)
1889 MIPS_SYS(sys_fsync , 1)
1890 MIPS_SYS(sys_sigreturn , 0)
1891 MIPS_SYS(sys_clone , 6) /* 4120 */
1892 MIPS_SYS(sys_setdomainname, 2)
1893 MIPS_SYS(sys_newuname , 1)
1894 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
1895 MIPS_SYS(sys_adjtimex , 1)
1896 MIPS_SYS(sys_mprotect , 3) /* 4125 */
1897 MIPS_SYS(sys_sigprocmask , 3)
1898 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
1899 MIPS_SYS(sys_init_module , 5)
1900 MIPS_SYS(sys_delete_module, 1)
1901 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
1902 MIPS_SYS(sys_quotactl , 0)
1903 MIPS_SYS(sys_getpgid , 1)
1904 MIPS_SYS(sys_fchdir , 1)
1905 MIPS_SYS(sys_bdflush , 2)
1906 MIPS_SYS(sys_sysfs , 3) /* 4135 */
1907 MIPS_SYS(sys_personality , 1)
1908 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
1909 MIPS_SYS(sys_setfsuid , 1)
1910 MIPS_SYS(sys_setfsgid , 1)
1911 MIPS_SYS(sys_llseek , 5) /* 4140 */
1912 MIPS_SYS(sys_getdents , 3)
1913 MIPS_SYS(sys_select , 5)
1914 MIPS_SYS(sys_flock , 2)
1915 MIPS_SYS(sys_msync , 3)
1916 MIPS_SYS(sys_readv , 3) /* 4145 */
1917 MIPS_SYS(sys_writev , 3)
1918 MIPS_SYS(sys_cacheflush , 3)
1919 MIPS_SYS(sys_cachectl , 3)
1920 MIPS_SYS(sys_sysmips , 4)
1921 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
1922 MIPS_SYS(sys_getsid , 1)
1923 MIPS_SYS(sys_fdatasync , 0)
1924 MIPS_SYS(sys_sysctl , 1)
1925 MIPS_SYS(sys_mlock , 2)
1926 MIPS_SYS(sys_munlock , 2) /* 4155 */
1927 MIPS_SYS(sys_mlockall , 1)
1928 MIPS_SYS(sys_munlockall , 0)
1929 MIPS_SYS(sys_sched_setparam, 2)
1930 MIPS_SYS(sys_sched_getparam, 2)
1931 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
1932 MIPS_SYS(sys_sched_getscheduler, 1)
1933 MIPS_SYS(sys_sched_yield , 0)
1934 MIPS_SYS(sys_sched_get_priority_max, 1)
1935 MIPS_SYS(sys_sched_get_priority_min, 1)
1936 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
1937 MIPS_SYS(sys_nanosleep, 2)
1938 MIPS_SYS(sys_mremap , 5)
1939 MIPS_SYS(sys_accept , 3)
1940 MIPS_SYS(sys_bind , 3)
1941 MIPS_SYS(sys_connect , 3) /* 4170 */
1942 MIPS_SYS(sys_getpeername , 3)
1943 MIPS_SYS(sys_getsockname , 3)
1944 MIPS_SYS(sys_getsockopt , 5)
1945 MIPS_SYS(sys_listen , 2)
1946 MIPS_SYS(sys_recv , 4) /* 4175 */
1947 MIPS_SYS(sys_recvfrom , 6)
1948 MIPS_SYS(sys_recvmsg , 3)
1949 MIPS_SYS(sys_send , 4)
1950 MIPS_SYS(sys_sendmsg , 3)
1951 MIPS_SYS(sys_sendto , 6) /* 4180 */
1952 MIPS_SYS(sys_setsockopt , 5)
1953 MIPS_SYS(sys_shutdown , 2)
1954 MIPS_SYS(sys_socket , 3)
1955 MIPS_SYS(sys_socketpair , 4)
1956 MIPS_SYS(sys_setresuid , 3) /* 4185 */
1957 MIPS_SYS(sys_getresuid , 3)
1958 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
1959 MIPS_SYS(sys_poll , 3)
1960 MIPS_SYS(sys_nfsservctl , 3)
1961 MIPS_SYS(sys_setresgid , 3) /* 4190 */
1962 MIPS_SYS(sys_getresgid , 3)
1963 MIPS_SYS(sys_prctl , 5)
1964 MIPS_SYS(sys_rt_sigreturn, 0)
1965 MIPS_SYS(sys_rt_sigaction, 4)
1966 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
1967 MIPS_SYS(sys_rt_sigpending, 2)
1968 MIPS_SYS(sys_rt_sigtimedwait, 4)
1969 MIPS_SYS(sys_rt_sigqueueinfo, 3)
1970 MIPS_SYS(sys_rt_sigsuspend, 0)
1971 MIPS_SYS(sys_pread64 , 6) /* 4200 */
1972 MIPS_SYS(sys_pwrite64 , 6)
1973 MIPS_SYS(sys_chown , 3)
1974 MIPS_SYS(sys_getcwd , 2)
1975 MIPS_SYS(sys_capget , 2)
1976 MIPS_SYS(sys_capset , 2) /* 4205 */
1977 MIPS_SYS(sys_sigaltstack , 2)
1978 MIPS_SYS(sys_sendfile , 4)
1979 MIPS_SYS(sys_ni_syscall , 0)
1980 MIPS_SYS(sys_ni_syscall , 0)
1981 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
1982 MIPS_SYS(sys_truncate64 , 4)
1983 MIPS_SYS(sys_ftruncate64 , 4)
1984 MIPS_SYS(sys_stat64 , 2)
1985 MIPS_SYS(sys_lstat64 , 2)
1986 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
1987 MIPS_SYS(sys_pivot_root , 2)
1988 MIPS_SYS(sys_mincore , 3)
1989 MIPS_SYS(sys_madvise , 3)
1990 MIPS_SYS(sys_getdents64 , 3)
1991 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
1992 MIPS_SYS(sys_ni_syscall , 0)
1993 MIPS_SYS(sys_gettid , 0)
1994 MIPS_SYS(sys_readahead , 5)
1995 MIPS_SYS(sys_setxattr , 5)
1996 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
1997 MIPS_SYS(sys_fsetxattr , 5)
1998 MIPS_SYS(sys_getxattr , 4)
1999 MIPS_SYS(sys_lgetxattr , 4)
2000 MIPS_SYS(sys_fgetxattr , 4)
2001 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2002 MIPS_SYS(sys_llistxattr , 3)
2003 MIPS_SYS(sys_flistxattr , 3)
2004 MIPS_SYS(sys_removexattr , 2)
2005 MIPS_SYS(sys_lremovexattr, 2)
2006 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2007 MIPS_SYS(sys_tkill , 2)
2008 MIPS_SYS(sys_sendfile64 , 5)
2009 MIPS_SYS(sys_futex , 6)
2010 MIPS_SYS(sys_sched_setaffinity, 3)
2011 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2012 MIPS_SYS(sys_io_setup , 2)
2013 MIPS_SYS(sys_io_destroy , 1)
2014 MIPS_SYS(sys_io_getevents, 5)
2015 MIPS_SYS(sys_io_submit , 3)
2016 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2017 MIPS_SYS(sys_exit_group , 1)
2018 MIPS_SYS(sys_lookup_dcookie, 3)
2019 MIPS_SYS(sys_epoll_create, 1)
2020 MIPS_SYS(sys_epoll_ctl , 4)
2021 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2022 MIPS_SYS(sys_remap_file_pages, 5)
2023 MIPS_SYS(sys_set_tid_address, 1)
2024 MIPS_SYS(sys_restart_syscall, 0)
2025 MIPS_SYS(sys_fadvise64_64, 7)
2026 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2027 MIPS_SYS(sys_fstatfs64 , 2)
2028 MIPS_SYS(sys_timer_create, 3)
2029 MIPS_SYS(sys_timer_settime, 4)
2030 MIPS_SYS(sys_timer_gettime, 2)
2031 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2032 MIPS_SYS(sys_timer_delete, 1)
2033 MIPS_SYS(sys_clock_settime, 2)
2034 MIPS_SYS(sys_clock_gettime, 2)
2035 MIPS_SYS(sys_clock_getres, 2)
2036 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2037 MIPS_SYS(sys_tgkill , 3)
2038 MIPS_SYS(sys_utimes , 2)
2039 MIPS_SYS(sys_mbind , 4)
2040 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2041 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2042 MIPS_SYS(sys_mq_open , 4)
2043 MIPS_SYS(sys_mq_unlink , 1)
2044 MIPS_SYS(sys_mq_timedsend, 5)
2045 MIPS_SYS(sys_mq_timedreceive, 5)
2046 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2047 MIPS_SYS(sys_mq_getsetattr, 3)
2048 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2049 MIPS_SYS(sys_waitid , 4)
2050 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2051 MIPS_SYS(sys_add_key , 5)
2052 MIPS_SYS(sys_request_key, 4)
2053 MIPS_SYS(sys_keyctl , 5)
2054 MIPS_SYS(sys_set_thread_area, 1)
2055 MIPS_SYS(sys_inotify_init, 0)
2056 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2057 MIPS_SYS(sys_inotify_rm_watch, 2)
2058 MIPS_SYS(sys_migrate_pages, 4)
2059 MIPS_SYS(sys_openat, 4)
2060 MIPS_SYS(sys_mkdirat, 3)
2061 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2062 MIPS_SYS(sys_fchownat, 5)
2063 MIPS_SYS(sys_futimesat, 3)
2064 MIPS_SYS(sys_fstatat64, 4)
2065 MIPS_SYS(sys_unlinkat, 3)
2066 MIPS_SYS(sys_renameat, 4) /* 4295 */
2067 MIPS_SYS(sys_linkat, 5)
2068 MIPS_SYS(sys_symlinkat, 3)
2069 MIPS_SYS(sys_readlinkat, 4)
2070 MIPS_SYS(sys_fchmodat, 3)
2071 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2072 MIPS_SYS(sys_pselect6, 6)
2073 MIPS_SYS(sys_ppoll, 5)
2074 MIPS_SYS(sys_unshare, 1)
2075 MIPS_SYS(sys_splice, 6)
2076 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2077 MIPS_SYS(sys_tee, 4)
2078 MIPS_SYS(sys_vmsplice, 4)
2079 MIPS_SYS(sys_move_pages, 6)
2080 MIPS_SYS(sys_set_robust_list, 2)
2081 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2082 MIPS_SYS(sys_kexec_load, 4)
2083 MIPS_SYS(sys_getcpu, 3)
2084 MIPS_SYS(sys_epoll_pwait, 6)
2085 MIPS_SYS(sys_ioprio_set, 3)
2086 MIPS_SYS(sys_ioprio_get, 2)
2087 MIPS_SYS(sys_utimensat, 4)
2088 MIPS_SYS(sys_signalfd, 3)
2089 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2090 MIPS_SYS(sys_eventfd, 1)
2091 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2092 MIPS_SYS(sys_timerfd_create, 2)
2093 MIPS_SYS(sys_timerfd_gettime, 2)
2094 MIPS_SYS(sys_timerfd_settime, 4)
2095 MIPS_SYS(sys_signalfd4, 4)
2096 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2097 MIPS_SYS(sys_epoll_create1, 1)
2098 MIPS_SYS(sys_dup3, 3)
2099 MIPS_SYS(sys_pipe2, 2)
2100 MIPS_SYS(sys_inotify_init1, 1)
2101 MIPS_SYS(sys_preadv, 5) /* 4330 */
2102 MIPS_SYS(sys_pwritev, 5)
2103 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2104 MIPS_SYS(sys_perf_event_open, 5)
2105 MIPS_SYS(sys_accept4, 4)
2106 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2107 MIPS_SYS(sys_fanotify_init, 2)
2108 MIPS_SYS(sys_fanotify_mark, 6)
2109 MIPS_SYS(sys_prlimit64, 4)
2110 MIPS_SYS(sys_name_to_handle_at, 5)
2111 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2112 MIPS_SYS(sys_clock_adjtime, 2)
2113 MIPS_SYS(sys_syncfs, 1)
2114 MIPS_SYS(sys_sendmmsg, 4)
2115 MIPS_SYS(sys_setns, 2)
2116 MIPS_SYS(sys_process_vm_readv, 6) /* 345 */
2117 MIPS_SYS(sys_process_vm_writev, 6)
2118 MIPS_SYS(sys_kcmp, 5)
2119 MIPS_SYS(sys_finit_module, 3)
2120 MIPS_SYS(sys_sched_setattr, 2)
2121 MIPS_SYS(sys_sched_getattr, 3) /* 350 */
2122 MIPS_SYS(sys_renameat2, 5)
2123 MIPS_SYS(sys_seccomp, 3)
2124 MIPS_SYS(sys_getrandom, 3)
2125 MIPS_SYS(sys_memfd_create, 2)
2126 MIPS_SYS(sys_bpf, 3) /* 355 */
2127 MIPS_SYS(sys_execveat, 5)
2128 MIPS_SYS(sys_userfaultfd, 1)
2129 MIPS_SYS(sys_membarrier, 2)
2130 MIPS_SYS(sys_mlock2, 3)
2131 MIPS_SYS(sys_copy_file_range, 6) /* 360 */
2132 MIPS_SYS(sys_preadv2, 6)
2133 MIPS_SYS(sys_pwritev2, 6)
2134 };
2135 # undef MIPS_SYS
2136 # endif /* O32 */
2137
2138 static int do_store_exclusive(CPUMIPSState *env)
2139 {
2140 target_ulong addr;
2141 target_ulong page_addr;
2142 target_ulong val;
2143 int flags;
2144 int segv = 0;
2145 int reg;
2146 int d;
2147
2148 addr = env->lladdr;
2149 page_addr = addr & TARGET_PAGE_MASK;
2150 start_exclusive();
2151 mmap_lock();
2152 flags = page_get_flags(page_addr);
2153 if ((flags & PAGE_READ) == 0) {
2154 segv = 1;
2155 } else {
2156 reg = env->llreg & 0x1f;
2157 d = (env->llreg & 0x20) != 0;
2158 if (d) {
2159 segv = get_user_s64(val, addr);
2160 } else {
2161 segv = get_user_s32(val, addr);
2162 }
2163 if (!segv) {
2164 if (val != env->llval) {
2165 env->active_tc.gpr[reg] = 0;
2166 } else {
2167 if (d) {
2168 segv = put_user_u64(env->llnewval, addr);
2169 } else {
2170 segv = put_user_u32(env->llnewval, addr);
2171 }
2172 if (!segv) {
2173 env->active_tc.gpr[reg] = 1;
2174 }
2175 }
2176 }
2177 }
2178 env->lladdr = -1;
2179 if (!segv) {
2180 env->active_tc.PC += 4;
2181 }
2182 mmap_unlock();
2183 end_exclusive();
2184 return segv;
2185 }
2186
2187 /* Break codes */
2188 enum {
2189 BRK_OVERFLOW = 6,
2190 BRK_DIVZERO = 7
2191 };
2192
2193 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2194 unsigned int code)
2195 {
2196 int ret = -1;
2197
2198 switch (code) {
2199 case BRK_OVERFLOW:
2200 case BRK_DIVZERO:
2201 info->si_signo = TARGET_SIGFPE;
2202 info->si_errno = 0;
2203 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2204 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2205 ret = 0;
2206 break;
2207 default:
2208 info->si_signo = TARGET_SIGTRAP;
2209 info->si_errno = 0;
2210 queue_signal(env, info->si_signo, QEMU_SI_FAULT, &*info);
2211 ret = 0;
2212 break;
2213 }
2214
2215 return ret;
2216 }
2217
2218 void cpu_loop(CPUMIPSState *env)
2219 {
2220 CPUState *cs = CPU(mips_env_get_cpu(env));
2221 target_siginfo_t info;
2222 int trapnr;
2223 abi_long ret;
2224 # ifdef TARGET_ABI_MIPSO32
2225 unsigned int syscall_num;
2226 # endif
2227
2228 for(;;) {
2229 cpu_exec_start(cs);
2230 trapnr = cpu_exec(cs);
2231 cpu_exec_end(cs);
2232 process_queued_cpu_work(cs);
2233
2234 switch(trapnr) {
2235 case EXCP_SYSCALL:
2236 env->active_tc.PC += 4;
2237 # ifdef TARGET_ABI_MIPSO32
2238 syscall_num = env->active_tc.gpr[2] - 4000;
2239 if (syscall_num >= sizeof(mips_syscall_args)) {
2240 ret = -TARGET_ENOSYS;
2241 } else {
2242 int nb_args;
2243 abi_ulong sp_reg;
2244 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2245
2246 nb_args = mips_syscall_args[syscall_num];
2247 sp_reg = env->active_tc.gpr[29];
2248 switch (nb_args) {
2249 /* these arguments are taken from the stack */
2250 case 8:
2251 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2252 goto done_syscall;
2253 }
2254 case 7:
2255 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2256 goto done_syscall;
2257 }
2258 case 6:
2259 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2260 goto done_syscall;
2261 }
2262 case 5:
2263 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2264 goto done_syscall;
2265 }
2266 default:
2267 break;
2268 }
2269 ret = do_syscall(env, env->active_tc.gpr[2],
2270 env->active_tc.gpr[4],
2271 env->active_tc.gpr[5],
2272 env->active_tc.gpr[6],
2273 env->active_tc.gpr[7],
2274 arg5, arg6, arg7, arg8);
2275 }
2276 done_syscall:
2277 # else
2278 ret = do_syscall(env, env->active_tc.gpr[2],
2279 env->active_tc.gpr[4], env->active_tc.gpr[5],
2280 env->active_tc.gpr[6], env->active_tc.gpr[7],
2281 env->active_tc.gpr[8], env->active_tc.gpr[9],
2282 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2283 # endif /* O32 */
2284 if (ret == -TARGET_ERESTARTSYS) {
2285 env->active_tc.PC -= 4;
2286 break;
2287 }
2288 if (ret == -TARGET_QEMU_ESIGRETURN) {
2289 /* Returning from a successful sigreturn syscall.
2290 Avoid clobbering register state. */
2291 break;
2292 }
2293 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2294 env->active_tc.gpr[7] = 1; /* error flag */
2295 ret = -ret;
2296 } else {
2297 env->active_tc.gpr[7] = 0; /* error flag */
2298 }
2299 env->active_tc.gpr[2] = ret;
2300 break;
2301 case EXCP_TLBL:
2302 case EXCP_TLBS:
2303 case EXCP_AdEL:
2304 case EXCP_AdES:
2305 info.si_signo = TARGET_SIGSEGV;
2306 info.si_errno = 0;
2307 /* XXX: check env->error_code */
2308 info.si_code = TARGET_SEGV_MAPERR;
2309 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2310 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2311 break;
2312 case EXCP_CpU:
2313 case EXCP_RI:
2314 info.si_signo = TARGET_SIGILL;
2315 info.si_errno = 0;
2316 info.si_code = 0;
2317 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2318 break;
2319 case EXCP_INTERRUPT:
2320 /* just indicate that signals should be handled asap */
2321 break;
2322 case EXCP_DEBUG:
2323 {
2324 int sig;
2325
2326 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2327 if (sig)
2328 {
2329 info.si_signo = sig;
2330 info.si_errno = 0;
2331 info.si_code = TARGET_TRAP_BRKPT;
2332 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2333 }
2334 }
2335 break;
2336 case EXCP_SC:
2337 if (do_store_exclusive(env)) {
2338 info.si_signo = TARGET_SIGSEGV;
2339 info.si_errno = 0;
2340 info.si_code = TARGET_SEGV_MAPERR;
2341 info._sifields._sigfault._addr = env->active_tc.PC;
2342 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2343 }
2344 break;
2345 case EXCP_DSPDIS:
2346 info.si_signo = TARGET_SIGILL;
2347 info.si_errno = 0;
2348 info.si_code = TARGET_ILL_ILLOPC;
2349 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2350 break;
2351 /* The code below was inspired by the MIPS Linux kernel trap
2352 * handling code in arch/mips/kernel/traps.c.
2353 */
2354 case EXCP_BREAK:
2355 {
2356 abi_ulong trap_instr;
2357 unsigned int code;
2358
2359 if (env->hflags & MIPS_HFLAG_M16) {
2360 if (env->insn_flags & ASE_MICROMIPS) {
2361 /* microMIPS mode */
2362 ret = get_user_u16(trap_instr, env->active_tc.PC);
2363 if (ret != 0) {
2364 goto error;
2365 }
2366
2367 if ((trap_instr >> 10) == 0x11) {
2368 /* 16-bit instruction */
2369 code = trap_instr & 0xf;
2370 } else {
2371 /* 32-bit instruction */
2372 abi_ulong instr_lo;
2373
2374 ret = get_user_u16(instr_lo,
2375 env->active_tc.PC + 2);
2376 if (ret != 0) {
2377 goto error;
2378 }
2379 trap_instr = (trap_instr << 16) | instr_lo;
2380 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2381 /* Unfortunately, microMIPS also suffers from
2382 the old assembler bug... */
2383 if (code >= (1 << 10)) {
2384 code >>= 10;
2385 }
2386 }
2387 } else {
2388 /* MIPS16e mode */
2389 ret = get_user_u16(trap_instr, env->active_tc.PC);
2390 if (ret != 0) {
2391 goto error;
2392 }
2393 code = (trap_instr >> 6) & 0x3f;
2394 }
2395 } else {
2396 ret = get_user_u32(trap_instr, env->active_tc.PC);
2397 if (ret != 0) {
2398 goto error;
2399 }
2400
2401 /* As described in the original Linux kernel code, the
2402 * below checks on 'code' are to work around an old
2403 * assembly bug.
2404 */
2405 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2406 if (code >= (1 << 10)) {
2407 code >>= 10;
2408 }
2409 }
2410
2411 if (do_break(env, &info, code) != 0) {
2412 goto error;
2413 }
2414 }
2415 break;
2416 case EXCP_TRAP:
2417 {
2418 abi_ulong trap_instr;
2419 unsigned int code = 0;
2420
2421 if (env->hflags & MIPS_HFLAG_M16) {
2422 /* microMIPS mode */
2423 abi_ulong instr[2];
2424
2425 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2426 get_user_u16(instr[1], env->active_tc.PC + 2);
2427
2428 trap_instr = (instr[0] << 16) | instr[1];
2429 } else {
2430 ret = get_user_u32(trap_instr, env->active_tc.PC);
2431 }
2432
2433 if (ret != 0) {
2434 goto error;
2435 }
2436
2437 /* The immediate versions don't provide a code. */
2438 if (!(trap_instr & 0xFC000000)) {
2439 if (env->hflags & MIPS_HFLAG_M16) {
2440 /* microMIPS mode */
2441 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2442 } else {
2443 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2444 }
2445 }
2446
2447 if (do_break(env, &info, code) != 0) {
2448 goto error;
2449 }
2450 }
2451 break;
2452 case EXCP_ATOMIC:
2453 cpu_exec_step_atomic(cs);
2454 break;
2455 default:
2456 error:
2457 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2458 abort();
2459 }
2460 process_pending_signals(env);
2461 }
2462 }
2463 #endif
2464
2465 #ifdef TARGET_OPENRISC
2466
2467 void cpu_loop(CPUOpenRISCState *env)
2468 {
2469 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2470 int trapnr, gdbsig;
2471 abi_long ret;
2472
2473 for (;;) {
2474 cpu_exec_start(cs);
2475 trapnr = cpu_exec(cs);
2476 cpu_exec_end(cs);
2477 process_queued_cpu_work(cs);
2478 gdbsig = 0;
2479
2480 switch (trapnr) {
2481 case EXCP_RESET:
2482 qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
2483 exit(EXIT_FAILURE);
2484 break;
2485 case EXCP_BUSERR:
2486 qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
2487 gdbsig = TARGET_SIGBUS;
2488 break;
2489 case EXCP_DPF:
2490 case EXCP_IPF:
2491 cpu_dump_state(cs, stderr, fprintf, 0);
2492 gdbsig = TARGET_SIGSEGV;
2493 break;
2494 case EXCP_TICK:
2495 qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
2496 break;
2497 case EXCP_ALIGN:
2498 qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
2499 gdbsig = TARGET_SIGBUS;
2500 break;
2501 case EXCP_ILLEGAL:
2502 qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
2503 gdbsig = TARGET_SIGILL;
2504 break;
2505 case EXCP_INT:
2506 qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
2507 break;
2508 case EXCP_DTLBMISS:
2509 case EXCP_ITLBMISS:
2510 qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
2511 break;
2512 case EXCP_RANGE:
2513 qemu_log_mask(CPU_LOG_INT, "\nRange\n");
2514 gdbsig = TARGET_SIGSEGV;
2515 break;
2516 case EXCP_SYSCALL:
2517 env->pc += 4; /* 0xc00; */
2518 ret = do_syscall(env,
2519 env->gpr[11], /* return value */
2520 env->gpr[3], /* r3 - r7 are params */
2521 env->gpr[4],
2522 env->gpr[5],
2523 env->gpr[6],
2524 env->gpr[7],
2525 env->gpr[8], 0, 0);
2526 if (ret == -TARGET_ERESTARTSYS) {
2527 env->pc -= 4;
2528 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2529 env->gpr[11] = ret;
2530 }
2531 break;
2532 case EXCP_FPE:
2533 qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
2534 break;
2535 case EXCP_TRAP:
2536 qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
2537 gdbsig = TARGET_SIGTRAP;
2538 break;
2539 case EXCP_NR:
2540 qemu_log_mask(CPU_LOG_INT, "\nNR\n");
2541 break;
2542 case EXCP_ATOMIC:
2543 cpu_exec_step_atomic(cs);
2544 break;
2545 default:
2546 EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
2547 trapnr);
2548 gdbsig = TARGET_SIGILL;
2549 break;
2550 }
2551 if (gdbsig) {
2552 gdb_handlesig(cs, gdbsig);
2553 if (gdbsig != TARGET_SIGTRAP) {
2554 exit(EXIT_FAILURE);
2555 }
2556 }
2557
2558 process_pending_signals(env);
2559 }
2560 }
2561
2562 #endif /* TARGET_OPENRISC */
2563
2564 #ifdef TARGET_SH4
2565 void cpu_loop(CPUSH4State *env)
2566 {
2567 CPUState *cs = CPU(sh_env_get_cpu(env));
2568 int trapnr, ret;
2569 target_siginfo_t info;
2570
2571 while (1) {
2572 cpu_exec_start(cs);
2573 trapnr = cpu_exec(cs);
2574 cpu_exec_end(cs);
2575 process_queued_cpu_work(cs);
2576
2577 switch (trapnr) {
2578 case 0x160:
2579 env->pc += 2;
2580 ret = do_syscall(env,
2581 env->gregs[3],
2582 env->gregs[4],
2583 env->gregs[5],
2584 env->gregs[6],
2585 env->gregs[7],
2586 env->gregs[0],
2587 env->gregs[1],
2588 0, 0);
2589 if (ret == -TARGET_ERESTARTSYS) {
2590 env->pc -= 2;
2591 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2592 env->gregs[0] = ret;
2593 }
2594 break;
2595 case EXCP_INTERRUPT:
2596 /* just indicate that signals should be handled asap */
2597 break;
2598 case EXCP_DEBUG:
2599 {
2600 int sig;
2601
2602 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2603 if (sig)
2604 {
2605 info.si_signo = sig;
2606 info.si_errno = 0;
2607 info.si_code = TARGET_TRAP_BRKPT;
2608 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2609 }
2610 }
2611 break;
2612 case 0xa0:
2613 case 0xc0:
2614 info.si_signo = TARGET_SIGSEGV;
2615 info.si_errno = 0;
2616 info.si_code = TARGET_SEGV_MAPERR;
2617 info._sifields._sigfault._addr = env->tea;
2618 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2619 break;
2620
2621 case EXCP_ATOMIC:
2622 cpu_exec_step_atomic(cs);
2623 break;
2624 default:
2625 printf ("Unhandled trap: 0x%x\n", trapnr);
2626 cpu_dump_state(cs, stderr, fprintf, 0);
2627 exit(EXIT_FAILURE);
2628 }
2629 process_pending_signals (env);
2630 }
2631 }
2632 #endif
2633
2634 #ifdef TARGET_CRIS
2635 void cpu_loop(CPUCRISState *env)
2636 {
2637 CPUState *cs = CPU(cris_env_get_cpu(env));
2638 int trapnr, ret;
2639 target_siginfo_t info;
2640
2641 while (1) {
2642 cpu_exec_start(cs);
2643 trapnr = cpu_exec(cs);
2644 cpu_exec_end(cs);
2645 process_queued_cpu_work(cs);
2646
2647 switch (trapnr) {
2648 case 0xaa:
2649 {
2650 info.si_signo = TARGET_SIGSEGV;
2651 info.si_errno = 0;
2652 /* XXX: check env->error_code */
2653 info.si_code = TARGET_SEGV_MAPERR;
2654 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2655 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2656 }
2657 break;
2658 case EXCP_INTERRUPT:
2659 /* just indicate that signals should be handled asap */
2660 break;
2661 case EXCP_BREAK:
2662 ret = do_syscall(env,
2663 env->regs[9],
2664 env->regs[10],
2665 env->regs[11],
2666 env->regs[12],
2667 env->regs[13],
2668 env->pregs[7],
2669 env->pregs[11],
2670 0, 0);
2671 if (ret == -TARGET_ERESTARTSYS) {
2672 env->pc -= 2;
2673 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2674 env->regs[10] = ret;
2675 }
2676 break;
2677 case EXCP_DEBUG:
2678 {
2679 int sig;
2680
2681 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2682 if (sig)
2683 {
2684 info.si_signo = sig;
2685 info.si_errno = 0;
2686 info.si_code = TARGET_TRAP_BRKPT;
2687 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2688 }
2689 }
2690 break;
2691 case EXCP_ATOMIC:
2692 cpu_exec_step_atomic(cs);
2693 break;
2694 default:
2695 printf ("Unhandled trap: 0x%x\n", trapnr);
2696 cpu_dump_state(cs, stderr, fprintf, 0);
2697 exit(EXIT_FAILURE);
2698 }
2699 process_pending_signals (env);
2700 }
2701 }
2702 #endif
2703
2704 #ifdef TARGET_MICROBLAZE
2705 void cpu_loop(CPUMBState *env)
2706 {
2707 CPUState *cs = CPU(mb_env_get_cpu(env));
2708 int trapnr, ret;
2709 target_siginfo_t info;
2710
2711 while (1) {
2712 cpu_exec_start(cs);
2713 trapnr = cpu_exec(cs);
2714 cpu_exec_end(cs);
2715 process_queued_cpu_work(cs);
2716
2717 switch (trapnr) {
2718 case 0xaa:
2719 {
2720 info.si_signo = TARGET_SIGSEGV;
2721 info.si_errno = 0;
2722 /* XXX: check env->error_code */
2723 info.si_code = TARGET_SEGV_MAPERR;
2724 info._sifields._sigfault._addr = 0;
2725 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2726 }
2727 break;
2728 case EXCP_INTERRUPT:
2729 /* just indicate that signals should be handled asap */
2730 break;
2731 case EXCP_BREAK:
2732 /* Return address is 4 bytes after the call. */
2733 env->regs[14] += 4;
2734 env->sregs[SR_PC] = env->regs[14];
2735 ret = do_syscall(env,
2736 env->regs[12],
2737 env->regs[5],
2738 env->regs[6],
2739 env->regs[7],
2740 env->regs[8],
2741 env->regs[9],
2742 env->regs[10],
2743 0, 0);
2744 if (ret == -TARGET_ERESTARTSYS) {
2745 /* Wind back to before the syscall. */
2746 env->sregs[SR_PC] -= 4;
2747 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2748 env->regs[3] = ret;
2749 }
2750 /* All syscall exits result in guest r14 being equal to the
2751 * PC we return to, because the kernel syscall exit "rtbd" does
2752 * this. (This is true even for sigreturn(); note that r14 is
2753 * not a userspace-usable register, as the kernel may clobber it
2754 * at any point.)
2755 */
2756 env->regs[14] = env->sregs[SR_PC];
2757 break;
2758 case EXCP_HW_EXCP:
2759 env->regs[17] = env->sregs[SR_PC] + 4;
2760 if (env->iflags & D_FLAG) {
2761 env->sregs[SR_ESR] |= 1 << 12;
2762 env->sregs[SR_PC] -= 4;
2763 /* FIXME: if branch was immed, replay the imm as well. */
2764 }
2765
2766 env->iflags &= ~(IMM_FLAG | D_FLAG);
2767
2768 switch (env->sregs[SR_ESR] & 31) {
2769 case ESR_EC_DIVZERO:
2770 info.si_signo = TARGET_SIGFPE;
2771 info.si_errno = 0;
2772 info.si_code = TARGET_FPE_FLTDIV;
2773 info._sifields._sigfault._addr = 0;
2774 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2775 break;
2776 case ESR_EC_FPU:
2777 info.si_signo = TARGET_SIGFPE;
2778 info.si_errno = 0;
2779 if (env->sregs[SR_FSR] & FSR_IO) {
2780 info.si_code = TARGET_FPE_FLTINV;
2781 }
2782 if (env->sregs[SR_FSR] & FSR_DZ) {
2783 info.si_code = TARGET_FPE_FLTDIV;
2784 }
2785 info._sifields._sigfault._addr = 0;
2786 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2787 break;
2788 default:
2789 printf ("Unhandled hw-exception: 0x%x\n",
2790 env->sregs[SR_ESR] & ESR_EC_MASK);
2791 cpu_dump_state(cs, stderr, fprintf, 0);
2792 exit(EXIT_FAILURE);
2793 break;
2794 }
2795 break;
2796 case EXCP_DEBUG:
2797 {
2798 int sig;
2799
2800 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2801 if (sig)
2802 {
2803 info.si_signo = sig;
2804 info.si_errno = 0;
2805 info.si_code = TARGET_TRAP_BRKPT;
2806 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2807 }
2808 }
2809 break;
2810 case EXCP_ATOMIC:
2811 cpu_exec_step_atomic(cs);
2812 break;
2813 default:
2814 printf ("Unhandled trap: 0x%x\n", trapnr);
2815 cpu_dump_state(cs, stderr, fprintf, 0);
2816 exit(EXIT_FAILURE);
2817 }
2818 process_pending_signals (env);
2819 }
2820 }
2821 #endif
2822
2823 #ifdef TARGET_M68K
2824
2825 void cpu_loop(CPUM68KState *env)
2826 {
2827 CPUState *cs = CPU(m68k_env_get_cpu(env));
2828 int trapnr;
2829 unsigned int n;
2830 target_siginfo_t info;
2831 TaskState *ts = cs->opaque;
2832
2833 for(;;) {
2834 cpu_exec_start(cs);
2835 trapnr = cpu_exec(cs);
2836 cpu_exec_end(cs);
2837 process_queued_cpu_work(cs);
2838
2839 switch(trapnr) {
2840 case EXCP_ILLEGAL:
2841 {
2842 if (ts->sim_syscalls) {
2843 uint16_t nr;
2844 get_user_u16(nr, env->pc + 2);
2845 env->pc += 4;
2846 do_m68k_simcall(env, nr);
2847 } else {
2848 goto do_sigill;
2849 }
2850 }
2851 break;
2852 case EXCP_HALT_INSN:
2853 /* Semihosing syscall. */
2854 env->pc += 4;
2855 do_m68k_semihosting(env, env->dregs[0]);
2856 break;
2857 case EXCP_LINEA:
2858 case EXCP_LINEF:
2859 case EXCP_UNSUPPORTED:
2860 do_sigill:
2861 info.si_signo = TARGET_SIGILL;
2862 info.si_errno = 0;
2863 info.si_code = TARGET_ILL_ILLOPN;
2864 info._sifields._sigfault._addr = env->pc;
2865 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2866 break;
2867 case EXCP_DIV0:
2868 info.si_signo = TARGET_SIGFPE;
2869 info.si_errno = 0;
2870 info.si_code = TARGET_FPE_INTDIV;
2871 info._sifields._sigfault._addr = env->pc;
2872 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2873 break;
2874 case EXCP_TRAP0:
2875 {
2876 abi_long ret;
2877 ts->sim_syscalls = 0;
2878 n = env->dregs[0];
2879 env->pc += 2;
2880 ret = do_syscall(env,
2881 n,
2882 env->dregs[1],
2883 env->dregs[2],
2884 env->dregs[3],
2885 env->dregs[4],
2886 env->dregs[5],
2887 env->aregs[0],
2888 0, 0);
2889 if (ret == -TARGET_ERESTARTSYS) {
2890 env->pc -= 2;
2891 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
2892 env->dregs[0] = ret;
2893 }
2894 }
2895 break;
2896 case EXCP_INTERRUPT:
2897 /* just indicate that signals should be handled asap */
2898 break;
2899 case EXCP_ACCESS:
2900 {
2901 info.si_signo = TARGET_SIGSEGV;
2902 info.si_errno = 0;
2903 /* XXX: check env->error_code */
2904 info.si_code = TARGET_SEGV_MAPERR;
2905 info._sifields._sigfault._addr = env->mmu.ar;
2906 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2907 }
2908 break;
2909 case EXCP_DEBUG:
2910 {
2911 int sig;
2912
2913 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2914 if (sig)
2915 {
2916 info.si_signo = sig;
2917 info.si_errno = 0;
2918 info.si_code = TARGET_TRAP_BRKPT;
2919 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2920 }
2921 }
2922 break;
2923 case EXCP_ATOMIC:
2924 cpu_exec_step_atomic(cs);
2925 break;
2926 default:
2927 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
2928 abort();
2929 }
2930 process_pending_signals(env);
2931 }
2932 }
2933 #endif /* TARGET_M68K */
2934
2935 #ifdef TARGET_ALPHA
2936 void cpu_loop(CPUAlphaState *env)
2937 {
2938 CPUState *cs = CPU(alpha_env_get_cpu(env));
2939 int trapnr;
2940 target_siginfo_t info;
2941 abi_long sysret;
2942
2943 while (1) {
2944 cpu_exec_start(cs);
2945 trapnr = cpu_exec(cs);
2946 cpu_exec_end(cs);
2947 process_queued_cpu_work(cs);
2948
2949 /* All of the traps imply a transition through PALcode, which
2950 implies an REI instruction has been executed. Which means
2951 that the intr_flag should be cleared. */
2952 env->intr_flag = 0;
2953
2954 switch (trapnr) {
2955 case EXCP_RESET:
2956 fprintf(stderr, "Reset requested. Exit\n");
2957 exit(EXIT_FAILURE);
2958 break;
2959 case EXCP_MCHK:
2960 fprintf(stderr, "Machine check exception. Exit\n");
2961 exit(EXIT_FAILURE);
2962 break;
2963 case EXCP_SMP_INTERRUPT:
2964 case EXCP_CLK_INTERRUPT:
2965 case EXCP_DEV_INTERRUPT:
2966 fprintf(stderr, "External interrupt. Exit\n");
2967 exit(EXIT_FAILURE);
2968 break;
2969 case EXCP_MMFAULT:
2970 env->lock_addr = -1;
2971 info.si_signo = TARGET_SIGSEGV;
2972 info.si_errno = 0;
2973 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
2974 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
2975 info._sifields._sigfault._addr = env->trap_arg0;
2976 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2977 break;
2978 case EXCP_UNALIGN:
2979 env->lock_addr = -1;
2980 info.si_signo = TARGET_SIGBUS;
2981 info.si_errno = 0;
2982 info.si_code = TARGET_BUS_ADRALN;
2983 info._sifields._sigfault._addr = env->trap_arg0;
2984 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2985 break;
2986 case EXCP_OPCDEC:
2987 do_sigill:
2988 env->lock_addr = -1;
2989 info.si_signo = TARGET_SIGILL;
2990 info.si_errno = 0;
2991 info.si_code = TARGET_ILL_ILLOPC;
2992 info._sifields._sigfault._addr = env->pc;
2993 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
2994 break;
2995 case EXCP_ARITH:
2996 env->lock_addr = -1;
2997 info.si_signo = TARGET_SIGFPE;
2998 info.si_errno = 0;
2999 info.si_code = TARGET_FPE_FLTINV;
3000 info._sifields._sigfault._addr = env->pc;
3001 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3002 break;
3003 case EXCP_FEN:
3004 /* No-op. Linux simply re-enables the FPU. */
3005 break;
3006 case EXCP_CALL_PAL:
3007 env->lock_addr = -1;
3008 switch (env->error_code) {
3009 case 0x80:
3010 /* BPT */
3011 info.si_signo = TARGET_SIGTRAP;
3012 info.si_errno = 0;
3013 info.si_code = TARGET_TRAP_BRKPT;
3014 info._sifields._sigfault._addr = env->pc;
3015 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3016 break;
3017 case 0x81:
3018 /* BUGCHK */
3019 info.si_signo = TARGET_SIGTRAP;
3020 info.si_errno = 0;
3021 info.si_code = 0;
3022 info._sifields._sigfault._addr = env->pc;
3023 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3024 break;
3025 case 0x83:
3026 /* CALLSYS */
3027 trapnr = env->ir[IR_V0];
3028 sysret = do_syscall(env, trapnr,
3029 env->ir[IR_A0], env->ir[IR_A1],
3030 env->ir[IR_A2], env->ir[IR_A3],
3031 env->ir[IR_A4], env->ir[IR_A5],
3032 0, 0);
3033 if (sysret == -TARGET_ERESTARTSYS) {
3034 env->pc -= 4;
3035 break;
3036 }
3037 if (sysret == -TARGET_QEMU_ESIGRETURN) {
3038 break;
3039 }
3040 /* Syscall writes 0 to V0 to bypass error check, similar
3041 to how this is handled internal to Linux kernel.
3042 (Ab)use trapnr temporarily as boolean indicating error. */
3043 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3044 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3045 env->ir[IR_A3] = trapnr;
3046 break;
3047 case 0x86:
3048 /* IMB */
3049 /* ??? We can probably elide the code using page_unprotect
3050 that is checking for self-modifying code. Instead we
3051 could simply call tb_flush here. Until we work out the
3052 changes required to turn off the extra write protection,
3053 this can be a no-op. */
3054 break;
3055 case 0x9E:
3056 /* RDUNIQUE */
3057 /* Handled in the translator for usermode. */
3058 abort();
3059 case 0x9F:
3060 /* WRUNIQUE */
3061 /* Handled in the translator for usermode. */
3062 abort();
3063 case 0xAA:
3064 /* GENTRAP */
3065 info.si_signo = TARGET_SIGFPE;
3066 switch (env->ir[IR_A0]) {
3067 case TARGET_GEN_INTOVF:
3068 info.si_code = TARGET_FPE_INTOVF;
3069 break;
3070 case TARGET_GEN_INTDIV:
3071 info.si_code = TARGET_FPE_INTDIV;
3072 break;
3073 case TARGET_GEN_FLTOVF:
3074 info.si_code = TARGET_FPE_FLTOVF;
3075 break;
3076 case TARGET_GEN_FLTUND:
3077 info.si_code = TARGET_FPE_FLTUND;
3078 break;
3079 case TARGET_GEN_FLTINV:
3080 info.si_code = TARGET_FPE_FLTINV;
3081 break;
3082 case TARGET_GEN_FLTINE:
3083 info.si_code = TARGET_FPE_FLTRES;
3084 break;
3085 case TARGET_GEN_ROPRAND:
3086 info.si_code = 0;
3087 break;
3088 default:
3089 info.si_signo = TARGET_SIGTRAP;
3090 info.si_code = 0;
3091 break;
3092 }
3093 info.si_errno = 0;
3094 info._sifields._sigfault._addr = env->pc;
3095 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3096 break;
3097 default:
3098 goto do_sigill;
3099 }
3100 break;
3101 case EXCP_DEBUG:
3102 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3103 if (info.si_signo) {
3104 env->lock_addr = -1;
3105 info.si_errno = 0;
3106 info.si_code = TARGET_TRAP_BRKPT;
3107 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3108 }
3109 break;
3110 case EXCP_INTERRUPT:
3111 /* Just indicate that signals should be handled asap. */
3112 break;
3113 case EXCP_ATOMIC:
3114 cpu_exec_step_atomic(cs);
3115 break;
3116 default:
3117 printf ("Unhandled trap: 0x%x\n", trapnr);
3118 cpu_dump_state(cs, stderr, fprintf, 0);
3119 exit(EXIT_FAILURE);
3120 }
3121 process_pending_signals (env);
3122 }
3123 }
3124 #endif /* TARGET_ALPHA */
3125
3126 #ifdef TARGET_S390X
3127 void cpu_loop(CPUS390XState *env)
3128 {
3129 CPUState *cs = CPU(s390_env_get_cpu(env));
3130 int trapnr, n, sig;
3131 target_siginfo_t info;
3132 target_ulong addr;
3133 abi_long ret;
3134
3135 while (1) {
3136 cpu_exec_start(cs);
3137 trapnr = cpu_exec(cs);
3138 cpu_exec_end(cs);
3139 process_queued_cpu_work(cs);
3140
3141 switch (trapnr) {
3142 case EXCP_INTERRUPT:
3143 /* Just indicate that signals should be handled asap. */
3144 break;
3145
3146 case EXCP_SVC:
3147 n = env->int_svc_code;
3148 if (!n) {
3149 /* syscalls > 255 */
3150 n = env->regs[1];
3151 }
3152 env->psw.addr += env->int_svc_ilen;
3153 ret = do_syscall(env, n, env->regs[2], env->regs[3],
3154 env->regs[4], env->regs[5],
3155 env->regs[6], env->regs[7], 0, 0);
3156 if (ret == -TARGET_ERESTARTSYS) {
3157 env->psw.addr -= env->int_svc_ilen;
3158 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3159 env->regs[2] = ret;
3160 }
3161 break;
3162
3163 case EXCP_DEBUG:
3164 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3165 if (sig) {
3166 n = TARGET_TRAP_BRKPT;
3167 goto do_signal_pc;
3168 }
3169 break;
3170 case EXCP_PGM:
3171 n = env->int_pgm_code;
3172 switch (n) {
3173 case PGM_OPERATION:
3174 case PGM_PRIVILEGED:
3175 sig = TARGET_SIGILL;
3176 n = TARGET_ILL_ILLOPC;
3177 goto do_signal_pc;
3178 case PGM_PROTECTION:
3179 case PGM_ADDRESSING:
3180 sig = TARGET_SIGSEGV;
3181 /* XXX: check env->error_code */
3182 n = TARGET_SEGV_MAPERR;
3183 addr = env->__excp_addr;
3184 goto do_signal;
3185 case PGM_EXECUTE:
3186 case PGM_SPECIFICATION:
3187 case PGM_SPECIAL_OP:
3188 case PGM_OPERAND:
3189 do_sigill_opn:
3190 sig = TARGET_SIGILL;
3191 n = TARGET_ILL_ILLOPN;
3192 goto do_signal_pc;
3193
3194 case PGM_FIXPT_OVERFLOW:
3195 sig = TARGET_SIGFPE;
3196 n = TARGET_FPE_INTOVF;
3197 goto do_signal_pc;
3198 case PGM_FIXPT_DIVIDE:
3199 sig = TARGET_SIGFPE;
3200 n = TARGET_FPE_INTDIV;
3201 goto do_signal_pc;
3202
3203 case PGM_DATA:
3204 n = (env->fpc >> 8) & 0xff;
3205 if (n == 0xff) {
3206 /* compare-and-trap */
3207 goto do_sigill_opn;
3208 } else {
3209 /* An IEEE exception, simulated or otherwise. */
3210 if (n & 0x80) {
3211 n = TARGET_FPE_FLTINV;
3212 } else if (n & 0x40) {
3213 n = TARGET_FPE_FLTDIV;
3214 } else if (n & 0x20) {
3215 n = TARGET_FPE_FLTOVF;
3216 } else if (n & 0x10) {
3217 n = TARGET_FPE_FLTUND;
3218 } else if (n & 0x08) {
3219 n = TARGET_FPE_FLTRES;
3220 } else {
3221 /* ??? Quantum exception; BFP, DFP error. */
3222 goto do_sigill_opn;
3223 }
3224 sig = TARGET_SIGFPE;
3225 goto do_signal_pc;
3226 }
3227
3228 default:
3229 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3230 cpu_dump_state(cs, stderr, fprintf, 0);
3231 exit(EXIT_FAILURE);
3232 }
3233 break;
3234
3235 do_signal_pc:
3236 addr = env->psw.addr;
3237 do_signal:
3238 info.si_signo = sig;
3239 info.si_errno = 0;
3240 info.si_code = n;
3241 info._sifields._sigfault._addr = addr;
3242 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3243 break;
3244
3245 case EXCP_ATOMIC:
3246 cpu_exec_step_atomic(cs);
3247 break;
3248 default:
3249 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3250 cpu_dump_state(cs, stderr, fprintf, 0);
3251 exit(EXIT_FAILURE);
3252 }
3253 process_pending_signals (env);
3254 }
3255 }
3256
3257 #endif /* TARGET_S390X */
3258
3259 #ifdef TARGET_TILEGX
3260
3261 static void gen_sigill_reg(CPUTLGState *env)
3262 {
3263 target_siginfo_t info;
3264
3265 info.si_signo = TARGET_SIGILL;
3266 info.si_errno = 0;
3267 info.si_code = TARGET_ILL_PRVREG;
3268 info._sifields._sigfault._addr = env->pc;
3269 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3270 }
3271
3272 static void do_signal(CPUTLGState *env, int signo, int sigcode)
3273 {
3274 target_siginfo_t info;
3275
3276 info.si_signo = signo;
3277 info.si_errno = 0;
3278 info._sifields._sigfault._addr = env->pc;
3279
3280 if (signo == TARGET_SIGSEGV) {
3281 /* The passed in sigcode is a dummy; check for a page mapping
3282 and pass either MAPERR or ACCERR. */
3283 target_ulong addr = env->excaddr;
3284 info._sifields._sigfault._addr = addr;
3285 if (page_check_range(addr, 1, PAGE_VALID) < 0) {
3286 sigcode = TARGET_SEGV_MAPERR;
3287 } else {
3288 sigcode = TARGET_SEGV_ACCERR;
3289 }
3290 }
3291 info.si_code = sigcode;
3292
3293 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3294 }
3295
3296 static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
3297 {
3298 env->excaddr = addr;
3299 do_signal(env, TARGET_SIGSEGV, 0);
3300 }
3301
3302 static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
3303 {
3304 if (unlikely(reg >= TILEGX_R_COUNT)) {
3305 switch (reg) {
3306 case TILEGX_R_SN:
3307 case TILEGX_R_ZERO:
3308 return;
3309 case TILEGX_R_IDN0:
3310 case TILEGX_R_IDN1:
3311 case TILEGX_R_UDN0:
3312 case TILEGX_R_UDN1:
3313 case TILEGX_R_UDN2:
3314 case TILEGX_R_UDN3:
3315 gen_sigill_reg(env);
3316 return;
3317 default:
3318 g_assert_not_reached();
3319 }
3320 }
3321 env->regs[reg] = val;
3322 }
3323
3324 /*
3325 * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
3326 * memory at the address held in the first source register. If the values are
3327 * not equal, then no memory operation is performed. If the values are equal,
3328 * the 8-byte quantity from the second source register is written into memory
3329 * at the address held in the first source register. In either case, the result
3330 * of the instruction is the value read from memory. The compare and write to
3331 * memory are atomic and thus can be used for synchronization purposes. This
3332 * instruction only operates for addresses aligned to a 8-byte boundary.
3333 * Unaligned memory access causes an Unaligned Data Reference interrupt.
3334 *
3335 * Functional Description (64-bit)
3336 * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
3337 * rf[Dest] = memVal;
3338 * if (memVal == SPR[CmpValueSPR])
3339 * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
3340 *
3341 * Functional Description (32-bit)
3342 * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
3343 * rf[Dest] = memVal;
3344 * if (memVal == signExtend32 (SPR[CmpValueSPR]))
3345 * memoryWriteWord (rf[SrcA], rf[SrcB]);
3346 *
3347 *
3348 * This function also processes exch and exch4 which need not process SPR.
3349 */
3350 static void do_exch(CPUTLGState *env, bool quad, bool cmp)
3351 {
3352 target_ulong addr;
3353 target_long val, sprval;
3354
3355 start_exclusive();
3356
3357 addr = env->atomic_srca;
3358 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3359 goto sigsegv_maperr;
3360 }
3361
3362 if (cmp) {
3363 if (quad) {
3364 sprval = env->spregs[TILEGX_SPR_CMPEXCH];
3365 } else {
3366 sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
3367 }
3368 }
3369
3370 if (!cmp || val == sprval) {
3371 target_long valb = env->atomic_srcb;
3372 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3373 goto sigsegv_maperr;
3374 }
3375 }
3376
3377 set_regval(env, env->atomic_dstr, val);
3378 end_exclusive();
3379 return;
3380
3381 sigsegv_maperr:
3382 end_exclusive();
3383 gen_sigsegv_maperr(env, addr);
3384 }
3385
3386 static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
3387 {
3388 int8_t write = 1;
3389 target_ulong addr;
3390 target_long val, valb;
3391
3392 start_exclusive();
3393
3394 addr = env->atomic_srca;
3395 valb = env->atomic_srcb;
3396 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3397 goto sigsegv_maperr;
3398 }
3399
3400 switch (trapnr) {
3401 case TILEGX_EXCP_OPCODE_FETCHADD:
3402 case TILEGX_EXCP_OPCODE_FETCHADD4:
3403 valb += val;
3404 break;
3405 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3406 valb += val;
3407 if (valb < 0) {
3408 write = 0;
3409 }
3410 break;
3411 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3412 valb += val;
3413 if ((int32_t)valb < 0) {
3414 write = 0;
3415 }
3416 break;
3417 case TILEGX_EXCP_OPCODE_FETCHAND:
3418 case TILEGX_EXCP_OPCODE_FETCHAND4:
3419 valb &= val;
3420 break;
3421 case TILEGX_EXCP_OPCODE_FETCHOR:
3422 case TILEGX_EXCP_OPCODE_FETCHOR4:
3423 valb |= val;
3424 break;
3425 default:
3426 g_assert_not_reached();
3427 }
3428
3429 if (write) {
3430 if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
3431 goto sigsegv_maperr;
3432 }
3433 }
3434
3435 set_regval(env, env->atomic_dstr, val);
3436 end_exclusive();
3437 return;
3438
3439 sigsegv_maperr:
3440 end_exclusive();
3441 gen_sigsegv_maperr(env, addr);
3442 }
3443
3444 void cpu_loop(CPUTLGState *env)
3445 {
3446 CPUState *cs = CPU(tilegx_env_get_cpu(env));
3447 int trapnr;
3448
3449 while (1) {
3450 cpu_exec_start(cs);
3451 trapnr = cpu_exec(cs);
3452 cpu_exec_end(cs);
3453 process_queued_cpu_work(cs);
3454
3455 switch (trapnr) {
3456 case TILEGX_EXCP_SYSCALL:
3457 {
3458 abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
3459 env->regs[0], env->regs[1],
3460 env->regs[2], env->regs[3],
3461 env->regs[4], env->regs[5],
3462 env->regs[6], env->regs[7]);
3463 if (ret == -TARGET_ERESTARTSYS) {
3464 env->pc -= 8;
3465 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
3466 env->regs[TILEGX_R_RE] = ret;
3467 env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
3468 }
3469 break;
3470 }
3471 case TILEGX_EXCP_OPCODE_EXCH:
3472 do_exch(env, true, false);
3473 break;
3474 case TILEGX_EXCP_OPCODE_EXCH4:
3475 do_exch(env, false, false);
3476 break;
3477 case TILEGX_EXCP_OPCODE_CMPEXCH:
3478 do_exch(env, true, true);
3479 break;
3480 case TILEGX_EXCP_OPCODE_CMPEXCH4:
3481 do_exch(env, false, true);
3482 break;
3483 case TILEGX_EXCP_OPCODE_FETCHADD:
3484 case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
3485 case TILEGX_EXCP_OPCODE_FETCHAND:
3486 case TILEGX_EXCP_OPCODE_FETCHOR:
3487 do_fetch(env, trapnr, true);
3488 break;
3489 case TILEGX_EXCP_OPCODE_FETCHADD4:
3490 case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
3491 case TILEGX_EXCP_OPCODE_FETCHAND4:
3492 case TILEGX_EXCP_OPCODE_FETCHOR4:
3493 do_fetch(env, trapnr, false);
3494 break;
3495 case TILEGX_EXCP_SIGNAL:
3496 do_signal(env, env->signo, env->sigcode);
3497 break;
3498 case TILEGX_EXCP_REG_IDN_ACCESS:
3499 case TILEGX_EXCP_REG_UDN_ACCESS:
3500 gen_sigill_reg(env);
3501 break;
3502 case EXCP_ATOMIC:
3503 cpu_exec_step_atomic(cs);
3504 break;
3505 default:
3506 fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
3507 g_assert_not_reached();
3508 }
3509 process_pending_signals(env);
3510 }
3511 }
3512
3513 #endif
3514
3515 #ifdef TARGET_HPPA
3516
3517 static abi_ulong hppa_lws(CPUHPPAState *env)
3518 {
3519 uint32_t which = env->gr[20];
3520 abi_ulong addr = env->gr[26];
3521 abi_ulong old = env->gr[25];
3522 abi_ulong new = env->gr[24];
3523 abi_ulong size, ret;
3524
3525 switch (which) {
3526 default:
3527 return -TARGET_ENOSYS;
3528
3529 case 0: /* elf32 atomic 32bit cmpxchg */
3530 if ((addr & 3) || !access_ok(VERIFY_WRITE, addr, 4)) {
3531 return -TARGET_EFAULT;
3532 }
3533 old = tswap32(old);
3534 new = tswap32(new);
3535 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3536 ret = tswap32(ret);
3537 break;
3538
3539 case 2: /* elf32 atomic "new" cmpxchg */
3540 size = env->gr[23];
3541 if (size >= 4) {
3542 return -TARGET_ENOSYS;
3543 }
3544 if (((addr | old | new) & ((1 << size) - 1))
3545 || !access_ok(VERIFY_WRITE, addr, 1 << size)
3546 || !access_ok(VERIFY_READ, old, 1 << size)
3547 || !access_ok(VERIFY_READ, new, 1 << size)) {
3548 return -TARGET_EFAULT;
3549 }
3550 /* Note that below we use host-endian loads so that the cmpxchg
3551 can be host-endian as well. */
3552 switch (size) {
3553 case 0:
3554 old = *(uint8_t *)g2h(old);
3555 new = *(uint8_t *)g2h(new);
3556 ret = atomic_cmpxchg((uint8_t *)g2h(addr), old, new);
3557 ret = ret != old;
3558 break;
3559 case 1:
3560 old = *(uint16_t *)g2h(old);
3561 new = *(uint16_t *)g2h(new);
3562 ret = atomic_cmpxchg((uint16_t *)g2h(addr), old, new);
3563 ret = ret != old;
3564 break;
3565 case 2:
3566 old = *(uint32_t *)g2h(old);
3567 new = *(uint32_t *)g2h(new);
3568 ret = atomic_cmpxchg((uint32_t *)g2h(addr), old, new);
3569 ret = ret != old;
3570 break;
3571 case 3:
3572 {
3573 uint64_t o64, n64, r64;
3574 o64 = *(uint64_t *)g2h(old);
3575 n64 = *(uint64_t *)g2h(new);
3576 #ifdef CONFIG_ATOMIC64
3577 r64 = atomic_cmpxchg__nocheck((uint64_t *)g2h(addr), o64, n64);
3578 ret = r64 != o64;
3579 #else
3580 start_exclusive();
3581 r64 = *(uint64_t *)g2h(addr);
3582 ret = 1;
3583 if (r64 == o64) {
3584 *(uint64_t *)g2h(addr) = n64;
3585 ret = 0;
3586 }
3587 end_exclusive();
3588 #endif
3589 }
3590 break;
3591 }
3592 break;
3593 }
3594
3595 env->gr[28] = ret;
3596 return 0;
3597 }
3598
3599 void cpu_loop(CPUHPPAState *env)
3600 {
3601 CPUState *cs = CPU(hppa_env_get_cpu(env));
3602 target_siginfo_t info;
3603 abi_ulong ret;
3604 int trapnr;
3605
3606 while (1) {
3607 cpu_exec_start(cs);
3608 trapnr = cpu_exec(cs);
3609 cpu_exec_end(cs);
3610 process_queued_cpu_work(cs);
3611
3612 switch (trapnr) {
3613 case EXCP_SYSCALL:
3614 ret = do_syscall(env, env->gr[20],
3615 env->gr[26], env->gr[25],
3616 env->gr[24], env->gr[23],
3617 env->gr[22], env->gr[21], 0, 0);
3618 switch (ret) {
3619 default:
3620 env->gr[28] = ret;
3621 /* We arrived here by faking the gateway page. Return. */
3622 env->iaoq_f = env->gr[31];
3623 env->iaoq_b = env->gr[31] + 4;
3624 break;
3625 case -TARGET_ERESTARTSYS:
3626 case -TARGET_QEMU_ESIGRETURN:
3627 break;
3628 }
3629 break;
3630 case EXCP_SYSCALL_LWS:
3631 env->gr[21] = hppa_lws(env);
3632 /* We arrived here by faking the gateway page. Return. */
3633 env->iaoq_f = env->gr[31];
3634 env->iaoq_b = env->gr[31] + 4;
3635 break;
3636 case EXCP_SIGSEGV:
3637 info.si_signo = TARGET_SIGSEGV;
3638 info.si_errno = 0;
3639 info.si_code = TARGET_SEGV_ACCERR;
3640 info._sifields._sigfault._addr = env->ior;
3641 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3642 break;
3643 case EXCP_SIGILL:
3644 info.si_signo = TARGET_SIGILL;
3645 info.si_errno = 0;
3646 info.si_code = TARGET_ILL_ILLOPN;
3647 info._sifields._sigfault._addr = env->iaoq_f;
3648 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3649 break;
3650 case EXCP_SIGFPE:
3651 info.si_signo = TARGET_SIGFPE;
3652 info.si_errno = 0;
3653 info.si_code = 0;
3654 info._sifields._sigfault._addr = env->iaoq_f;
3655 queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
3656 break;
3657 case EXCP_DEBUG:
3658 trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
3659 if (trapnr) {
3660 info.si_signo = trapnr;
3661 info.si_errno = 0;
3662 info.si_code = TARGET_TRAP_BRKPT;
3663 queue_signal(env, trapnr, QEMU_SI_FAULT, &info);
3664 }
3665 break;
3666 case EXCP_INTERRUPT:
3667 /* just indicate that signals should be handled asap */
3668 break;
3669 default:
3670 g_assert_not_reached();
3671 }
3672 process_pending_signals(env);
3673 }
3674 }
3675
3676 #endif /* TARGET_HPPA */
3677
3678 THREAD CPUState *thread_cpu;
3679
3680 bool qemu_cpu_is_self(CPUState *cpu)
3681 {
3682 return thread_cpu == cpu;
3683 }
3684
3685 void qemu_cpu_kick(CPUState *cpu)
3686 {
3687 cpu_exit(cpu);
3688 }
3689
3690 void task_settid(TaskState *ts)
3691 {
3692 if (ts->ts_tid == 0) {
3693 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3694 }
3695 }
3696
3697 void stop_all_tasks(void)
3698 {
3699 /*
3700 * We trust that when using NPTL, start_exclusive()
3701 * handles thread stopping correctly.
3702 */
3703 start_exclusive();
3704 }
3705
3706 /* Assumes contents are already zeroed. */
3707 void init_task_state(TaskState *ts)
3708 {
3709 ts->used = 1;
3710 }
3711
3712 CPUArchState *cpu_copy(CPUArchState *env)
3713 {
3714 CPUState *cpu = ENV_GET_CPU(env);
3715 CPUState *new_cpu = cpu_init(cpu_model);
3716 CPUArchState *new_env = new_cpu->env_ptr;
3717 CPUBreakpoint *bp;
3718 CPUWatchpoint *wp;
3719
3720 /* Reset non arch specific state */
3721 cpu_reset(new_cpu);
3722
3723 memcpy(new_env, env, sizeof(CPUArchState));
3724
3725 /* Clone all break/watchpoints.
3726 Note: Once we support ptrace with hw-debug register access, make sure
3727 BP_CPU break/watchpoints are handled correctly on clone. */
3728 QTAILQ_INIT(&new_cpu->breakpoints);
3729 QTAILQ_INIT(&new_cpu->watchpoints);
3730 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3731 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3732 }
3733 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3734 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3735 }
3736
3737 return new_env;
3738 }
3739
3740 static void handle_arg_help(const char *arg)
3741 {
3742 usage(EXIT_SUCCESS);
3743 }
3744
3745 static void handle_arg_log(const char *arg)
3746 {
3747 int mask;
3748
3749 mask = qemu_str_to_log_mask(arg);
3750 if (!mask) {
3751 qemu_print_log_usage(stdout);
3752 exit(EXIT_FAILURE);
3753 }
3754 qemu_log_needs_buffers();
3755 qemu_set_log(mask);
3756 }
3757
3758 static void handle_arg_log_filename(const char *arg)
3759 {
3760 qemu_set_log_filename(arg, &error_fatal);
3761 }
3762
3763 static void handle_arg_set_env(const char *arg)
3764 {
3765 char *r, *p, *token;
3766 r = p = strdup(arg);
3767 while ((token = strsep(&p, ",")) != NULL) {
3768 if (envlist_setenv(envlist, token) != 0) {
3769 usage(EXIT_FAILURE);
3770 }
3771 }
3772 free(r);
3773 }
3774
3775 static void handle_arg_unset_env(const char *arg)
3776 {
3777 char *r, *p, *token;
3778 r = p = strdup(arg);
3779 while ((token = strsep(&p, ",")) != NULL) {
3780 if (envlist_unsetenv(envlist, token) != 0) {
3781 usage(EXIT_FAILURE);
3782 }
3783 }
3784 free(r);
3785 }
3786
3787 static void handle_arg_argv0(const char *arg)
3788 {
3789 argv0 = strdup(arg);
3790 }
3791
3792 static void handle_arg_stack_size(const char *arg)
3793 {
3794 char *p;
3795 guest_stack_size = strtoul(arg, &p, 0);
3796 if (guest_stack_size == 0) {
3797 usage(EXIT_FAILURE);
3798 }
3799
3800 if (*p == 'M') {
3801 guest_stack_size *= 1024 * 1024;
3802 } else if (*p == 'k' || *p == 'K') {
3803 guest_stack_size *= 1024;
3804 }
3805 }
3806
3807 static void handle_arg_ld_prefix(const char *arg)
3808 {
3809 interp_prefix = strdup(arg);
3810 }
3811
3812 static void handle_arg_pagesize(const char *arg)
3813 {
3814 qemu_host_page_size = atoi(arg);
3815 if (qemu_host_page_size == 0 ||
3816 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3817 fprintf(stderr, "page size must be a power of two\n");
3818 exit(EXIT_FAILURE);
3819 }
3820 }
3821
3822 static void handle_arg_randseed(const char *arg)
3823 {
3824 unsigned long long seed;
3825
3826 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3827 fprintf(stderr, "Invalid seed number: %s\n", arg);
3828 exit(EXIT_FAILURE);
3829 }
3830 srand(seed);
3831 }
3832
3833 static void handle_arg_gdb(const char *arg)
3834 {
3835 gdbstub_port = atoi(arg);
3836 }
3837
3838 static void handle_arg_uname(const char *arg)
3839 {
3840 qemu_uname_release = strdup(arg);
3841 }
3842
3843 static void handle_arg_cpu(const char *arg)
3844 {
3845 cpu_model = strdup(arg);
3846 if (cpu_model == NULL || is_help_option(cpu_model)) {
3847 /* XXX: implement xxx_cpu_list for targets that still miss it */
3848 #if defined(cpu_list)
3849 cpu_list(stdout, &fprintf);
3850 #endif
3851 exit(EXIT_FAILURE);
3852 }
3853 }
3854
3855 static void handle_arg_guest_base(const char *arg)
3856 {
3857 guest_base = strtol(arg, NULL, 0);
3858 have_guest_base = 1;
3859 }
3860
3861 static void handle_arg_reserved_va(const char *arg)
3862 {
3863 char *p;
3864 int shift = 0;
3865 reserved_va = strtoul(arg, &p, 0);
3866 switch (*p) {
3867 case 'k':
3868 case 'K':
3869 shift = 10;
3870 break;
3871 case 'M':
3872 shift = 20;
3873 break;
3874 case 'G':
3875 shift = 30;
3876 break;
3877 }
3878 if (shift) {
3879 unsigned long unshifted = reserved_va;
3880 p++;
3881 reserved_va <<= shift;
3882 if (((reserved_va >> shift) != unshifted)
3883 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3884 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3885 #endif
3886 ) {
3887 fprintf(stderr, "Reserved virtual address too big\n");
3888 exit(EXIT_FAILURE);
3889 }
3890 }
3891 if (*p) {
3892 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3893 exit(EXIT_FAILURE);
3894 }
3895 }
3896
3897 static void handle_arg_singlestep(const char *arg)
3898 {
3899 singlestep = 1;
3900 }
3901
3902 static void handle_arg_strace(const char *arg)
3903 {
3904 do_strace = 1;
3905 }
3906
3907 static void handle_arg_version(const char *arg)
3908 {
3909 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3910 "\n" QEMU_COPYRIGHT "\n");
3911 exit(EXIT_SUCCESS);
3912 }
3913
3914 static char *trace_file;
3915 static void handle_arg_trace(const char *arg)
3916 {
3917 g_free(trace_file);
3918 trace_file = trace_opt_parse(arg);
3919 }
3920
3921 struct qemu_argument {
3922 const char *argv;
3923 const char *env;
3924 bool has_arg;
3925 void (*handle_opt)(const char *arg);
3926 const char *example;
3927 const char *help;
3928 };
3929
3930 static const struct qemu_argument arg_table[] = {
3931 {"h", "", false, handle_arg_help,
3932 "", "print this help"},
3933 {"help", "", false, handle_arg_help,
3934 "", ""},
3935 {"g", "QEMU_GDB", true, handle_arg_gdb,
3936 "port", "wait gdb connection to 'port'"},
3937 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3938 "path", "set the elf interpreter prefix to 'path'"},
3939 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3940 "size", "set the stack size to 'size' bytes"},
3941 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3942 "model", "select CPU (-cpu help for list)"},
3943 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3944 "var=value", "sets targets environment variable (see below)"},
3945 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3946 "var", "unsets targets environment variable (see below)"},
3947 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3948 "argv0", "forces target process argv[0] to be 'argv0'"},
3949 {"r", "QEMU_UNAME", true, handle_arg_uname,
3950 "uname", "set qemu uname release string to 'uname'"},
3951 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3952 "address", "set guest_base address to 'address'"},
3953 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3954 "size", "reserve 'size' bytes for guest virtual address space"},
3955 {"d", "QEMU_LOG", true, handle_arg_log,
3956 "item[,...]", "enable logging of specified items "
3957 "(use '-d help' for a list of items)"},
3958 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3959 "logfile", "write logs to 'logfile' (default stderr)"},
3960 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3961 "pagesize", "set the host page size to 'pagesize'"},
3962 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3963 "", "run in singlestep mode"},
3964 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3965 "", "log system calls"},
3966 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3967 "", "Seed for pseudo-random number generator"},
3968 {"trace", "QEMU_TRACE", true, handle_arg_trace,
3969 "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"},
3970 {"version", "QEMU_VERSION", false, handle_arg_version,
3971 "", "display version information and exit"},
3972 {NULL, NULL, false, NULL, NULL, NULL}
3973 };
3974
3975 static void usage(int exitcode)
3976 {
3977 const struct qemu_argument *arginfo;
3978 int maxarglen;
3979 int maxenvlen;
3980
3981 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3982 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3983 "\n"
3984 "Options and associated environment variables:\n"
3985 "\n");
3986
3987 /* Calculate column widths. We must always have at least enough space
3988 * for the column header.
3989 */
3990 maxarglen = strlen("Argument");
3991 maxenvlen = strlen("Env-variable");
3992
3993 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3994 int arglen = strlen(arginfo->argv);
3995 if (arginfo->has_arg) {
3996 arglen += strlen(arginfo->example) + 1;
3997 }
3998 if (strlen(arginfo->env) > maxenvlen) {
3999 maxenvlen = strlen(arginfo->env);
4000 }
4001 if (arglen > maxarglen) {
4002 maxarglen = arglen;
4003 }
4004 }
4005
4006 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
4007 maxenvlen, "Env-variable");
4008
4009 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4010 if (arginfo->has_arg) {
4011 printf("-%s %-*s %-*s %s\n", arginfo->argv,
4012 (int)(maxarglen - strlen(arginfo->argv) - 1),
4013 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
4014 } else {
4015 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
4016 maxenvlen, arginfo->env,
4017 arginfo->help);
4018 }
4019 }
4020
4021 printf("\n"
4022 "Defaults:\n"
4023 "QEMU_LD_PREFIX = %s\n"
4024 "QEMU_STACK_SIZE = %ld byte\n",
4025 interp_prefix,
4026 guest_stack_size);
4027
4028 printf("\n"
4029 "You can use -E and -U options or the QEMU_SET_ENV and\n"
4030 "QEMU_UNSET_ENV environment variables to set and unset\n"
4031 "environment variables for the target process.\n"
4032 "It is possible to provide several variables by separating them\n"
4033 "by commas in getsubopt(3) style. Additionally it is possible to\n"
4034 "provide the -E and -U options multiple times.\n"
4035 "The following lines are equivalent:\n"
4036 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
4037 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
4038 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
4039 "Note that if you provide several changes to a single variable\n"
4040 "the last change will stay in effect.\n");
4041
4042 exit(exitcode);
4043 }
4044
4045 static int parse_args(int argc, char **argv)
4046 {
4047 const char *r;
4048 int optind;
4049 const struct qemu_argument *arginfo;
4050
4051 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4052 if (arginfo->env == NULL) {
4053 continue;
4054 }
4055
4056 r = getenv(arginfo->env);
4057 if (r != NULL) {
4058 arginfo->handle_opt(r);
4059 }
4060 }
4061
4062 optind = 1;
4063 for (;;) {
4064 if (optind >= argc) {
4065 break;
4066 }
4067 r = argv[optind];
4068 if (r[0] != '-') {
4069 break;
4070 }
4071 optind++;
4072 r++;
4073 if (!strcmp(r, "-")) {
4074 break;
4075 }
4076 /* Treat --foo the same as -foo. */
4077 if (r[0] == '-') {
4078 r++;
4079 }
4080
4081 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
4082 if (!strcmp(r, arginfo->argv)) {
4083 if (arginfo->has_arg) {
4084 if (optind >= argc) {
4085 (void) fprintf(stderr,
4086 "qemu: missing argument for option '%s'\n", r);
4087 exit(EXIT_FAILURE);
4088 }
4089 arginfo->handle_opt(argv[optind]);
4090 optind++;
4091 } else {
4092 arginfo->handle_opt(NULL);
4093 }
4094 break;
4095 }
4096 }
4097
4098 /* no option matched the current argv */
4099 if (arginfo->handle_opt == NULL) {
4100 (void) fprintf(stderr, "qemu: unknown option '%s'\n", r);
4101 exit(EXIT_FAILURE);
4102 }
4103 }
4104
4105 if (optind >= argc) {
4106 (void) fprintf(stderr, "qemu: no user program specified\n");
4107 exit(EXIT_FAILURE);
4108 }
4109
4110 filename = argv[optind];
4111 exec_path = argv[optind];
4112
4113 return optind;
4114 }
4115
4116 int main(int argc, char **argv, char **envp)
4117 {
4118 struct target_pt_regs regs1, *regs = &regs1;
4119 struct image_info info1, *info = &info1;
4120 struct linux_binprm bprm;
4121 TaskState *ts;
4122 CPUArchState *env;
4123 CPUState *cpu;
4124 int optind;
4125 char **target_environ, **wrk;
4126 char **target_argv;
4127 int target_argc;
4128 int i;
4129 int ret;
4130 int execfd;
4131
4132 module_call_init(MODULE_INIT_TRACE);
4133 qemu_init_cpu_list();
4134 module_call_init(MODULE_INIT_QOM);
4135
4136 if ((envlist = envlist_create()) == NULL) {
4137 (void) fprintf(stderr, "Unable to allocate envlist\n");
4138 exit(EXIT_FAILURE);
4139 }
4140
4141 /* add current environment into the list */
4142 for (wrk = environ; *wrk != NULL; wrk++) {
4143 (void) envlist_setenv(envlist, *wrk);
4144 }
4145
4146 /* Read the stack limit from the kernel. If it's "unlimited",
4147 then we can do little else besides use the default. */
4148 {
4149 struct rlimit lim;
4150 if (getrlimit(RLIMIT_STACK, &lim) == 0
4151 && lim.rlim_cur != RLIM_INFINITY
4152 && lim.rlim_cur == (target_long)lim.rlim_cur) {
4153 guest_stack_size = lim.rlim_cur;
4154 }
4155 }
4156
4157 cpu_model = NULL;
4158
4159 srand(time(NULL));
4160
4161 qemu_add_opts(&qemu_trace_opts);
4162
4163 optind = parse_args(argc, argv);
4164
4165 if (!trace_init_backends()) {
4166 exit(1);
4167 }
4168 trace_init_file(trace_file);
4169
4170 /* Zero out regs */
4171 memset(regs, 0, sizeof(struct target_pt_regs));
4172
4173 /* Zero out image_info */
4174 memset(info, 0, sizeof(struct image_info));
4175
4176 memset(&bprm, 0, sizeof (bprm));
4177
4178 /* Scan interp_prefix dir for replacement files. */
4179 init_paths(interp_prefix);
4180
4181 init_qemu_uname_release();
4182
4183 if (cpu_model == NULL) {
4184 #if defined(TARGET_I386)
4185 #ifdef TARGET_X86_64
4186 cpu_model = "qemu64";
4187 #else
4188 cpu_model = "qemu32";
4189 #endif
4190 #elif defined(TARGET_ARM)
4191 cpu_model = "any";
4192 #elif defined(TARGET_UNICORE32)
4193 cpu_model = "any";
4194 #elif defined(TARGET_M68K)
4195 cpu_model = "any";
4196 #elif defined(TARGET_SPARC)
4197 #ifdef TARGET_SPARC64
4198 cpu_model = "TI UltraSparc II";
4199 #else
4200 cpu_model = "Fujitsu MB86904";
4201 #endif
4202 #elif defined(TARGET_MIPS)
4203 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
4204 cpu_model = "5KEf";
4205 #else
4206 cpu_model = "24Kf";
4207 #endif
4208 #elif defined TARGET_OPENRISC
4209 cpu_model = "or1200";
4210 #elif defined(TARGET_PPC)
4211 # ifdef TARGET_PPC64
4212 cpu_model = "POWER8";
4213 # else
4214 cpu_model = "750";
4215 # endif
4216 #elif defined TARGET_SH4
4217 cpu_model = TYPE_SH7785_CPU;
4218 #else
4219 cpu_model = "any";
4220 #endif
4221 }
4222 tcg_exec_init(0);
4223 /* NOTE: we need to init the CPU at this stage to get
4224 qemu_host_page_size */
4225 cpu = cpu_init(cpu_model);
4226 if (!cpu) {
4227 fprintf(stderr, "Unable to find CPU definition\n");
4228 exit(EXIT_FAILURE);
4229 }
4230 env = cpu->env_ptr;
4231 cpu_reset(cpu);
4232
4233 thread_cpu = cpu;
4234
4235 if (getenv("QEMU_STRACE")) {
4236 do_strace = 1;
4237 }
4238
4239 if (getenv("QEMU_RAND_SEED")) {
4240 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
4241 }
4242
4243 target_environ = envlist_to_environ(envlist, NULL);
4244 envlist_free(envlist);
4245
4246 /*
4247 * Now that page sizes are configured in cpu_init() we can do
4248 * proper page alignment for guest_base.
4249 */
4250 guest_base = HOST_PAGE_ALIGN(guest_base);
4251
4252 if (reserved_va || have_guest_base) {
4253 guest_base = init_guest_space(guest_base, reserved_va, 0,
4254 have_guest_base);
4255 if (guest_base == (unsigned long)-1) {
4256 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
4257 "space for use as guest address space (check your virtual "
4258 "memory ulimit setting or reserve less using -R option)\n",
4259 reserved_va);
4260 exit(EXIT_FAILURE);
4261 }
4262
4263 if (reserved_va) {
4264 mmap_next_start = reserved_va;
4265 }
4266 }
4267
4268 /*
4269 * Read in mmap_min_addr kernel parameter. This value is used
4270 * When loading the ELF image to determine whether guest_base
4271 * is needed. It is also used in mmap_find_vma.
4272 */
4273 {
4274 FILE *fp;
4275
4276 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
4277 unsigned long tmp;
4278 if (fscanf(fp, "%lu", &tmp) == 1) {
4279 mmap_min_addr = tmp;
4280 qemu_log_mask(CPU_LOG_PAGE, "host mmap_min_addr=0x%lx\n", mmap_min_addr);
4281 }
4282 fclose(fp);
4283 }
4284 }
4285
4286 /*
4287 * Prepare copy of argv vector for target.
4288 */
4289 target_argc = argc - optind;
4290 target_argv = calloc(target_argc + 1, sizeof (char *));
4291 if (target_argv == NULL) {
4292 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
4293 exit(EXIT_FAILURE);
4294 }
4295
4296 /*
4297 * If argv0 is specified (using '-0' switch) we replace
4298 * argv[0] pointer with the given one.
4299 */
4300 i = 0;
4301 if (argv0 != NULL) {
4302 target_argv[i++] = strdup(argv0);
4303 }
4304 for (; i < target_argc; i++) {
4305 target_argv[i] = strdup(argv[optind + i]);
4306 }
4307 target_argv[target_argc] = NULL;
4308
4309 ts = g_new0(TaskState, 1);
4310 init_task_state(ts);
4311 /* build Task State */
4312 ts->info = info;
4313 ts->bprm = &bprm;
4314 cpu->opaque = ts;
4315 task_settid(ts);
4316
4317 execfd = qemu_getauxval(AT_EXECFD);
4318 if (execfd == 0) {
4319 execfd = open(filename, O_RDONLY);
4320 if (execfd < 0) {
4321 printf("Error while loading %s: %s\n", filename, strerror(errno));
4322 _exit(EXIT_FAILURE);
4323 }
4324 }
4325
4326 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4327 info, &bprm);
4328 if (ret != 0) {
4329 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4330 _exit(EXIT_FAILURE);
4331 }
4332
4333 for (wrk = target_environ; *wrk; wrk++) {
4334 free(*wrk);
4335 }
4336
4337 free(target_environ);
4338
4339 if (qemu_loglevel_mask(CPU_LOG_PAGE)) {
4340 qemu_log("guest_base 0x%lx\n", guest_base);
4341 log_page_dump();
4342
4343 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4344 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4345 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n", info->start_code);
4346 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n", info->start_data);
4347 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4348 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n", info->start_stack);
4349 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4350 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4351 qemu_log("argv_start 0x" TARGET_ABI_FMT_lx "\n", info->arg_start);
4352 qemu_log("env_start 0x" TARGET_ABI_FMT_lx "\n",
4353 info->arg_end + (abi_ulong)sizeof(abi_ulong));
4354 qemu_log("auxv_start 0x" TARGET_ABI_FMT_lx "\n", info->saved_auxv);
4355 }
4356
4357 target_set_brk(info->brk);
4358 syscall_init();
4359 signal_init();
4360
4361 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4362 generating the prologue until now so that the prologue can take
4363 the real value of GUEST_BASE into account. */
4364 tcg_prologue_init(&tcg_ctx);
4365
4366 #if defined(TARGET_I386)
4367 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4368 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4369 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4370 env->cr[4] |= CR4_OSFXSR_MASK;
4371 env->hflags |= HF_OSFXSR_MASK;
4372 }
4373 #ifndef TARGET_ABI32
4374 /* enable 64 bit mode if possible */
4375 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4376 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4377 exit(EXIT_FAILURE);
4378 }
4379 env->cr[4] |= CR4_PAE_MASK;
4380 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4381 env->hflags |= HF_LMA_MASK;
4382 #endif
4383
4384 /* flags setup : we activate the IRQs by default as in user mode */
4385 env->eflags |= IF_MASK;
4386
4387 /* linux register setup */
4388 #ifndef TARGET_ABI32
4389 env->regs[R_EAX] = regs->rax;
4390 env->regs[R_EBX] = regs->rbx;
4391 env->regs[R_ECX] = regs->rcx;
4392 env->regs[R_EDX] = regs->rdx;
4393 env->regs[R_ESI] = regs->rsi;
4394 env->regs[R_EDI] = regs->rdi;
4395 env->regs[R_EBP] = regs->rbp;
4396 env->regs[R_ESP] = regs->rsp;
4397 env->eip = regs->rip;
4398 #else
4399 env->regs[R_EAX] = regs->eax;
4400 env->regs[R_EBX] = regs->ebx;
4401 env->regs[R_ECX] = regs->ecx;
4402 env->regs[R_EDX] = regs->edx;
4403 env->regs[R_ESI] = regs->esi;
4404 env->regs[R_EDI] = regs->edi;
4405 env->regs[R_EBP] = regs->ebp;
4406 env->regs[R_ESP] = regs->esp;
4407 env->eip = regs->eip;
4408 #endif
4409
4410 /* linux interrupt setup */
4411 #ifndef TARGET_ABI32
4412 env->idt.limit = 511;
4413 #else
4414 env->idt.limit = 255;
4415 #endif
4416 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4417 PROT_READ|PROT_WRITE,
4418 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4419 idt_table = g2h(env->idt.base);
4420 set_idt(0, 0);
4421 set_idt(1, 0);
4422 set_idt(2, 0);
4423 set_idt(3, 3);
4424 set_idt(4, 3);
4425 set_idt(5, 0);
4426 set_idt(6, 0);
4427 set_idt(7, 0);
4428 set_idt(8, 0);
4429 set_idt(9, 0);
4430 set_idt(10, 0);
4431 set_idt(11, 0);
4432 set_idt(12, 0);
4433 set_idt(13, 0);
4434 set_idt(14, 0);
4435 set_idt(15, 0);
4436 set_idt(16, 0);
4437 set_idt(17, 0);
4438 set_idt(18, 0);
4439 set_idt(19, 0);
4440 set_idt(0x80, 3);
4441
4442 /* linux segment setup */
4443 {
4444 uint64_t *gdt_table;
4445 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4446 PROT_READ|PROT_WRITE,
4447 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4448 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4449 gdt_table = g2h(env->gdt.base);
4450 #ifdef TARGET_ABI32
4451 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4452 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4453 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4454 #else
4455 /* 64 bit code segment */
4456 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4457 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4458 DESC_L_MASK |
4459 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4460 #endif
4461 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4462 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4463 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4464 }
4465 cpu_x86_load_seg(env, R_CS, __USER_CS);
4466 cpu_x86_load_seg(env, R_SS, __USER_DS);
4467 #ifdef TARGET_ABI32
4468 cpu_x86_load_seg(env, R_DS, __USER_DS);
4469 cpu_x86_load_seg(env, R_ES, __USER_DS);
4470 cpu_x86_load_seg(env, R_FS, __USER_DS);
4471 cpu_x86_load_seg(env, R_GS, __USER_DS);
4472 /* This hack makes Wine work... */
4473 env->segs[R_FS].selector = 0;
4474 #else
4475 cpu_x86_load_seg(env, R_DS, 0);
4476 cpu_x86_load_seg(env, R_ES, 0);
4477 cpu_x86_load_seg(env, R_FS, 0);
4478 cpu_x86_load_seg(env, R_GS, 0);
4479 #endif
4480 #elif defined(TARGET_AARCH64)
4481 {
4482 int i;
4483
4484 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4485 fprintf(stderr,
4486 "The selected ARM CPU does not support 64 bit mode\n");
4487 exit(EXIT_FAILURE);
4488 }
4489
4490 for (i = 0; i < 31; i++) {
4491 env->xregs[i] = regs->regs[i];
4492 }
4493 env->pc = regs->pc;
4494 env->xregs[31] = regs->sp;
4495 }
4496 #elif defined(TARGET_ARM)
4497 {
4498 int i;
4499 cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
4500 CPSRWriteByInstr);
4501 for(i = 0; i < 16; i++) {
4502 env->regs[i] = regs->uregs[i];
4503 }
4504 #ifdef TARGET_WORDS_BIGENDIAN
4505 /* Enable BE8. */
4506 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4507 && (info->elf_flags & EF_ARM_BE8)) {
4508 env->uncached_cpsr |= CPSR_E;
4509 env->cp15.sctlr_el[1] |= SCTLR_E0E;
4510 } else {
4511 env->cp15.sctlr_el[1] |= SCTLR_B;
4512 }
4513 #endif
4514 }
4515 #elif defined(TARGET_UNICORE32)
4516 {
4517 int i;
4518 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4519 for (i = 0; i < 32; i++) {
4520 env->regs[i] = regs->uregs[i];
4521 }
4522 }
4523 #elif defined(TARGET_SPARC)
4524 {
4525 int i;
4526 env->pc = regs->pc;
4527 env->npc = regs->npc;
4528 env->y = regs->y;
4529 for(i = 0; i < 8; i++)
4530 env->gregs[i] = regs->u_regs[i];
4531 for(i = 0; i < 8; i++)
4532 env->regwptr[i] = regs->u_regs[i + 8];
4533 }
4534 #elif defined(TARGET_PPC)
4535 {
4536 int i;
4537
4538 #if defined(TARGET_PPC64)
4539 int flag = (env->insns_flags2 & PPC2_BOOKE206) ? MSR_CM : MSR_SF;
4540 #if defined(TARGET_ABI32)
4541 env->msr &= ~((target_ulong)1 << flag);
4542 #else
4543 env->msr |= (target_ulong)1 << flag;
4544 #endif
4545 #endif
4546 env->nip = regs->nip;
4547 for(i = 0; i < 32; i++) {
4548 env->gpr[i] = regs->gpr[i];
4549 }
4550 }
4551 #elif defined(TARGET_M68K)
4552 {
4553 env->pc = regs->pc;
4554 env->dregs[0] = regs->d0;
4555 env->dregs[1] = regs->d1;
4556 env->dregs[2] = regs->d2;
4557 env->dregs[3] = regs->d3;
4558 env->dregs[4] = regs->d4;
4559 env->dregs[5] = regs->d5;
4560 env->dregs[6] = regs->d6;
4561 env->dregs[7] = regs->d7;
4562 env->aregs[0] = regs->a0;
4563 env->aregs[1] = regs->a1;
4564 env->aregs[2] = regs->a2;
4565 env->aregs[3] = regs->a3;
4566 env->aregs[4] = regs->a4;
4567 env->aregs[5] = regs->a5;
4568 env->aregs[6] = regs->a6;
4569 env->aregs[7] = regs->usp;
4570 env->sr = regs->sr;
4571 ts->sim_syscalls = 1;
4572 }
4573 #elif defined(TARGET_MICROBLAZE)
4574 {
4575 env->regs[0] = regs->r0;
4576 env->regs[1] = regs->r1;
4577 env->regs[2] = regs->r2;
4578 env->regs[3] = regs->r3;
4579 env->regs[4] = regs->r4;
4580 env->regs[5] = regs->r5;
4581 env->regs[6] = regs->r6;
4582 env->regs[7] = regs->r7;
4583 env->regs[8] = regs->r8;
4584 env->regs[9] = regs->r9;
4585 env->regs[10] = regs->r10;
4586 env->regs[11] = regs->r11;
4587 env->regs[12] = regs->r12;
4588 env->regs[13] = regs->r13;
4589 env->regs[14] = regs->r14;
4590 env->regs[15] = regs->r15;
4591 env->regs[16] = regs->r16;
4592 env->regs[17] = regs->r17;
4593 env->regs[18] = regs->r18;
4594 env->regs[19] = regs->r19;
4595 env->regs[20] = regs->r20;
4596 env->regs[21] = regs->r21;
4597 env->regs[22] = regs->r22;
4598 env->regs[23] = regs->r23;
4599 env->regs[24] = regs->r24;
4600 env->regs[25] = regs->r25;
4601 env->regs[26] = regs->r26;
4602 env->regs[27] = regs->r27;
4603 env->regs[28] = regs->r28;
4604 env->regs[29] = regs->r29;
4605 env->regs[30] = regs->r30;
4606 env->regs[31] = regs->r31;
4607 env->sregs[SR_PC] = regs->pc;
4608 }
4609 #elif defined(TARGET_MIPS)
4610 {
4611 int i;
4612
4613 for(i = 0; i < 32; i++) {
4614 env->active_tc.gpr[i] = regs->regs[i];
4615 }
4616 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4617 if (regs->cp0_epc & 1) {
4618 env->hflags |= MIPS_HFLAG_M16;
4619 }
4620 if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
4621 ((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
4622 if ((env->active_fpu.fcr31_rw_bitmask &
4623 (1 << FCR31_NAN2008)) == 0) {
4624 fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
4625 exit(1);
4626 }
4627 if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
4628 env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
4629 } else {
4630 env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
4631 }
4632 restore_snan_bit_mode(env);
4633 }
4634 }
4635 #elif defined(TARGET_OPENRISC)
4636 {
4637 int i;
4638
4639 for (i = 0; i < 32; i++) {
4640 env->gpr[i] = regs->gpr[i];
4641 }
4642
4643 env->sr = regs->sr;
4644 env->pc = regs->pc;
4645 }
4646 #elif defined(TARGET_SH4)
4647 {
4648 int i;
4649
4650 for(i = 0; i < 16; i++) {
4651 env->gregs[i] = regs->regs[i];
4652 }
4653 env->pc = regs->pc;
4654 }
4655 #elif defined(TARGET_ALPHA)
4656 {
4657 int i;
4658
4659 for(i = 0; i < 28; i++) {
4660 env->ir[i] = ((abi_ulong *)regs)[i];
4661 }
4662 env->ir[IR_SP] = regs->usp;
4663 env->pc = regs->pc;
4664 }
4665 #elif defined(TARGET_CRIS)
4666 {
4667 env->regs[0] = regs->r0;
4668 env->regs[1] = regs->r1;
4669 env->regs[2] = regs->r2;
4670 env->regs[3] = regs->r3;
4671 env->regs[4] = regs->r4;
4672 env->regs[5] = regs->r5;
4673 env->regs[6] = regs->r6;
4674 env->regs[7] = regs->r7;
4675 env->regs[8] = regs->r8;
4676 env->regs[9] = regs->r9;
4677 env->regs[10] = regs->r10;
4678 env->regs[11] = regs->r11;
4679 env->regs[12] = regs->r12;
4680 env->regs[13] = regs->r13;
4681 env->regs[14] = info->start_stack;
4682 env->regs[15] = regs->acr;
4683 env->pc = regs->erp;
4684 }
4685 #elif defined(TARGET_S390X)
4686 {
4687 int i;
4688 for (i = 0; i < 16; i++) {
4689 env->regs[i] = regs->gprs[i];
4690 }
4691 env->psw.mask = regs->psw.mask;
4692 env->psw.addr = regs->psw.addr;
4693 }
4694 #elif defined(TARGET_TILEGX)
4695 {
4696 int i;
4697 for (i = 0; i < TILEGX_R_COUNT; i++) {
4698 env->regs[i] = regs->regs[i];
4699 }
4700 for (i = 0; i < TILEGX_SPR_COUNT; i++) {
4701 env->spregs[i] = 0;
4702 }
4703 env->pc = regs->pc;
4704 }
4705 #elif defined(TARGET_HPPA)
4706 {
4707 int i;
4708 for (i = 1; i < 32; i++) {
4709 env->gr[i] = regs->gr[i];
4710 }
4711 env->iaoq_f = regs->iaoq[0];
4712 env->iaoq_b = regs->iaoq[1];
4713 }
4714 #else
4715 #error unsupported target CPU
4716 #endif
4717
4718 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4719 ts->stack_base = info->start_stack;
4720 ts->heap_base = info->brk;
4721 /* This will be filled in on the first SYS_HEAPINFO call. */
4722 ts->heap_limit = 0;
4723 #endif
4724
4725 if (gdbstub_port) {
4726 if (gdbserver_start(gdbstub_port) < 0) {
4727 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4728 gdbstub_port);
4729 exit(EXIT_FAILURE);
4730 }
4731 gdb_handlesig(cpu, 0);
4732 }
4733 cpu_loop(env);
4734 /* never exits */
4735 return 0;
4736 }
AR7 emulation for QEMU