target/i386/gdbstub.c

   1 /*
   2  * x86 gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qemu-common.h"
  22 #include "cpu.h"
  23 #include "exec/gdbstub.h"
  24
  25 #ifdef TARGET_X86_64
  26 static const int gpr_map[16] = {
  27     R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
  28     8, 9, 10, 11, 12, 13, 14, 15
  29 };
  30 #else
  31 #define gpr_map gpr_map32
  32 #endif
  33 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
  34
  35 #define IDX_IP_REG      CPU_NB_REGS
  36 #define IDX_FLAGS_REG   (IDX_IP_REG + 1)
  37 #define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
  38 #define IDX_FP_REGS     (IDX_SEG_REGS + 6)
  39 #define IDX_XMM_REGS    (IDX_FP_REGS + 16)
  40 #define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)
  41
  42 int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
  43 {
  44     X86CPU *cpu = X86_CPU(cs);
  45     CPUX86State *env = &cpu->env;
  46
  47     /* N.B. GDB can't deal with changes in registers or sizes in the middle
  48        of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
  49        as if we're on a 64-bit cpu. */
  50
  51     if (n < CPU_NB_REGS) {
  52         if (TARGET_LONG_BITS == 64) {
  53             if (env->hflags & HF_CS64_MASK) {
  54                 return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
  55             } else if (n < CPU_NB_REGS32) {
  56                 return gdb_get_reg64(mem_buf,
  57                                      env->regs[gpr_map[n]] & 0xffffffffUL);
  58             } else {
  59                 memset(mem_buf, 0, sizeof(target_ulong));
  60                 return sizeof(target_ulong);
  61             }
  62         } else {
  63             return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
  64         }
  65     } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
  66 #ifdef USE_X86LDOUBLE
  67         /* FIXME: byteswap float values - after fixing fpregs layout. */
  68         memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
  69 #else
  70         memset(mem_buf, 0, 10);
  71 #endif
  72         return 10;
  73     } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
  74         n -= IDX_XMM_REGS;
  75         if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
  76             stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
  77             stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
  78             return 16;
  79         }
  80     } else {
  81         switch (n) {
  82         case IDX_IP_REG:
  83             if (TARGET_LONG_BITS == 64) {
  84                 if (env->hflags & HF_CS64_MASK) {
  85                     return gdb_get_reg64(mem_buf, env->eip);
  86                 } else {
  87                     return gdb_get_reg64(mem_buf, env->eip & 0xffffffffUL);
  88                 }
  89             } else {
  90                 return gdb_get_reg32(mem_buf, env->eip);
  91             }
  92         case IDX_FLAGS_REG:
  93             return gdb_get_reg32(mem_buf, env->eflags);
  94
  95         case IDX_SEG_REGS:
  96             return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
  97         case IDX_SEG_REGS + 1:
  98             return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
  99         case IDX_SEG_REGS + 2:
 100             return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
 101         case IDX_SEG_REGS + 3:
 102             return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
 103         case IDX_SEG_REGS + 4:
 104             return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
 105         case IDX_SEG_REGS + 5:
 106             return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
 107
 108         case IDX_FP_REGS + 8:
 109             return gdb_get_reg32(mem_buf, env->fpuc);
 110         case IDX_FP_REGS + 9:
 111             return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
 112                                           (env->fpstt & 0x7) << 11);
 113         case IDX_FP_REGS + 10:
 114             return gdb_get_reg32(mem_buf, 0); /* ftag */
 115         case IDX_FP_REGS + 11:
 116             return gdb_get_reg32(mem_buf, 0); /* fiseg */
 117         case IDX_FP_REGS + 12:
 118             return gdb_get_reg32(mem_buf, 0); /* fioff */
 119         case IDX_FP_REGS + 13:
 120             return gdb_get_reg32(mem_buf, 0); /* foseg */
 121         case IDX_FP_REGS + 14:
 122             return gdb_get_reg32(mem_buf, 0); /* fooff */
 123         case IDX_FP_REGS + 15:
 124             return gdb_get_reg32(mem_buf, 0); /* fop */
 125
 126         case IDX_MXCSR_REG:
 127             return gdb_get_reg32(mem_buf, env->mxcsr);
 128         }
 129     }
 130     return 0;
 131 }
 132
 133 static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf)
 134 {
 135     CPUX86State *env = &cpu->env;
 136     uint16_t selector = ldl_p(mem_buf);
 137
 138     if (selector != env->segs[sreg].selector) {
 139 #if defined(CONFIG_USER_ONLY)
 140         cpu_x86_load_seg(env, sreg, selector);
 141 #else
 142         unsigned int limit, flags;
 143         target_ulong base;
 144
 145         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 146             int dpl = (env->eflags & VM_MASK) ? 3 : 0;
 147             base = selector << 4;
 148             limit = 0xffff;
 149             flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 150                     DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
 151         } else {
 152             if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
 153                                          &flags)) {
 154                 return 4;
 155             }
 156         }
 157         cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
 158 #endif
 159     }
 160     return 4;
 161 }
 162
 163 int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 164 {
 165     X86CPU *cpu = X86_CPU(cs);
 166     CPUX86State *env = &cpu->env;
 167     uint32_t tmp;
 168
 169     /* N.B. GDB can't deal with changes in registers or sizes in the middle
 170        of a session. So if we're in 32-bit mode on a 64-bit cpu, still act
 171        as if we're on a 64-bit cpu. */
 172
 173     if (n < CPU_NB_REGS) {
 174         if (TARGET_LONG_BITS == 64) {
 175             if (env->hflags & HF_CS64_MASK) {
 176                 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
 177             } else if (n < CPU_NB_REGS32) {
 178                 env->regs[gpr_map[n]] = ldtul_p(mem_buf) & 0xffffffffUL;
 179             }
 180             return sizeof(target_ulong);
 181         } else if (n < CPU_NB_REGS32) {
 182             n = gpr_map32[n];
 183             env->regs[n] &= ~0xffffffffUL;
 184             env->regs[n] |= (uint32_t)ldl_p(mem_buf);
 185             return 4;
 186         }
 187     } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 188 #ifdef USE_X86LDOUBLE
 189         /* FIXME: byteswap float values - after fixing fpregs layout. */
 190         memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
 191 #endif
 192         return 10;
 193     } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 194         n -= IDX_XMM_REGS;
 195         if (n < CPU_NB_REGS32 || TARGET_LONG_BITS == 64) {
 196             env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
 197             env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
 198             return 16;
 199         }
 200     } else {
 201         switch (n) {
 202         case IDX_IP_REG:
 203             if (TARGET_LONG_BITS == 64) {
 204                 if (env->hflags & HF_CS64_MASK) {
 205                     env->eip = ldq_p(mem_buf);
 206                 } else {
 207                     env->eip = ldq_p(mem_buf) & 0xffffffffUL;
 208                 }
 209                 return 8;
 210             } else {
 211                 env->eip &= ~0xffffffffUL;
 212                 env->eip |= (uint32_t)ldl_p(mem_buf);
 213                 return 4;
 214             }
 215         case IDX_FLAGS_REG:
 216             env->eflags = ldl_p(mem_buf);
 217             return 4;
 218
 219         case IDX_SEG_REGS:
 220             return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
 221         case IDX_SEG_REGS + 1:
 222             return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
 223         case IDX_SEG_REGS + 2:
 224             return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
 225         case IDX_SEG_REGS + 3:
 226             return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
 227         case IDX_SEG_REGS + 4:
 228             return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
 229         case IDX_SEG_REGS + 5:
 230             return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
 231
 232         case IDX_FP_REGS + 8:
 233             cpu_set_fpuc(env, ldl_p(mem_buf));
 234             return 4;
 235         case IDX_FP_REGS + 9:
 236             tmp = ldl_p(mem_buf);
 237             env->fpstt = (tmp >> 11) & 7;
 238             env->fpus = tmp & ~0x3800;
 239             return 4;
 240         case IDX_FP_REGS + 10: /* ftag */
 241             return 4;
 242         case IDX_FP_REGS + 11: /* fiseg */
 243             return 4;
 244         case IDX_FP_REGS + 12: /* fioff */
 245             return 4;
 246         case IDX_FP_REGS + 13: /* foseg */
 247             return 4;
 248         case IDX_FP_REGS + 14: /* fooff */
 249             return 4;
 250         case IDX_FP_REGS + 15: /* fop */
 251             return 4;
 252
 253         case IDX_MXCSR_REG:
 254             cpu_set_mxcsr(env, ldl_p(mem_buf));
 255             return 4;
 256         }
 257     }
 258     /* Unrecognised register.  */
 259     return 0;
 260 }