hw/s390x/s390-pci-bus.h

   1 /*
   2  * s390 PCI BUS definitions
   3  *
   4  * Copyright 2014 IBM Corp.
   5  * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com>
   6  *            Hong Bo Li <lihbbj@cn.ibm.com>
   7  *            Yi Min Zhao <zyimin@cn.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or (at
  10  * your option) any later version. See the COPYING file in the top-level
  11  * directory.
  12  */
  13
  14 #ifndef HW_S390_PCI_BUS_H
  15 #define HW_S390_PCI_BUS_H
  16
  17 #include "hw/pci/pci.h"
  18 #include "hw/pci/pci_host.h"
  19 #include "hw/s390x/sclp.h"
  20 #include "hw/s390x/s390_flic.h"
  21 #include "hw/s390x/css.h"
  22
  23 #define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
  24 #define TYPE_S390_PCI_BUS "s390-pcibus"
  25 #define TYPE_S390_PCI_DEVICE "zpci"
  26 #define TYPE_S390_PCI_IOMMU "s390-pci-iommu"
  27 #define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region"
  28 #define FH_MASK_ENABLE   0x80000000
  29 #define FH_MASK_INSTANCE 0x7f000000
  30 #define FH_MASK_SHM      0x00ff0000
  31 #define FH_MASK_INDEX    0x0000ffff
  32 #define FH_SHM_VFIO      0x00010000
  33 #define FH_SHM_EMUL      0x00020000
  34 #define ZPCI_MAX_FID 0xffffffff
  35 #define ZPCI_MAX_UID 0xffff
  36 #define UID_UNDEFINED 0
  37 #define UID_CHECKING_ENABLED 0x01
  38 #define HOT_UNPLUG_TIMEOUT (NANOSECONDS_PER_SECOND * 60 * 5)
  39
  40 #define S390_PCI_HOST_BRIDGE(obj) \
  41     OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
  42 #define S390_PCI_BUS(obj) \
  43     OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS)
  44 #define S390_PCI_DEVICE(obj) \
  45     OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE)
  46 #define S390_PCI_IOMMU(obj) \
  47     OBJECT_CHECK(S390PCIIOMMU, (obj), TYPE_S390_PCI_IOMMU)
  48
  49 #define HP_EVENT_TO_CONFIGURED        0x0301
  50 #define HP_EVENT_RESERVED_TO_STANDBY  0x0302
  51 #define HP_EVENT_DECONFIGURE_REQUEST  0x0303
  52 #define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
  53 #define HP_EVENT_STANDBY_TO_RESERVED  0x0308
  54
  55 #define ERR_EVENT_INVALAS 0x1
  56 #define ERR_EVENT_OORANGE 0x2
  57 #define ERR_EVENT_INVALTF 0x3
  58 #define ERR_EVENT_TPROTE  0x4
  59 #define ERR_EVENT_APROTE  0x5
  60 #define ERR_EVENT_KEYE    0x6
  61 #define ERR_EVENT_INVALTE 0x7
  62 #define ERR_EVENT_INVALTL 0x8
  63 #define ERR_EVENT_TT      0x9
  64 #define ERR_EVENT_INVALMS 0xa
  65 #define ERR_EVENT_SERR    0xb
  66 #define ERR_EVENT_NOMSI   0x10
  67 #define ERR_EVENT_INVALBV 0x11
  68 #define ERR_EVENT_AIBV    0x12
  69 #define ERR_EVENT_AIRERR  0x13
  70 #define ERR_EVENT_FMBA    0x2a
  71 #define ERR_EVENT_FMBUP   0x2b
  72 #define ERR_EVENT_FMBPRO  0x2c
  73 #define ERR_EVENT_CCONF   0x30
  74 #define ERR_EVENT_SERVAC  0x3a
  75 #define ERR_EVENT_PERMERR 0x3b
  76
  77 #define ERR_EVENT_Q_BIT 0x2
  78 #define ERR_EVENT_MVN_OFFSET 16
  79
  80 #define ZPCI_MSI_VEC_BITS 11
  81 #define ZPCI_MSI_VEC_MASK 0x7ff
  82
  83 #define ZPCI_MSI_ADDR  0xfe00000000000000ULL
  84 #define ZPCI_SDMA_ADDR 0x100000000ULL
  85 #define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
  86
  87 #define PAGE_SHIFT      12
  88 #define PAGE_SIZE       (1 << PAGE_SHIFT)
  89 #define PAGE_MASK       (~(PAGE_SIZE-1))
  90 #define PAGE_DEFAULT_ACC        0
  91 #define PAGE_DEFAULT_KEY        (PAGE_DEFAULT_ACC << 4)
  92
  93 /* I/O Translation Anchor (IOTA) */
  94 enum ZpciIoatDtype {
  95     ZPCI_IOTA_STO = 0,
  96     ZPCI_IOTA_RTTO = 1,
  97     ZPCI_IOTA_RSTO = 2,
  98     ZPCI_IOTA_RFTO = 3,
  99     ZPCI_IOTA_PFAA = 4,
 100     ZPCI_IOTA_IOPFAA = 5,
 101     ZPCI_IOTA_IOPTO = 7
 102 };
 103
 104 #define ZPCI_IOTA_IOT_ENABLED           0x800ULL
 105 #define ZPCI_IOTA_DT_ST                 (ZPCI_IOTA_STO  << 2)
 106 #define ZPCI_IOTA_DT_RT                 (ZPCI_IOTA_RTTO << 2)
 107 #define ZPCI_IOTA_DT_RS                 (ZPCI_IOTA_RSTO << 2)
 108 #define ZPCI_IOTA_DT_RF                 (ZPCI_IOTA_RFTO << 2)
 109 #define ZPCI_IOTA_DT_PF                 (ZPCI_IOTA_PFAA << 2)
 110 #define ZPCI_IOTA_FS_4K                 0
 111 #define ZPCI_IOTA_FS_1M                 1
 112 #define ZPCI_IOTA_FS_2G                 2
 113 #define ZPCI_KEY                        (PAGE_DEFAULT_KEY << 5)
 114
 115 #define ZPCI_IOTA_STO_FLAG  (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
 116 #define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
 117 #define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
 118 #define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
 119 #define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
 120                              ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
 121
 122 /* I/O Region and segment tables */
 123 #define ZPCI_INDEX_MASK         0x7ffULL
 124
 125 #define ZPCI_TABLE_TYPE_MASK    0xc
 126 #define ZPCI_TABLE_TYPE_RFX     0xc
 127 #define ZPCI_TABLE_TYPE_RSX     0x8
 128 #define ZPCI_TABLE_TYPE_RTX     0x4
 129 #define ZPCI_TABLE_TYPE_SX      0x0
 130
 131 #define ZPCI_TABLE_LEN_RFX      0x3
 132 #define ZPCI_TABLE_LEN_RSX      0x3
 133 #define ZPCI_TABLE_LEN_RTX      0x3
 134
 135 #define ZPCI_TABLE_OFFSET_MASK  0xc0
 136 #define ZPCI_TABLE_SIZE         0x4000
 137 #define ZPCI_TABLE_ALIGN        ZPCI_TABLE_SIZE
 138 #define ZPCI_TABLE_ENTRY_SIZE   (sizeof(unsigned long))
 139 #define ZPCI_TABLE_ENTRIES      (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
 140
 141 #define ZPCI_TABLE_BITS         11
 142 #define ZPCI_PT_BITS            8
 143 #define ZPCI_ST_SHIFT           (ZPCI_PT_BITS + PAGE_SHIFT)
 144 #define ZPCI_RT_SHIFT           (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
 145
 146 #define ZPCI_RTE_FLAG_MASK      0x3fffULL
 147 #define ZPCI_RTE_ADDR_MASK      (~ZPCI_RTE_FLAG_MASK)
 148 #define ZPCI_STE_FLAG_MASK      0x7ffULL
 149 #define ZPCI_STE_ADDR_MASK      (~ZPCI_STE_FLAG_MASK)
 150
 151 /* I/O Page tables */
 152 #define ZPCI_PTE_VALID_MASK             0x400
 153 #define ZPCI_PTE_INVALID                0x400
 154 #define ZPCI_PTE_VALID                  0x000
 155 #define ZPCI_PT_SIZE                    0x800
 156 #define ZPCI_PT_ALIGN                   ZPCI_PT_SIZE
 157 #define ZPCI_PT_ENTRIES                 (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
 158 #define ZPCI_PT_MASK                    (ZPCI_PT_ENTRIES - 1)
 159
 160 #define ZPCI_PTE_FLAG_MASK              0xfffULL
 161 #define ZPCI_PTE_ADDR_MASK              (~ZPCI_PTE_FLAG_MASK)
 162
 163 /* Shared bits */
 164 #define ZPCI_TABLE_VALID                0x00
 165 #define ZPCI_TABLE_INVALID              0x20
 166 #define ZPCI_TABLE_PROTECTED            0x200
 167 #define ZPCI_TABLE_UNPROTECTED          0x000
 168
 169 #define ZPCI_TABLE_VALID_MASK           0x20
 170 #define ZPCI_TABLE_PROT_MASK            0x200
 171
 172 /* PCI Function States
 173  *
 174  * reserved: default; device has just been plugged or is in progress of being
 175  *           unplugged
 176  * standby: device is present but not configured; transition from any
 177  *          configured state/to this state via sclp configure/deconfigure
 178  *
 179  * The following states make up the "configured" meta-state:
 180  * disabled: device is configured but not enabled; transition between this
 181  *           state and enabled via clp enable/disable
 182  * enbaled: device is ready for use; transition to disabled via clp disable;
 183  *          may enter an error state
 184  * blocked: ignore all DMA and interrupts; transition back to enabled or from
 185  *          error state via mpcifc
 186  * error: an error occurred; transition back to enabled via mpcifc
 187  * permanent error: an unrecoverable error occurred; transition to standby via
 188  *                  sclp deconfigure
 189  */
 190 typedef enum {
 191     ZPCI_FS_RESERVED,
 192     ZPCI_FS_STANDBY,
 193     ZPCI_FS_DISABLED,
 194     ZPCI_FS_ENABLED,
 195     ZPCI_FS_BLOCKED,
 196     ZPCI_FS_ERROR,
 197     ZPCI_FS_PERMANENT_ERROR,
 198 } ZpciState;
 199
 200 typedef struct SeiContainer {
 201     QTAILQ_ENTRY(SeiContainer) link;
 202     uint32_t fid;
 203     uint32_t fh;
 204     uint8_t cc;
 205     uint16_t pec;
 206     uint64_t faddr;
 207     uint32_t e;
 208 } SeiContainer;
 209
 210 typedef struct PciCcdfErr {
 211     uint32_t reserved1;
 212     uint32_t fh;
 213     uint32_t fid;
 214     uint32_t e;
 215     uint64_t faddr;
 216     uint32_t reserved3;
 217     uint16_t reserved4;
 218     uint16_t pec;
 219 } QEMU_PACKED PciCcdfErr;
 220
 221 typedef struct PciCcdfAvail {
 222     uint32_t reserved1;
 223     uint32_t fh;
 224     uint32_t fid;
 225     uint32_t reserved2;
 226     uint32_t reserved3;
 227     uint32_t reserved4;
 228     uint32_t reserved5;
 229     uint16_t reserved6;
 230     uint16_t pec;
 231 } QEMU_PACKED PciCcdfAvail;
 232
 233 typedef struct ChscSeiNt2Res {
 234     uint16_t length;
 235     uint16_t code;
 236     uint16_t reserved1;
 237     uint8_t reserved2;
 238     uint8_t nt;
 239     uint8_t flags;
 240     uint8_t reserved3;
 241     uint8_t reserved4;
 242     uint8_t cc;
 243     uint32_t reserved5[13];
 244     uint8_t ccdf[4016];
 245 } QEMU_PACKED ChscSeiNt2Res;
 246
 247 typedef struct PciCfgSccb {
 248     SCCBHeader header;
 249     uint8_t atype;
 250     uint8_t reserved1;
 251     uint16_t reserved2;
 252     uint32_t aid;
 253 } QEMU_PACKED PciCfgSccb;
 254
 255 typedef struct S390MsixInfo {
 256     bool available;
 257     uint8_t table_bar;
 258     uint8_t pba_bar;
 259     uint16_t entries;
 260     uint32_t table_offset;
 261     uint32_t pba_offset;
 262 } S390MsixInfo;
 263
 264 typedef struct S390PCIBusDevice S390PCIBusDevice;
 265 typedef struct S390PCIIOMMU {
 266     Object parent_obj;
 267     S390PCIBusDevice *pbdev;
 268     AddressSpace as;
 269     MemoryRegion mr;
 270     IOMMUMemoryRegion iommu_mr;
 271     bool enabled;
 272     uint64_t g_iota;
 273     uint64_t pba;
 274     uint64_t pal;
 275 } S390PCIIOMMU;
 276
 277 typedef struct S390PCIIOMMUTable {
 278     uint64_t key;
 279     S390PCIIOMMU *iommu[PCI_SLOT_MAX];
 280 } S390PCIIOMMUTable;
 281
 282 struct S390PCIBusDevice {
 283     DeviceState qdev;
 284     PCIDevice *pdev;
 285     ZpciState state;
 286     char *target;
 287     uint16_t uid;
 288     uint32_t idx;
 289     uint32_t fh;
 290     uint32_t fid;
 291     bool fid_defined;
 292     uint64_t fmb_addr;
 293     uint8_t isc;
 294     uint16_t noi;
 295     uint8_t sum;
 296     S390MsixInfo msix;
 297     AdapterRoutes routes;
 298     S390PCIIOMMU *iommu;
 299     MemoryRegion msix_notify_mr;
 300     IndAddr *summary_ind;
 301     IndAddr *indicator;
 302     QEMUTimer *release_timer;
 303     QTAILQ_ENTRY(S390PCIBusDevice) link;
 304 };
 305
 306 typedef struct S390PCIBus {
 307     BusState qbus;
 308 } S390PCIBus;
 309
 310 typedef struct S390pciState {
 311     PCIHostState parent_obj;
 312     uint32_t next_idx;
 313     int bus_no;
 314     S390PCIBus *bus;
 315     GHashTable *iommu_table;
 316     GHashTable *zpci_table;
 317     QTAILQ_HEAD(, SeiContainer) pending_sei;
 318     QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs;
 319 } S390pciState;
 320
 321 S390pciState *s390_get_phb(void);
 322 int chsc_sei_nt2_get_event(void *res);
 323 int chsc_sei_nt2_have_event(void);
 324 void s390_pci_sclp_configure(SCCB *sccb);
 325 void s390_pci_sclp_deconfigure(SCCB *sccb);
 326 void s390_pci_iommu_enable(S390PCIIOMMU *iommu);
 327 void s390_pci_iommu_disable(S390PCIIOMMU *iommu);
 328 void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
 329                                    uint64_t faddr, uint32_t e);
 330 S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx);
 331 S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh);
 332 S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid);
 333 S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s,
 334                                                S390PCIBusDevice *pbdev);
 335
 336 #endif