hw/ppc/spapr_hcall.c

   1 #include "qemu/osdep.h"
   2 #include "qapi/error.h"
   3 #include "sysemu/hw_accel.h"
   4 #include "sysemu/sysemu.h"
   5 #include "qemu/log.h"
   6 #include "qemu/error-report.h"
   7 #include "cpu.h"
   8 #include "exec/exec-all.h"
   9 #include "helper_regs.h"
  10 #include "hw/ppc/spapr.h"
  11 #include "mmu-hash64.h"
  12 #include "cpu-models.h"
  13 #include "trace.h"
  14 #include "kvm_ppc.h"
  15 #include "hw/ppc/spapr_ovec.h"
  16 #include "qemu/error-report.h"
  17 #include "mmu-book3s-v3.h"
  18
  19 struct SPRSyncState {
  20     int spr;
  21     target_ulong value;
  22     target_ulong mask;
  23 };
  24
  25 static void do_spr_sync(CPUState *cs, run_on_cpu_data arg)
  26 {
  27     struct SPRSyncState *s = arg.host_ptr;
  28     PowerPCCPU *cpu = POWERPC_CPU(cs);
  29     CPUPPCState *env = &cpu->env;
  30
  31     cpu_synchronize_state(cs);
  32     env->spr[s->spr] &= ~s->mask;
  33     env->spr[s->spr] |= s->value;
  34 }
  35
  36 static void set_spr(CPUState *cs, int spr, target_ulong value,
  37                     target_ulong mask)
  38 {
  39     struct SPRSyncState s = {
  40         .spr = spr,
  41         .value = value,
  42         .mask = mask
  43     };
  44     run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s));
  45 }
  46
  47 static bool has_spr(PowerPCCPU *cpu, int spr)
  48 {
  49     /* We can test whether the SPR is defined by checking for a valid name */
  50     return cpu->env.spr_cb[spr].name != NULL;
  51 }
  52
  53 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex)
  54 {
  55     /*
  56      * hash value/pteg group index is normalized by HPT mask
  57      */
  58     if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) {
  59         return false;
  60     }
  61     return true;
  62 }
  63
  64 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr)
  65 {
  66     MachineState *machine = MACHINE(spapr);
  67     MemoryHotplugState *hpms = &spapr->hotplug_memory;
  68
  69     if (addr < machine->ram_size) {
  70         return true;
  71     }
  72     if ((addr >= hpms->base)
  73         && ((addr - hpms->base) < memory_region_size(&hpms->mr))) {
  74         return true;
  75     }
  76
  77     return false;
  78 }
  79
  80 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
  81                             target_ulong opcode, target_ulong *args)
  82 {
  83     target_ulong flags = args[0];
  84     target_ulong ptex = args[1];
  85     target_ulong pteh = args[2];
  86     target_ulong ptel = args[3];
  87     unsigned apshift;
  88     target_ulong raddr;
  89     target_ulong slot;
  90     const ppc_hash_pte64_t *hptes;
  91
  92     apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
  93     if (!apshift) {
  94         /* Bad page size encoding */
  95         return H_PARAMETER;
  96     }
  97
  98     raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
  99
 100     if (is_ram_address(spapr, raddr)) {
 101         /* Regular RAM - should have WIMG=0010 */
 102         if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
 103             return H_PARAMETER;
 104         }
 105     } else {
 106         target_ulong wimg_flags;
 107         /* Looks like an IO address */
 108         /* FIXME: What WIMG combinations could be sensible for IO?
 109          * For now we allow WIMG=010x, but are there others? */
 110         /* FIXME: Should we check against registered IO addresses? */
 111         wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M));
 112
 113         if (wimg_flags != HPTE64_R_I &&
 114             wimg_flags != (HPTE64_R_I | HPTE64_R_M)) {
 115             return H_PARAMETER;
 116         }
 117     }
 118
 119     pteh &= ~0x60ULL;
 120
 121     if (!valid_ptex(cpu, ptex)) {
 122         return H_PARAMETER;
 123     }
 124
 125     slot = ptex & 7ULL;
 126     ptex = ptex & ~7ULL;
 127
 128     if (likely((flags & H_EXACT) == 0)) {
 129         hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
 130         for (slot = 0; slot < 8; slot++) {
 131             if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) {
 132                 break;
 133             }
 134         }
 135         ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
 136         if (slot == 8) {
 137             return H_PTEG_FULL;
 138         }
 139     } else {
 140         hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1);
 141         if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) {
 142             ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1);
 143             return H_PTEG_FULL;
 144         }
 145         ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
 146     }
 147
 148     ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);
 149
 150     args[0] = ptex + slot;
 151     return H_SUCCESS;
 152 }
 153
 154 typedef enum {
 155     REMOVE_SUCCESS = 0,
 156     REMOVE_NOT_FOUND = 1,
 157     REMOVE_PARM = 2,
 158     REMOVE_HW = 3,
 159 } RemoveResult;
 160
 161 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,
 162                                 target_ulong avpn,
 163                                 target_ulong flags,
 164                                 target_ulong *vp, target_ulong *rp)
 165 {
 166     const ppc_hash_pte64_t *hptes;
 167     target_ulong v, r;
 168
 169     if (!valid_ptex(cpu, ptex)) {
 170         return REMOVE_PARM;
 171     }
 172
 173     hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
 174     v = ppc_hash64_hpte0(cpu, hptes, 0);
 175     r = ppc_hash64_hpte1(cpu, hptes, 0);
 176     ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
 177
 178     if ((v & HPTE64_V_VALID) == 0 ||
 179         ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
 180         ((flags & H_ANDCOND) && (v & avpn) != 0)) {
 181         return REMOVE_NOT_FOUND;
 182     }
 183     *vp = v;
 184     *rp = r;
 185     ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
 186     ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
 187     return REMOVE_SUCCESS;
 188 }
 189
 190 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 191                              target_ulong opcode, target_ulong *args)
 192 {
 193     CPUPPCState *env = &cpu->env;
 194     target_ulong flags = args[0];
 195     target_ulong ptex = args[1];
 196     target_ulong avpn = args[2];
 197     RemoveResult ret;
 198
 199     ret = remove_hpte(cpu, ptex, avpn, flags,
 200                       &args[0], &args[1]);
 201
 202     switch (ret) {
 203     case REMOVE_SUCCESS:
 204         check_tlb_flush(env, true);
 205         return H_SUCCESS;
 206
 207     case REMOVE_NOT_FOUND:
 208         return H_NOT_FOUND;
 209
 210     case REMOVE_PARM:
 211         return H_PARAMETER;
 212
 213     case REMOVE_HW:
 214         return H_HARDWARE;
 215     }
 216
 217     g_assert_not_reached();
 218 }
 219
 220 #define H_BULK_REMOVE_TYPE             0xc000000000000000ULL
 221 #define   H_BULK_REMOVE_REQUEST        0x4000000000000000ULL
 222 #define   H_BULK_REMOVE_RESPONSE       0x8000000000000000ULL
 223 #define   H_BULK_REMOVE_END            0xc000000000000000ULL
 224 #define H_BULK_REMOVE_CODE             0x3000000000000000ULL
 225 #define   H_BULK_REMOVE_SUCCESS        0x0000000000000000ULL
 226 #define   H_BULK_REMOVE_NOT_FOUND      0x1000000000000000ULL
 227 #define   H_BULK_REMOVE_PARM           0x2000000000000000ULL
 228 #define   H_BULK_REMOVE_HW             0x3000000000000000ULL
 229 #define H_BULK_REMOVE_RC               0x0c00000000000000ULL
 230 #define H_BULK_REMOVE_FLAGS            0x0300000000000000ULL
 231 #define   H_BULK_REMOVE_ABSOLUTE       0x0000000000000000ULL
 232 #define   H_BULK_REMOVE_ANDCOND        0x0100000000000000ULL
 233 #define   H_BULK_REMOVE_AVPN           0x0200000000000000ULL
 234 #define H_BULK_REMOVE_PTEX             0x00ffffffffffffffULL
 235
 236 #define H_BULK_REMOVE_MAX_BATCH        4
 237
 238 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 239                                   target_ulong opcode, target_ulong *args)
 240 {
 241     CPUPPCState *env = &cpu->env;
 242     int i;
 243     target_ulong rc = H_SUCCESS;
 244
 245     for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
 246         target_ulong *tsh = &args[i*2];
 247         target_ulong tsl = args[i*2 + 1];
 248         target_ulong v, r, ret;
 249
 250         if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
 251             break;
 252         } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
 253             return H_PARAMETER;
 254         }
 255
 256         *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
 257         *tsh |= H_BULK_REMOVE_RESPONSE;
 258
 259         if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
 260             *tsh |= H_BULK_REMOVE_PARM;
 261             return H_PARAMETER;
 262         }
 263
 264         ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
 265                           (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
 266                           &v, &r);
 267
 268         *tsh |= ret << 60;
 269
 270         switch (ret) {
 271         case REMOVE_SUCCESS:
 272             *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
 273             break;
 274
 275         case REMOVE_PARM:
 276             rc = H_PARAMETER;
 277             goto exit;
 278
 279         case REMOVE_HW:
 280             rc = H_HARDWARE;
 281             goto exit;
 282         }
 283     }
 284  exit:
 285     check_tlb_flush(env, true);
 286
 287     return rc;
 288 }
 289
 290 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 291                               target_ulong opcode, target_ulong *args)
 292 {
 293     CPUPPCState *env = &cpu->env;
 294     target_ulong flags = args[0];
 295     target_ulong ptex = args[1];
 296     target_ulong avpn = args[2];
 297     const ppc_hash_pte64_t *hptes;
 298     target_ulong v, r;
 299
 300     if (!valid_ptex(cpu, ptex)) {
 301         return H_PARAMETER;
 302     }
 303
 304     hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
 305     v = ppc_hash64_hpte0(cpu, hptes, 0);
 306     r = ppc_hash64_hpte1(cpu, hptes, 0);
 307     ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
 308
 309     if ((v & HPTE64_V_VALID) == 0 ||
 310         ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
 311         return H_NOT_FOUND;
 312     }
 313
 314     r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
 315            HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
 316     r |= (flags << 55) & HPTE64_R_PP0;
 317     r |= (flags << 48) & HPTE64_R_KEY_HI;
 318     r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
 319     ppc_hash64_store_hpte(cpu, ptex,
 320                           (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
 321     ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
 322     /* Flush the tlb */
 323     check_tlb_flush(env, true);
 324     /* Don't need a memory barrier, due to qemu's global lock */
 325     ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);
 326     return H_SUCCESS;
 327 }
 328
 329 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 330                            target_ulong opcode, target_ulong *args)
 331 {
 332     target_ulong flags = args[0];
 333     target_ulong ptex = args[1];
 334     uint8_t *hpte;
 335     int i, ridx, n_entries = 1;
 336
 337     if (!valid_ptex(cpu, ptex)) {
 338         return H_PARAMETER;
 339     }
 340
 341     if (flags & H_READ_4) {
 342         /* Clear the two low order bits */
 343         ptex &= ~(3ULL);
 344         n_entries = 4;
 345     }
 346
 347     hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64);
 348
 349     for (i = 0, ridx = 0; i < n_entries; i++) {
 350         args[ridx++] = ldq_p(hpte);
 351         args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
 352         hpte += HASH_PTE_SIZE_64;
 353     }
 354
 355     return H_SUCCESS;
 356 }
 357
 358 struct sPAPRPendingHPT {
 359     /* These fields are read-only after initialization */
 360     int shift;
 361     QemuThread thread;
 362
 363     /* These fields are protected by the BQL */
 364     bool complete;
 365
 366     /* These fields are private to the preparation thread if
 367      * !complete, otherwise protected by the BQL */
 368     int ret;
 369     void *hpt;
 370 };
 371
 372 static void free_pending_hpt(sPAPRPendingHPT *pending)
 373 {
 374     if (pending->hpt) {
 375         qemu_vfree(pending->hpt);
 376     }
 377
 378     g_free(pending);
 379 }
 380
 381 static void *hpt_prepare_thread(void *opaque)
 382 {
 383     sPAPRPendingHPT *pending = opaque;
 384     size_t size = 1ULL << pending->shift;
 385
 386     pending->hpt = qemu_memalign(size, size);
 387     if (pending->hpt) {
 388         memset(pending->hpt, 0, size);
 389         pending->ret = H_SUCCESS;
 390     } else {
 391         pending->ret = H_NO_MEM;
 392     }
 393
 394     qemu_mutex_lock_iothread();
 395
 396     if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) {
 397         /* Ready to go */
 398         pending->complete = true;
 399     } else {
 400         /* We've been cancelled, clean ourselves up */
 401         free_pending_hpt(pending);
 402     }
 403
 404     qemu_mutex_unlock_iothread();
 405     return NULL;
 406 }
 407
 408 /* Must be called with BQL held */
 409 static void cancel_hpt_prepare(sPAPRMachineState *spapr)
 410 {
 411     sPAPRPendingHPT *pending = spapr->pending_hpt;
 412
 413     /* Let the thread know it's cancelled */
 414     spapr->pending_hpt = NULL;
 415
 416     if (!pending) {
 417         /* Nothing to do */
 418         return;
 419     }
 420
 421     if (!pending->complete) {
 422         /* thread will clean itself up */
 423         return;
 424     }
 425
 426     free_pending_hpt(pending);
 427 }
 428
 429 /* Convert a return code from the KVM ioctl()s implementing resize HPT
 430  * into a PAPR hypercall return code */
 431 static target_ulong resize_hpt_convert_rc(int ret)
 432 {
 433     if (ret >= 100000) {
 434         return H_LONG_BUSY_ORDER_100_SEC;
 435     } else if (ret >= 10000) {
 436         return H_LONG_BUSY_ORDER_10_SEC;
 437     } else if (ret >= 1000) {
 438         return H_LONG_BUSY_ORDER_1_SEC;
 439     } else if (ret >= 100) {
 440         return H_LONG_BUSY_ORDER_100_MSEC;
 441     } else if (ret >= 10) {
 442         return H_LONG_BUSY_ORDER_10_MSEC;
 443     } else if (ret > 0) {
 444         return H_LONG_BUSY_ORDER_1_MSEC;
 445     }
 446
 447     switch (ret) {
 448     case 0:
 449         return H_SUCCESS;
 450     case -EPERM:
 451         return H_AUTHORITY;
 452     case -EINVAL:
 453         return H_PARAMETER;
 454     case -ENXIO:
 455         return H_CLOSED;
 456     case -ENOSPC:
 457         return H_PTEG_FULL;
 458     case -EBUSY:
 459         return H_BUSY;
 460     case -ENOMEM:
 461         return H_NO_MEM;
 462     default:
 463         return H_HARDWARE;
 464     }
 465 }
 466
 467 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
 468                                          sPAPRMachineState *spapr,
 469                                          target_ulong opcode,
 470                                          target_ulong *args)
 471 {
 472     target_ulong flags = args[0];
 473     int shift = args[1];
 474     sPAPRPendingHPT *pending = spapr->pending_hpt;
 475     uint64_t current_ram_size = MACHINE(spapr)->ram_size;
 476     int rc;
 477
 478     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
 479         return H_AUTHORITY;
 480     }
 481
 482     if (!spapr->htab_shift) {
 483         /* Radix guest, no HPT */
 484         return H_NOT_AVAILABLE;
 485     }
 486
 487     trace_spapr_h_resize_hpt_prepare(flags, shift);
 488
 489     if (flags != 0) {
 490         return H_PARAMETER;
 491     }
 492
 493     if (shift && ((shift < 18) || (shift > 46))) {
 494         return H_PARAMETER;
 495     }
 496
 497     current_ram_size = pc_existing_dimms_capacity(&error_fatal);
 498
 499     /* We only allow the guest to allocate an HPT one order above what
 500      * we'd normally give them (to stop a small guest claiming a huge
 501      * chunk of resources in the HPT */
 502     if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) {
 503         return H_RESOURCE;
 504     }
 505
 506     rc = kvmppc_resize_hpt_prepare(cpu, flags, shift);
 507     if (rc != -ENOSYS) {
 508         return resize_hpt_convert_rc(rc);
 509     }
 510
 511     if (pending) {
 512         /* something already in progress */
 513         if (pending->shift == shift) {
 514             /* and it's suitable */
 515             if (pending->complete) {
 516                 return pending->ret;
 517             } else {
 518                 return H_LONG_BUSY_ORDER_100_MSEC;
 519             }
 520         }
 521
 522         /* not suitable, cancel and replace */
 523         cancel_hpt_prepare(spapr);
 524     }
 525
 526     if (!shift) {
 527         /* nothing to do */
 528         return H_SUCCESS;
 529     }
 530
 531     /* start new prepare */
 532
 533     pending = g_new0(sPAPRPendingHPT, 1);
 534     pending->shift = shift;
 535     pending->ret = H_HARDWARE;
 536
 537     qemu_thread_create(&pending->thread, "sPAPR HPT prepare",
 538                        hpt_prepare_thread, pending, QEMU_THREAD_DETACHED);
 539
 540     spapr->pending_hpt = pending;
 541
 542     /* In theory we could estimate the time more accurately based on
 543      * the new size, but there's not much point */
 544     return H_LONG_BUSY_ORDER_100_MSEC;
 545 }
 546
 547 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot)
 548 {
 549     uint8_t *addr = htab;
 550
 551     addr += pteg * HASH_PTEG_SIZE_64;
 552     addr += slot * HASH_PTE_SIZE_64;
 553     return  ldq_p(addr);
 554 }
 555
 556 static void new_hpte_store(void *htab, uint64_t pteg, int slot,
 557                            uint64_t pte0, uint64_t pte1)
 558 {
 559     uint8_t *addr = htab;
 560
 561     addr += pteg * HASH_PTEG_SIZE_64;
 562     addr += slot * HASH_PTE_SIZE_64;
 563
 564     stq_p(addr, pte0);
 565     stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1);
 566 }
 567
 568 static int rehash_hpte(PowerPCCPU *cpu,
 569                        const ppc_hash_pte64_t *hptes,
 570                        void *old_hpt, uint64_t oldsize,
 571                        void *new_hpt, uint64_t newsize,
 572                        uint64_t pteg, int slot)
 573 {
 574     uint64_t old_hash_mask = (oldsize >> 7) - 1;
 575     uint64_t new_hash_mask = (newsize >> 7) - 1;
 576     target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot);
 577     target_ulong pte1;
 578     uint64_t avpn;
 579     unsigned base_pg_shift;
 580     uint64_t hash, new_pteg, replace_pte0;
 581
 582     if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) {
 583         return H_SUCCESS;
 584     }
 585
 586     pte1 = ppc_hash64_hpte1(cpu, hptes, slot);
 587
 588     base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
 589     assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
 590     avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
 591
 592     if (pte0 & HPTE64_V_SECONDARY) {
 593         pteg = ~pteg;
 594     }
 595
 596     if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) {
 597         uint64_t offset, vsid;
 598
 599         /* We only have 28 - 23 bits of offset in avpn */
 600         offset = (avpn & 0x1f) << 23;
 601         vsid = avpn >> 5;
 602         /* We can find more bits from the pteg value */
 603         if (base_pg_shift < 23) {
 604             offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift;
 605         }
 606
 607         hash = vsid ^ (offset >> base_pg_shift);
 608     } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) {
 609         uint64_t offset, vsid;
 610
 611         /* We only have 40 - 23 bits of seg_off in avpn */
 612         offset = (avpn & 0x1ffff) << 23;
 613         vsid = avpn >> 17;
 614         if (base_pg_shift < 23) {
 615             offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask)
 616                 << base_pg_shift;
 617         }
 618
 619         hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift);
 620     } else {
 621         error_report("rehash_pte: Bad segment size in HPTE");
 622         return H_HARDWARE;
 623     }
 624
 625     new_pteg = hash & new_hash_mask;
 626     if (pte0 & HPTE64_V_SECONDARY) {
 627         assert(~pteg == (hash & old_hash_mask));
 628         new_pteg = ~new_pteg;
 629     } else {
 630         assert(pteg == (hash & old_hash_mask));
 631     }
 632     assert((oldsize != newsize) || (pteg == new_pteg));
 633     replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot);
 634     /*
 635      * Strictly speaking, we don't need all these tests, since we only
 636      * ever rehash bolted HPTEs.  We might in future handle non-bolted
 637      * HPTEs, though so make the logic correct for those cases as
 638      * well.
 639      */
 640     if (replace_pte0 & HPTE64_V_VALID) {
 641         assert(newsize < oldsize);
 642         if (replace_pte0 & HPTE64_V_BOLTED) {
 643             if (pte0 & HPTE64_V_BOLTED) {
 644                 /* Bolted collision, nothing we can do */
 645                 return H_PTEG_FULL;
 646             } else {
 647                 /* Discard this hpte */
 648                 return H_SUCCESS;
 649             }
 650         }
 651     }
 652
 653     new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1);
 654     return H_SUCCESS;
 655 }
 656
 657 static int rehash_hpt(PowerPCCPU *cpu,
 658                       void *old_hpt, uint64_t oldsize,
 659                       void *new_hpt, uint64_t newsize)
 660 {
 661     uint64_t n_ptegs = oldsize >> 7;
 662     uint64_t pteg;
 663     int slot;
 664     int rc;
 665
 666     for (pteg = 0; pteg < n_ptegs; pteg++) {
 667         hwaddr ptex = pteg * HPTES_PER_GROUP;
 668         const ppc_hash_pte64_t *hptes
 669             = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
 670
 671         if (!hptes) {
 672             return H_HARDWARE;
 673         }
 674
 675         for (slot = 0; slot < HPTES_PER_GROUP; slot++) {
 676             rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize,
 677                              pteg, slot);
 678             if (rc != H_SUCCESS) {
 679                 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
 680                 return rc;
 681             }
 682         }
 683         ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
 684     }
 685
 686     return H_SUCCESS;
 687 }
 688
 689 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
 690                                         sPAPRMachineState *spapr,
 691                                         target_ulong opcode,
 692                                         target_ulong *args)
 693 {
 694     target_ulong flags = args[0];
 695     target_ulong shift = args[1];
 696     sPAPRPendingHPT *pending = spapr->pending_hpt;
 697     int rc;
 698     size_t newsize;
 699
 700     if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
 701         return H_AUTHORITY;
 702     }
 703
 704     trace_spapr_h_resize_hpt_commit(flags, shift);
 705
 706     rc = kvmppc_resize_hpt_commit(cpu, flags, shift);
 707     if (rc != -ENOSYS) {
 708         return resize_hpt_convert_rc(rc);
 709     }
 710
 711     if (flags != 0) {
 712         return H_PARAMETER;
 713     }
 714
 715     if (!pending || (pending->shift != shift)) {
 716         /* no matching prepare */
 717         return H_CLOSED;
 718     }
 719
 720     if (!pending->complete) {
 721         /* prepare has not completed */
 722         return H_BUSY;
 723     }
 724
 725     /* Shouldn't have got past PREPARE without an HPT */
 726     g_assert(spapr->htab_shift);
 727
 728     newsize = 1ULL << pending->shift;
 729     rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr),
 730                     pending->hpt, newsize);
 731     if (rc == H_SUCCESS) {
 732         qemu_vfree(spapr->htab);
 733         spapr->htab = pending->hpt;
 734         spapr->htab_shift = pending->shift;
 735
 736         if (kvm_enabled()) {
 737             /* For KVM PR, update the HPT pointer */
 738             target_ulong sdr1 = (target_ulong)(uintptr_t)spapr->htab
 739                 | (spapr->htab_shift - 18);
 740             kvmppc_update_sdr1(sdr1);
 741         }
 742
 743         pending->hpt = NULL; /* so it's not free()d */
 744     }
 745
 746     /* Clean up */
 747     spapr->pending_hpt = NULL;
 748     free_pending_hpt(pending);
 749
 750     return rc;
 751 }
 752
 753 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 754                                 target_ulong opcode, target_ulong *args)
 755 {
 756     cpu_synchronize_state(CPU(cpu));
 757     cpu->env.spr[SPR_SPRG0] = args[0];
 758
 759     return H_SUCCESS;
 760 }
 761
 762 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 763                                target_ulong opcode, target_ulong *args)
 764 {
 765     if (!has_spr(cpu, SPR_DABR)) {
 766         return H_HARDWARE;              /* DABR register not available */
 767     }
 768     cpu_synchronize_state(CPU(cpu));
 769
 770     if (has_spr(cpu, SPR_DABRX)) {
 771         cpu->env.spr[SPR_DABRX] = 0x3;  /* Use Problem and Privileged state */
 772     } else if (!(args[0] & 0x4)) {      /* Breakpoint Translation set? */
 773         return H_RESERVED_DABR;
 774     }
 775
 776     cpu->env.spr[SPR_DABR] = args[0];
 777     return H_SUCCESS;
 778 }
 779
 780 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 781                                 target_ulong opcode, target_ulong *args)
 782 {
 783     target_ulong dabrx = args[1];
 784
 785     if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) {
 786         return H_HARDWARE;
 787     }
 788
 789     if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0
 790         || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) {
 791         return H_PARAMETER;
 792     }
 793
 794     cpu_synchronize_state(CPU(cpu));
 795     cpu->env.spr[SPR_DABRX] = dabrx;
 796     cpu->env.spr[SPR_DABR] = args[0];
 797
 798     return H_SUCCESS;
 799 }
 800
 801 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 802                                 target_ulong opcode, target_ulong *args)
 803 {
 804     target_ulong flags = args[0];
 805     hwaddr dst = args[1];
 806     hwaddr src = args[2];
 807     hwaddr len = TARGET_PAGE_SIZE;
 808     uint8_t *pdst, *psrc;
 809     target_long ret = H_SUCCESS;
 810
 811     if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE
 812                   | H_COPY_PAGE | H_ZERO_PAGE)) {
 813         qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n",
 814                       flags);
 815         return H_PARAMETER;
 816     }
 817
 818     /* Map-in destination */
 819     if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) {
 820         return H_PARAMETER;
 821     }
 822     pdst = cpu_physical_memory_map(dst, &len, 1);
 823     if (!pdst || len != TARGET_PAGE_SIZE) {
 824         return H_PARAMETER;
 825     }
 826
 827     if (flags & H_COPY_PAGE) {
 828         /* Map-in source, copy to destination, and unmap source again */
 829         if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) {
 830             ret = H_PARAMETER;
 831             goto unmap_out;
 832         }
 833         psrc = cpu_physical_memory_map(src, &len, 0);
 834         if (!psrc || len != TARGET_PAGE_SIZE) {
 835             ret = H_PARAMETER;
 836             goto unmap_out;
 837         }
 838         memcpy(pdst, psrc, len);
 839         cpu_physical_memory_unmap(psrc, len, 0, len);
 840     } else if (flags & H_ZERO_PAGE) {
 841         memset(pdst, 0, len);          /* Just clear the destination page */
 842     }
 843
 844     if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) {
 845         kvmppc_dcbst_range(cpu, pdst, len);
 846     }
 847     if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) {
 848         if (kvm_enabled()) {
 849             kvmppc_icbi_range(cpu, pdst, len);
 850         } else {
 851             tb_flush(CPU(cpu));
 852         }
 853     }
 854
 855 unmap_out:
 856     cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len);
 857     return ret;
 858 }
 859
 860 #define FLAGS_REGISTER_VPA         0x0000200000000000ULL
 861 #define FLAGS_REGISTER_DTL         0x0000400000000000ULL
 862 #define FLAGS_REGISTER_SLBSHADOW   0x0000600000000000ULL
 863 #define FLAGS_DEREGISTER_VPA       0x0000a00000000000ULL
 864 #define FLAGS_DEREGISTER_DTL       0x0000c00000000000ULL
 865 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
 866
 867 #define VPA_MIN_SIZE           640
 868 #define VPA_SIZE_OFFSET        0x4
 869 #define VPA_SHARED_PROC_OFFSET 0x9
 870 #define VPA_SHARED_PROC_VAL    0x2
 871
 872 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
 873 {
 874     CPUState *cs = CPU(ppc_env_get_cpu(env));
 875     uint16_t size;
 876     uint8_t tmp;
 877
 878     if (vpa == 0) {
 879         hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
 880         return H_HARDWARE;
 881     }
 882
 883     if (vpa % env->dcache_line_size) {
 884         return H_PARAMETER;
 885     }
 886     /* FIXME: bounds check the address */
 887
 888     size = lduw_be_phys(cs->as, vpa + 0x4);
 889
 890     if (size < VPA_MIN_SIZE) {
 891         return H_PARAMETER;
 892     }
 893
 894     /* VPA is not allowed to cross a page boundary */
 895     if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
 896         return H_PARAMETER;
 897     }
 898
 899     env->vpa_addr = vpa;
 900
 901     tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
 902     tmp |= VPA_SHARED_PROC_VAL;
 903     stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
 904
 905     return H_SUCCESS;
 906 }
 907
 908 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
 909 {
 910     if (env->slb_shadow_addr) {
 911         return H_RESOURCE;
 912     }
 913
 914     if (env->dtl_addr) {
 915         return H_RESOURCE;
 916     }
 917
 918     env->vpa_addr = 0;
 919     return H_SUCCESS;
 920 }
 921
 922 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
 923 {
 924     CPUState *cs = CPU(ppc_env_get_cpu(env));
 925     uint32_t size;
 926
 927     if (addr == 0) {
 928         hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
 929         return H_HARDWARE;
 930     }
 931
 932     size = ldl_be_phys(cs->as, addr + 0x4);
 933     if (size < 0x8) {
 934         return H_PARAMETER;
 935     }
 936
 937     if ((addr / 4096) != ((addr + size - 1) / 4096)) {
 938         return H_PARAMETER;
 939     }
 940
 941     if (!env->vpa_addr) {
 942         return H_RESOURCE;
 943     }
 944
 945     env->slb_shadow_addr = addr;
 946     env->slb_shadow_size = size;
 947
 948     return H_SUCCESS;
 949 }
 950
 951 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
 952 {
 953     env->slb_shadow_addr = 0;
 954     env->slb_shadow_size = 0;
 955     return H_SUCCESS;
 956 }
 957
 958 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
 959 {
 960     CPUState *cs = CPU(ppc_env_get_cpu(env));
 961     uint32_t size;
 962
 963     if (addr == 0) {
 964         hcall_dprintf("Can't cope with DTL at logical 0\n");
 965         return H_HARDWARE;
 966     }
 967
 968     size = ldl_be_phys(cs->as, addr + 0x4);
 969
 970     if (size < 48) {
 971         return H_PARAMETER;
 972     }
 973
 974     if (!env->vpa_addr) {
 975         return H_RESOURCE;
 976     }
 977
 978     env->dtl_addr = addr;
 979     env->dtl_size = size;
 980
 981     return H_SUCCESS;
 982 }
 983
 984 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
 985 {
 986     env->dtl_addr = 0;
 987     env->dtl_size = 0;
 988
 989     return H_SUCCESS;
 990 }
 991
 992 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 993                                    target_ulong opcode, target_ulong *args)
 994 {
 995     target_ulong flags = args[0];
 996     target_ulong procno = args[1];
 997     target_ulong vpa = args[2];
 998     target_ulong ret = H_PARAMETER;
 999     CPUPPCState *tenv;
1000     PowerPCCPU *tcpu;
1001
1002     tcpu = ppc_get_vcpu_by_dt_id(procno);
1003     if (!tcpu) {
1004         return H_PARAMETER;
1005     }
1006     tenv = &tcpu->env;
1007
1008     switch (flags) {
1009     case FLAGS_REGISTER_VPA:
1010         ret = register_vpa(tenv, vpa);
1011         break;
1012
1013     case FLAGS_DEREGISTER_VPA:
1014         ret = deregister_vpa(tenv, vpa);
1015         break;
1016
1017     case FLAGS_REGISTER_SLBSHADOW:
1018         ret = register_slb_shadow(tenv, vpa);
1019         break;
1020
1021     case FLAGS_DEREGISTER_SLBSHADOW:
1022         ret = deregister_slb_shadow(tenv, vpa);
1023         break;
1024
1025     case FLAGS_REGISTER_DTL:
1026         ret = register_dtl(tenv, vpa);
1027         break;
1028
1029     case FLAGS_DEREGISTER_DTL:
1030         ret = deregister_dtl(tenv, vpa);
1031         break;
1032     }
1033
1034     return ret;
1035 }
1036
1037 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1038                            target_ulong opcode, target_ulong *args)
1039 {
1040     CPUPPCState *env = &cpu->env;
1041     CPUState *cs = CPU(cpu);
1042
1043     env->msr |= (1ULL << MSR_EE);
1044     hreg_compute_hflags(env);
1045     if (!cpu_has_work(cs)) {
1046         cs->halted = 1;
1047         cs->exception_index = EXCP_HLT;
1048         cs->exit_request = 1;
1049     }
1050     return H_SUCCESS;
1051 }
1052
1053 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1054                            target_ulong opcode, target_ulong *args)
1055 {
1056     target_ulong rtas_r3 = args[0];
1057     uint32_t token = rtas_ld(rtas_r3, 0);
1058     uint32_t nargs = rtas_ld(rtas_r3, 1);
1059     uint32_t nret = rtas_ld(rtas_r3, 2);
1060
1061     return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12,
1062                            nret, rtas_r3 + 12 + 4*nargs);
1063 }
1064
1065 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1066                                    target_ulong opcode, target_ulong *args)
1067 {
1068     CPUState *cs = CPU(cpu);
1069     target_ulong size = args[0];
1070     target_ulong addr = args[1];
1071
1072     switch (size) {
1073     case 1:
1074         args[0] = ldub_phys(cs->as, addr);
1075         return H_SUCCESS;
1076     case 2:
1077         args[0] = lduw_phys(cs->as, addr);
1078         return H_SUCCESS;
1079     case 4:
1080         args[0] = ldl_phys(cs->as, addr);
1081         return H_SUCCESS;
1082     case 8:
1083         args[0] = ldq_phys(cs->as, addr);
1084         return H_SUCCESS;
1085     }
1086     return H_PARAMETER;
1087 }
1088
1089 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1090                                     target_ulong opcode, target_ulong *args)
1091 {
1092     CPUState *cs = CPU(cpu);
1093
1094     target_ulong size = args[0];
1095     target_ulong addr = args[1];
1096     target_ulong val  = args[2];
1097
1098     switch (size) {
1099     case 1:
1100         stb_phys(cs->as, addr, val);
1101         return H_SUCCESS;
1102     case 2:
1103         stw_phys(cs->as, addr, val);
1104         return H_SUCCESS;
1105     case 4:
1106         stl_phys(cs->as, addr, val);
1107         return H_SUCCESS;
1108     case 8:
1109         stq_phys(cs->as, addr, val);
1110         return H_SUCCESS;
1111     }
1112     return H_PARAMETER;
1113 }
1114
1115 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1116                                     target_ulong opcode, target_ulong *args)
1117 {
1118     CPUState *cs = CPU(cpu);
1119
1120     target_ulong dst   = args[0]; /* Destination address */
1121     target_ulong src   = args[1]; /* Source address */
1122     target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
1123     target_ulong count = args[3]; /* Element count */
1124     target_ulong op    = args[4]; /* 0 = copy, 1 = invert */
1125     uint64_t tmp;
1126     unsigned int mask = (1 << esize) - 1;
1127     int step = 1 << esize;
1128
1129     if (count > 0x80000000) {
1130         return H_PARAMETER;
1131     }
1132
1133     if ((dst & mask) || (src & mask) || (op > 1)) {
1134         return H_PARAMETER;
1135     }
1136
1137     if (dst >= src && dst < (src + (count << esize))) {
1138             dst = dst + ((count - 1) << esize);
1139             src = src + ((count - 1) << esize);
1140             step = -step;
1141     }
1142
1143     while (count--) {
1144         switch (esize) {
1145         case 0:
1146             tmp = ldub_phys(cs->as, src);
1147             break;
1148         case 1:
1149             tmp = lduw_phys(cs->as, src);
1150             break;
1151         case 2:
1152             tmp = ldl_phys(cs->as, src);
1153             break;
1154         case 3:
1155             tmp = ldq_phys(cs->as, src);
1156             break;
1157         default:
1158             return H_PARAMETER;
1159         }
1160         if (op == 1) {
1161             tmp = ~tmp;
1162         }
1163         switch (esize) {
1164         case 0:
1165             stb_phys(cs->as, dst, tmp);
1166             break;
1167         case 1:
1168             stw_phys(cs->as, dst, tmp);
1169             break;
1170         case 2:
1171             stl_phys(cs->as, dst, tmp);
1172             break;
1173         case 3:
1174             stq_phys(cs->as, dst, tmp);
1175             break;
1176         }
1177         dst = dst + step;
1178         src = src + step;
1179     }
1180
1181     return H_SUCCESS;
1182 }
1183
1184 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1185                                    target_ulong opcode, target_ulong *args)
1186 {
1187     /* Nothing to do on emulation, KVM will trap this in the kernel */
1188     return H_SUCCESS;
1189 }
1190
1191 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1192                                    target_ulong opcode, target_ulong *args)
1193 {
1194     /* Nothing to do on emulation, KVM will trap this in the kernel */
1195     return H_SUCCESS;
1196 }
1197
1198 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu,
1199                                            target_ulong mflags,
1200                                            target_ulong value1,
1201                                            target_ulong value2)
1202 {
1203     CPUState *cs;
1204
1205     if (value1) {
1206         return H_P3;
1207     }
1208     if (value2) {
1209         return H_P4;
1210     }
1211
1212     switch (mflags) {
1213     case H_SET_MODE_ENDIAN_BIG:
1214         CPU_FOREACH(cs) {
1215             set_spr(cs, SPR_LPCR, 0, LPCR_ILE);
1216         }
1217         spapr_pci_switch_vga(true);
1218         return H_SUCCESS;
1219
1220     case H_SET_MODE_ENDIAN_LITTLE:
1221         CPU_FOREACH(cs) {
1222             set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE);
1223         }
1224         spapr_pci_switch_vga(false);
1225         return H_SUCCESS;
1226     }
1227
1228     return H_UNSUPPORTED_FLAG;
1229 }
1230
1231 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu,
1232                                                         target_ulong mflags,
1233                                                         target_ulong value1,
1234                                                         target_ulong value2)
1235 {
1236     CPUState *cs;
1237     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
1238
1239     if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
1240         return H_P2;
1241     }
1242     if (value1) {
1243         return H_P3;
1244     }
1245     if (value2) {
1246         return H_P4;
1247     }
1248
1249     if (mflags == AIL_RESERVED) {
1250         return H_UNSUPPORTED_FLAG;
1251     }
1252
1253     CPU_FOREACH(cs) {
1254         set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL);
1255     }
1256
1257     return H_SUCCESS;
1258 }
1259
1260 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1261                                target_ulong opcode, target_ulong *args)
1262 {
1263     target_ulong resource = args[1];
1264     target_ulong ret = H_P2;
1265
1266     switch (resource) {
1267     case H_SET_MODE_RESOURCE_LE:
1268         ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]);
1269         break;
1270     case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
1271         ret = h_set_mode_resource_addr_trans_mode(cpu, args[0],
1272                                                   args[2], args[3]);
1273         break;
1274     }
1275
1276     return ret;
1277 }
1278
1279 static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1280                                 target_ulong opcode, target_ulong *args)
1281 {
1282     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
1283                   opcode, " (H_CLEAN_SLB)");
1284     return H_FUNCTION;
1285 }
1286
1287 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1288                                      target_ulong opcode, target_ulong *args)
1289 {
1290     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
1291                   opcode, " (H_INVALIDATE_PID)");
1292     return H_FUNCTION;
1293 }
1294
1295 static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr,
1296                                        uint64_t patbe_old, uint64_t patbe_new)
1297 {
1298     /*
1299      * We have 4 Options:
1300      * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing
1301      * HASH->RADIX                                  : Free HPT
1302      * RADIX->HASH                                  : Allocate HPT
1303      * NOTHING->HASH                                : Allocate HPT
1304      * Note: NOTHING implies the case where we said the guest could choose
1305      *       later and so assumed radix and now it's called H_REG_PROC_TBL
1306      */
1307
1308     if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) {
1309         /* We assume RADIX, so this catches all the "Do Nothing" cases */
1310     } else if (!(patbe_old & PATBE1_GR)) {
1311         /* HASH->RADIX : Free HPT */
1312         spapr_free_hpt(spapr);
1313     } else if (!(patbe_new & PATBE1_GR)) {
1314         /* RADIX->HASH || NOTHING->HASH : Allocate HPT */
1315         spapr_setup_hpt_and_vrma(spapr);
1316     }
1317     return;
1318 }
1319
1320 #define FLAGS_MASK              0x01FULL
1321 #define FLAG_MODIFY             0x10
1322 #define FLAG_REGISTER           0x08
1323 #define FLAG_RADIX              0x04
1324 #define FLAG_HASH_PROC_TBL      0x02
1325 #define FLAG_GTSE               0x01
1326
1327 static target_ulong h_register_process_table(PowerPCCPU *cpu,
1328                                              sPAPRMachineState *spapr,
1329                                              target_ulong opcode,
1330                                              target_ulong *args)
1331 {
1332     CPUState *cs;
1333     target_ulong flags = args[0];
1334     target_ulong proc_tbl = args[1];
1335     target_ulong page_size = args[2];
1336     target_ulong table_size = args[3];
1337     uint64_t cproc;
1338
1339     if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */
1340         return H_PARAMETER;
1341     }
1342     if (flags & FLAG_MODIFY) {
1343         if (flags & FLAG_REGISTER) {
1344             if (flags & FLAG_RADIX) { /* Register new RADIX process table */
1345                 if (proc_tbl & 0xfff || proc_tbl >> 60) {
1346                     return H_P2;
1347                 } else if (page_size) {
1348                     return H_P3;
1349                 } else if (table_size > 24) {
1350                     return H_P4;
1351                 }
1352                 cproc = PATBE1_GR | proc_tbl | table_size;
1353             } else { /* Register new HPT process table */
1354                 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */
1355                     /* TODO - Not Supported */
1356                     /* Technically caused by flag bits => H_PARAMETER */
1357                     return H_PARAMETER;
1358                 } else { /* Hash with SLB */
1359                     if (proc_tbl >> 38) {
1360                         return H_P2;
1361                     } else if (page_size & ~0x7) {
1362                         return H_P3;
1363                     } else if (table_size > 24) {
1364                         return H_P4;
1365                     }
1366                 }
1367                 cproc = (proc_tbl << 25) | page_size << 5 | table_size;
1368             }
1369
1370         } else { /* Deregister current process table */
1371             /* Set to benign value: (current GR) | 0. This allows
1372              * deregistration in KVM to succeed even if the radix bit in flags
1373              * doesn't match the radix bit in the old PATB. */
1374             cproc = spapr->patb_entry & PATBE1_GR;
1375         }
1376     } else { /* Maintain current registration */
1377         if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) {
1378             /* Technically caused by flag bits => H_PARAMETER */
1379             return H_PARAMETER; /* Existing Process Table Mismatch */
1380         }
1381         cproc = spapr->patb_entry;
1382     }
1383
1384     /* Check if we need to setup OR free the hpt */
1385     spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc);
1386
1387     spapr->patb_entry = cproc; /* Save new process table */
1388
1389     /* Update the UPRT and GTSE bits in the LPCR for all cpus */
1390     CPU_FOREACH(cs) {
1391         set_spr(cs, SPR_LPCR,
1392                 ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) |
1393                 ((flags & FLAG_GTSE) ? LPCR_GTSE : 0),
1394                 LPCR_UPRT | LPCR_GTSE);
1395     }
1396
1397     if (kvm_enabled()) {
1398         return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX,
1399                                        flags & FLAG_GTSE, cproc);
1400     }
1401     return H_SUCCESS;
1402 }
1403
1404 #define H_SIGNAL_SYS_RESET_ALL         -1
1405 #define H_SIGNAL_SYS_RESET_ALLBUTSELF  -2
1406
1407 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
1408                                        sPAPRMachineState *spapr,
1409                                        target_ulong opcode, target_ulong *args)
1410 {
1411     target_long target = args[0];
1412     CPUState *cs;
1413
1414     if (target < 0) {
1415         /* Broadcast */
1416         if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1417             return H_PARAMETER;
1418         }
1419
1420         CPU_FOREACH(cs) {
1421             PowerPCCPU *c = POWERPC_CPU(cs);
1422
1423             if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1424                 if (c == cpu) {
1425                     continue;
1426                 }
1427             }
1428             run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1429         }
1430         return H_SUCCESS;
1431
1432     } else {
1433         /* Unicast */
1434         cs = CPU(ppc_get_vcpu_by_dt_id(target));
1435         if (cs) {
1436             run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1437             return H_SUCCESS;
1438         }
1439         return H_PARAMETER;
1440     }
1441 }
1442
1443 static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu,
1444                               target_ulong *addr, Error **errp)
1445 {
1446     bool explicit_match = false; /* Matched the CPU's real PVR */
1447     uint32_t max_compat = spapr->max_compat_pvr;
1448     uint32_t best_compat = 0;
1449     int i;
1450
1451     /*
1452      * We scan the supplied table of PVRs looking for two things
1453      *   1. Is our real CPU PVR in the list?
1454      *   2. What's the "best" listed logical PVR
1455      */
1456     for (i = 0; i < 512; ++i) {
1457         uint32_t pvr, pvr_mask;
1458
1459         pvr_mask = ldl_be_phys(&address_space_memory, *addr);
1460         pvr = ldl_be_phys(&address_space_memory, *addr + 4);
1461         *addr += 8;
1462
1463         if (~pvr_mask & pvr) {
1464             break; /* Terminator record */
1465         }
1466
1467         if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) {
1468             explicit_match = true;
1469         } else {
1470             if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) {
1471                 best_compat = pvr;
1472             }
1473         }
1474     }
1475
1476     if ((best_compat == 0) && (!explicit_match || max_compat)) {
1477         /* We couldn't find a suitable compatibility mode, and either
1478          * the guest doesn't support "raw" mode for this CPU, or raw
1479          * mode is disabled because a maximum compat mode is set */
1480         error_setg(errp, "Couldn't negotiate a suitable PVR during CAS");
1481         return 0;
1482     }
1483
1484     /* Parsing finished */
1485     trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat);
1486
1487     return best_compat;
1488 }
1489
1490 static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
1491                                                   sPAPRMachineState *spapr,
1492                                                   target_ulong opcode,
1493                                                   target_ulong *args)
1494 {
1495     /* Working address in data buffer */
1496     target_ulong addr = ppc64_phys_to_real(args[0]);
1497     target_ulong ov_table;
1498     uint32_t cas_pvr;
1499     sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates;
1500     bool guest_radix;
1501     Error *local_err = NULL;
1502
1503     cas_pvr = cas_check_pvr(spapr, cpu, &addr, &local_err);
1504     if (local_err) {
1505         error_report_err(local_err);
1506         return H_HARDWARE;
1507     }
1508
1509     /* Update CPUs */
1510     if (cpu->compat_pvr != cas_pvr) {
1511         ppc_set_compat_all(cas_pvr, &local_err);
1512         if (local_err) {
1513             error_report_err(local_err);
1514             return H_HARDWARE;
1515         }
1516     }
1517
1518     /* For the future use: here @ov_table points to the first option vector */
1519     ov_table = addr;
1520
1521     ov1_guest = spapr_ovec_parse_vector(ov_table, 1);
1522     ov5_guest = spapr_ovec_parse_vector(ov_table, 5);
1523     if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) {
1524         error_report("guest requested hash and radix MMU, which is invalid.");
1525         exit(EXIT_FAILURE);
1526     }
1527     /* The radix/hash bit in byte 24 requires special handling: */
1528     guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300);
1529     spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300);
1530
1531     /*
1532      * HPT resizing is a bit of a special case, because when enabled
1533      * we assume an HPT guest will support it until it says it
1534      * doesn't, instead of assuming it won't support it until it says
1535      * it does.  Strictly speaking that approach could break for
1536      * guests which don't make a CAS call, but those are so old we
1537      * don't care about them.  Without that assumption we'd have to
1538      * make at least a temporary allocation of an HPT sized for max
1539      * memory, which could be impossibly difficult under KVM HV if
1540      * maxram is large.
1541      */
1542     if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) {
1543         int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1544
1545         if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) {
1546             error_report(
1547                 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required");
1548             exit(1);
1549         }
1550
1551         if (spapr->htab_shift < maxshift) {
1552             CPUState *cs;
1553
1554             /* Guest doesn't know about HPT resizing, so we
1555              * pre-emptively resize for the maximum permitted RAM.  At
1556              * the point this is called, nothing should have been
1557              * entered into the existing HPT */
1558             spapr_reallocate_hpt(spapr, maxshift, &error_fatal);
1559             CPU_FOREACH(cs) {
1560                 if (kvm_enabled()) {
1561                     /* For KVM PR, update the HPT pointer */
1562                     target_ulong sdr1 = (target_ulong)(uintptr_t)spapr->htab
1563                         | (spapr->htab_shift - 18);
1564                     kvmppc_update_sdr1(sdr1);
1565                 }
1566             }
1567         }
1568     }
1569
1570     /* NOTE: there are actually a number of ov5 bits where input from the
1571      * guest is always zero, and the platform/QEMU enables them independently
1572      * of guest input. To model these properly we'd want some sort of mask,
1573      * but since they only currently apply to memory migration as defined
1574      * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need
1575      * to worry about this for now.
1576      */
1577     ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas);
1578     /* full range of negotiated ov5 capabilities */
1579     spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest);
1580     spapr_ovec_cleanup(ov5_guest);
1581     /* capabilities that have been added since CAS-generated guest reset.
1582      * if capabilities have since been removed, generate another reset
1583      */
1584     ov5_updates = spapr_ovec_new();
1585     spapr->cas_reboot = spapr_ovec_diff(ov5_updates,
1586                                         ov5_cas_old, spapr->ov5_cas);
1587     /* Now that processing is finished, set the radix/hash bit for the
1588      * guest if it requested a valid mode; otherwise terminate the boot. */
1589     if (guest_radix) {
1590         if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) {
1591             error_report("Guest requested unavailable MMU mode (radix).");
1592             exit(EXIT_FAILURE);
1593         }
1594         spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300);
1595     } else {
1596         if (kvm_enabled() && kvmppc_has_cap_mmu_radix()
1597             && !kvmppc_has_cap_mmu_hash_v3()) {
1598             error_report("Guest requested unavailable MMU mode (hash).");
1599             exit(EXIT_FAILURE);
1600         }
1601     }
1602     spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest,
1603                                                           OV1_PPC_3_00);
1604     if (!spapr->cas_reboot) {
1605         spapr->cas_reboot =
1606             (spapr_h_cas_compose_response(spapr, args[1], args[2],
1607                                           ov5_updates) != 0);
1608     }
1609     spapr_ovec_cleanup(ov5_updates);
1610
1611     if (spapr->cas_reboot) {
1612         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1613     } else {
1614         /* If ppc_spapr_reset() did not set up a HPT but one is necessary
1615          * (because the guest isn't going to use radix) then set it up here. */
1616         if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) {
1617             /* legacy hash or new hash: */
1618             spapr_setup_hpt_and_vrma(spapr);
1619         }
1620     }
1621
1622     return H_SUCCESS;
1623 }
1624
1625 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
1626 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
1627
1628 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
1629 {
1630     spapr_hcall_fn *slot;
1631
1632     if (opcode <= MAX_HCALL_OPCODE) {
1633         assert((opcode & 0x3) == 0);
1634
1635         slot = &papr_hypercall_table[opcode / 4];
1636     } else {
1637         assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
1638
1639         slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1640     }
1641
1642     assert(!(*slot));
1643     *slot = fn;
1644 }
1645
1646 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
1647                              target_ulong *args)
1648 {
1649     sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1650
1651     if ((opcode <= MAX_HCALL_OPCODE)
1652         && ((opcode & 0x3) == 0)) {
1653         spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
1654
1655         if (fn) {
1656             return fn(cpu, spapr, opcode, args);
1657         }
1658     } else if ((opcode >= KVMPPC_HCALL_BASE) &&
1659                (opcode <= KVMPPC_HCALL_MAX)) {
1660         spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1661
1662         if (fn) {
1663             return fn(cpu, spapr, opcode, args);
1664         }
1665     }
1666
1667     qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n",
1668                   opcode);
1669     return H_FUNCTION;
1670 }
1671
1672 static void hypercall_register_types(void)
1673 {
1674     /* hcall-pft */
1675     spapr_register_hypercall(H_ENTER, h_enter);
1676     spapr_register_hypercall(H_REMOVE, h_remove);
1677     spapr_register_hypercall(H_PROTECT, h_protect);
1678     spapr_register_hypercall(H_READ, h_read);
1679
1680     /* hcall-bulk */
1681     spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
1682
1683     /* hcall-hpt-resize */
1684     spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare);
1685     spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit);
1686
1687     /* hcall-splpar */
1688     spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
1689     spapr_register_hypercall(H_CEDE, h_cede);
1690     spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset);
1691
1692     /* processor register resource access h-calls */
1693     spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0);
1694     spapr_register_hypercall(H_SET_DABR, h_set_dabr);
1695     spapr_register_hypercall(H_SET_XDABR, h_set_xdabr);
1696     spapr_register_hypercall(H_PAGE_INIT, h_page_init);
1697     spapr_register_hypercall(H_SET_MODE, h_set_mode);
1698
1699     /* In Memory Table MMU h-calls */
1700     spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb);
1701     spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid);
1702     spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table);
1703
1704     /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
1705      * here between the "CI" and the "CACHE" variants, they will use whatever
1706      * mapping attributes qemu is using. When using KVM, the kernel will
1707      * enforce the attributes more strongly
1708      */
1709     spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
1710     spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
1711     spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
1712     spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
1713     spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
1714     spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
1715     spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);
1716
1717     /* qemu/KVM-PPC specific hcalls */
1718     spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
1719
1720     /* ibm,client-architecture-support support */
1721     spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
1722 }
1723
1724 type_init(hypercall_register_types)