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qxl: call qemu_spice_display_init_common for secondary devices
[qemu/ar7.git] / hw / ppc / ppc405_uc.c
blobf6fe3e6f5e29c6412d9abb01ffca727010317d69
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "qemu-common.h"
27 #include "cpu.h"
28 #include "hw/hw.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/boards.h"
31 #include "ppc405.h"
32 #include "hw/char/serial.h"
33 #include "qemu/timer.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/log.h"
36 #include "exec/address-spaces.h"
37
38 //#define DEBUG_OPBA
39 //#define DEBUG_SDRAM
40 //#define DEBUG_GPIO
41 //#define DEBUG_SERIAL
42 //#define DEBUG_OCM
43 //#define DEBUG_I2C
44 //#define DEBUG_GPT
45 //#define DEBUG_MAL
46 //#define DEBUG_CLOCKS
47 //#define DEBUG_CLOCKS_LL
48
49 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
50 uint32_t flags)
51 {
52 CPUState *cs = CPU(ppc_env_get_cpu(env));
53 ram_addr_t bdloc;
54 int i, n;
55
56 /* We put the bd structure at the top of memory */
57 if (bd->bi_memsize >= 0x01000000UL)
58 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
59 else
60 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
61 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
62 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
63 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
64 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
65 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
66 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
67 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
68 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
69 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
70 for (i = 0; i < 6; i++) {
71 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
72 }
73 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
74 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
75 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
76 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
77 for (i = 0; i < 4; i++) {
78 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
79 }
80 for (i = 0; i < 32; i++) {
81 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
82 }
83 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
84 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
85 for (i = 0; i < 6; i++) {
86 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
87 }
88 n = 0x6A;
89 if (flags & 0x00000001) {
90 for (i = 0; i < 6; i++)
91 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
92 }
93 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
94 n += 4;
95 for (i = 0; i < 2; i++) {
96 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
97 n += 4;
98 }
99
100 return bdloc;
101 }
102
103 /*****************************************************************************/
104 /* Shared peripherals */
105
106 /*****************************************************************************/
107 /* Peripheral local bus arbitrer */
108 enum {
109 PLB0_BESR = 0x084,
110 PLB0_BEAR = 0x086,
111 PLB0_ACR = 0x087,
112 };
113
114 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
115 struct ppc4xx_plb_t {
116 uint32_t acr;
117 uint32_t bear;
118 uint32_t besr;
119 };
120
121 static uint32_t dcr_read_plb (void *opaque, int dcrn)
122 {
123 ppc4xx_plb_t *plb;
124 uint32_t ret;
125
126 plb = opaque;
127 switch (dcrn) {
128 case PLB0_ACR:
129 ret = plb->acr;
130 break;
131 case PLB0_BEAR:
132 ret = plb->bear;
133 break;
134 case PLB0_BESR:
135 ret = plb->besr;
136 break;
137 default:
138 /* Avoid gcc warning */
139 ret = 0;
140 break;
141 }
142
143 return ret;
144 }
145
146 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
147 {
148 ppc4xx_plb_t *plb;
149
150 plb = opaque;
151 switch (dcrn) {
152 case PLB0_ACR:
153 /* We don't care about the actual parameters written as
154 * we don't manage any priorities on the bus
155 */
156 plb->acr = val & 0xF8000000;
157 break;
158 case PLB0_BEAR:
159 /* Read only */
160 break;
161 case PLB0_BESR:
162 /* Write-clear */
163 plb->besr &= ~val;
164 break;
165 }
166 }
167
168 static void ppc4xx_plb_reset (void *opaque)
169 {
170 ppc4xx_plb_t *plb;
171
172 plb = opaque;
173 plb->acr = 0x00000000;
174 plb->bear = 0x00000000;
175 plb->besr = 0x00000000;
176 }
177
178 static void ppc4xx_plb_init(CPUPPCState *env)
179 {
180 ppc4xx_plb_t *plb;
181
182 plb = g_malloc0(sizeof(ppc4xx_plb_t));
183 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
184 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
185 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
186 qemu_register_reset(ppc4xx_plb_reset, plb);
187 }
188
189 /*****************************************************************************/
190 /* PLB to OPB bridge */
191 enum {
192 POB0_BESR0 = 0x0A0,
193 POB0_BESR1 = 0x0A2,
194 POB0_BEAR = 0x0A4,
195 };
196
197 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
198 struct ppc4xx_pob_t {
199 uint32_t bear;
200 uint32_t besr0;
201 uint32_t besr1;
202 };
203
204 static uint32_t dcr_read_pob (void *opaque, int dcrn)
205 {
206 ppc4xx_pob_t *pob;
207 uint32_t ret;
208
209 pob = opaque;
210 switch (dcrn) {
211 case POB0_BEAR:
212 ret = pob->bear;
213 break;
214 case POB0_BESR0:
215 ret = pob->besr0;
216 break;
217 case POB0_BESR1:
218 ret = pob->besr1;
219 break;
220 default:
221 /* Avoid gcc warning */
222 ret = 0;
223 break;
224 }
225
226 return ret;
227 }
228
229 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
230 {
231 ppc4xx_pob_t *pob;
232
233 pob = opaque;
234 switch (dcrn) {
235 case POB0_BEAR:
236 /* Read only */
237 break;
238 case POB0_BESR0:
239 /* Write-clear */
240 pob->besr0 &= ~val;
241 break;
242 case POB0_BESR1:
243 /* Write-clear */
244 pob->besr1 &= ~val;
245 break;
246 }
247 }
248
249 static void ppc4xx_pob_reset (void *opaque)
250 {
251 ppc4xx_pob_t *pob;
252
253 pob = opaque;
254 /* No error */
255 pob->bear = 0x00000000;
256 pob->besr0 = 0x0000000;
257 pob->besr1 = 0x0000000;
258 }
259
260 static void ppc4xx_pob_init(CPUPPCState *env)
261 {
262 ppc4xx_pob_t *pob;
263
264 pob = g_malloc0(sizeof(ppc4xx_pob_t));
265 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
266 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
267 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
268 qemu_register_reset(ppc4xx_pob_reset, pob);
269 }
270
271 /*****************************************************************************/
272 /* OPB arbitrer */
273 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
274 struct ppc4xx_opba_t {
275 MemoryRegion io;
276 uint8_t cr;
277 uint8_t pr;
278 };
279
280 static uint32_t opba_readb (void *opaque, hwaddr addr)
281 {
282 ppc4xx_opba_t *opba;
283 uint32_t ret;
284
285 #ifdef DEBUG_OPBA
286 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
287 #endif
288 opba = opaque;
289 switch (addr) {
290 case 0x00:
291 ret = opba->cr;
292 break;
293 case 0x01:
294 ret = opba->pr;
295 break;
296 default:
297 ret = 0x00;
298 break;
299 }
300
301 return ret;
302 }
303
304 static void opba_writeb (void *opaque,
305 hwaddr addr, uint32_t value)
306 {
307 ppc4xx_opba_t *opba;
308
309 #ifdef DEBUG_OPBA
310 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
311 value);
312 #endif
313 opba = opaque;
314 switch (addr) {
315 case 0x00:
316 opba->cr = value & 0xF8;
317 break;
318 case 0x01:
319 opba->pr = value & 0xFF;
320 break;
321 default:
322 break;
323 }
324 }
325
326 static uint32_t opba_readw (void *opaque, hwaddr addr)
327 {
328 uint32_t ret;
329
330 #ifdef DEBUG_OPBA
331 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
332 #endif
333 ret = opba_readb(opaque, addr) << 8;
334 ret |= opba_readb(opaque, addr + 1);
335
336 return ret;
337 }
338
339 static void opba_writew (void *opaque,
340 hwaddr addr, uint32_t value)
341 {
342 #ifdef DEBUG_OPBA
343 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
344 value);
345 #endif
346 opba_writeb(opaque, addr, value >> 8);
347 opba_writeb(opaque, addr + 1, value);
348 }
349
350 static uint32_t opba_readl (void *opaque, hwaddr addr)
351 {
352 uint32_t ret;
353
354 #ifdef DEBUG_OPBA
355 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
356 #endif
357 ret = opba_readb(opaque, addr) << 24;
358 ret |= opba_readb(opaque, addr + 1) << 16;
359
360 return ret;
361 }
362
363 static void opba_writel (void *opaque,
364 hwaddr addr, uint32_t value)
365 {
366 #ifdef DEBUG_OPBA
367 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
368 value);
369 #endif
370 opba_writeb(opaque, addr, value >> 24);
371 opba_writeb(opaque, addr + 1, value >> 16);
372 }
373
374 static const MemoryRegionOps opba_ops = {
375 .old_mmio = {
376 .read = { opba_readb, opba_readw, opba_readl, },
377 .write = { opba_writeb, opba_writew, opba_writel, },
378 },
379 .endianness = DEVICE_NATIVE_ENDIAN,
380 };
381
382 static void ppc4xx_opba_reset (void *opaque)
383 {
384 ppc4xx_opba_t *opba;
385
386 opba = opaque;
387 opba->cr = 0x00; /* No dynamic priorities - park disabled */
388 opba->pr = 0x11;
389 }
390
391 static void ppc4xx_opba_init(hwaddr base)
392 {
393 ppc4xx_opba_t *opba;
394
395 opba = g_malloc0(sizeof(ppc4xx_opba_t));
396 #ifdef DEBUG_OPBA
397 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
398 #endif
399 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
400 memory_region_add_subregion(get_system_memory(), base, &opba->io);
401 qemu_register_reset(ppc4xx_opba_reset, opba);
402 }
403
404 /*****************************************************************************/
405 /* Code decompression controller */
406 /* XXX: TODO */
407
408 /*****************************************************************************/
409 /* Peripheral controller */
410 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
411 struct ppc4xx_ebc_t {
412 uint32_t addr;
413 uint32_t bcr[8];
414 uint32_t bap[8];
415 uint32_t bear;
416 uint32_t besr0;
417 uint32_t besr1;
418 uint32_t cfg;
419 };
420
421 enum {
422 EBC0_CFGADDR = 0x012,
423 EBC0_CFGDATA = 0x013,
424 };
425
426 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
427 {
428 ppc4xx_ebc_t *ebc;
429 uint32_t ret;
430
431 ebc = opaque;
432 switch (dcrn) {
433 case EBC0_CFGADDR:
434 ret = ebc->addr;
435 break;
436 case EBC0_CFGDATA:
437 switch (ebc->addr) {
438 case 0x00: /* B0CR */
439 ret = ebc->bcr[0];
440 break;
441 case 0x01: /* B1CR */
442 ret = ebc->bcr[1];
443 break;
444 case 0x02: /* B2CR */
445 ret = ebc->bcr[2];
446 break;
447 case 0x03: /* B3CR */
448 ret = ebc->bcr[3];
449 break;
450 case 0x04: /* B4CR */
451 ret = ebc->bcr[4];
452 break;
453 case 0x05: /* B5CR */
454 ret = ebc->bcr[5];
455 break;
456 case 0x06: /* B6CR */
457 ret = ebc->bcr[6];
458 break;
459 case 0x07: /* B7CR */
460 ret = ebc->bcr[7];
461 break;
462 case 0x10: /* B0AP */
463 ret = ebc->bap[0];
464 break;
465 case 0x11: /* B1AP */
466 ret = ebc->bap[1];
467 break;
468 case 0x12: /* B2AP */
469 ret = ebc->bap[2];
470 break;
471 case 0x13: /* B3AP */
472 ret = ebc->bap[3];
473 break;
474 case 0x14: /* B4AP */
475 ret = ebc->bap[4];
476 break;
477 case 0x15: /* B5AP */
478 ret = ebc->bap[5];
479 break;
480 case 0x16: /* B6AP */
481 ret = ebc->bap[6];
482 break;
483 case 0x17: /* B7AP */
484 ret = ebc->bap[7];
485 break;
486 case 0x20: /* BEAR */
487 ret = ebc->bear;
488 break;
489 case 0x21: /* BESR0 */
490 ret = ebc->besr0;
491 break;
492 case 0x22: /* BESR1 */
493 ret = ebc->besr1;
494 break;
495 case 0x23: /* CFG */
496 ret = ebc->cfg;
497 break;
498 default:
499 ret = 0x00000000;
500 break;
501 }
502 break;
503 default:
504 ret = 0x00000000;
505 break;
506 }
507
508 return ret;
509 }
510
511 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
512 {
513 ppc4xx_ebc_t *ebc;
514
515 ebc = opaque;
516 switch (dcrn) {
517 case EBC0_CFGADDR:
518 ebc->addr = val;
519 break;
520 case EBC0_CFGDATA:
521 switch (ebc->addr) {
522 case 0x00: /* B0CR */
523 break;
524 case 0x01: /* B1CR */
525 break;
526 case 0x02: /* B2CR */
527 break;
528 case 0x03: /* B3CR */
529 break;
530 case 0x04: /* B4CR */
531 break;
532 case 0x05: /* B5CR */
533 break;
534 case 0x06: /* B6CR */
535 break;
536 case 0x07: /* B7CR */
537 break;
538 case 0x10: /* B0AP */
539 break;
540 case 0x11: /* B1AP */
541 break;
542 case 0x12: /* B2AP */
543 break;
544 case 0x13: /* B3AP */
545 break;
546 case 0x14: /* B4AP */
547 break;
548 case 0x15: /* B5AP */
549 break;
550 case 0x16: /* B6AP */
551 break;
552 case 0x17: /* B7AP */
553 break;
554 case 0x20: /* BEAR */
555 break;
556 case 0x21: /* BESR0 */
557 break;
558 case 0x22: /* BESR1 */
559 break;
560 case 0x23: /* CFG */
561 break;
562 default:
563 break;
564 }
565 break;
566 default:
567 break;
568 }
569 }
570
571 static void ebc_reset (void *opaque)
572 {
573 ppc4xx_ebc_t *ebc;
574 int i;
575
576 ebc = opaque;
577 ebc->addr = 0x00000000;
578 ebc->bap[0] = 0x7F8FFE80;
579 ebc->bcr[0] = 0xFFE28000;
580 for (i = 0; i < 8; i++) {
581 ebc->bap[i] = 0x00000000;
582 ebc->bcr[i] = 0x00000000;
583 }
584 ebc->besr0 = 0x00000000;
585 ebc->besr1 = 0x00000000;
586 ebc->cfg = 0x80400000;
587 }
588
589 static void ppc405_ebc_init(CPUPPCState *env)
590 {
591 ppc4xx_ebc_t *ebc;
592
593 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
594 qemu_register_reset(&ebc_reset, ebc);
595 ppc_dcr_register(env, EBC0_CFGADDR,
596 ebc, &dcr_read_ebc, &dcr_write_ebc);
597 ppc_dcr_register(env, EBC0_CFGDATA,
598 ebc, &dcr_read_ebc, &dcr_write_ebc);
599 }
600
601 /*****************************************************************************/
602 /* DMA controller */
603 enum {
604 DMA0_CR0 = 0x100,
605 DMA0_CT0 = 0x101,
606 DMA0_DA0 = 0x102,
607 DMA0_SA0 = 0x103,
608 DMA0_SG0 = 0x104,
609 DMA0_CR1 = 0x108,
610 DMA0_CT1 = 0x109,
611 DMA0_DA1 = 0x10A,
612 DMA0_SA1 = 0x10B,
613 DMA0_SG1 = 0x10C,
614 DMA0_CR2 = 0x110,
615 DMA0_CT2 = 0x111,
616 DMA0_DA2 = 0x112,
617 DMA0_SA2 = 0x113,
618 DMA0_SG2 = 0x114,
619 DMA0_CR3 = 0x118,
620 DMA0_CT3 = 0x119,
621 DMA0_DA3 = 0x11A,
622 DMA0_SA3 = 0x11B,
623 DMA0_SG3 = 0x11C,
624 DMA0_SR = 0x120,
625 DMA0_SGC = 0x123,
626 DMA0_SLP = 0x125,
627 DMA0_POL = 0x126,
628 };
629
630 typedef struct ppc405_dma_t ppc405_dma_t;
631 struct ppc405_dma_t {
632 qemu_irq irqs[4];
633 uint32_t cr[4];
634 uint32_t ct[4];
635 uint32_t da[4];
636 uint32_t sa[4];
637 uint32_t sg[4];
638 uint32_t sr;
639 uint32_t sgc;
640 uint32_t slp;
641 uint32_t pol;
642 };
643
644 static uint32_t dcr_read_dma (void *opaque, int dcrn)
645 {
646 return 0;
647 }
648
649 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
650 {
651 }
652
653 static void ppc405_dma_reset (void *opaque)
654 {
655 ppc405_dma_t *dma;
656 int i;
657
658 dma = opaque;
659 for (i = 0; i < 4; i++) {
660 dma->cr[i] = 0x00000000;
661 dma->ct[i] = 0x00000000;
662 dma->da[i] = 0x00000000;
663 dma->sa[i] = 0x00000000;
664 dma->sg[i] = 0x00000000;
665 }
666 dma->sr = 0x00000000;
667 dma->sgc = 0x00000000;
668 dma->slp = 0x7C000000;
669 dma->pol = 0x00000000;
670 }
671
672 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
673 {
674 ppc405_dma_t *dma;
675
676 dma = g_malloc0(sizeof(ppc405_dma_t));
677 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
678 qemu_register_reset(&ppc405_dma_reset, dma);
679 ppc_dcr_register(env, DMA0_CR0,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_CT0,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_DA0,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_SA0,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_SG0,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_CR1,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_CT1,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_DA1,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_SA1,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_SG1,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_CR2,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_CT2,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_DA2,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_SA2,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_SG2,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_CR3,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_CT3,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_DA3,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_SA3,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_SG3,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 ppc_dcr_register(env, DMA0_SR,
720 dma, &dcr_read_dma, &dcr_write_dma);
721 ppc_dcr_register(env, DMA0_SGC,
722 dma, &dcr_read_dma, &dcr_write_dma);
723 ppc_dcr_register(env, DMA0_SLP,
724 dma, &dcr_read_dma, &dcr_write_dma);
725 ppc_dcr_register(env, DMA0_POL,
726 dma, &dcr_read_dma, &dcr_write_dma);
727 }
728
729 /*****************************************************************************/
730 /* GPIO */
731 typedef struct ppc405_gpio_t ppc405_gpio_t;
732 struct ppc405_gpio_t {
733 MemoryRegion io;
734 uint32_t or;
735 uint32_t tcr;
736 uint32_t osrh;
737 uint32_t osrl;
738 uint32_t tsrh;
739 uint32_t tsrl;
740 uint32_t odr;
741 uint32_t ir;
742 uint32_t rr1;
743 uint32_t isr1h;
744 uint32_t isr1l;
745 };
746
747 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
748 {
749 #ifdef DEBUG_GPIO
750 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
751 #endif
752
753 return 0;
754 }
755
756 static void ppc405_gpio_writeb (void *opaque,
757 hwaddr addr, uint32_t value)
758 {
759 #ifdef DEBUG_GPIO
760 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
761 value);
762 #endif
763 }
764
765 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
766 {
767 #ifdef DEBUG_GPIO
768 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
769 #endif
770
771 return 0;
772 }
773
774 static void ppc405_gpio_writew (void *opaque,
775 hwaddr addr, uint32_t value)
776 {
777 #ifdef DEBUG_GPIO
778 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
779 value);
780 #endif
781 }
782
783 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
784 {
785 #ifdef DEBUG_GPIO
786 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
787 #endif
788
789 return 0;
790 }
791
792 static void ppc405_gpio_writel (void *opaque,
793 hwaddr addr, uint32_t value)
794 {
795 #ifdef DEBUG_GPIO
796 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
797 value);
798 #endif
799 }
800
801 static const MemoryRegionOps ppc405_gpio_ops = {
802 .old_mmio = {
803 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
804 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
805 },
806 .endianness = DEVICE_NATIVE_ENDIAN,
807 };
808
809 static void ppc405_gpio_reset (void *opaque)
810 {
811 }
812
813 static void ppc405_gpio_init(hwaddr base)
814 {
815 ppc405_gpio_t *gpio;
816
817 gpio = g_malloc0(sizeof(ppc405_gpio_t));
818 #ifdef DEBUG_GPIO
819 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
820 #endif
821 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
822 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
823 qemu_register_reset(&ppc405_gpio_reset, gpio);
824 }
825
826 /*****************************************************************************/
827 /* On Chip Memory */
828 enum {
829 OCM0_ISARC = 0x018,
830 OCM0_ISACNTL = 0x019,
831 OCM0_DSARC = 0x01A,
832 OCM0_DSACNTL = 0x01B,
833 };
834
835 typedef struct ppc405_ocm_t ppc405_ocm_t;
836 struct ppc405_ocm_t {
837 MemoryRegion ram;
838 MemoryRegion isarc_ram;
839 MemoryRegion dsarc_ram;
840 uint32_t isarc;
841 uint32_t isacntl;
842 uint32_t dsarc;
843 uint32_t dsacntl;
844 };
845
846 static void ocm_update_mappings (ppc405_ocm_t *ocm,
847 uint32_t isarc, uint32_t isacntl,
848 uint32_t dsarc, uint32_t dsacntl)
849 {
850 #ifdef DEBUG_OCM
851 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
852 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
853 " (%08" PRIx32 " %08" PRIx32 ")\n",
854 isarc, isacntl, dsarc, dsacntl,
855 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
856 #endif
857 if (ocm->isarc != isarc ||
858 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
859 if (ocm->isacntl & 0x80000000) {
860 /* Unmap previously assigned memory region */
861 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
862 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
863 }
864 if (isacntl & 0x80000000) {
865 /* Map new instruction memory region */
866 #ifdef DEBUG_OCM
867 printf("OCM map ISA %08" PRIx32 "\n", isarc);
868 #endif
869 memory_region_add_subregion(get_system_memory(), isarc,
870 &ocm->isarc_ram);
871 }
872 }
873 if (ocm->dsarc != dsarc ||
874 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
875 if (ocm->dsacntl & 0x80000000) {
876 /* Beware not to unmap the region we just mapped */
877 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
878 /* Unmap previously assigned memory region */
879 #ifdef DEBUG_OCM
880 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
881 #endif
882 memory_region_del_subregion(get_system_memory(),
883 &ocm->dsarc_ram);
884 }
885 }
886 if (dsacntl & 0x80000000) {
887 /* Beware not to remap the region we just mapped */
888 if (!(isacntl & 0x80000000) || dsarc != isarc) {
889 /* Map new data memory region */
890 #ifdef DEBUG_OCM
891 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
892 #endif
893 memory_region_add_subregion(get_system_memory(), dsarc,
894 &ocm->dsarc_ram);
895 }
896 }
897 }
898 }
899
900 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
901 {
902 ppc405_ocm_t *ocm;
903 uint32_t ret;
904
905 ocm = opaque;
906 switch (dcrn) {
907 case OCM0_ISARC:
908 ret = ocm->isarc;
909 break;
910 case OCM0_ISACNTL:
911 ret = ocm->isacntl;
912 break;
913 case OCM0_DSARC:
914 ret = ocm->dsarc;
915 break;
916 case OCM0_DSACNTL:
917 ret = ocm->dsacntl;
918 break;
919 default:
920 ret = 0;
921 break;
922 }
923
924 return ret;
925 }
926
927 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
928 {
929 ppc405_ocm_t *ocm;
930 uint32_t isarc, dsarc, isacntl, dsacntl;
931
932 ocm = opaque;
933 isarc = ocm->isarc;
934 dsarc = ocm->dsarc;
935 isacntl = ocm->isacntl;
936 dsacntl = ocm->dsacntl;
937 switch (dcrn) {
938 case OCM0_ISARC:
939 isarc = val & 0xFC000000;
940 break;
941 case OCM0_ISACNTL:
942 isacntl = val & 0xC0000000;
943 break;
944 case OCM0_DSARC:
945 isarc = val & 0xFC000000;
946 break;
947 case OCM0_DSACNTL:
948 isacntl = val & 0xC0000000;
949 break;
950 }
951 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
952 ocm->isarc = isarc;
953 ocm->dsarc = dsarc;
954 ocm->isacntl = isacntl;
955 ocm->dsacntl = dsacntl;
956 }
957
958 static void ocm_reset (void *opaque)
959 {
960 ppc405_ocm_t *ocm;
961 uint32_t isarc, dsarc, isacntl, dsacntl;
962
963 ocm = opaque;
964 isarc = 0x00000000;
965 isacntl = 0x00000000;
966 dsarc = 0x00000000;
967 dsacntl = 0x00000000;
968 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
969 ocm->isarc = isarc;
970 ocm->dsarc = dsarc;
971 ocm->isacntl = isacntl;
972 ocm->dsacntl = dsacntl;
973 }
974
975 static void ppc405_ocm_init(CPUPPCState *env)
976 {
977 ppc405_ocm_t *ocm;
978
979 ocm = g_malloc0(sizeof(ppc405_ocm_t));
980 /* XXX: Size is 4096 or 0x04000000 */
981 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096,
982 &error_fatal);
983 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram,
984 0, 4096);
985 qemu_register_reset(&ocm_reset, ocm);
986 ppc_dcr_register(env, OCM0_ISARC,
987 ocm, &dcr_read_ocm, &dcr_write_ocm);
988 ppc_dcr_register(env, OCM0_ISACNTL,
989 ocm, &dcr_read_ocm, &dcr_write_ocm);
990 ppc_dcr_register(env, OCM0_DSARC,
991 ocm, &dcr_read_ocm, &dcr_write_ocm);
992 ppc_dcr_register(env, OCM0_DSACNTL,
993 ocm, &dcr_read_ocm, &dcr_write_ocm);
994 }
995
996 /*****************************************************************************/
997 /* I2C controller */
998 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
999 struct ppc4xx_i2c_t {
1000 qemu_irq irq;
1001 MemoryRegion iomem;
1002 uint8_t mdata;
1003 uint8_t lmadr;
1004 uint8_t hmadr;
1005 uint8_t cntl;
1006 uint8_t mdcntl;
1007 uint8_t sts;
1008 uint8_t extsts;
1009 uint8_t sdata;
1010 uint8_t lsadr;
1011 uint8_t hsadr;
1012 uint8_t clkdiv;
1013 uint8_t intrmsk;
1014 uint8_t xfrcnt;
1015 uint8_t xtcntlss;
1016 uint8_t directcntl;
1017 };
1018
1019 static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
1020 {
1021 ppc4xx_i2c_t *i2c;
1022 uint32_t ret;
1023
1024 #ifdef DEBUG_I2C
1025 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1026 #endif
1027 i2c = opaque;
1028 switch (addr) {
1029 case 0x00:
1030 // i2c_readbyte(&i2c->mdata);
1031 ret = i2c->mdata;
1032 break;
1033 case 0x02:
1034 ret = i2c->sdata;
1035 break;
1036 case 0x04:
1037 ret = i2c->lmadr;
1038 break;
1039 case 0x05:
1040 ret = i2c->hmadr;
1041 break;
1042 case 0x06:
1043 ret = i2c->cntl;
1044 break;
1045 case 0x07:
1046 ret = i2c->mdcntl;
1047 break;
1048 case 0x08:
1049 ret = i2c->sts;
1050 break;
1051 case 0x09:
1052 ret = i2c->extsts;
1053 break;
1054 case 0x0A:
1055 ret = i2c->lsadr;
1056 break;
1057 case 0x0B:
1058 ret = i2c->hsadr;
1059 break;
1060 case 0x0C:
1061 ret = i2c->clkdiv;
1062 break;
1063 case 0x0D:
1064 ret = i2c->intrmsk;
1065 break;
1066 case 0x0E:
1067 ret = i2c->xfrcnt;
1068 break;
1069 case 0x0F:
1070 ret = i2c->xtcntlss;
1071 break;
1072 case 0x10:
1073 ret = i2c->directcntl;
1074 break;
1075 default:
1076 ret = 0x00;
1077 break;
1078 }
1079 #ifdef DEBUG_I2C
1080 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1081 #endif
1082
1083 return ret;
1084 }
1085
1086 static void ppc4xx_i2c_writeb (void *opaque,
1087 hwaddr addr, uint32_t value)
1088 {
1089 ppc4xx_i2c_t *i2c;
1090
1091 #ifdef DEBUG_I2C
1092 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1093 value);
1094 #endif
1095 i2c = opaque;
1096 switch (addr) {
1097 case 0x00:
1098 i2c->mdata = value;
1099 // i2c_sendbyte(&i2c->mdata);
1100 break;
1101 case 0x02:
1102 i2c->sdata = value;
1103 break;
1104 case 0x04:
1105 i2c->lmadr = value;
1106 break;
1107 case 0x05:
1108 i2c->hmadr = value;
1109 break;
1110 case 0x06:
1111 i2c->cntl = value;
1112 break;
1113 case 0x07:
1114 i2c->mdcntl = value & 0xDF;
1115 break;
1116 case 0x08:
1117 i2c->sts &= ~(value & 0x0A);
1118 break;
1119 case 0x09:
1120 i2c->extsts &= ~(value & 0x8F);
1121 break;
1122 case 0x0A:
1123 i2c->lsadr = value;
1124 break;
1125 case 0x0B:
1126 i2c->hsadr = value;
1127 break;
1128 case 0x0C:
1129 i2c->clkdiv = value;
1130 break;
1131 case 0x0D:
1132 i2c->intrmsk = value;
1133 break;
1134 case 0x0E:
1135 i2c->xfrcnt = value & 0x77;
1136 break;
1137 case 0x0F:
1138 i2c->xtcntlss = value;
1139 break;
1140 case 0x10:
1141 i2c->directcntl = value & 0x7;
1142 break;
1143 }
1144 }
1145
1146 static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
1147 {
1148 uint32_t ret;
1149
1150 #ifdef DEBUG_I2C
1151 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1152 #endif
1153 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1154 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1155
1156 return ret;
1157 }
1158
1159 static void ppc4xx_i2c_writew (void *opaque,
1160 hwaddr addr, uint32_t value)
1161 {
1162 #ifdef DEBUG_I2C
1163 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1164 value);
1165 #endif
1166 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1167 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1168 }
1169
1170 static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
1171 {
1172 uint32_t ret;
1173
1174 #ifdef DEBUG_I2C
1175 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1176 #endif
1177 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1178 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1179 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1180 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1181
1182 return ret;
1183 }
1184
1185 static void ppc4xx_i2c_writel (void *opaque,
1186 hwaddr addr, uint32_t value)
1187 {
1188 #ifdef DEBUG_I2C
1189 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1190 value);
1191 #endif
1192 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1193 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1194 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1195 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1196 }
1197
1198 static const MemoryRegionOps i2c_ops = {
1199 .old_mmio = {
1200 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1201 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1202 },
1203 .endianness = DEVICE_NATIVE_ENDIAN,
1204 };
1205
1206 static void ppc4xx_i2c_reset (void *opaque)
1207 {
1208 ppc4xx_i2c_t *i2c;
1209
1210 i2c = opaque;
1211 i2c->mdata = 0x00;
1212 i2c->sdata = 0x00;
1213 i2c->cntl = 0x00;
1214 i2c->mdcntl = 0x00;
1215 i2c->sts = 0x00;
1216 i2c->extsts = 0x00;
1217 i2c->clkdiv = 0x00;
1218 i2c->xfrcnt = 0x00;
1219 i2c->directcntl = 0x0F;
1220 }
1221
1222 static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
1223 {
1224 ppc4xx_i2c_t *i2c;
1225
1226 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1227 i2c->irq = irq;
1228 #ifdef DEBUG_I2C
1229 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1230 #endif
1231 memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
1232 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1233 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1234 }
1235
1236 /*****************************************************************************/
1237 /* General purpose timers */
1238 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1239 struct ppc4xx_gpt_t {
1240 MemoryRegion iomem;
1241 int64_t tb_offset;
1242 uint32_t tb_freq;
1243 QEMUTimer *timer;
1244 qemu_irq irqs[5];
1245 uint32_t oe;
1246 uint32_t ol;
1247 uint32_t im;
1248 uint32_t is;
1249 uint32_t ie;
1250 uint32_t comp[5];
1251 uint32_t mask[5];
1252 };
1253
1254 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1255 {
1256 #ifdef DEBUG_GPT
1257 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1258 #endif
1259 /* XXX: generate a bus fault */
1260 return -1;
1261 }
1262
1263 static void ppc4xx_gpt_writeb (void *opaque,
1264 hwaddr addr, uint32_t value)
1265 {
1266 #ifdef DEBUG_I2C
1267 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1268 value);
1269 #endif
1270 /* XXX: generate a bus fault */
1271 }
1272
1273 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1274 {
1275 #ifdef DEBUG_GPT
1276 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1277 #endif
1278 /* XXX: generate a bus fault */
1279 return -1;
1280 }
1281
1282 static void ppc4xx_gpt_writew (void *opaque,
1283 hwaddr addr, uint32_t value)
1284 {
1285 #ifdef DEBUG_I2C
1286 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1287 value);
1288 #endif
1289 /* XXX: generate a bus fault */
1290 }
1291
1292 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1293 {
1294 /* XXX: TODO */
1295 return 0;
1296 }
1297
1298 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1299 {
1300 /* XXX: TODO */
1301 }
1302
1303 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1304 {
1305 uint32_t mask;
1306 int i;
1307
1308 mask = 0x80000000;
1309 for (i = 0; i < 5; i++) {
1310 if (gpt->oe & mask) {
1311 /* Output is enabled */
1312 if (ppc4xx_gpt_compare(gpt, i)) {
1313 /* Comparison is OK */
1314 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1315 } else {
1316 /* Comparison is KO */
1317 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1318 }
1319 }
1320 mask = mask >> 1;
1321 }
1322 }
1323
1324 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1325 {
1326 uint32_t mask;
1327 int i;
1328
1329 mask = 0x00008000;
1330 for (i = 0; i < 5; i++) {
1331 if (gpt->is & gpt->im & mask)
1332 qemu_irq_raise(gpt->irqs[i]);
1333 else
1334 qemu_irq_lower(gpt->irqs[i]);
1335 mask = mask >> 1;
1336 }
1337 }
1338
1339 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1340 {
1341 /* XXX: TODO */
1342 }
1343
1344 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1345 {
1346 ppc4xx_gpt_t *gpt;
1347 uint32_t ret;
1348 int idx;
1349
1350 #ifdef DEBUG_GPT
1351 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1352 #endif
1353 gpt = opaque;
1354 switch (addr) {
1355 case 0x00:
1356 /* Time base counter */
1357 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1358 gpt->tb_freq, NANOSECONDS_PER_SECOND);
1359 break;
1360 case 0x10:
1361 /* Output enable */
1362 ret = gpt->oe;
1363 break;
1364 case 0x14:
1365 /* Output level */
1366 ret = gpt->ol;
1367 break;
1368 case 0x18:
1369 /* Interrupt mask */
1370 ret = gpt->im;
1371 break;
1372 case 0x1C:
1373 case 0x20:
1374 /* Interrupt status */
1375 ret = gpt->is;
1376 break;
1377 case 0x24:
1378 /* Interrupt enable */
1379 ret = gpt->ie;
1380 break;
1381 case 0x80 ... 0x90:
1382 /* Compare timer */
1383 idx = (addr - 0x80) >> 2;
1384 ret = gpt->comp[idx];
1385 break;
1386 case 0xC0 ... 0xD0:
1387 /* Compare mask */
1388 idx = (addr - 0xC0) >> 2;
1389 ret = gpt->mask[idx];
1390 break;
1391 default:
1392 ret = -1;
1393 break;
1394 }
1395
1396 return ret;
1397 }
1398
1399 static void ppc4xx_gpt_writel (void *opaque,
1400 hwaddr addr, uint32_t value)
1401 {
1402 ppc4xx_gpt_t *gpt;
1403 int idx;
1404
1405 #ifdef DEBUG_I2C
1406 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1407 value);
1408 #endif
1409 gpt = opaque;
1410 switch (addr) {
1411 case 0x00:
1412 /* Time base counter */
1413 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq)
1414 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1415 ppc4xx_gpt_compute_timer(gpt);
1416 break;
1417 case 0x10:
1418 /* Output enable */
1419 gpt->oe = value & 0xF8000000;
1420 ppc4xx_gpt_set_outputs(gpt);
1421 break;
1422 case 0x14:
1423 /* Output level */
1424 gpt->ol = value & 0xF8000000;
1425 ppc4xx_gpt_set_outputs(gpt);
1426 break;
1427 case 0x18:
1428 /* Interrupt mask */
1429 gpt->im = value & 0x0000F800;
1430 break;
1431 case 0x1C:
1432 /* Interrupt status set */
1433 gpt->is |= value & 0x0000F800;
1434 ppc4xx_gpt_set_irqs(gpt);
1435 break;
1436 case 0x20:
1437 /* Interrupt status clear */
1438 gpt->is &= ~(value & 0x0000F800);
1439 ppc4xx_gpt_set_irqs(gpt);
1440 break;
1441 case 0x24:
1442 /* Interrupt enable */
1443 gpt->ie = value & 0x0000F800;
1444 ppc4xx_gpt_set_irqs(gpt);
1445 break;
1446 case 0x80 ... 0x90:
1447 /* Compare timer */
1448 idx = (addr - 0x80) >> 2;
1449 gpt->comp[idx] = value & 0xF8000000;
1450 ppc4xx_gpt_compute_timer(gpt);
1451 break;
1452 case 0xC0 ... 0xD0:
1453 /* Compare mask */
1454 idx = (addr - 0xC0) >> 2;
1455 gpt->mask[idx] = value & 0xF8000000;
1456 ppc4xx_gpt_compute_timer(gpt);
1457 break;
1458 }
1459 }
1460
1461 static const MemoryRegionOps gpt_ops = {
1462 .old_mmio = {
1463 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1464 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1465 },
1466 .endianness = DEVICE_NATIVE_ENDIAN,
1467 };
1468
1469 static void ppc4xx_gpt_cb (void *opaque)
1470 {
1471 ppc4xx_gpt_t *gpt;
1472
1473 gpt = opaque;
1474 ppc4xx_gpt_set_irqs(gpt);
1475 ppc4xx_gpt_set_outputs(gpt);
1476 ppc4xx_gpt_compute_timer(gpt);
1477 }
1478
1479 static void ppc4xx_gpt_reset (void *opaque)
1480 {
1481 ppc4xx_gpt_t *gpt;
1482 int i;
1483
1484 gpt = opaque;
1485 timer_del(gpt->timer);
1486 gpt->oe = 0x00000000;
1487 gpt->ol = 0x00000000;
1488 gpt->im = 0x00000000;
1489 gpt->is = 0x00000000;
1490 gpt->ie = 0x00000000;
1491 for (i = 0; i < 5; i++) {
1492 gpt->comp[i] = 0x00000000;
1493 gpt->mask[i] = 0x00000000;
1494 }
1495 }
1496
1497 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1498 {
1499 ppc4xx_gpt_t *gpt;
1500 int i;
1501
1502 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1503 for (i = 0; i < 5; i++) {
1504 gpt->irqs[i] = irqs[i];
1505 }
1506 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1507 #ifdef DEBUG_GPT
1508 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1509 #endif
1510 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1511 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1512 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1513 }
1514
1515 /*****************************************************************************/
1516 /* MAL */
1517 enum {
1518 MAL0_CFG = 0x180,
1519 MAL0_ESR = 0x181,
1520 MAL0_IER = 0x182,
1521 MAL0_TXCASR = 0x184,
1522 MAL0_TXCARR = 0x185,
1523 MAL0_TXEOBISR = 0x186,
1524 MAL0_TXDEIR = 0x187,
1525 MAL0_RXCASR = 0x190,
1526 MAL0_RXCARR = 0x191,
1527 MAL0_RXEOBISR = 0x192,
1528 MAL0_RXDEIR = 0x193,
1529 MAL0_TXCTP0R = 0x1A0,
1530 MAL0_TXCTP1R = 0x1A1,
1531 MAL0_TXCTP2R = 0x1A2,
1532 MAL0_TXCTP3R = 0x1A3,
1533 MAL0_RXCTP0R = 0x1C0,
1534 MAL0_RXCTP1R = 0x1C1,
1535 MAL0_RCBS0 = 0x1E0,
1536 MAL0_RCBS1 = 0x1E1,
1537 };
1538
1539 typedef struct ppc40x_mal_t ppc40x_mal_t;
1540 struct ppc40x_mal_t {
1541 qemu_irq irqs[4];
1542 uint32_t cfg;
1543 uint32_t esr;
1544 uint32_t ier;
1545 uint32_t txcasr;
1546 uint32_t txcarr;
1547 uint32_t txeobisr;
1548 uint32_t txdeir;
1549 uint32_t rxcasr;
1550 uint32_t rxcarr;
1551 uint32_t rxeobisr;
1552 uint32_t rxdeir;
1553 uint32_t txctpr[4];
1554 uint32_t rxctpr[2];
1555 uint32_t rcbs[2];
1556 };
1557
1558 static void ppc40x_mal_reset (void *opaque);
1559
1560 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1561 {
1562 ppc40x_mal_t *mal;
1563 uint32_t ret;
1564
1565 mal = opaque;
1566 switch (dcrn) {
1567 case MAL0_CFG:
1568 ret = mal->cfg;
1569 break;
1570 case MAL0_ESR:
1571 ret = mal->esr;
1572 break;
1573 case MAL0_IER:
1574 ret = mal->ier;
1575 break;
1576 case MAL0_TXCASR:
1577 ret = mal->txcasr;
1578 break;
1579 case MAL0_TXCARR:
1580 ret = mal->txcarr;
1581 break;
1582 case MAL0_TXEOBISR:
1583 ret = mal->txeobisr;
1584 break;
1585 case MAL0_TXDEIR:
1586 ret = mal->txdeir;
1587 break;
1588 case MAL0_RXCASR:
1589 ret = mal->rxcasr;
1590 break;
1591 case MAL0_RXCARR:
1592 ret = mal->rxcarr;
1593 break;
1594 case MAL0_RXEOBISR:
1595 ret = mal->rxeobisr;
1596 break;
1597 case MAL0_RXDEIR:
1598 ret = mal->rxdeir;
1599 break;
1600 case MAL0_TXCTP0R:
1601 ret = mal->txctpr[0];
1602 break;
1603 case MAL0_TXCTP1R:
1604 ret = mal->txctpr[1];
1605 break;
1606 case MAL0_TXCTP2R:
1607 ret = mal->txctpr[2];
1608 break;
1609 case MAL0_TXCTP3R:
1610 ret = mal->txctpr[3];
1611 break;
1612 case MAL0_RXCTP0R:
1613 ret = mal->rxctpr[0];
1614 break;
1615 case MAL0_RXCTP1R:
1616 ret = mal->rxctpr[1];
1617 break;
1618 case MAL0_RCBS0:
1619 ret = mal->rcbs[0];
1620 break;
1621 case MAL0_RCBS1:
1622 ret = mal->rcbs[1];
1623 break;
1624 default:
1625 ret = 0;
1626 break;
1627 }
1628
1629 return ret;
1630 }
1631
1632 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1633 {
1634 ppc40x_mal_t *mal;
1635 int idx;
1636
1637 mal = opaque;
1638 switch (dcrn) {
1639 case MAL0_CFG:
1640 if (val & 0x80000000)
1641 ppc40x_mal_reset(mal);
1642 mal->cfg = val & 0x00FFC087;
1643 break;
1644 case MAL0_ESR:
1645 /* Read/clear */
1646 mal->esr &= ~val;
1647 break;
1648 case MAL0_IER:
1649 mal->ier = val & 0x0000001F;
1650 break;
1651 case MAL0_TXCASR:
1652 mal->txcasr = val & 0xF0000000;
1653 break;
1654 case MAL0_TXCARR:
1655 mal->txcarr = val & 0xF0000000;
1656 break;
1657 case MAL0_TXEOBISR:
1658 /* Read/clear */
1659 mal->txeobisr &= ~val;
1660 break;
1661 case MAL0_TXDEIR:
1662 /* Read/clear */
1663 mal->txdeir &= ~val;
1664 break;
1665 case MAL0_RXCASR:
1666 mal->rxcasr = val & 0xC0000000;
1667 break;
1668 case MAL0_RXCARR:
1669 mal->rxcarr = val & 0xC0000000;
1670 break;
1671 case MAL0_RXEOBISR:
1672 /* Read/clear */
1673 mal->rxeobisr &= ~val;
1674 break;
1675 case MAL0_RXDEIR:
1676 /* Read/clear */
1677 mal->rxdeir &= ~val;
1678 break;
1679 case MAL0_TXCTP0R:
1680 idx = 0;
1681 goto update_tx_ptr;
1682 case MAL0_TXCTP1R:
1683 idx = 1;
1684 goto update_tx_ptr;
1685 case MAL0_TXCTP2R:
1686 idx = 2;
1687 goto update_tx_ptr;
1688 case MAL0_TXCTP3R:
1689 idx = 3;
1690 update_tx_ptr:
1691 mal->txctpr[idx] = val;
1692 break;
1693 case MAL0_RXCTP0R:
1694 idx = 0;
1695 goto update_rx_ptr;
1696 case MAL0_RXCTP1R:
1697 idx = 1;
1698 update_rx_ptr:
1699 mal->rxctpr[idx] = val;
1700 break;
1701 case MAL0_RCBS0:
1702 idx = 0;
1703 goto update_rx_size;
1704 case MAL0_RCBS1:
1705 idx = 1;
1706 update_rx_size:
1707 mal->rcbs[idx] = val & 0x000000FF;
1708 break;
1709 }
1710 }
1711
1712 static void ppc40x_mal_reset (void *opaque)
1713 {
1714 ppc40x_mal_t *mal;
1715
1716 mal = opaque;
1717 mal->cfg = 0x0007C000;
1718 mal->esr = 0x00000000;
1719 mal->ier = 0x00000000;
1720 mal->rxcasr = 0x00000000;
1721 mal->rxdeir = 0x00000000;
1722 mal->rxeobisr = 0x00000000;
1723 mal->txcasr = 0x00000000;
1724 mal->txdeir = 0x00000000;
1725 mal->txeobisr = 0x00000000;
1726 }
1727
1728 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
1729 {
1730 ppc40x_mal_t *mal;
1731 int i;
1732
1733 mal = g_malloc0(sizeof(ppc40x_mal_t));
1734 for (i = 0; i < 4; i++)
1735 mal->irqs[i] = irqs[i];
1736 qemu_register_reset(&ppc40x_mal_reset, mal);
1737 ppc_dcr_register(env, MAL0_CFG,
1738 mal, &dcr_read_mal, &dcr_write_mal);
1739 ppc_dcr_register(env, MAL0_ESR,
1740 mal, &dcr_read_mal, &dcr_write_mal);
1741 ppc_dcr_register(env, MAL0_IER,
1742 mal, &dcr_read_mal, &dcr_write_mal);
1743 ppc_dcr_register(env, MAL0_TXCASR,
1744 mal, &dcr_read_mal, &dcr_write_mal);
1745 ppc_dcr_register(env, MAL0_TXCARR,
1746 mal, &dcr_read_mal, &dcr_write_mal);
1747 ppc_dcr_register(env, MAL0_TXEOBISR,
1748 mal, &dcr_read_mal, &dcr_write_mal);
1749 ppc_dcr_register(env, MAL0_TXDEIR,
1750 mal, &dcr_read_mal, &dcr_write_mal);
1751 ppc_dcr_register(env, MAL0_RXCASR,
1752 mal, &dcr_read_mal, &dcr_write_mal);
1753 ppc_dcr_register(env, MAL0_RXCARR,
1754 mal, &dcr_read_mal, &dcr_write_mal);
1755 ppc_dcr_register(env, MAL0_RXEOBISR,
1756 mal, &dcr_read_mal, &dcr_write_mal);
1757 ppc_dcr_register(env, MAL0_RXDEIR,
1758 mal, &dcr_read_mal, &dcr_write_mal);
1759 ppc_dcr_register(env, MAL0_TXCTP0R,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_TXCTP1R,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 ppc_dcr_register(env, MAL0_TXCTP2R,
1764 mal, &dcr_read_mal, &dcr_write_mal);
1765 ppc_dcr_register(env, MAL0_TXCTP3R,
1766 mal, &dcr_read_mal, &dcr_write_mal);
1767 ppc_dcr_register(env, MAL0_RXCTP0R,
1768 mal, &dcr_read_mal, &dcr_write_mal);
1769 ppc_dcr_register(env, MAL0_RXCTP1R,
1770 mal, &dcr_read_mal, &dcr_write_mal);
1771 ppc_dcr_register(env, MAL0_RCBS0,
1772 mal, &dcr_read_mal, &dcr_write_mal);
1773 ppc_dcr_register(env, MAL0_RCBS1,
1774 mal, &dcr_read_mal, &dcr_write_mal);
1775 }
1776
1777 /*****************************************************************************/
1778 /* SPR */
1779 void ppc40x_core_reset(PowerPCCPU *cpu)
1780 {
1781 CPUPPCState *env = &cpu->env;
1782 target_ulong dbsr;
1783
1784 printf("Reset PowerPC core\n");
1785 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1786 dbsr = env->spr[SPR_40x_DBSR];
1787 dbsr &= ~0x00000300;
1788 dbsr |= 0x00000100;
1789 env->spr[SPR_40x_DBSR] = dbsr;
1790 }
1791
1792 void ppc40x_chip_reset(PowerPCCPU *cpu)
1793 {
1794 CPUPPCState *env = &cpu->env;
1795 target_ulong dbsr;
1796
1797 printf("Reset PowerPC chip\n");
1798 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1799 /* XXX: TODO reset all internal peripherals */
1800 dbsr = env->spr[SPR_40x_DBSR];
1801 dbsr &= ~0x00000300;
1802 dbsr |= 0x00000200;
1803 env->spr[SPR_40x_DBSR] = dbsr;
1804 }
1805
1806 void ppc40x_system_reset(PowerPCCPU *cpu)
1807 {
1808 printf("Reset PowerPC system\n");
1809 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1810 }
1811
1812 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1813 {
1814 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1815
1816 switch ((val >> 28) & 0x3) {
1817 case 0x0:
1818 /* No action */
1819 break;
1820 case 0x1:
1821 /* Core reset */
1822 ppc40x_core_reset(cpu);
1823 break;
1824 case 0x2:
1825 /* Chip reset */
1826 ppc40x_chip_reset(cpu);
1827 break;
1828 case 0x3:
1829 /* System reset */
1830 ppc40x_system_reset(cpu);
1831 break;
1832 }
1833 }
1834
1835 /*****************************************************************************/
1836 /* PowerPC 405CR */
1837 enum {
1838 PPC405CR_CPC0_PLLMR = 0x0B0,
1839 PPC405CR_CPC0_CR0 = 0x0B1,
1840 PPC405CR_CPC0_CR1 = 0x0B2,
1841 PPC405CR_CPC0_PSR = 0x0B4,
1842 PPC405CR_CPC0_JTAGID = 0x0B5,
1843 PPC405CR_CPC0_ER = 0x0B9,
1844 PPC405CR_CPC0_FR = 0x0BA,
1845 PPC405CR_CPC0_SR = 0x0BB,
1846 };
1847
1848 enum {
1849 PPC405CR_CPU_CLK = 0,
1850 PPC405CR_TMR_CLK = 1,
1851 PPC405CR_PLB_CLK = 2,
1852 PPC405CR_SDRAM_CLK = 3,
1853 PPC405CR_OPB_CLK = 4,
1854 PPC405CR_EXT_CLK = 5,
1855 PPC405CR_UART_CLK = 6,
1856 PPC405CR_CLK_NB = 7,
1857 };
1858
1859 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1860 struct ppc405cr_cpc_t {
1861 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1862 uint32_t sysclk;
1863 uint32_t psr;
1864 uint32_t cr0;
1865 uint32_t cr1;
1866 uint32_t jtagid;
1867 uint32_t pllmr;
1868 uint32_t er;
1869 uint32_t fr;
1870 };
1871
1872 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1873 {
1874 uint64_t VCO_out, PLL_out;
1875 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1876 int M, D0, D1, D2;
1877
1878 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1879 if (cpc->pllmr & 0x80000000) {
1880 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1881 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1882 M = D0 * D1 * D2;
1883 VCO_out = (uint64_t)cpc->sysclk * M;
1884 if (VCO_out < 400000000 || VCO_out > 800000000) {
1885 /* PLL cannot lock */
1886 cpc->pllmr &= ~0x80000000;
1887 goto bypass_pll;
1888 }
1889 PLL_out = VCO_out / D2;
1890 } else {
1891 /* Bypass PLL */
1892 bypass_pll:
1893 M = D0;
1894 PLL_out = (uint64_t)cpc->sysclk * M;
1895 }
1896 CPU_clk = PLL_out;
1897 if (cpc->cr1 & 0x00800000)
1898 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1899 else
1900 TMR_clk = CPU_clk;
1901 PLB_clk = CPU_clk / D0;
1902 SDRAM_clk = PLB_clk;
1903 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1904 OPB_clk = PLB_clk / D0;
1905 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1906 EXT_clk = PLB_clk / D0;
1907 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1908 UART_clk = CPU_clk / D0;
1909 /* Setup CPU clocks */
1910 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1911 /* Setup time-base clock */
1912 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1913 /* Setup PLB clock */
1914 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1915 /* Setup SDRAM clock */
1916 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1917 /* Setup OPB clock */
1918 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1919 /* Setup external clock */
1920 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1921 /* Setup UART clock */
1922 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1923 }
1924
1925 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1926 {
1927 ppc405cr_cpc_t *cpc;
1928 uint32_t ret;
1929
1930 cpc = opaque;
1931 switch (dcrn) {
1932 case PPC405CR_CPC0_PLLMR:
1933 ret = cpc->pllmr;
1934 break;
1935 case PPC405CR_CPC0_CR0:
1936 ret = cpc->cr0;
1937 break;
1938 case PPC405CR_CPC0_CR1:
1939 ret = cpc->cr1;
1940 break;
1941 case PPC405CR_CPC0_PSR:
1942 ret = cpc->psr;
1943 break;
1944 case PPC405CR_CPC0_JTAGID:
1945 ret = cpc->jtagid;
1946 break;
1947 case PPC405CR_CPC0_ER:
1948 ret = cpc->er;
1949 break;
1950 case PPC405CR_CPC0_FR:
1951 ret = cpc->fr;
1952 break;
1953 case PPC405CR_CPC0_SR:
1954 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1955 break;
1956 default:
1957 /* Avoid gcc warning */
1958 ret = 0;
1959 break;
1960 }
1961
1962 return ret;
1963 }
1964
1965 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1966 {
1967 ppc405cr_cpc_t *cpc;
1968
1969 cpc = opaque;
1970 switch (dcrn) {
1971 case PPC405CR_CPC0_PLLMR:
1972 cpc->pllmr = val & 0xFFF77C3F;
1973 break;
1974 case PPC405CR_CPC0_CR0:
1975 cpc->cr0 = val & 0x0FFFFFFE;
1976 break;
1977 case PPC405CR_CPC0_CR1:
1978 cpc->cr1 = val & 0x00800000;
1979 break;
1980 case PPC405CR_CPC0_PSR:
1981 /* Read-only */
1982 break;
1983 case PPC405CR_CPC0_JTAGID:
1984 /* Read-only */
1985 break;
1986 case PPC405CR_CPC0_ER:
1987 cpc->er = val & 0xBFFC0000;
1988 break;
1989 case PPC405CR_CPC0_FR:
1990 cpc->fr = val & 0xBFFC0000;
1991 break;
1992 case PPC405CR_CPC0_SR:
1993 /* Read-only */
1994 break;
1995 }
1996 }
1997
1998 static void ppc405cr_cpc_reset (void *opaque)
1999 {
2000 ppc405cr_cpc_t *cpc;
2001 int D;
2002
2003 cpc = opaque;
2004 /* Compute PLLMR value from PSR settings */
2005 cpc->pllmr = 0x80000000;
2006 /* PFWD */
2007 switch ((cpc->psr >> 30) & 3) {
2008 case 0:
2009 /* Bypass */
2010 cpc->pllmr &= ~0x80000000;
2011 break;
2012 case 1:
2013 /* Divide by 3 */
2014 cpc->pllmr |= 5 << 16;
2015 break;
2016 case 2:
2017 /* Divide by 4 */
2018 cpc->pllmr |= 4 << 16;
2019 break;
2020 case 3:
2021 /* Divide by 6 */
2022 cpc->pllmr |= 2 << 16;
2023 break;
2024 }
2025 /* PFBD */
2026 D = (cpc->psr >> 28) & 3;
2027 cpc->pllmr |= (D + 1) << 20;
2028 /* PT */
2029 D = (cpc->psr >> 25) & 7;
2030 switch (D) {
2031 case 0x2:
2032 cpc->pllmr |= 0x13;
2033 break;
2034 case 0x4:
2035 cpc->pllmr |= 0x15;
2036 break;
2037 case 0x5:
2038 cpc->pllmr |= 0x16;
2039 break;
2040 default:
2041 break;
2042 }
2043 /* PDC */
2044 D = (cpc->psr >> 23) & 3;
2045 cpc->pllmr |= D << 26;
2046 /* ODP */
2047 D = (cpc->psr >> 21) & 3;
2048 cpc->pllmr |= D << 10;
2049 /* EBPD */
2050 D = (cpc->psr >> 17) & 3;
2051 cpc->pllmr |= D << 24;
2052 cpc->cr0 = 0x0000003C;
2053 cpc->cr1 = 0x2B0D8800;
2054 cpc->er = 0x00000000;
2055 cpc->fr = 0x00000000;
2056 ppc405cr_clk_setup(cpc);
2057 }
2058
2059 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2060 {
2061 int D;
2062
2063 /* XXX: this should be read from IO pins */
2064 cpc->psr = 0x00000000; /* 8 bits ROM */
2065 /* PFWD */
2066 D = 0x2; /* Divide by 4 */
2067 cpc->psr |= D << 30;
2068 /* PFBD */
2069 D = 0x1; /* Divide by 2 */
2070 cpc->psr |= D << 28;
2071 /* PDC */
2072 D = 0x1; /* Divide by 2 */
2073 cpc->psr |= D << 23;
2074 /* PT */
2075 D = 0x5; /* M = 16 */
2076 cpc->psr |= D << 25;
2077 /* ODP */
2078 D = 0x1; /* Divide by 2 */
2079 cpc->psr |= D << 21;
2080 /* EBDP */
2081 D = 0x2; /* Divide by 4 */
2082 cpc->psr |= D << 17;
2083 }
2084
2085 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
2086 uint32_t sysclk)
2087 {
2088 ppc405cr_cpc_t *cpc;
2089
2090 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2091 memcpy(cpc->clk_setup, clk_setup,
2092 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2093 cpc->sysclk = sysclk;
2094 cpc->jtagid = 0x42051049;
2095 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2096 &dcr_read_crcpc, &dcr_write_crcpc);
2097 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2098 &dcr_read_crcpc, &dcr_write_crcpc);
2099 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2100 &dcr_read_crcpc, &dcr_write_crcpc);
2101 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2102 &dcr_read_crcpc, &dcr_write_crcpc);
2103 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2104 &dcr_read_crcpc, &dcr_write_crcpc);
2105 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2106 &dcr_read_crcpc, &dcr_write_crcpc);
2107 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2108 &dcr_read_crcpc, &dcr_write_crcpc);
2109 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2110 &dcr_read_crcpc, &dcr_write_crcpc);
2111 ppc405cr_clk_init(cpc);
2112 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2113 }
2114
2115 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
2116 MemoryRegion ram_memories[4],
2117 hwaddr ram_bases[4],
2118 hwaddr ram_sizes[4],
2119 uint32_t sysclk, qemu_irq **picp,
2120 int do_init)
2121 {
2122 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2123 qemu_irq dma_irqs[4];
2124 PowerPCCPU *cpu;
2125 CPUPPCState *env;
2126 qemu_irq *pic, *irqs;
2127
2128 memset(clk_setup, 0, sizeof(clk_setup));
2129 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2130 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2131 env = &cpu->env;
2132 /* Memory mapped devices registers */
2133 /* PLB arbitrer */
2134 ppc4xx_plb_init(env);
2135 /* PLB to OPB bridge */
2136 ppc4xx_pob_init(env);
2137 /* OBP arbitrer */
2138 ppc4xx_opba_init(0xef600600);
2139 /* Universal interrupt controller */
2140 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2141 irqs[PPCUIC_OUTPUT_INT] =
2142 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2143 irqs[PPCUIC_OUTPUT_CINT] =
2144 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2145 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2146 *picp = pic;
2147 /* SDRAM controller */
2148 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2149 ram_bases, ram_sizes, do_init);
2150 /* External bus controller */
2151 ppc405_ebc_init(env);
2152 /* DMA controller */
2153 dma_irqs[0] = pic[26];
2154 dma_irqs[1] = pic[25];
2155 dma_irqs[2] = pic[24];
2156 dma_irqs[3] = pic[23];
2157 ppc405_dma_init(env, dma_irqs);
2158 /* Serial ports */
2159 if (serial_hds[0] != NULL) {
2160 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2161 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2162 DEVICE_BIG_ENDIAN);
2163 }
2164 if (serial_hds[1] != NULL) {
2165 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2166 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2167 DEVICE_BIG_ENDIAN);
2168 }
2169 /* IIC controller */
2170 ppc405_i2c_init(0xef600500, pic[2]);
2171 /* GPIO */
2172 ppc405_gpio_init(0xef600700);
2173 /* CPU control */
2174 ppc405cr_cpc_init(env, clk_setup, sysclk);
2175
2176 return env;
2177 }
2178
2179 /*****************************************************************************/
2180 /* PowerPC 405EP */
2181 /* CPU control */
2182 enum {
2183 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2184 PPC405EP_CPC0_BOOT = 0x0F1,
2185 PPC405EP_CPC0_EPCTL = 0x0F3,
2186 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2187 PPC405EP_CPC0_UCR = 0x0F5,
2188 PPC405EP_CPC0_SRR = 0x0F6,
2189 PPC405EP_CPC0_JTAGID = 0x0F7,
2190 PPC405EP_CPC0_PCI = 0x0F9,
2191 #if 0
2192 PPC405EP_CPC0_ER = xxx,
2193 PPC405EP_CPC0_FR = xxx,
2194 PPC405EP_CPC0_SR = xxx,
2195 #endif
2196 };
2197
2198 enum {
2199 PPC405EP_CPU_CLK = 0,
2200 PPC405EP_PLB_CLK = 1,
2201 PPC405EP_OPB_CLK = 2,
2202 PPC405EP_EBC_CLK = 3,
2203 PPC405EP_MAL_CLK = 4,
2204 PPC405EP_PCI_CLK = 5,
2205 PPC405EP_UART0_CLK = 6,
2206 PPC405EP_UART1_CLK = 7,
2207 PPC405EP_CLK_NB = 8,
2208 };
2209
2210 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2211 struct ppc405ep_cpc_t {
2212 uint32_t sysclk;
2213 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2214 uint32_t boot;
2215 uint32_t epctl;
2216 uint32_t pllmr[2];
2217 uint32_t ucr;
2218 uint32_t srr;
2219 uint32_t jtagid;
2220 uint32_t pci;
2221 /* Clock and power management */
2222 uint32_t er;
2223 uint32_t fr;
2224 uint32_t sr;
2225 };
2226
2227 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2228 {
2229 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2230 uint32_t UART0_clk, UART1_clk;
2231 uint64_t VCO_out, PLL_out;
2232 int M, D;
2233
2234 VCO_out = 0;
2235 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2236 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2237 #ifdef DEBUG_CLOCKS_LL
2238 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2239 #endif
2240 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2241 #ifdef DEBUG_CLOCKS_LL
2242 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2243 #endif
2244 VCO_out = (uint64_t)cpc->sysclk * M * D;
2245 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2246 /* Error - unlock the PLL */
2247 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2248 #if 0
2249 cpc->pllmr[1] &= ~0x80000000;
2250 goto pll_bypass;
2251 #endif
2252 }
2253 PLL_out = VCO_out / D;
2254 /* Pretend the PLL is locked */
2255 cpc->boot |= 0x00000001;
2256 } else {
2257 #if 0
2258 pll_bypass:
2259 #endif
2260 PLL_out = cpc->sysclk;
2261 if (cpc->pllmr[1] & 0x40000000) {
2262 /* Pretend the PLL is not locked */
2263 cpc->boot &= ~0x00000001;
2264 }
2265 }
2266 /* Now, compute all other clocks */
2267 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2268 #ifdef DEBUG_CLOCKS_LL
2269 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2270 #endif
2271 CPU_clk = PLL_out / D;
2272 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2273 #ifdef DEBUG_CLOCKS_LL
2274 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2275 #endif
2276 PLB_clk = CPU_clk / D;
2277 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2278 #ifdef DEBUG_CLOCKS_LL
2279 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2280 #endif
2281 OPB_clk = PLB_clk / D;
2282 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2283 #ifdef DEBUG_CLOCKS_LL
2284 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2285 #endif
2286 EBC_clk = PLB_clk / D;
2287 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2288 #ifdef DEBUG_CLOCKS_LL
2289 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2290 #endif
2291 MAL_clk = PLB_clk / D;
2292 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2293 #ifdef DEBUG_CLOCKS_LL
2294 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2295 #endif
2296 PCI_clk = PLB_clk / D;
2297 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2298 #ifdef DEBUG_CLOCKS_LL
2299 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2300 #endif
2301 UART0_clk = PLL_out / D;
2302 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2303 #ifdef DEBUG_CLOCKS_LL
2304 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2305 #endif
2306 UART1_clk = PLL_out / D;
2307 #ifdef DEBUG_CLOCKS
2308 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2309 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2310 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2311 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2312 " UART1 %" PRIu32 "\n",
2313 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2314 UART0_clk, UART1_clk);
2315 #endif
2316 /* Setup CPU clocks */
2317 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2318 /* Setup PLB clock */
2319 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2320 /* Setup OPB clock */
2321 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2322 /* Setup external clock */
2323 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2324 /* Setup MAL clock */
2325 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2326 /* Setup PCI clock */
2327 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2328 /* Setup UART0 clock */
2329 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2330 /* Setup UART1 clock */
2331 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2332 }
2333
2334 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2335 {
2336 ppc405ep_cpc_t *cpc;
2337 uint32_t ret;
2338
2339 cpc = opaque;
2340 switch (dcrn) {
2341 case PPC405EP_CPC0_BOOT:
2342 ret = cpc->boot;
2343 break;
2344 case PPC405EP_CPC0_EPCTL:
2345 ret = cpc->epctl;
2346 break;
2347 case PPC405EP_CPC0_PLLMR0:
2348 ret = cpc->pllmr[0];
2349 break;
2350 case PPC405EP_CPC0_PLLMR1:
2351 ret = cpc->pllmr[1];
2352 break;
2353 case PPC405EP_CPC0_UCR:
2354 ret = cpc->ucr;
2355 break;
2356 case PPC405EP_CPC0_SRR:
2357 ret = cpc->srr;
2358 break;
2359 case PPC405EP_CPC0_JTAGID:
2360 ret = cpc->jtagid;
2361 break;
2362 case PPC405EP_CPC0_PCI:
2363 ret = cpc->pci;
2364 break;
2365 default:
2366 /* Avoid gcc warning */
2367 ret = 0;
2368 break;
2369 }
2370
2371 return ret;
2372 }
2373
2374 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2375 {
2376 ppc405ep_cpc_t *cpc;
2377
2378 cpc = opaque;
2379 switch (dcrn) {
2380 case PPC405EP_CPC0_BOOT:
2381 /* Read-only register */
2382 break;
2383 case PPC405EP_CPC0_EPCTL:
2384 /* Don't care for now */
2385 cpc->epctl = val & 0xC00000F3;
2386 break;
2387 case PPC405EP_CPC0_PLLMR0:
2388 cpc->pllmr[0] = val & 0x00633333;
2389 ppc405ep_compute_clocks(cpc);
2390 break;
2391 case PPC405EP_CPC0_PLLMR1:
2392 cpc->pllmr[1] = val & 0xC0F73FFF;
2393 ppc405ep_compute_clocks(cpc);
2394 break;
2395 case PPC405EP_CPC0_UCR:
2396 /* UART control - don't care for now */
2397 cpc->ucr = val & 0x003F7F7F;
2398 break;
2399 case PPC405EP_CPC0_SRR:
2400 cpc->srr = val;
2401 break;
2402 case PPC405EP_CPC0_JTAGID:
2403 /* Read-only */
2404 break;
2405 case PPC405EP_CPC0_PCI:
2406 cpc->pci = val;
2407 break;
2408 }
2409 }
2410
2411 static void ppc405ep_cpc_reset (void *opaque)
2412 {
2413 ppc405ep_cpc_t *cpc = opaque;
2414
2415 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2416 cpc->epctl = 0x00000000;
2417 cpc->pllmr[0] = 0x00011010;
2418 cpc->pllmr[1] = 0x40000000;
2419 cpc->ucr = 0x00000000;
2420 cpc->srr = 0x00040000;
2421 cpc->pci = 0x00000000;
2422 cpc->er = 0x00000000;
2423 cpc->fr = 0x00000000;
2424 cpc->sr = 0x00000000;
2425 ppc405ep_compute_clocks(cpc);
2426 }
2427
2428 /* XXX: sysclk should be between 25 and 100 MHz */
2429 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
2430 uint32_t sysclk)
2431 {
2432 ppc405ep_cpc_t *cpc;
2433
2434 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2435 memcpy(cpc->clk_setup, clk_setup,
2436 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2437 cpc->jtagid = 0x20267049;
2438 cpc->sysclk = sysclk;
2439 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2440 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2441 &dcr_read_epcpc, &dcr_write_epcpc);
2442 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2443 &dcr_read_epcpc, &dcr_write_epcpc);
2444 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2445 &dcr_read_epcpc, &dcr_write_epcpc);
2446 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2447 &dcr_read_epcpc, &dcr_write_epcpc);
2448 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2449 &dcr_read_epcpc, &dcr_write_epcpc);
2450 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2451 &dcr_read_epcpc, &dcr_write_epcpc);
2452 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2453 &dcr_read_epcpc, &dcr_write_epcpc);
2454 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2455 &dcr_read_epcpc, &dcr_write_epcpc);
2456 #if 0
2457 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2458 &dcr_read_epcpc, &dcr_write_epcpc);
2459 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2460 &dcr_read_epcpc, &dcr_write_epcpc);
2461 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2462 &dcr_read_epcpc, &dcr_write_epcpc);
2463 #endif
2464 }
2465
2466 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
2467 MemoryRegion ram_memories[2],
2468 hwaddr ram_bases[2],
2469 hwaddr ram_sizes[2],
2470 uint32_t sysclk, qemu_irq **picp,
2471 int do_init)
2472 {
2473 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2474 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2475 PowerPCCPU *cpu;
2476 CPUPPCState *env;
2477 qemu_irq *pic, *irqs;
2478
2479 memset(clk_setup, 0, sizeof(clk_setup));
2480 /* init CPUs */
2481 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2482 &tlb_clk_setup, sysclk);
2483 env = &cpu->env;
2484 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2485 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2486 /* Internal devices init */
2487 /* Memory mapped devices registers */
2488 /* PLB arbitrer */
2489 ppc4xx_plb_init(env);
2490 /* PLB to OPB bridge */
2491 ppc4xx_pob_init(env);
2492 /* OBP arbitrer */
2493 ppc4xx_opba_init(0xef600600);
2494 /* Initialize timers */
2495 ppc_booke_timers_init(cpu, sysclk, 0);
2496 /* Universal interrupt controller */
2497 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2498 irqs[PPCUIC_OUTPUT_INT] =
2499 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2500 irqs[PPCUIC_OUTPUT_CINT] =
2501 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2502 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2503 *picp = pic;
2504 /* SDRAM controller */
2505 /* XXX 405EP has no ECC interrupt */
2506 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2507 ram_bases, ram_sizes, do_init);
2508 /* External bus controller */
2509 ppc405_ebc_init(env);
2510 /* DMA controller */
2511 dma_irqs[0] = pic[5];
2512 dma_irqs[1] = pic[6];
2513 dma_irqs[2] = pic[7];
2514 dma_irqs[3] = pic[8];
2515 ppc405_dma_init(env, dma_irqs);
2516 /* IIC controller */
2517 ppc405_i2c_init(0xef600500, pic[2]);
2518 /* GPIO */
2519 ppc405_gpio_init(0xef600700);
2520 /* Serial ports */
2521 if (serial_hds[0] != NULL) {
2522 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2523 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2524 DEVICE_BIG_ENDIAN);
2525 }
2526 if (serial_hds[1] != NULL) {
2527 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2528 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2529 DEVICE_BIG_ENDIAN);
2530 }
2531 /* OCM */
2532 ppc405_ocm_init(env);
2533 /* GPT */
2534 gpt_irqs[0] = pic[19];
2535 gpt_irqs[1] = pic[20];
2536 gpt_irqs[2] = pic[21];
2537 gpt_irqs[3] = pic[22];
2538 gpt_irqs[4] = pic[23];
2539 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2540 /* PCI */
2541 /* Uses pic[3], pic[16], pic[18] */
2542 /* MAL */
2543 mal_irqs[0] = pic[11];
2544 mal_irqs[1] = pic[12];
2545 mal_irqs[2] = pic[13];
2546 mal_irqs[3] = pic[14];
2547 ppc405_mal_init(env, mal_irqs);
2548 /* Ethernet */
2549 /* Uses pic[9], pic[15], pic[17] */
2550 /* CPU control */
2551 ppc405ep_cpc_init(env, clk_setup, sysclk);
2552
2553 return env;
2554 }
AR7 emulation for QEMU