target/xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef XTENSA_CPU_H
  29 #define XTENSA_CPU_H
  30
  31 #define ALIGNED_ONLY
  32 #define TARGET_LONG_BITS 32
  33
  34 #define CPUArchState struct CPUXtensaState
  35
  36 #include "qemu-common.h"
  37 #include "cpu-qom.h"
  38 #include "exec/cpu-defs.h"
  39 #include "fpu/softfloat.h"
  40 #include "xtensa-isa.h"
  41
  42 #define NB_MMU_MODES 4
  43
  44 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  45 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  46 #define TARGET_PAGE_BITS 12
  47
  48 enum {
  49     /* Additional instructions */
  50     XTENSA_OPTION_CODE_DENSITY,
  51     XTENSA_OPTION_LOOP,
  52     XTENSA_OPTION_EXTENDED_L32R,
  53     XTENSA_OPTION_16_BIT_IMUL,
  54     XTENSA_OPTION_32_BIT_IMUL,
  55     XTENSA_OPTION_32_BIT_IMUL_HIGH,
  56     XTENSA_OPTION_32_BIT_IDIV,
  57     XTENSA_OPTION_MAC16,
  58     XTENSA_OPTION_MISC_OP_NSA,
  59     XTENSA_OPTION_MISC_OP_MINMAX,
  60     XTENSA_OPTION_MISC_OP_SEXT,
  61     XTENSA_OPTION_MISC_OP_CLAMPS,
  62     XTENSA_OPTION_COPROCESSOR,
  63     XTENSA_OPTION_BOOLEAN,
  64     XTENSA_OPTION_FP_COPROCESSOR,
  65     XTENSA_OPTION_MP_SYNCHRO,
  66     XTENSA_OPTION_CONDITIONAL_STORE,
  67     XTENSA_OPTION_ATOMCTL,
  68     XTENSA_OPTION_DEPBITS,
  69
  70     /* Interrupts and exceptions */
  71     XTENSA_OPTION_EXCEPTION,
  72     XTENSA_OPTION_RELOCATABLE_VECTOR,
  73     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  74     XTENSA_OPTION_INTERRUPT,
  75     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  76     XTENSA_OPTION_TIMER_INTERRUPT,
  77
  78     /* Local memory */
  79     XTENSA_OPTION_ICACHE,
  80     XTENSA_OPTION_ICACHE_TEST,
  81     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  82     XTENSA_OPTION_DCACHE,
  83     XTENSA_OPTION_DCACHE_TEST,
  84     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  85     XTENSA_OPTION_IRAM,
  86     XTENSA_OPTION_IROM,
  87     XTENSA_OPTION_DRAM,
  88     XTENSA_OPTION_DROM,
  89     XTENSA_OPTION_XLMI,
  90     XTENSA_OPTION_HW_ALIGNMENT,
  91     XTENSA_OPTION_MEMORY_ECC_PARITY,
  92
  93     /* Memory protection and translation */
  94     XTENSA_OPTION_REGION_PROTECTION,
  95     XTENSA_OPTION_REGION_TRANSLATION,
  96     XTENSA_OPTION_MMU,
  97     XTENSA_OPTION_CACHEATTR,
  98
  99     /* Other */
 100     XTENSA_OPTION_WINDOWED_REGISTER,
 101     XTENSA_OPTION_PROCESSOR_INTERFACE,
 102     XTENSA_OPTION_MISC_SR,
 103     XTENSA_OPTION_THREAD_POINTER,
 104     XTENSA_OPTION_PROCESSOR_ID,
 105     XTENSA_OPTION_DEBUG,
 106     XTENSA_OPTION_TRACE_PORT,
 107     XTENSA_OPTION_EXTERN_REGS,
 108 };
 109
 110 enum {
 111     EXPSTATE = 230,
 112     THREADPTR = 231,
 113     FCR = 232,
 114     FSR = 233,
 115 };
 116
 117 enum {
 118     LBEG = 0,
 119     LEND = 1,
 120     LCOUNT = 2,
 121     SAR = 3,
 122     BR = 4,
 123     LITBASE = 5,
 124     SCOMPARE1 = 12,
 125     ACCLO = 16,
 126     ACCHI = 17,
 127     MR = 32,
 128     WINDOW_BASE = 72,
 129     WINDOW_START = 73,
 130     PTEVADDR = 83,
 131     MMID = 89,
 132     RASID = 90,
 133     ITLBCFG = 91,
 134     DTLBCFG = 92,
 135     IBREAKENABLE = 96,
 136     MEMCTL = 97,
 137     CACHEATTR = 98,
 138     ATOMCTL = 99,
 139     DDR = 104,
 140     IBREAKA = 128,
 141     DBREAKA = 144,
 142     DBREAKC = 160,
 143     CONFIGID0 = 176,
 144     EPC1 = 177,
 145     DEPC = 192,
 146     EPS2 = 194,
 147     CONFIGID1 = 208,
 148     EXCSAVE1 = 209,
 149     CPENABLE = 224,
 150     INTSET = 226,
 151     INTCLEAR = 227,
 152     INTENABLE = 228,
 153     PS = 230,
 154     VECBASE = 231,
 155     EXCCAUSE = 232,
 156     DEBUGCAUSE = 233,
 157     CCOUNT = 234,
 158     PRID = 235,
 159     ICOUNT = 236,
 160     ICOUNTLEVEL = 237,
 161     EXCVADDR = 238,
 162     CCOMPARE = 240,
 163     MISC = 244,
 164 };
 165
 166 #define PS_INTLEVEL 0xf
 167 #define PS_INTLEVEL_SHIFT 0
 168
 169 #define PS_EXCM 0x10
 170 #define PS_UM 0x20
 171
 172 #define PS_RING 0xc0
 173 #define PS_RING_SHIFT 6
 174
 175 #define PS_OWB 0xf00
 176 #define PS_OWB_SHIFT 8
 177
 178 #define PS_CALLINC 0x30000
 179 #define PS_CALLINC_SHIFT 16
 180 #define PS_CALLINC_LEN 2
 181
 182 #define PS_WOE 0x40000
 183
 184 #define DEBUGCAUSE_IC 0x1
 185 #define DEBUGCAUSE_IB 0x2
 186 #define DEBUGCAUSE_DB 0x4
 187 #define DEBUGCAUSE_BI 0x8
 188 #define DEBUGCAUSE_BN 0x10
 189 #define DEBUGCAUSE_DI 0x20
 190 #define DEBUGCAUSE_DBNUM 0xf00
 191 #define DEBUGCAUSE_DBNUM_SHIFT 8
 192
 193 #define DBREAKC_SB 0x80000000
 194 #define DBREAKC_LB 0x40000000
 195 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
 196 #define DBREAKC_MASK 0x3f
 197
 198 #define MEMCTL_INIT 0x00800000
 199 #define MEMCTL_IUSEWAYS_SHIFT 18
 200 #define MEMCTL_IUSEWAYS_LEN 5
 201 #define MEMCTL_IUSEWAYS_MASK 0x007c0000
 202 #define MEMCTL_DALLOCWAYS_SHIFT 13
 203 #define MEMCTL_DALLOCWAYS_LEN 5
 204 #define MEMCTL_DALLOCWAYS_MASK 0x0003e000
 205 #define MEMCTL_DUSEWAYS_SHIFT 8
 206 #define MEMCTL_DUSEWAYS_LEN 5
 207 #define MEMCTL_DUSEWAYS_MASK 0x00001f00
 208 #define MEMCTL_ISNP 0x4
 209 #define MEMCTL_DSNP 0x2
 210 #define MEMCTL_IL0EN 0x1
 211
 212 #define MAX_INSN_LENGTH 64
 213 #define MAX_OPCODE_ARGS 16
 214 #define MAX_NAREG 64
 215 #define MAX_NINTERRUPT 32
 216 #define MAX_NLEVEL 6
 217 #define MAX_NNMI 1
 218 #define MAX_NCCOMPARE 3
 219 #define MAX_TLB_WAY_SIZE 8
 220 #define MAX_NDBREAK 2
 221 #define MAX_NMEMORY 4
 222
 223 #define REGION_PAGE_MASK 0xe0000000
 224
 225 #define PAGE_CACHE_MASK    0x700
 226 #define PAGE_CACHE_SHIFT   8
 227 #define PAGE_CACHE_INVALID 0x000
 228 #define PAGE_CACHE_BYPASS  0x100
 229 #define PAGE_CACHE_WT      0x200
 230 #define PAGE_CACHE_WB      0x400
 231 #define PAGE_CACHE_ISOLATE 0x600
 232
 233 enum {
 234     /* Static vectors */
 235     EXC_RESET0,
 236     EXC_RESET1,
 237     EXC_MEMORY_ERROR,
 238
 239     /* Dynamic vectors */
 240     EXC_WINDOW_OVERFLOW4,
 241     EXC_WINDOW_UNDERFLOW4,
 242     EXC_WINDOW_OVERFLOW8,
 243     EXC_WINDOW_UNDERFLOW8,
 244     EXC_WINDOW_OVERFLOW12,
 245     EXC_WINDOW_UNDERFLOW12,
 246     EXC_IRQ,
 247     EXC_KERNEL,
 248     EXC_USER,
 249     EXC_DOUBLE,
 250     EXC_DEBUG,
 251     EXC_MAX
 252 };
 253
 254 enum {
 255     ILLEGAL_INSTRUCTION_CAUSE = 0,
 256     SYSCALL_CAUSE,
 257     INSTRUCTION_FETCH_ERROR_CAUSE,
 258     LOAD_STORE_ERROR_CAUSE,
 259     LEVEL1_INTERRUPT_CAUSE,
 260     ALLOCA_CAUSE,
 261     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 262     PRIVILEGED_CAUSE = 8,
 263     LOAD_STORE_ALIGNMENT_CAUSE,
 264
 265     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 266     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 267     INSTR_PIF_ADDR_ERROR_CAUSE,
 268     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 269
 270     INST_TLB_MISS_CAUSE,
 271     INST_TLB_MULTI_HIT_CAUSE,
 272     INST_FETCH_PRIVILEGE_CAUSE,
 273     INST_FETCH_PROHIBITED_CAUSE = 20,
 274     LOAD_STORE_TLB_MISS_CAUSE = 24,
 275     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 276     LOAD_STORE_PRIVILEGE_CAUSE,
 277     LOAD_PROHIBITED_CAUSE = 28,
 278     STORE_PROHIBITED_CAUSE,
 279
 280     COPROCESSOR0_DISABLED = 32,
 281 };
 282
 283 typedef enum {
 284     INTTYPE_LEVEL,
 285     INTTYPE_EDGE,
 286     INTTYPE_NMI,
 287     INTTYPE_SOFTWARE,
 288     INTTYPE_TIMER,
 289     INTTYPE_DEBUG,
 290     INTTYPE_WRITE_ERR,
 291     INTTYPE_PROFILING,
 292     INTTYPE_MAX
 293 } interrupt_type;
 294
 295 struct CPUXtensaState;
 296
 297 typedef struct xtensa_tlb_entry {
 298     uint32_t vaddr;
 299     uint32_t paddr;
 300     uint8_t asid;
 301     uint8_t attr;
 302     bool variable;
 303 } xtensa_tlb_entry;
 304
 305 typedef struct xtensa_tlb {
 306     unsigned nways;
 307     const unsigned way_size[10];
 308     bool varway56;
 309     unsigned nrefillentries;
 310 } xtensa_tlb;
 311
 312 typedef struct XtensaGdbReg {
 313     int targno;
 314     int type;
 315     int group;
 316     unsigned size;
 317 } XtensaGdbReg;
 318
 319 typedef struct XtensaGdbRegmap {
 320     int num_regs;
 321     int num_core_regs;
 322     /* PC + a + ar + sr + ur */
 323     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
 324 } XtensaGdbRegmap;
 325
 326 typedef struct XtensaCcompareTimer {
 327     struct CPUXtensaState *env;
 328     QEMUTimer *timer;
 329 } XtensaCcompareTimer;
 330
 331 typedef struct XtensaMemory {
 332     unsigned num;
 333     struct XtensaMemoryRegion {
 334         uint32_t addr;
 335         uint32_t size;
 336     } location[MAX_NMEMORY];
 337 } XtensaMemory;
 338
 339 typedef struct DisasContext DisasContext;
 340 typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[],
 341                                const uint32_t par[]);
 342
 343 typedef struct XtensaOpcodeOps {
 344     const char *name;
 345     XtensaOpcodeOp translate;
 346     const uint32_t *par;
 347 } XtensaOpcodeOps;
 348
 349 typedef struct XtensaOpcodeTranslators {
 350     unsigned num_opcodes;
 351     const XtensaOpcodeOps *opcode;
 352 } XtensaOpcodeTranslators;
 353
 354 extern const XtensaOpcodeTranslators xtensa_core_opcodes;
 355 extern const XtensaOpcodeTranslators xtensa_fpu2000_opcodes;
 356
 357 struct XtensaConfig {
 358     const char *name;
 359     uint64_t options;
 360     XtensaGdbRegmap gdb_regmap;
 361     unsigned nareg;
 362     int excm_level;
 363     int ndepc;
 364     uint32_t vecbase;
 365     uint32_t exception_vector[EXC_MAX];
 366     unsigned ninterrupt;
 367     unsigned nlevel;
 368     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
 369     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
 370     uint32_t inttype_mask[INTTYPE_MAX];
 371     struct {
 372         uint32_t level;
 373         interrupt_type inttype;
 374     } interrupt[MAX_NINTERRUPT];
 375     unsigned nccompare;
 376     uint32_t timerint[MAX_NCCOMPARE];
 377     unsigned nextint;
 378     unsigned extint[MAX_NINTERRUPT];
 379
 380     unsigned debug_level;
 381     unsigned nibreak;
 382     unsigned ndbreak;
 383
 384     unsigned icache_ways;
 385     unsigned dcache_ways;
 386     uint32_t memctl_mask;
 387
 388     XtensaMemory instrom;
 389     XtensaMemory instram;
 390     XtensaMemory datarom;
 391     XtensaMemory dataram;
 392     XtensaMemory sysrom;
 393     XtensaMemory sysram;
 394
 395     uint32_t configid[2];
 396
 397     void *isa_internal;
 398     xtensa_isa isa;
 399     XtensaOpcodeOps **opcode_ops;
 400     const XtensaOpcodeTranslators **opcode_translators;
 401
 402     uint32_t clock_freq_khz;
 403
 404     xtensa_tlb itlb;
 405     xtensa_tlb dtlb;
 406 };
 407
 408 typedef struct XtensaConfigList {
 409     const XtensaConfig *config;
 410     struct XtensaConfigList *next;
 411 } XtensaConfigList;
 412
 413 #ifdef HOST_WORDS_BIGENDIAN
 414 enum {
 415     FP_F32_HIGH,
 416     FP_F32_LOW,
 417 };
 418 #else
 419 enum {
 420     FP_F32_LOW,
 421     FP_F32_HIGH,
 422 };
 423 #endif
 424
 425 typedef struct CPUXtensaState {
 426     const XtensaConfig *config;
 427     uint32_t regs[16];
 428     uint32_t pc;
 429     uint32_t sregs[256];
 430     uint32_t uregs[256];
 431     uint32_t phys_regs[MAX_NAREG];
 432     union {
 433         float32 f32[2];
 434         float64 f64;
 435     } fregs[16];
 436     float_status fp_status;
 437
 438     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
 439     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
 440     unsigned autorefill_idx;
 441     bool runstall;
 442     AddressSpace *address_space_er;
 443     MemoryRegion *system_er;
 444     int pending_irq_level; /* level of last raised IRQ */
 445     void **irq_inputs;
 446     XtensaCcompareTimer ccompare[MAX_NCCOMPARE];
 447     uint64_t time_base;
 448     uint64_t ccount_time;
 449     uint32_t ccount_base;
 450
 451     int exception_taken;
 452     int yield_needed;
 453     unsigned static_vectors;
 454
 455     /* Watchpoints for DBREAK registers */
 456     struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
 457
 458     CPU_COMMON
 459 } CPUXtensaState;
 460
 461 /**
 462  * XtensaCPU:
 463  * @env: #CPUXtensaState
 464  *
 465  * An Xtensa CPU.
 466  */
 467 struct XtensaCPU {
 468     /*< private >*/
 469     CPUState parent_obj;
 470     /*< public >*/
 471
 472     CPUXtensaState env;
 473 };
 474
 475 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
 476 {
 477     return container_of(env, XtensaCPU, env);
 478 }
 479
 480 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
 481
 482 #define ENV_OFFSET offsetof(XtensaCPU, env)
 483
 484 void xtensa_cpu_do_interrupt(CPUState *cpu);
 485 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
 486 void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
 487                                      bool is_write, bool is_exec, int opaque,
 488                                      unsigned size);
 489 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
 490                            fprintf_function cpu_fprintf, int flags);
 491 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 492 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 493 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 494 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
 495                                     MMUAccessType access_type,
 496                                     int mmu_idx, uintptr_t retaddr);
 497
 498 #define cpu_signal_handler cpu_xtensa_signal_handler
 499 #define cpu_list xtensa_cpu_list
 500
 501 #define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU
 502 #define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX
 503
 504 #ifdef TARGET_WORDS_BIGENDIAN
 505 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
 506 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "fsf"
 507 #else
 508 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
 509 #define XTENSA_DEFAULT_CPU_NOMMU_MODEL "de212"
 510 #endif
 511 #define XTENSA_DEFAULT_CPU_TYPE \
 512     XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_MODEL)
 513 #define XTENSA_DEFAULT_CPU_NOMMU_TYPE \
 514     XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL)
 515
 516 #define cpu_init(cpu_model) cpu_generic_init(TYPE_XTENSA_CPU, cpu_model)
 517
 518 void xtensa_translate_init(void);
 519 void xtensa_breakpoint_handler(CPUState *cs);
 520 void xtensa_finalize_config(XtensaConfig *config);
 521 void xtensa_register_core(XtensaConfigList *node);
 522 void xtensa_sim_open_console(Chardev *chr);
 523 void check_interrupts(CPUXtensaState *s);
 524 void xtensa_irq_init(CPUXtensaState *env);
 525 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
 526 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
 527 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 528 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 529 void xtensa_sync_window_from_phys(CPUXtensaState *env);
 530 void xtensa_sync_phys_from_window(CPUXtensaState *env);
 531 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
 532 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 533         uint32_t *vpn, uint32_t wi, uint32_t *ei);
 534 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 535         uint32_t *pwi, uint32_t *pei, uint8_t *pring);
 536 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 537         xtensa_tlb_entry *entry, bool dtlb,
 538         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 539 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 540         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 541 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 542         uint32_t vaddr, int is_write, int mmu_idx,
 543         uint32_t *paddr, uint32_t *page_size, unsigned *access);
 544 void reset_mmu(CPUXtensaState *env);
 545 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
 546 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
 547 static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env)
 548 {
 549     return env->system_er;
 550 }
 551
 552 static inline void xtensa_select_static_vectors(CPUXtensaState *env,
 553                                                 unsigned n)
 554 {
 555     assert(n < 2);
 556     env->static_vectors = n;
 557 }
 558 void xtensa_runstall(CPUXtensaState *env, bool runstall);
 559 XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t,
 560                                         const char *opcode);
 561
 562 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 563 #define XTENSA_OPTION_ALL (~(uint64_t)0)
 564
 565 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
 566         uint64_t opt)
 567 {
 568     return (config->options & opt) != 0;
 569 }
 570
 571 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 572 {
 573     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
 574 }
 575
 576 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
 577 {
 578     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 579     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 580         level = env->config->excm_level;
 581     }
 582     return level;
 583 }
 584
 585 static inline int xtensa_get_ring(const CPUXtensaState *env)
 586 {
 587     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 588         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 589     } else {
 590         return 0;
 591     }
 592 }
 593
 594 static inline int xtensa_get_cring(const CPUXtensaState *env)
 595 {
 596     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 597             (env->sregs[PS] & PS_EXCM) == 0) {
 598         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 599     } else {
 600         return 0;
 601     }
 602 }
 603
 604 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
 605         bool dtlb, unsigned wi, unsigned ei)
 606 {
 607     return dtlb ?
 608         env->dtlb[wi] + ei :
 609         env->itlb[wi] + ei;
 610 }
 611
 612 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
 613 {
 614     return env->sregs[WINDOW_START] |
 615         (env->sregs[WINDOW_START] << env->config->nareg / 4);
 616 }
 617
 618 /* MMU modes definitions */
 619 #define MMU_MODE0_SUFFIX _ring0
 620 #define MMU_MODE1_SUFFIX _ring1
 621 #define MMU_MODE2_SUFFIX _ring2
 622 #define MMU_MODE3_SUFFIX _ring3
 623
 624 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
 625 {
 626     return xtensa_get_cring(env);
 627 }
 628
 629 #define XTENSA_TBFLAG_RING_MASK 0x3
 630 #define XTENSA_TBFLAG_EXCM 0x4
 631 #define XTENSA_TBFLAG_LITBASE 0x8
 632 #define XTENSA_TBFLAG_DEBUG 0x10
 633 #define XTENSA_TBFLAG_ICOUNT 0x20
 634 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
 635 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
 636 #define XTENSA_TBFLAG_EXCEPTION 0x4000
 637 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
 638 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
 639 #define XTENSA_TBFLAG_YIELD 0x20000
 640
 641 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
 642         target_ulong *cs_base, uint32_t *flags)
 643 {
 644     CPUState *cs = CPU(xtensa_env_get_cpu(env));
 645
 646     *pc = env->pc;
 647     *cs_base = 0;
 648     *flags = 0;
 649     *flags |= xtensa_get_ring(env);
 650     if (env->sregs[PS] & PS_EXCM) {
 651         *flags |= XTENSA_TBFLAG_EXCM;
 652     }
 653     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
 654             (env->sregs[LITBASE] & 1)) {
 655         *flags |= XTENSA_TBFLAG_LITBASE;
 656     }
 657     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
 658         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 659             *flags |= XTENSA_TBFLAG_DEBUG;
 660         }
 661         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
 662             *flags |= XTENSA_TBFLAG_ICOUNT;
 663         }
 664     }
 665     if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
 666         *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
 667     }
 668     if (cs->singlestep_enabled && env->exception_taken) {
 669         *flags |= XTENSA_TBFLAG_EXCEPTION;
 670     }
 671     if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
 672         (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
 673         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
 674             (env->sregs[WINDOW_BASE] + 1);
 675         uint32_t w = ctz32(windowstart | 0x8);
 676
 677         *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
 678     } else {
 679         *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
 680     }
 681     if (env->yield_needed) {
 682         *flags |= XTENSA_TBFLAG_YIELD;
 683     }
 684 }
 685
 686 #include "exec/cpu-all.h"
 687
 688 #endif