target/ppc/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "exec/exec-all.h"
   5 #include "hw/hw.h"
   6 #include "hw/boards.h"
   7 #include "sysemu/kvm.h"
   8 #include "helper_regs.h"
   9 #include "mmu-hash64.h"
  10 #include "migration/cpu.h"
  11 #include "qapi/error.h"
  12 #include "kvm_ppc.h"
  13
  14 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
  15 {
  16     PowerPCCPU *cpu = opaque;
  17     CPUPPCState *env = &cpu->env;
  18     unsigned int i, j;
  19     target_ulong sdr1;
  20     uint32_t fpscr;
  21     target_ulong xer;
  22
  23     for (i = 0; i < 32; i++)
  24         qemu_get_betls(f, &env->gpr[i]);
  25 #if !defined(TARGET_PPC64)
  26     for (i = 0; i < 32; i++)
  27         qemu_get_betls(f, &env->gprh[i]);
  28 #endif
  29     qemu_get_betls(f, &env->lr);
  30     qemu_get_betls(f, &env->ctr);
  31     for (i = 0; i < 8; i++)
  32         qemu_get_be32s(f, &env->crf[i]);
  33     qemu_get_betls(f, &xer);
  34     cpu_write_xer(env, xer);
  35     qemu_get_betls(f, &env->reserve_addr);
  36     qemu_get_betls(f, &env->msr);
  37     for (i = 0; i < 4; i++)
  38         qemu_get_betls(f, &env->tgpr[i]);
  39     for (i = 0; i < 32; i++) {
  40         union {
  41             float64 d;
  42             uint64_t l;
  43         } u;
  44         u.l = qemu_get_be64(f);
  45         env->fpr[i] = u.d;
  46     }
  47     qemu_get_be32s(f, &fpscr);
  48     env->fpscr = fpscr;
  49     qemu_get_sbe32s(f, &env->access_type);
  50 #if defined(TARGET_PPC64)
  51     qemu_get_betls(f, &env->spr[SPR_ASR]);
  52     qemu_get_sbe32s(f, &env->slb_nr);
  53 #endif
  54     qemu_get_betls(f, &sdr1);
  55     for (i = 0; i < 32; i++)
  56         qemu_get_betls(f, &env->sr[i]);
  57     for (i = 0; i < 2; i++)
  58         for (j = 0; j < 8; j++)
  59             qemu_get_betls(f, &env->DBAT[i][j]);
  60     for (i = 0; i < 2; i++)
  61         for (j = 0; j < 8; j++)
  62             qemu_get_betls(f, &env->IBAT[i][j]);
  63     qemu_get_sbe32s(f, &env->nb_tlb);
  64     qemu_get_sbe32s(f, &env->tlb_per_way);
  65     qemu_get_sbe32s(f, &env->nb_ways);
  66     qemu_get_sbe32s(f, &env->last_way);
  67     qemu_get_sbe32s(f, &env->id_tlbs);
  68     qemu_get_sbe32s(f, &env->nb_pids);
  69     if (env->tlb.tlb6) {
  70         // XXX assumes 6xx
  71         for (i = 0; i < env->nb_tlb; i++) {
  72             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  73             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  74             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  75         }
  76     }
  77     for (i = 0; i < 4; i++)
  78         qemu_get_betls(f, &env->pb[i]);
  79     for (i = 0; i < 1024; i++)
  80         qemu_get_betls(f, &env->spr[i]);
  81     if (!cpu->vhyp) {
  82         ppc_store_sdr1(env, sdr1);
  83     }
  84     qemu_get_be32s(f, &env->vscr);
  85     qemu_get_be64s(f, &env->spe_acc);
  86     qemu_get_be32s(f, &env->spe_fscr);
  87     qemu_get_betls(f, &env->msr_mask);
  88     qemu_get_be32s(f, &env->flags);
  89     qemu_get_sbe32s(f, &env->error_code);
  90     qemu_get_be32s(f, &env->pending_interrupts);
  91     qemu_get_be32s(f, &env->irq_input_state);
  92     for (i = 0; i < POWERPC_EXCP_NB; i++)
  93         qemu_get_betls(f, &env->excp_vectors[i]);
  94     qemu_get_betls(f, &env->excp_prefix);
  95     qemu_get_betls(f, &env->ivor_mask);
  96     qemu_get_betls(f, &env->ivpr_mask);
  97     qemu_get_betls(f, &env->hreset_vector);
  98     qemu_get_betls(f, &env->nip);
  99     qemu_get_betls(f, &env->hflags);
 100     qemu_get_betls(f, &env->hflags_nmsr);
 101     qemu_get_sbe32(f); /* Discard unused mmu_idx */
 102     qemu_get_sbe32(f); /* Discard unused power_mode */
 103
 104     /* Recompute mmu indices */
 105     hreg_compute_mem_idx(env);
 106
 107     return 0;
 108 }
 109
 110 static int get_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field)
 111 {
 112     ppc_avr_t *v = pv;
 113
 114     v->u64[0] = qemu_get_be64(f);
 115     v->u64[1] = qemu_get_be64(f);
 116
 117     return 0;
 118 }
 119
 120 static int put_avr(QEMUFile *f, void *pv, size_t size, VMStateField *field,
 121                    QJSON *vmdesc)
 122 {
 123     ppc_avr_t *v = pv;
 124
 125     qemu_put_be64(f, v->u64[0]);
 126     qemu_put_be64(f, v->u64[1]);
 127     return 0;
 128 }
 129
 130 static const VMStateInfo vmstate_info_avr = {
 131     .name = "avr",
 132     .get  = get_avr,
 133     .put  = put_avr,
 134 };
 135
 136 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 137     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 138
 139 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 140     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 141
 142 static bool cpu_pre_2_8_migration(void *opaque, int version_id)
 143 {
 144     PowerPCCPU *cpu = opaque;
 145
 146     return cpu->pre_2_8_migration;
 147 }
 148
 149 static int cpu_pre_save(void *opaque)
 150 {
 151     PowerPCCPU *cpu = opaque;
 152     CPUPPCState *env = &cpu->env;
 153     int i;
 154     uint64_t insns_compat_mask =
 155         PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB
 156         | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES
 157         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES
 158         | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT
 159         | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ
 160         | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC
 161         | PPC_64B | PPC_64BX | PPC_ALTIVEC
 162         | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD;
 163     uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX
 164         | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206
 165         | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206
 166         | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207
 167         | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207
 168         | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM;
 169
 170     env->spr[SPR_LR] = env->lr;
 171     env->spr[SPR_CTR] = env->ctr;
 172     env->spr[SPR_XER] = cpu_read_xer(env);
 173 #if defined(TARGET_PPC64)
 174     env->spr[SPR_CFAR] = env->cfar;
 175 #endif
 176     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 177
 178     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 179         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 180         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 181         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 182         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 183     }
 184     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 185         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 186         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 187         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 188         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 189     }
 190
 191     /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */
 192     if (cpu->pre_2_8_migration) {
 193         cpu->mig_msr_mask = env->msr_mask;
 194         cpu->mig_insns_flags = env->insns_flags & insns_compat_mask;
 195         cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2;
 196         cpu->mig_nb_BATs = env->nb_BATs;
 197     }
 198
 199     return 0;
 200 }
 201
 202 /*
 203  * Determine if a given PVR is a "close enough" match to the CPU
 204  * object.  For TCG and KVM PR it would probably be sufficient to
 205  * require an exact PVR match.  However for KVM HV the user is
 206  * restricted to a PVR exactly matching the host CPU.  The correct way
 207  * to handle this is to put the guest into an architected
 208  * compatibility mode.  However, to allow a more forgiving transition
 209  * and migration from before this was widely done, we allow migration
 210  * between sufficiently similar PVRs, as determined by the CPU class's
 211  * pvr_match() hook.
 212  */
 213 static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr)
 214 {
 215     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 216
 217     if (pvr == pcc->pvr) {
 218         return true;
 219     }
 220     return pcc->pvr_match(pcc, pvr);
 221 }
 222
 223 static int cpu_post_load(void *opaque, int version_id)
 224 {
 225     PowerPCCPU *cpu = opaque;
 226     CPUPPCState *env = &cpu->env;
 227     int i;
 228     target_ulong msr;
 229
 230     /*
 231      * If we're operating in compat mode, we should be ok as long as
 232      * the destination supports the same compatiblity mode.
 233      *
 234      * Otherwise, however, we require that the destination has exactly
 235      * the same CPU model as the source.
 236      */
 237
 238 #if defined(TARGET_PPC64)
 239     if (cpu->compat_pvr) {
 240         uint32_t compat_pvr = cpu->compat_pvr;
 241         Error *local_err = NULL;
 242
 243         cpu->compat_pvr = 0;
 244         ppc_set_compat(cpu, compat_pvr, &local_err);
 245         if (local_err) {
 246             error_report_err(local_err);
 247             return -1;
 248         }
 249     } else
 250 #endif
 251     {
 252         if (!pvr_match(cpu, env->spr[SPR_PVR])) {
 253             return -1;
 254         }
 255     }
 256
 257     /*
 258      * If we're running with KVM HV, there is a chance that the guest
 259      * is running with KVM HV and its kernel does not have the
 260      * capability of dealing with a different PVR other than this
 261      * exact host PVR in KVM_SET_SREGS. If that happens, the
 262      * guest freezes after migration.
 263      *
 264      * The function kvmppc_pvr_workaround_required does this verification
 265      * by first checking if the kernel has the cap, returning true immediately
 266      * if that is the case. Otherwise, it checks if we're running in KVM PR.
 267      * If the guest kernel does not have the cap and we're not running KVM-PR
 268      * (so, it is running KVM-HV), we need to ensure that KVM_SET_SREGS will
 269      * receive the PVR it expects as a workaround.
 270      *
 271      */
 272 #if defined(CONFIG_KVM)
 273     if (kvmppc_pvr_workaround_required(cpu)) {
 274         env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 275     }
 276 #endif
 277
 278     env->lr = env->spr[SPR_LR];
 279     env->ctr = env->spr[SPR_CTR];
 280     cpu_write_xer(env, env->spr[SPR_XER]);
 281 #if defined(TARGET_PPC64)
 282     env->cfar = env->spr[SPR_CFAR];
 283 #endif
 284     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 285
 286     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 287         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 288         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 289         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 290         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 291     }
 292     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 293         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 294         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 295         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 296         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 297     }
 298
 299     if (!cpu->vhyp) {
 300         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 301     }
 302
 303     /* Invalidate all supported msr bits except MSR_TGPR/MSR_HVB before restoring */
 304     msr = env->msr;
 305     env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
 306     ppc_store_msr(env, msr);
 307
 308     hreg_compute_mem_idx(env);
 309
 310     return 0;
 311 }
 312
 313 static bool fpu_needed(void *opaque)
 314 {
 315     PowerPCCPU *cpu = opaque;
 316
 317     return (cpu->env.insns_flags & PPC_FLOAT);
 318 }
 319
 320 static const VMStateDescription vmstate_fpu = {
 321     .name = "cpu/fpu",
 322     .version_id = 1,
 323     .minimum_version_id = 1,
 324     .needed = fpu_needed,
 325     .fields = (VMStateField[]) {
 326         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 327         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 328         VMSTATE_END_OF_LIST()
 329     },
 330 };
 331
 332 static bool altivec_needed(void *opaque)
 333 {
 334     PowerPCCPU *cpu = opaque;
 335
 336     return (cpu->env.insns_flags & PPC_ALTIVEC);
 337 }
 338
 339 static const VMStateDescription vmstate_altivec = {
 340     .name = "cpu/altivec",
 341     .version_id = 1,
 342     .minimum_version_id = 1,
 343     .needed = altivec_needed,
 344     .fields = (VMStateField[]) {
 345         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 346         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 347         VMSTATE_END_OF_LIST()
 348     },
 349 };
 350
 351 static bool vsx_needed(void *opaque)
 352 {
 353     PowerPCCPU *cpu = opaque;
 354
 355     return (cpu->env.insns_flags2 & PPC2_VSX);
 356 }
 357
 358 static const VMStateDescription vmstate_vsx = {
 359     .name = "cpu/vsx",
 360     .version_id = 1,
 361     .minimum_version_id = 1,
 362     .needed = vsx_needed,
 363     .fields = (VMStateField[]) {
 364         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 365         VMSTATE_END_OF_LIST()
 366     },
 367 };
 368
 369 #ifdef TARGET_PPC64
 370 /* Transactional memory state */
 371 static bool tm_needed(void *opaque)
 372 {
 373     PowerPCCPU *cpu = opaque;
 374     CPUPPCState *env = &cpu->env;
 375     return msr_ts;
 376 }
 377
 378 static const VMStateDescription vmstate_tm = {
 379     .name = "cpu/tm",
 380     .version_id = 1,
 381     .minimum_version_id = 1,
 382     .minimum_version_id_old = 1,
 383     .needed = tm_needed,
 384     .fields      = (VMStateField []) {
 385         VMSTATE_UINTTL_ARRAY(env.tm_gpr, PowerPCCPU, 32),
 386         VMSTATE_AVR_ARRAY(env.tm_vsr, PowerPCCPU, 64),
 387         VMSTATE_UINT64(env.tm_cr, PowerPCCPU),
 388         VMSTATE_UINT64(env.tm_lr, PowerPCCPU),
 389         VMSTATE_UINT64(env.tm_ctr, PowerPCCPU),
 390         VMSTATE_UINT64(env.tm_fpscr, PowerPCCPU),
 391         VMSTATE_UINT64(env.tm_amr, PowerPCCPU),
 392         VMSTATE_UINT64(env.tm_ppr, PowerPCCPU),
 393         VMSTATE_UINT64(env.tm_vrsave, PowerPCCPU),
 394         VMSTATE_UINT32(env.tm_vscr, PowerPCCPU),
 395         VMSTATE_UINT64(env.tm_dscr, PowerPCCPU),
 396         VMSTATE_UINT64(env.tm_tar, PowerPCCPU),
 397         VMSTATE_END_OF_LIST()
 398     },
 399 };
 400 #endif
 401
 402 static bool sr_needed(void *opaque)
 403 {
 404 #ifdef TARGET_PPC64
 405     PowerPCCPU *cpu = opaque;
 406
 407     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 408 #else
 409     return true;
 410 #endif
 411 }
 412
 413 static const VMStateDescription vmstate_sr = {
 414     .name = "cpu/sr",
 415     .version_id = 1,
 416     .minimum_version_id = 1,
 417     .needed = sr_needed,
 418     .fields = (VMStateField[]) {
 419         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 420         VMSTATE_END_OF_LIST()
 421     },
 422 };
 423
 424 #ifdef TARGET_PPC64
 425 static int get_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field)
 426 {
 427     ppc_slb_t *v = pv;
 428
 429     v->esid = qemu_get_be64(f);
 430     v->vsid = qemu_get_be64(f);
 431
 432     return 0;
 433 }
 434
 435 static int put_slbe(QEMUFile *f, void *pv, size_t size, VMStateField *field,
 436                     QJSON *vmdesc)
 437 {
 438     ppc_slb_t *v = pv;
 439
 440     qemu_put_be64(f, v->esid);
 441     qemu_put_be64(f, v->vsid);
 442     return 0;
 443 }
 444
 445 static const VMStateInfo vmstate_info_slbe = {
 446     .name = "slbe",
 447     .get  = get_slbe,
 448     .put  = put_slbe,
 449 };
 450
 451 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 452     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 453
 454 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 455     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 456
 457 static bool slb_needed(void *opaque)
 458 {
 459     PowerPCCPU *cpu = opaque;
 460
 461     /* We don't support any of the old segment table based 64-bit CPUs */
 462     return (cpu->env.mmu_model & POWERPC_MMU_64);
 463 }
 464
 465 static int slb_post_load(void *opaque, int version_id)
 466 {
 467     PowerPCCPU *cpu = opaque;
 468     CPUPPCState *env = &cpu->env;
 469     int i;
 470
 471     /* We've pulled in the raw esid and vsid values from the migration
 472      * stream, but we need to recompute the page size pointers */
 473     for (i = 0; i < env->slb_nr; i++) {
 474         if (ppc_store_slb(cpu, i, env->slb[i].esid, env->slb[i].vsid) < 0) {
 475             /* Migration source had bad values in its SLB */
 476             return -1;
 477         }
 478     }
 479
 480     return 0;
 481 }
 482
 483 static const VMStateDescription vmstate_slb = {
 484     .name = "cpu/slb",
 485     .version_id = 1,
 486     .minimum_version_id = 1,
 487     .needed = slb_needed,
 488     .post_load = slb_post_load,
 489     .fields = (VMStateField[]) {
 490         VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL),
 491         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 492         VMSTATE_END_OF_LIST()
 493     }
 494 };
 495 #endif /* TARGET_PPC64 */
 496
 497 static const VMStateDescription vmstate_tlb6xx_entry = {
 498     .name = "cpu/tlb6xx_entry",
 499     .version_id = 1,
 500     .minimum_version_id = 1,
 501     .fields = (VMStateField[]) {
 502         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 503         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 504         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 505         VMSTATE_END_OF_LIST()
 506     },
 507 };
 508
 509 static bool tlb6xx_needed(void *opaque)
 510 {
 511     PowerPCCPU *cpu = opaque;
 512     CPUPPCState *env = &cpu->env;
 513
 514     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 515 }
 516
 517 static const VMStateDescription vmstate_tlb6xx = {
 518     .name = "cpu/tlb6xx",
 519     .version_id = 1,
 520     .minimum_version_id = 1,
 521     .needed = tlb6xx_needed,
 522     .fields = (VMStateField[]) {
 523         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 524         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 525                                             env.nb_tlb,
 526                                             vmstate_tlb6xx_entry,
 527                                             ppc6xx_tlb_t),
 528         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 529         VMSTATE_END_OF_LIST()
 530     }
 531 };
 532
 533 static const VMStateDescription vmstate_tlbemb_entry = {
 534     .name = "cpu/tlbemb_entry",
 535     .version_id = 1,
 536     .minimum_version_id = 1,
 537     .fields = (VMStateField[]) {
 538         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 539         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 540         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 541         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 542         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 543         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 544         VMSTATE_END_OF_LIST()
 545     },
 546 };
 547
 548 static bool tlbemb_needed(void *opaque)
 549 {
 550     PowerPCCPU *cpu = opaque;
 551     CPUPPCState *env = &cpu->env;
 552
 553     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 554 }
 555
 556 static bool pbr403_needed(void *opaque)
 557 {
 558     PowerPCCPU *cpu = opaque;
 559     uint32_t pvr = cpu->env.spr[SPR_PVR];
 560
 561     return (pvr & 0xffff0000) == 0x00200000;
 562 }
 563
 564 static const VMStateDescription vmstate_pbr403 = {
 565     .name = "cpu/pbr403",
 566     .version_id = 1,
 567     .minimum_version_id = 1,
 568     .needed = pbr403_needed,
 569     .fields = (VMStateField[]) {
 570         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 571         VMSTATE_END_OF_LIST()
 572     },
 573 };
 574
 575 static const VMStateDescription vmstate_tlbemb = {
 576     .name = "cpu/tlb6xx",
 577     .version_id = 1,
 578     .minimum_version_id = 1,
 579     .needed = tlbemb_needed,
 580     .fields = (VMStateField[]) {
 581         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 582         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 583                                             env.nb_tlb,
 584                                             vmstate_tlbemb_entry,
 585                                             ppcemb_tlb_t),
 586         /* 403 protection registers */
 587         VMSTATE_END_OF_LIST()
 588     },
 589     .subsections = (const VMStateDescription*[]) {
 590         &vmstate_pbr403,
 591         NULL
 592     }
 593 };
 594
 595 static const VMStateDescription vmstate_tlbmas_entry = {
 596     .name = "cpu/tlbmas_entry",
 597     .version_id = 1,
 598     .minimum_version_id = 1,
 599     .fields = (VMStateField[]) {
 600         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 601         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 602         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 603         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 604         VMSTATE_END_OF_LIST()
 605     },
 606 };
 607
 608 static bool tlbmas_needed(void *opaque)
 609 {
 610     PowerPCCPU *cpu = opaque;
 611     CPUPPCState *env = &cpu->env;
 612
 613     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 614 }
 615
 616 static const VMStateDescription vmstate_tlbmas = {
 617     .name = "cpu/tlbmas",
 618     .version_id = 1,
 619     .minimum_version_id = 1,
 620     .needed = tlbmas_needed,
 621     .fields = (VMStateField[]) {
 622         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
 623         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 624                                             env.nb_tlb,
 625                                             vmstate_tlbmas_entry,
 626                                             ppcmas_tlb_t),
 627         VMSTATE_END_OF_LIST()
 628     }
 629 };
 630
 631 static bool compat_needed(void *opaque)
 632 {
 633     PowerPCCPU *cpu = opaque;
 634
 635     assert(!(cpu->compat_pvr && !cpu->vhyp));
 636     return !cpu->pre_2_10_migration && cpu->compat_pvr != 0;
 637 }
 638
 639 static const VMStateDescription vmstate_compat = {
 640     .name = "cpu/compat",
 641     .version_id = 1,
 642     .minimum_version_id = 1,
 643     .needed = compat_needed,
 644     .fields = (VMStateField[]) {
 645         VMSTATE_UINT32(compat_pvr, PowerPCCPU),
 646         VMSTATE_END_OF_LIST()
 647     }
 648 };
 649
 650 const VMStateDescription vmstate_ppc_cpu = {
 651     .name = "cpu",
 652     .version_id = 5,
 653     .minimum_version_id = 5,
 654     .minimum_version_id_old = 4,
 655     .load_state_old = cpu_load_old,
 656     .pre_save = cpu_pre_save,
 657     .post_load = cpu_post_load,
 658     .fields = (VMStateField[]) {
 659         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 660
 661         /* User mode architected state */
 662         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 663 #if !defined(TARGET_PPC64)
 664         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 665 #endif
 666         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 667         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 668
 669         /* SPRs */
 670         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 671         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 672
 673         /* Reservation */
 674         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 675
 676         /* Supervisor mode architected state */
 677         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 678
 679         /* Internal state */
 680         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 681         /* FIXME: access_type? */
 682
 683         /* Sanity checking */
 684         VMSTATE_UINTTL_TEST(mig_msr_mask, PowerPCCPU, cpu_pre_2_8_migration),
 685         VMSTATE_UINT64_TEST(mig_insns_flags, PowerPCCPU, cpu_pre_2_8_migration),
 686         VMSTATE_UINT64_TEST(mig_insns_flags2, PowerPCCPU,
 687                             cpu_pre_2_8_migration),
 688         VMSTATE_UINT32_TEST(mig_nb_BATs, PowerPCCPU, cpu_pre_2_8_migration),
 689         VMSTATE_END_OF_LIST()
 690     },
 691     .subsections = (const VMStateDescription*[]) {
 692         &vmstate_fpu,
 693         &vmstate_altivec,
 694         &vmstate_vsx,
 695         &vmstate_sr,
 696 #ifdef TARGET_PPC64
 697         &vmstate_tm,
 698         &vmstate_slb,
 699 #endif /* TARGET_PPC64 */
 700         &vmstate_tlb6xx,
 701         &vmstate_tlbemb,
 702         &vmstate_tlbmas,
 703         &vmstate_compat,
 704         NULL
 705     }
 706 };