target/arm/helper-a64.c

   1 /*
   2  *  AArch64 specific helpers
   3  *
   4  *  Copyright (c) 2013 Alexander Graf <agraf@suse.de>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/gdbstub.h"
  23 #include "exec/helper-proto.h"
  24 #include "qemu/host-utils.h"
  25 #include "qemu/log.h"
  26 #include "sysemu/sysemu.h"
  27 #include "qemu/bitops.h"
  28 #include "internals.h"
  29 #include "qemu/crc32c.h"
  30 #include "exec/exec-all.h"
  31 #include "exec/cpu_ldst.h"
  32 #include "qemu/int128.h"
  33 #include "tcg.h"
  34 #include <zlib.h> /* For crc32 */
  35
  36 /* C2.4.7 Multiply and divide */
  37 /* special cases for 0 and LLONG_MIN are mandated by the standard */
  38 uint64_t HELPER(udiv64)(uint64_t num, uint64_t den)
  39 {
  40     if (den == 0) {
  41         return 0;
  42     }
  43     return num / den;
  44 }
  45
  46 int64_t HELPER(sdiv64)(int64_t num, int64_t den)
  47 {
  48     if (den == 0) {
  49         return 0;
  50     }
  51     if (num == LLONG_MIN && den == -1) {
  52         return LLONG_MIN;
  53     }
  54     return num / den;
  55 }
  56
  57 uint64_t HELPER(rbit64)(uint64_t x)
  58 {
  59     return revbit64(x);
  60 }
  61
  62 /* Convert a softfloat float_relation_ (as returned by
  63  * the float*_compare functions) to the correct ARM
  64  * NZCV flag state.
  65  */
  66 static inline uint32_t float_rel_to_flags(int res)
  67 {
  68     uint64_t flags;
  69     switch (res) {
  70     case float_relation_equal:
  71         flags = PSTATE_Z | PSTATE_C;
  72         break;
  73     case float_relation_less:
  74         flags = PSTATE_N;
  75         break;
  76     case float_relation_greater:
  77         flags = PSTATE_C;
  78         break;
  79     case float_relation_unordered:
  80     default:
  81         flags = PSTATE_C | PSTATE_V;
  82         break;
  83     }
  84     return flags;
  85 }
  86
  87 uint64_t HELPER(vfp_cmps_a64)(float32 x, float32 y, void *fp_status)
  88 {
  89     return float_rel_to_flags(float32_compare_quiet(x, y, fp_status));
  90 }
  91
  92 uint64_t HELPER(vfp_cmpes_a64)(float32 x, float32 y, void *fp_status)
  93 {
  94     return float_rel_to_flags(float32_compare(x, y, fp_status));
  95 }
  96
  97 uint64_t HELPER(vfp_cmpd_a64)(float64 x, float64 y, void *fp_status)
  98 {
  99     return float_rel_to_flags(float64_compare_quiet(x, y, fp_status));
 100 }
 101
 102 uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
 103 {
 104     return float_rel_to_flags(float64_compare(x, y, fp_status));
 105 }
 106
 107 float32 HELPER(vfp_mulxs)(float32 a, float32 b, void *fpstp)
 108 {
 109     float_status *fpst = fpstp;
 110
 111     a = float32_squash_input_denormal(a, fpst);
 112     b = float32_squash_input_denormal(b, fpst);
 113
 114     if ((float32_is_zero(a) && float32_is_infinity(b)) ||
 115         (float32_is_infinity(a) && float32_is_zero(b))) {
 116         /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
 117         return make_float32((1U << 30) |
 118                             ((float32_val(a) ^ float32_val(b)) & (1U << 31)));
 119     }
 120     return float32_mul(a, b, fpst);
 121 }
 122
 123 float64 HELPER(vfp_mulxd)(float64 a, float64 b, void *fpstp)
 124 {
 125     float_status *fpst = fpstp;
 126
 127     a = float64_squash_input_denormal(a, fpst);
 128     b = float64_squash_input_denormal(b, fpst);
 129
 130     if ((float64_is_zero(a) && float64_is_infinity(b)) ||
 131         (float64_is_infinity(a) && float64_is_zero(b))) {
 132         /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
 133         return make_float64((1ULL << 62) |
 134                             ((float64_val(a) ^ float64_val(b)) & (1ULL << 63)));
 135     }
 136     return float64_mul(a, b, fpst);
 137 }
 138
 139 uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
 140                           uint32_t rn, uint32_t numregs)
 141 {
 142     /* Helper function for SIMD TBL and TBX. We have to do the table
 143      * lookup part for the 64 bits worth of indices we're passed in.
 144      * result is the initial results vector (either zeroes for TBL
 145      * or some guest values for TBX), rn the register number where
 146      * the table starts, and numregs the number of registers in the table.
 147      * We return the results of the lookups.
 148      */
 149     int shift;
 150
 151     for (shift = 0; shift < 64; shift += 8) {
 152         int index = extract64(indices, shift, 8);
 153         if (index < 16 * numregs) {
 154             /* Convert index (a byte offset into the virtual table
 155              * which is a series of 128-bit vectors concatenated)
 156              * into the correct register element plus a bit offset
 157              * into that element, bearing in mind that the table
 158              * can wrap around from V31 to V0.
 159              */
 160             int elt = (rn * 2 + (index >> 3)) % 64;
 161             int bitidx = (index & 7) * 8;
 162             uint64_t *q = aa64_vfp_qreg(env, elt >> 1);
 163             uint64_t val = extract64(q[elt & 1], bitidx, 8);
 164
 165             result = deposit64(result, shift, 8, val);
 166         }
 167     }
 168     return result;
 169 }
 170
 171 /* 64bit/double versions of the neon float compare functions */
 172 uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp)
 173 {
 174     float_status *fpst = fpstp;
 175     return -float64_eq_quiet(a, b, fpst);
 176 }
 177
 178 uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp)
 179 {
 180     float_status *fpst = fpstp;
 181     return -float64_le(b, a, fpst);
 182 }
 183
 184 uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
 185 {
 186     float_status *fpst = fpstp;
 187     return -float64_lt(b, a, fpst);
 188 }
 189
 190 /* Reciprocal step and sqrt step. Note that unlike the A32/T32
 191  * versions, these do a fully fused multiply-add or
 192  * multiply-add-and-halve.
 193  */
 194 #define float32_two make_float32(0x40000000)
 195 #define float32_three make_float32(0x40400000)
 196 #define float32_one_point_five make_float32(0x3fc00000)
 197
 198 #define float64_two make_float64(0x4000000000000000ULL)
 199 #define float64_three make_float64(0x4008000000000000ULL)
 200 #define float64_one_point_five make_float64(0x3FF8000000000000ULL)
 201
 202 float32 HELPER(recpsf_f32)(float32 a, float32 b, void *fpstp)
 203 {
 204     float_status *fpst = fpstp;
 205
 206     a = float32_squash_input_denormal(a, fpst);
 207     b = float32_squash_input_denormal(b, fpst);
 208
 209     a = float32_chs(a);
 210     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
 211         (float32_is_infinity(b) && float32_is_zero(a))) {
 212         return float32_two;
 213     }
 214     return float32_muladd(a, b, float32_two, 0, fpst);
 215 }
 216
 217 float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
 218 {
 219     float_status *fpst = fpstp;
 220
 221     a = float64_squash_input_denormal(a, fpst);
 222     b = float64_squash_input_denormal(b, fpst);
 223
 224     a = float64_chs(a);
 225     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
 226         (float64_is_infinity(b) && float64_is_zero(a))) {
 227         return float64_two;
 228     }
 229     return float64_muladd(a, b, float64_two, 0, fpst);
 230 }
 231
 232 float32 HELPER(rsqrtsf_f32)(float32 a, float32 b, void *fpstp)
 233 {
 234     float_status *fpst = fpstp;
 235
 236     a = float32_squash_input_denormal(a, fpst);
 237     b = float32_squash_input_denormal(b, fpst);
 238
 239     a = float32_chs(a);
 240     if ((float32_is_infinity(a) && float32_is_zero(b)) ||
 241         (float32_is_infinity(b) && float32_is_zero(a))) {
 242         return float32_one_point_five;
 243     }
 244     return float32_muladd(a, b, float32_three, float_muladd_halve_result, fpst);
 245 }
 246
 247 float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void *fpstp)
 248 {
 249     float_status *fpst = fpstp;
 250
 251     a = float64_squash_input_denormal(a, fpst);
 252     b = float64_squash_input_denormal(b, fpst);
 253
 254     a = float64_chs(a);
 255     if ((float64_is_infinity(a) && float64_is_zero(b)) ||
 256         (float64_is_infinity(b) && float64_is_zero(a))) {
 257         return float64_one_point_five;
 258     }
 259     return float64_muladd(a, b, float64_three, float_muladd_halve_result, fpst);
 260 }
 261
 262 /* Pairwise long add: add pairs of adjacent elements into
 263  * double-width elements in the result (eg _s8 is an 8x8->16 op)
 264  */
 265 uint64_t HELPER(neon_addlp_s8)(uint64_t a)
 266 {
 267     uint64_t nsignmask = 0x0080008000800080ULL;
 268     uint64_t wsignmask = 0x8000800080008000ULL;
 269     uint64_t elementmask = 0x00ff00ff00ff00ffULL;
 270     uint64_t tmp1, tmp2;
 271     uint64_t res, signres;
 272
 273     /* Extract odd elements, sign extend each to a 16 bit field */
 274     tmp1 = a & elementmask;
 275     tmp1 ^= nsignmask;
 276     tmp1 |= wsignmask;
 277     tmp1 = (tmp1 - nsignmask) ^ wsignmask;
 278     /* Ditto for the even elements */
 279     tmp2 = (a >> 8) & elementmask;
 280     tmp2 ^= nsignmask;
 281     tmp2 |= wsignmask;
 282     tmp2 = (tmp2 - nsignmask) ^ wsignmask;
 283
 284     /* calculate the result by summing bits 0..14, 16..22, etc,
 285      * and then adjusting the sign bits 15, 23, etc manually.
 286      * This ensures the addition can't overflow the 16 bit field.
 287      */
 288     signres = (tmp1 ^ tmp2) & wsignmask;
 289     res = (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask);
 290     res ^= signres;
 291
 292     return res;
 293 }
 294
 295 uint64_t HELPER(neon_addlp_u8)(uint64_t a)
 296 {
 297     uint64_t tmp;
 298
 299     tmp = a & 0x00ff00ff00ff00ffULL;
 300     tmp += (a >> 8) & 0x00ff00ff00ff00ffULL;
 301     return tmp;
 302 }
 303
 304 uint64_t HELPER(neon_addlp_s16)(uint64_t a)
 305 {
 306     int32_t reslo, reshi;
 307
 308     reslo = (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16);
 309     reshi = (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48);
 310
 311     return (uint32_t)reslo | (((uint64_t)reshi) << 32);
 312 }
 313
 314 uint64_t HELPER(neon_addlp_u16)(uint64_t a)
 315 {
 316     uint64_t tmp;
 317
 318     tmp = a & 0x0000ffff0000ffffULL;
 319     tmp += (a >> 16) & 0x0000ffff0000ffffULL;
 320     return tmp;
 321 }
 322
 323 /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
 324 float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
 325 {
 326     float_status *fpst = fpstp;
 327     uint32_t val32, sbit;
 328     int32_t exp;
 329
 330     if (float32_is_any_nan(a)) {
 331         float32 nan = a;
 332         if (float32_is_signaling_nan(a, fpst)) {
 333             float_raise(float_flag_invalid, fpst);
 334             nan = float32_maybe_silence_nan(a, fpst);
 335         }
 336         if (fpst->default_nan_mode) {
 337             nan = float32_default_nan(fpst);
 338         }
 339         return nan;
 340     }
 341
 342     val32 = float32_val(a);
 343     sbit = 0x80000000ULL & val32;
 344     exp = extract32(val32, 23, 8);
 345
 346     if (exp == 0) {
 347         return make_float32(sbit | (0xfe << 23));
 348     } else {
 349         return make_float32(sbit | (~exp & 0xff) << 23);
 350     }
 351 }
 352
 353 float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
 354 {
 355     float_status *fpst = fpstp;
 356     uint64_t val64, sbit;
 357     int64_t exp;
 358
 359     if (float64_is_any_nan(a)) {
 360         float64 nan = a;
 361         if (float64_is_signaling_nan(a, fpst)) {
 362             float_raise(float_flag_invalid, fpst);
 363             nan = float64_maybe_silence_nan(a, fpst);
 364         }
 365         if (fpst->default_nan_mode) {
 366             nan = float64_default_nan(fpst);
 367         }
 368         return nan;
 369     }
 370
 371     val64 = float64_val(a);
 372     sbit = 0x8000000000000000ULL & val64;
 373     exp = extract64(float64_val(a), 52, 11);
 374
 375     if (exp == 0) {
 376         return make_float64(sbit | (0x7feULL << 52));
 377     } else {
 378         return make_float64(sbit | (~exp & 0x7ffULL) << 52);
 379     }
 380 }
 381
 382 float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env)
 383 {
 384     /* Von Neumann rounding is implemented by using round-to-zero
 385      * and then setting the LSB of the result if Inexact was raised.
 386      */
 387     float32 r;
 388     float_status *fpst = &env->vfp.fp_status;
 389     float_status tstat = *fpst;
 390     int exflags;
 391
 392     set_float_rounding_mode(float_round_to_zero, &tstat);
 393     set_float_exception_flags(0, &tstat);
 394     r = float64_to_float32(a, &tstat);
 395     r = float32_maybe_silence_nan(r, &tstat);
 396     exflags = get_float_exception_flags(&tstat);
 397     if (exflags & float_flag_inexact) {
 398         r = make_float32(float32_val(r) | 1);
 399     }
 400     exflags |= get_float_exception_flags(fpst);
 401     set_float_exception_flags(exflags, fpst);
 402     return r;
 403 }
 404
 405 /* 64-bit versions of the CRC helpers. Note that although the operation
 406  * (and the prototypes of crc32c() and crc32() mean that only the bottom
 407  * 32 bits of the accumulator and result are used, we pass and return
 408  * uint64_t for convenience of the generated code. Unlike the 32-bit
 409  * instruction set versions, val may genuinely have 64 bits of data in it.
 410  * The upper bytes of val (above the number specified by 'bytes') must have
 411  * been zeroed out by the caller.
 412  */
 413 uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
 414 {
 415     uint8_t buf[8];
 416
 417     stq_le_p(buf, val);
 418
 419     /* zlib crc32 converts the accumulator and output to one's complement.  */
 420     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
 421 }
 422
 423 uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
 424 {
 425     uint8_t buf[8];
 426
 427     stq_le_p(buf, val);
 428
 429     /* Linux crc32c converts the output to one's complement.  */
 430     return crc32c(acc, buf, bytes) ^ 0xffffffff;
 431 }
 432
 433 /* Returns 0 on success; 1 otherwise.  */
 434 static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr,
 435                                        uint64_t new_lo, uint64_t new_hi,
 436                                        bool parallel, uintptr_t ra)
 437 {
 438     Int128 oldv, cmpv, newv;
 439     bool success;
 440
 441     cmpv = int128_make128(env->exclusive_val, env->exclusive_high);
 442     newv = int128_make128(new_lo, new_hi);
 443
 444     if (parallel) {
 445 #ifndef CONFIG_ATOMIC128
 446         cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
 447 #else
 448         int mem_idx = cpu_mmu_index(env, false);
 449         TCGMemOpIdx oi = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
 450         oldv = helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra);
 451         success = int128_eq(oldv, cmpv);
 452 #endif
 453     } else {
 454         uint64_t o0, o1;
 455
 456 #ifdef CONFIG_USER_ONLY
 457         /* ??? Enforce alignment.  */
 458         uint64_t *haddr = g2h(addr);
 459
 460         helper_retaddr = ra;
 461         o0 = ldq_le_p(haddr + 0);
 462         o1 = ldq_le_p(haddr + 1);
 463         oldv = int128_make128(o0, o1);
 464
 465         success = int128_eq(oldv, cmpv);
 466         if (success) {
 467             stq_le_p(haddr + 0, int128_getlo(newv));
 468             stq_le_p(haddr + 1, int128_gethi(newv));
 469         }
 470         helper_retaddr = 0;
 471 #else
 472         int mem_idx = cpu_mmu_index(env, false);
 473         TCGMemOpIdx oi0 = make_memop_idx(MO_LEQ | MO_ALIGN_16, mem_idx);
 474         TCGMemOpIdx oi1 = make_memop_idx(MO_LEQ, mem_idx);
 475
 476         o0 = helper_le_ldq_mmu(env, addr + 0, oi0, ra);
 477         o1 = helper_le_ldq_mmu(env, addr + 8, oi1, ra);
 478         oldv = int128_make128(o0, o1);
 479
 480         success = int128_eq(oldv, cmpv);
 481         if (success) {
 482             helper_le_stq_mmu(env, addr + 0, int128_getlo(newv), oi1, ra);
 483             helper_le_stq_mmu(env, addr + 8, int128_gethi(newv), oi1, ra);
 484         }
 485 #endif
 486     }
 487
 488     return !success;
 489 }
 490
 491 uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr,
 492                                               uint64_t new_lo, uint64_t new_hi)
 493 {
 494     return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false, GETPC());
 495 }
 496
 497 uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr,
 498                                               uint64_t new_lo, uint64_t new_hi)
 499 {
 500     return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true, GETPC());
 501 }
 502
 503 static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr,
 504                                        uint64_t new_lo, uint64_t new_hi,
 505                                        bool parallel, uintptr_t ra)
 506 {
 507     Int128 oldv, cmpv, newv;
 508     bool success;
 509
 510     /* high and low need to be switched here because this is not actually a
 511      * 128bit store but two doublewords stored consecutively
 512      */
 513     cmpv = int128_make128(env->exclusive_high, env->exclusive_val);
 514     newv = int128_make128(new_hi, new_lo);
 515
 516     if (parallel) {
 517 #ifndef CONFIG_ATOMIC128
 518         cpu_loop_exit_atomic(ENV_GET_CPU(env), ra);
 519 #else
 520         int mem_idx = cpu_mmu_index(env, false);
 521         TCGMemOpIdx oi = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
 522         oldv = helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra);
 523         success = int128_eq(oldv, cmpv);
 524 #endif
 525     } else {
 526         uint64_t o0, o1;
 527
 528 #ifdef CONFIG_USER_ONLY
 529         /* ??? Enforce alignment.  */
 530         uint64_t *haddr = g2h(addr);
 531
 532         helper_retaddr = ra;
 533         o1 = ldq_be_p(haddr + 0);
 534         o0 = ldq_be_p(haddr + 1);
 535         oldv = int128_make128(o0, o1);
 536
 537         success = int128_eq(oldv, cmpv);
 538         if (success) {
 539             stq_be_p(haddr + 0, int128_gethi(newv));
 540             stq_be_p(haddr + 1, int128_getlo(newv));
 541         }
 542         helper_retaddr = 0;
 543 #else
 544         int mem_idx = cpu_mmu_index(env, false);
 545         TCGMemOpIdx oi0 = make_memop_idx(MO_BEQ | MO_ALIGN_16, mem_idx);
 546         TCGMemOpIdx oi1 = make_memop_idx(MO_BEQ, mem_idx);
 547
 548         o1 = helper_be_ldq_mmu(env, addr + 0, oi0, ra);
 549         o0 = helper_be_ldq_mmu(env, addr + 8, oi1, ra);
 550         oldv = int128_make128(o0, o1);
 551
 552         success = int128_eq(oldv, cmpv);
 553         if (success) {
 554             helper_be_stq_mmu(env, addr + 0, int128_gethi(newv), oi1, ra);
 555             helper_be_stq_mmu(env, addr + 8, int128_getlo(newv), oi1, ra);
 556         }
 557 #endif
 558     }
 559
 560     return !success;
 561 }
 562
 563 uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
 564                                      uint64_t new_lo, uint64_t new_hi)
 565 {
 566     return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false, GETPC());
 567 }
 568
 569 uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr,
 570                                      uint64_t new_lo, uint64_t new_hi)
 571 {
 572     return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true, GETPC());
 573 }