4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
25 #include "internals.h"
26 #include "qemu-common.h"
27 #include "exec/exec-all.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/loader.h"
32 #include "hw/arm/arm.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/hw_accel.h"
36 #include "disas/capstone.h"
38 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
40 ARMCPU
*cpu
= ARM_CPU(cs
);
42 cpu
->env
.regs
[15] = value
;
45 static bool arm_cpu_has_work(CPUState
*cs
)
47 ARMCPU
*cpu
= ARM_CPU(cs
);
49 return (cpu
->power_state
!= PSCI_OFF
)
50 && cs
->interrupt_request
&
51 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
52 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
53 | CPU_INTERRUPT_EXITTB
);
56 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHook
*hook
,
59 /* We currently only support registering a single hook function */
60 assert(!cpu
->el_change_hook
);
61 cpu
->el_change_hook
= hook
;
62 cpu
->el_change_hook_opaque
= opaque
;
65 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
67 /* Reset a single ARMCPRegInfo register */
68 ARMCPRegInfo
*ri
= value
;
71 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
76 ri
->resetfn(&cpu
->env
, ri
);
80 /* A zero offset is never possible as it would be regs[0]
81 * so we use it to indicate that reset is being handled elsewhere.
82 * This is basically only used for fields in non-core coprocessors
83 * (like the pxa2xx ones).
85 if (!ri
->fieldoffset
) {
89 if (cpreg_field_is_64bit(ri
)) {
90 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
92 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
96 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
98 /* Purely an assertion check: we've already done reset once,
99 * so now check that running the reset for the cpreg doesn't
100 * change its value. This traps bugs where two different cpregs
101 * both try to reset the same state field but to different values.
103 ARMCPRegInfo
*ri
= value
;
104 ARMCPU
*cpu
= opaque
;
105 uint64_t oldvalue
, newvalue
;
107 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
111 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
112 cp_reg_reset(key
, value
, opaque
);
113 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
114 assert(oldvalue
== newvalue
);
117 /* CPUClass::reset() */
118 static void arm_cpu_reset(CPUState
*s
)
120 ARMCPU
*cpu
= ARM_CPU(s
);
121 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
122 CPUARMState
*env
= &cpu
->env
;
124 acc
->parent_reset(s
);
126 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
128 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
129 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
131 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
132 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->mvfr0
;
133 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->mvfr1
;
134 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->mvfr2
;
136 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
137 s
->halted
= cpu
->start_powered_off
;
139 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
140 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
143 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
144 /* 64 bit CPUs always start in 64 bit mode */
146 #if defined(CONFIG_USER_ONLY)
147 env
->pstate
= PSTATE_MODE_EL0t
;
148 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
149 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
150 /* and to the FP/Neon instructions */
151 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
153 /* Reset into the highest available EL */
154 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
155 env
->pstate
= PSTATE_MODE_EL3h
;
156 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
157 env
->pstate
= PSTATE_MODE_EL2h
;
159 env
->pstate
= PSTATE_MODE_EL1h
;
161 env
->pc
= cpu
->rvbar
;
164 #if defined(CONFIG_USER_ONLY)
165 /* Userspace expects access to cp10 and cp11 for FP/Neon */
166 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
170 #if defined(CONFIG_USER_ONLY)
171 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
172 /* For user mode we must enable access to coprocessors */
173 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
174 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
175 env
->cp15
.c15_cpar
= 3;
176 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
177 env
->cp15
.c15_cpar
= 1;
180 /* SVC mode with interrupts disabled. */
181 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
182 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
184 if (arm_feature(env
, ARM_FEATURE_M
)) {
185 uint32_t initial_msp
; /* Loaded from 0x0 */
186 uint32_t initial_pc
; /* Loaded from 0x4 */
189 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
190 env
->v7m
.secure
= true;
192 /* This bit resets to 0 if security is supported, but 1 if
193 * it is not. The bit is not present in v7M, but we set it
194 * here so we can avoid having to make checks on it conditional
195 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
197 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
200 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
201 * that it resets to 1, so QEMU always does that rather than making
202 * it dependent on CPU model. In v8M it is RES1.
204 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
205 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
206 if (arm_feature(env
, ARM_FEATURE_V8
)) {
207 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
208 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
209 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
212 /* Unlike A/R profile, M profile defines the reset LR value */
213 env
->regs
[14] = 0xffffffff;
215 /* Load the initial SP and PC from the vector table at address 0 */
218 /* Address zero is covered by ROM which hasn't yet been
219 * copied into physical memory.
221 initial_msp
= ldl_p(rom
);
222 initial_pc
= ldl_p(rom
+ 4);
224 /* Address zero not covered by a ROM blob, or the ROM blob
225 * is in non-modifiable memory and this is a second reset after
226 * it got copied into memory. In the latter case, rom_ptr
227 * will return a NULL pointer and we should use ldl_phys instead.
229 initial_msp
= ldl_phys(s
->as
, 0);
230 initial_pc
= ldl_phys(s
->as
, 4);
233 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
234 env
->regs
[15] = initial_pc
& ~1;
235 env
->thumb
= initial_pc
& 1;
238 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
239 * executing as AArch32 then check if highvecs are enabled and
240 * adjust the PC accordingly.
242 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
243 env
->regs
[15] = 0xFFFF0000;
246 /* M profile requires that reset clears the exclusive monitor;
247 * A profile does not, but clearing it makes more sense than having it
248 * set with an exclusive access on address zero.
250 arm_clear_exclusive(env
);
252 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
255 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
256 if (cpu
->pmsav7_dregion
> 0) {
257 if (arm_feature(env
, ARM_FEATURE_V8
)) {
258 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
259 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
260 * cpu
->pmsav7_dregion
);
261 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
262 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
263 * cpu
->pmsav7_dregion
);
264 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
265 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
266 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
267 * cpu
->pmsav7_dregion
);
268 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
269 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
270 * cpu
->pmsav7_dregion
);
272 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
273 memset(env
->pmsav7
.drbar
, 0,
274 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
275 memset(env
->pmsav7
.drsr
, 0,
276 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
277 memset(env
->pmsav7
.dracr
, 0,
278 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
281 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
282 env
->pmsav7
.rnr
[M_REG_S
] = 0;
283 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
284 env
->pmsav8
.mair0
[M_REG_S
] = 0;
285 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
286 env
->pmsav8
.mair1
[M_REG_S
] = 0;
289 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
290 if (cpu
->sau_sregion
> 0) {
291 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
292 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
295 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
296 * the Cortex-M33 does.
301 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
302 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
303 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
304 set_float_detect_tininess(float_tininess_before_rounding
,
305 &env
->vfp
.fp_status
);
306 set_float_detect_tininess(float_tininess_before_rounding
,
307 &env
->vfp
.standard_fp_status
);
308 #ifndef CONFIG_USER_ONLY
310 kvm_arm_reset_vcpu(cpu
);
314 hw_breakpoint_update_all(cpu
);
315 hw_watchpoint_update_all(cpu
);
318 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
320 CPUClass
*cc
= CPU_GET_CLASS(cs
);
321 CPUARMState
*env
= cs
->env_ptr
;
322 uint32_t cur_el
= arm_current_el(env
);
323 bool secure
= arm_is_secure(env
);
328 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
330 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
331 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
332 cs
->exception_index
= excp_idx
;
333 env
->exception
.target_el
= target_el
;
334 cc
->do_interrupt(cs
);
338 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
340 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
341 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
342 cs
->exception_index
= excp_idx
;
343 env
->exception
.target_el
= target_el
;
344 cc
->do_interrupt(cs
);
348 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
349 excp_idx
= EXCP_VIRQ
;
351 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
352 cs
->exception_index
= excp_idx
;
353 env
->exception
.target_el
= target_el
;
354 cc
->do_interrupt(cs
);
358 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
359 excp_idx
= EXCP_VFIQ
;
361 if (arm_excp_unmasked(cs
, excp_idx
, target_el
)) {
362 cs
->exception_index
= excp_idx
;
363 env
->exception
.target_el
= target_el
;
364 cc
->do_interrupt(cs
);
372 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
373 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
375 CPUClass
*cc
= CPU_GET_CLASS(cs
);
376 ARMCPU
*cpu
= ARM_CPU(cs
);
377 CPUARMState
*env
= &cpu
->env
;
380 /* ARMv7-M interrupt masking works differently than -A or -R.
381 * There is no FIQ/IRQ distinction. Instead of I and F bits
382 * masking FIQ and IRQ interrupts, an exception is taken only
383 * if it is higher priority than the current execution priority
384 * (which depends on state like BASEPRI, FAULTMASK and the
385 * currently active exception).
387 if (interrupt_request
& CPU_INTERRUPT_HARD
388 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
389 cs
->exception_index
= EXCP_IRQ
;
390 cc
->do_interrupt(cs
);
397 #ifndef CONFIG_USER_ONLY
398 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
400 ARMCPU
*cpu
= opaque
;
401 CPUARMState
*env
= &cpu
->env
;
402 CPUState
*cs
= CPU(cpu
);
403 static const int mask
[] = {
404 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
405 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
406 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
407 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
413 assert(arm_feature(env
, ARM_FEATURE_EL2
));
418 cpu_interrupt(cs
, mask
[irq
]);
420 cpu_reset_interrupt(cs
, mask
[irq
]);
424 g_assert_not_reached();
428 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
431 ARMCPU
*cpu
= opaque
;
432 CPUState
*cs
= CPU(cpu
);
433 int kvm_irq
= KVM_ARM_IRQ_TYPE_CPU
<< KVM_ARM_IRQ_TYPE_SHIFT
;
437 kvm_irq
|= KVM_ARM_IRQ_CPU_IRQ
;
440 kvm_irq
|= KVM_ARM_IRQ_CPU_FIQ
;
443 g_assert_not_reached();
445 kvm_irq
|= cs
->cpu_index
<< KVM_ARM_IRQ_VCPU_SHIFT
;
446 kvm_set_irq(kvm_state
, kvm_irq
, level
? 1 : 0);
450 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
452 ARMCPU
*cpu
= ARM_CPU(cs
);
453 CPUARMState
*env
= &cpu
->env
;
455 cpu_synchronize_state(cs
);
456 return arm_cpu_data_is_big_endian(env
);
461 static inline void set_feature(CPUARMState
*env
, int feature
)
463 env
->features
|= 1ULL << feature
;
466 static inline void unset_feature(CPUARMState
*env
, int feature
)
468 env
->features
&= ~(1ULL << feature
);
472 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
474 return print_insn_arm(pc
| 1, info
);
477 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
479 ARMCPU
*ac
= ARM_CPU(cpu
);
480 CPUARMState
*env
= &ac
->env
;
484 /* We might not be compiled with the A64 disassembler
485 * because it needs a C++ compiler. Leave print_insn
486 * unset in this case to use the caller default behaviour.
488 #if defined(CONFIG_ARM_A64_DIS)
489 info
->print_insn
= print_insn_arm_a64
;
491 info
->cap_arch
= CS_ARCH_ARM64
;
492 info
->cap_insn_unit
= 4;
493 info
->cap_insn_split
= 4;
497 info
->print_insn
= print_insn_thumb1
;
498 info
->cap_insn_unit
= 2;
499 info
->cap_insn_split
= 4;
500 cap_mode
= CS_MODE_THUMB
;
502 info
->print_insn
= print_insn_arm
;
503 info
->cap_insn_unit
= 4;
504 info
->cap_insn_split
= 4;
505 cap_mode
= CS_MODE_ARM
;
507 if (arm_feature(env
, ARM_FEATURE_V8
)) {
508 cap_mode
|= CS_MODE_V8
;
510 if (arm_feature(env
, ARM_FEATURE_M
)) {
511 cap_mode
|= CS_MODE_MCLASS
;
513 info
->cap_arch
= CS_ARCH_ARM
;
514 info
->cap_mode
= cap_mode
;
517 sctlr_b
= arm_sctlr_b(env
);
518 if (bswap_code(sctlr_b
)) {
519 #ifdef TARGET_WORDS_BIGENDIAN
520 info
->endian
= BFD_ENDIAN_LITTLE
;
522 info
->endian
= BFD_ENDIAN_BIG
;
525 info
->flags
&= ~INSN_ARM_BE32
;
526 #ifndef CONFIG_USER_ONLY
528 info
->flags
|= INSN_ARM_BE32
;
533 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
535 uint32_t Aff1
= idx
/ clustersz
;
536 uint32_t Aff0
= idx
% clustersz
;
537 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
540 static void arm_cpu_initfn(Object
*obj
)
542 CPUState
*cs
= CPU(obj
);
543 ARMCPU
*cpu
= ARM_CPU(obj
);
545 cs
->env_ptr
= &cpu
->env
;
546 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
549 #ifndef CONFIG_USER_ONLY
550 /* Our inbound IRQ and FIQ lines */
552 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
553 * the same interface as non-KVM CPUs.
555 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
557 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
560 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
561 arm_gt_ptimer_cb
, cpu
);
562 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
563 arm_gt_vtimer_cb
, cpu
);
564 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
565 arm_gt_htimer_cb
, cpu
);
566 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, GTIMER_SCALE
,
567 arm_gt_stimer_cb
, cpu
);
568 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
569 ARRAY_SIZE(cpu
->gt_timer_outputs
));
571 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
572 "gicv3-maintenance-interrupt", 1);
573 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
577 /* DTB consumers generally don't in fact care what the 'compatible'
578 * string is, so always provide some string and trust that a hypothetical
579 * picky DTB consumer will also provide a helpful error message.
581 cpu
->dtb_compatible
= "qemu,unknown";
582 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
583 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
586 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
590 static Property arm_cpu_reset_cbar_property
=
591 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
593 static Property arm_cpu_reset_hivecs_property
=
594 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
596 static Property arm_cpu_rvbar_property
=
597 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
599 static Property arm_cpu_has_el2_property
=
600 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
602 static Property arm_cpu_has_el3_property
=
603 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
605 static Property arm_cpu_cfgend_property
=
606 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
608 /* use property name "pmu" to match other archs and virt tools */
609 static Property arm_cpu_has_pmu_property
=
610 DEFINE_PROP_BOOL("pmu", ARMCPU
, has_pmu
, true);
612 static Property arm_cpu_has_mpu_property
=
613 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
615 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
616 * because the CPU initfn will have already set cpu->pmsav7_dregion to
617 * the right value for that particular CPU type, and we don't want
618 * to override that with an incorrect constant value.
620 static Property arm_cpu_pmsav7_dregion_property
=
621 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
623 qdev_prop_uint32
, uint32_t);
625 static void arm_cpu_post_init(Object
*obj
)
627 ARMCPU
*cpu
= ARM_CPU(obj
);
629 /* M profile implies PMSA. We have to do this here rather than
630 * in realize with the other feature-implication checks because
631 * we look at the PMSA bit to see if we should add some properties.
633 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
634 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
637 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
638 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
639 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
,
643 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
644 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
,
648 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
649 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
,
653 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
654 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
655 * prevent "has_el3" from existing on CPUs which cannot support EL3.
657 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
,
660 #ifndef CONFIG_USER_ONLY
661 object_property_add_link(obj
, "secure-memory",
663 (Object
**)&cpu
->secure_memory
,
664 qdev_prop_allow_set_link_before_realize
,
665 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
670 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
671 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
,
675 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
676 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_pmu_property
,
680 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
681 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
,
683 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
684 qdev_property_add_static(DEVICE(obj
),
685 &arm_cpu_pmsav7_dregion_property
,
690 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
,
694 static void arm_cpu_finalizefn(Object
*obj
)
696 ARMCPU
*cpu
= ARM_CPU(obj
);
697 g_hash_table_destroy(cpu
->cp_regs
);
700 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
702 CPUState
*cs
= CPU(dev
);
703 ARMCPU
*cpu
= ARM_CPU(dev
);
704 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
705 CPUARMState
*env
= &cpu
->env
;
707 Error
*local_err
= NULL
;
709 cpu_exec_realizefn(cs
, &local_err
);
710 if (local_err
!= NULL
) {
711 error_propagate(errp
, local_err
);
715 /* Some features automatically imply others: */
716 if (arm_feature(env
, ARM_FEATURE_V8
)) {
717 set_feature(env
, ARM_FEATURE_V7
);
718 set_feature(env
, ARM_FEATURE_ARM_DIV
);
719 set_feature(env
, ARM_FEATURE_LPAE
);
721 if (arm_feature(env
, ARM_FEATURE_V7
)) {
722 set_feature(env
, ARM_FEATURE_VAPA
);
723 set_feature(env
, ARM_FEATURE_THUMB2
);
724 set_feature(env
, ARM_FEATURE_MPIDR
);
725 if (!arm_feature(env
, ARM_FEATURE_M
)) {
726 set_feature(env
, ARM_FEATURE_V6K
);
728 set_feature(env
, ARM_FEATURE_V6
);
731 /* Always define VBAR for V7 CPUs even if it doesn't exist in
732 * non-EL3 configs. This is needed by some legacy boards.
734 set_feature(env
, ARM_FEATURE_VBAR
);
736 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
737 set_feature(env
, ARM_FEATURE_V6
);
738 set_feature(env
, ARM_FEATURE_MVFR
);
740 if (arm_feature(env
, ARM_FEATURE_V6
)) {
741 set_feature(env
, ARM_FEATURE_V5
);
742 set_feature(env
, ARM_FEATURE_JAZELLE
);
743 if (!arm_feature(env
, ARM_FEATURE_M
)) {
744 set_feature(env
, ARM_FEATURE_AUXCR
);
747 if (arm_feature(env
, ARM_FEATURE_V5
)) {
748 set_feature(env
, ARM_FEATURE_V4T
);
750 if (arm_feature(env
, ARM_FEATURE_M
)) {
751 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
753 if (arm_feature(env
, ARM_FEATURE_ARM_DIV
)) {
754 set_feature(env
, ARM_FEATURE_THUMB_DIV
);
756 if (arm_feature(env
, ARM_FEATURE_VFP4
)) {
757 set_feature(env
, ARM_FEATURE_VFP3
);
758 set_feature(env
, ARM_FEATURE_VFP_FP16
);
760 if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
761 set_feature(env
, ARM_FEATURE_VFP
);
763 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
764 set_feature(env
, ARM_FEATURE_V7MP
);
765 set_feature(env
, ARM_FEATURE_PXN
);
767 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
768 set_feature(env
, ARM_FEATURE_CBAR
);
770 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
771 !arm_feature(env
, ARM_FEATURE_M
)) {
772 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
775 if (arm_feature(env
, ARM_FEATURE_V7
) &&
776 !arm_feature(env
, ARM_FEATURE_M
) &&
777 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
778 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
783 /* For CPUs which might have tiny 1K pages, or which have an
784 * MPU and might have small region sizes, stick with 1K pages.
788 if (!set_preferred_target_page_bits(pagebits
)) {
789 /* This can only ever happen for hotplugging a CPU, or if
790 * the board code incorrectly creates a CPU which it has
791 * promised via minimum_page_size that it will not.
793 error_setg(errp
, "This CPU requires a smaller page size than the "
798 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
799 * We don't support setting cluster ID ([16..23]) (known as Aff2
800 * in later ARM ARM versions), or any of the higher affinity level fields,
801 * so these bits always RAZ.
803 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
804 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
805 ARM_DEFAULT_CPUS_PER_CLUSTER
);
808 if (cpu
->reset_hivecs
) {
809 cpu
->reset_sctlr
|= (1 << 13);
813 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
814 cpu
->reset_sctlr
|= SCTLR_EE
;
816 cpu
->reset_sctlr
|= SCTLR_B
;
821 /* If the has_el3 CPU property is disabled then we need to disable the
824 unset_feature(env
, ARM_FEATURE_EL3
);
826 /* Disable the security extension feature bits in the processor feature
827 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
829 cpu
->id_pfr1
&= ~0xf0;
830 cpu
->id_aa64pfr0
&= ~0xf000;
834 unset_feature(env
, ARM_FEATURE_EL2
);
838 unset_feature(env
, ARM_FEATURE_PMU
);
839 cpu
->id_aa64dfr0
&= ~0xf00;
842 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
843 /* Disable the hypervisor feature bits in the processor feature
844 * registers if we don't have EL2. These are id_pfr1[15:12] and
845 * id_aa64pfr0_el1[11:8].
847 cpu
->id_aa64pfr0
&= ~0xf00;
848 cpu
->id_pfr1
&= ~0xf000;
851 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
852 * to false or by setting pmsav7-dregion to 0.
855 cpu
->pmsav7_dregion
= 0;
857 if (cpu
->pmsav7_dregion
== 0) {
858 cpu
->has_mpu
= false;
861 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
862 arm_feature(env
, ARM_FEATURE_V7
)) {
863 uint32_t nr
= cpu
->pmsav7_dregion
;
866 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
871 if (arm_feature(env
, ARM_FEATURE_V8
)) {
873 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
874 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
875 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
876 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
877 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
880 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
881 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
882 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
887 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
888 uint32_t nr
= cpu
->sau_sregion
;
891 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
896 env
->sau
.rbar
= g_new0(uint32_t, nr
);
897 env
->sau
.rlar
= g_new0(uint32_t, nr
);
901 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
902 set_feature(env
, ARM_FEATURE_VBAR
);
905 register_cp_regs_for_features(cpu
);
906 arm_cpu_register_gdb_regs_for_features(cpu
);
908 init_cpreg_list(cpu
);
910 #ifndef CONFIG_USER_ONLY
911 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
914 if (!cpu
->secure_memory
) {
915 cpu
->secure_memory
= cs
->memory
;
917 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
922 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
928 acc
->parent_realize(dev
, errp
);
931 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
937 cpuname
= g_strsplit(cpu_model
, ",", 1);
938 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpuname
[0]);
939 oc
= object_class_by_name(typename
);
942 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
943 object_class_is_abstract(oc
)) {
949 /* CPU models. These are not needed for the AArch64 linux-user build. */
950 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
952 static void arm926_initfn(Object
*obj
)
954 ARMCPU
*cpu
= ARM_CPU(obj
);
956 cpu
->dtb_compatible
= "arm,arm926";
957 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
958 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
959 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
960 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
961 set_feature(&cpu
->env
, ARM_FEATURE_JAZELLE
);
962 cpu
->midr
= 0x41069265;
963 cpu
->reset_fpsid
= 0x41011090;
964 cpu
->ctr
= 0x1dd20d2;
965 cpu
->reset_sctlr
= 0x00090078;
968 static void arm946_initfn(Object
*obj
)
970 ARMCPU
*cpu
= ARM_CPU(obj
);
972 cpu
->dtb_compatible
= "arm,arm946";
973 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
974 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
975 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
976 cpu
->midr
= 0x41059461;
977 cpu
->ctr
= 0x0f004006;
978 cpu
->reset_sctlr
= 0x00000078;
981 static void arm1026_initfn(Object
*obj
)
983 ARMCPU
*cpu
= ARM_CPU(obj
);
985 cpu
->dtb_compatible
= "arm,arm1026";
986 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
987 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
988 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
989 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
990 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
991 set_feature(&cpu
->env
, ARM_FEATURE_JAZELLE
);
992 cpu
->midr
= 0x4106a262;
993 cpu
->reset_fpsid
= 0x410110a0;
994 cpu
->ctr
= 0x1dd20d2;
995 cpu
->reset_sctlr
= 0x00090078;
996 cpu
->reset_auxcr
= 1;
998 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
999 ARMCPRegInfo ifar
= {
1000 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1002 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1005 define_one_arm_cp_reg(cpu
, &ifar
);
1009 static void arm1136_r2_initfn(Object
*obj
)
1011 ARMCPU
*cpu
= ARM_CPU(obj
);
1012 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1013 * older core than plain "arm1136". In particular this does not
1014 * have the v6K features.
1015 * These ID register values are correct for 1136 but may be wrong
1016 * for 1136_r2 (in particular r0p2 does not actually implement most
1017 * of the ID registers).
1020 cpu
->dtb_compatible
= "arm,arm1136";
1021 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1022 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1023 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1024 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1025 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1026 cpu
->midr
= 0x4107b362;
1027 cpu
->reset_fpsid
= 0x410120b4;
1028 cpu
->mvfr0
= 0x11111111;
1029 cpu
->mvfr1
= 0x00000000;
1030 cpu
->ctr
= 0x1dd20d2;
1031 cpu
->reset_sctlr
= 0x00050078;
1032 cpu
->id_pfr0
= 0x111;
1036 cpu
->id_mmfr0
= 0x01130003;
1037 cpu
->id_mmfr1
= 0x10030302;
1038 cpu
->id_mmfr2
= 0x01222110;
1039 cpu
->id_isar0
= 0x00140011;
1040 cpu
->id_isar1
= 0x12002111;
1041 cpu
->id_isar2
= 0x11231111;
1042 cpu
->id_isar3
= 0x01102131;
1043 cpu
->id_isar4
= 0x141;
1044 cpu
->reset_auxcr
= 7;
1047 static void arm1136_initfn(Object
*obj
)
1049 ARMCPU
*cpu
= ARM_CPU(obj
);
1051 cpu
->dtb_compatible
= "arm,arm1136";
1052 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1053 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1054 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1055 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1056 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1057 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1058 cpu
->midr
= 0x4117b363;
1059 cpu
->reset_fpsid
= 0x410120b4;
1060 cpu
->mvfr0
= 0x11111111;
1061 cpu
->mvfr1
= 0x00000000;
1062 cpu
->ctr
= 0x1dd20d2;
1063 cpu
->reset_sctlr
= 0x00050078;
1064 cpu
->id_pfr0
= 0x111;
1068 cpu
->id_mmfr0
= 0x01130003;
1069 cpu
->id_mmfr1
= 0x10030302;
1070 cpu
->id_mmfr2
= 0x01222110;
1071 cpu
->id_isar0
= 0x00140011;
1072 cpu
->id_isar1
= 0x12002111;
1073 cpu
->id_isar2
= 0x11231111;
1074 cpu
->id_isar3
= 0x01102131;
1075 cpu
->id_isar4
= 0x141;
1076 cpu
->reset_auxcr
= 7;
1079 static void arm1176_initfn(Object
*obj
)
1081 ARMCPU
*cpu
= ARM_CPU(obj
);
1083 cpu
->dtb_compatible
= "arm,arm1176";
1084 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1085 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1086 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1087 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1088 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1089 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1090 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1091 cpu
->midr
= 0x410fb767;
1092 cpu
->reset_fpsid
= 0x410120b5;
1093 cpu
->mvfr0
= 0x11111111;
1094 cpu
->mvfr1
= 0x00000000;
1095 cpu
->ctr
= 0x1dd20d2;
1096 cpu
->reset_sctlr
= 0x00050078;
1097 cpu
->id_pfr0
= 0x111;
1098 cpu
->id_pfr1
= 0x11;
1099 cpu
->id_dfr0
= 0x33;
1101 cpu
->id_mmfr0
= 0x01130003;
1102 cpu
->id_mmfr1
= 0x10030302;
1103 cpu
->id_mmfr2
= 0x01222100;
1104 cpu
->id_isar0
= 0x0140011;
1105 cpu
->id_isar1
= 0x12002111;
1106 cpu
->id_isar2
= 0x11231121;
1107 cpu
->id_isar3
= 0x01102131;
1108 cpu
->id_isar4
= 0x01141;
1109 cpu
->reset_auxcr
= 7;
1112 static void arm11mpcore_initfn(Object
*obj
)
1114 ARMCPU
*cpu
= ARM_CPU(obj
);
1116 cpu
->dtb_compatible
= "arm,arm11mpcore";
1117 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1118 set_feature(&cpu
->env
, ARM_FEATURE_VFP
);
1119 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1120 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
1121 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1122 cpu
->midr
= 0x410fb022;
1123 cpu
->reset_fpsid
= 0x410120b4;
1124 cpu
->mvfr0
= 0x11111111;
1125 cpu
->mvfr1
= 0x00000000;
1126 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
1127 cpu
->id_pfr0
= 0x111;
1131 cpu
->id_mmfr0
= 0x01100103;
1132 cpu
->id_mmfr1
= 0x10020302;
1133 cpu
->id_mmfr2
= 0x01222000;
1134 cpu
->id_isar0
= 0x00100011;
1135 cpu
->id_isar1
= 0x12002111;
1136 cpu
->id_isar2
= 0x11221011;
1137 cpu
->id_isar3
= 0x01102131;
1138 cpu
->id_isar4
= 0x141;
1139 cpu
->reset_auxcr
= 1;
1142 static void cortex_m3_initfn(Object
*obj
)
1144 ARMCPU
*cpu
= ARM_CPU(obj
);
1145 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1146 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1147 cpu
->midr
= 0x410fc231;
1148 cpu
->pmsav7_dregion
= 8;
1151 static void cortex_m4_initfn(Object
*obj
)
1153 ARMCPU
*cpu
= ARM_CPU(obj
);
1155 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1156 set_feature(&cpu
->env
, ARM_FEATURE_M
);
1157 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
1158 cpu
->midr
= 0x410fc240; /* r0p0 */
1159 cpu
->pmsav7_dregion
= 8;
1162 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
1164 CPUClass
*cc
= CPU_CLASS(oc
);
1166 #ifndef CONFIG_USER_ONLY
1167 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
1170 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
1173 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
1174 /* Dummy the TCM region regs for the moment */
1175 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
1176 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1177 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
1178 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
1179 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
1180 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
1184 static void cortex_r5_initfn(Object
*obj
)
1186 ARMCPU
*cpu
= ARM_CPU(obj
);
1188 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1189 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DIV
);
1190 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1191 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1192 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1193 cpu
->midr
= 0x411fc153; /* r1p3 */
1194 cpu
->id_pfr0
= 0x0131;
1195 cpu
->id_pfr1
= 0x001;
1196 cpu
->id_dfr0
= 0x010400;
1198 cpu
->id_mmfr0
= 0x0210030;
1199 cpu
->id_mmfr1
= 0x00000000;
1200 cpu
->id_mmfr2
= 0x01200000;
1201 cpu
->id_mmfr3
= 0x0211;
1202 cpu
->id_isar0
= 0x2101111;
1203 cpu
->id_isar1
= 0x13112111;
1204 cpu
->id_isar2
= 0x21232141;
1205 cpu
->id_isar3
= 0x01112131;
1206 cpu
->id_isar4
= 0x0010142;
1207 cpu
->id_isar5
= 0x0;
1208 cpu
->mp_is_up
= true;
1209 cpu
->pmsav7_dregion
= 16;
1210 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
1213 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
1214 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
1215 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1216 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1217 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1221 static void cortex_a8_initfn(Object
*obj
)
1223 ARMCPU
*cpu
= ARM_CPU(obj
);
1225 cpu
->dtb_compatible
= "arm,cortex-a8";
1226 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1227 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1228 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1229 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1230 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1231 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1232 cpu
->midr
= 0x410fc080;
1233 cpu
->reset_fpsid
= 0x410330c0;
1234 cpu
->mvfr0
= 0x11110222;
1235 cpu
->mvfr1
= 0x00011111;
1236 cpu
->ctr
= 0x82048004;
1237 cpu
->reset_sctlr
= 0x00c50078;
1238 cpu
->id_pfr0
= 0x1031;
1239 cpu
->id_pfr1
= 0x11;
1240 cpu
->id_dfr0
= 0x400;
1242 cpu
->id_mmfr0
= 0x31100003;
1243 cpu
->id_mmfr1
= 0x20000000;
1244 cpu
->id_mmfr2
= 0x01202000;
1245 cpu
->id_mmfr3
= 0x11;
1246 cpu
->id_isar0
= 0x00101111;
1247 cpu
->id_isar1
= 0x12112111;
1248 cpu
->id_isar2
= 0x21232031;
1249 cpu
->id_isar3
= 0x11112131;
1250 cpu
->id_isar4
= 0x00111142;
1251 cpu
->dbgdidr
= 0x15141000;
1252 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
1253 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
1254 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
1255 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
1256 cpu
->reset_auxcr
= 2;
1257 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
1260 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
1261 /* power_control should be set to maximum latency. Again,
1262 * default to 0 and set by private hook
1264 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1265 .access
= PL1_RW
, .resetvalue
= 0,
1266 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
1267 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
1268 .access
= PL1_RW
, .resetvalue
= 0,
1269 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
1270 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
1271 .access
= PL1_RW
, .resetvalue
= 0,
1272 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
1273 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1274 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1275 /* TLB lockdown control */
1276 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
1277 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1278 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
1279 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
1280 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
1281 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1282 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
1283 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1284 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
1285 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
1289 static void cortex_a9_initfn(Object
*obj
)
1291 ARMCPU
*cpu
= ARM_CPU(obj
);
1293 cpu
->dtb_compatible
= "arm,cortex-a9";
1294 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1295 set_feature(&cpu
->env
, ARM_FEATURE_VFP3
);
1296 set_feature(&cpu
->env
, ARM_FEATURE_VFP_FP16
);
1297 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1298 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1299 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1300 /* Note that A9 supports the MP extensions even for
1301 * A9UP and single-core A9MP (which are both different
1302 * and valid configurations; we don't model A9UP).
1304 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
1305 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
1306 cpu
->midr
= 0x410fc090;
1307 cpu
->reset_fpsid
= 0x41033090;
1308 cpu
->mvfr0
= 0x11110222;
1309 cpu
->mvfr1
= 0x01111111;
1310 cpu
->ctr
= 0x80038003;
1311 cpu
->reset_sctlr
= 0x00c50078;
1312 cpu
->id_pfr0
= 0x1031;
1313 cpu
->id_pfr1
= 0x11;
1314 cpu
->id_dfr0
= 0x000;
1316 cpu
->id_mmfr0
= 0x00100103;
1317 cpu
->id_mmfr1
= 0x20000000;
1318 cpu
->id_mmfr2
= 0x01230000;
1319 cpu
->id_mmfr3
= 0x00002111;
1320 cpu
->id_isar0
= 0x00101111;
1321 cpu
->id_isar1
= 0x13112111;
1322 cpu
->id_isar2
= 0x21232041;
1323 cpu
->id_isar3
= 0x11112131;
1324 cpu
->id_isar4
= 0x00111142;
1325 cpu
->dbgdidr
= 0x35141000;
1326 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
1327 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
1328 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
1329 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
1332 #ifndef CONFIG_USER_ONLY
1333 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1335 /* Linux wants the number of processors from here.
1336 * Might as well set the interrupt-controller bit too.
1338 return ((smp_cpus
- 1) << 24) | (1 << 23);
1342 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
1343 #ifndef CONFIG_USER_ONLY
1344 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
1345 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
1346 .writefn
= arm_cp_write_ignore
, },
1348 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
1349 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1353 static void cortex_a7_initfn(Object
*obj
)
1355 ARMCPU
*cpu
= ARM_CPU(obj
);
1357 cpu
->dtb_compatible
= "arm,cortex-a7";
1358 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1359 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1360 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1361 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1362 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1363 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1364 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1365 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1366 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1367 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1368 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
1369 cpu
->midr
= 0x410fc075;
1370 cpu
->reset_fpsid
= 0x41023075;
1371 cpu
->mvfr0
= 0x10110222;
1372 cpu
->mvfr1
= 0x11111111;
1373 cpu
->ctr
= 0x84448003;
1374 cpu
->reset_sctlr
= 0x00c50078;
1375 cpu
->id_pfr0
= 0x00001131;
1376 cpu
->id_pfr1
= 0x00011011;
1377 cpu
->id_dfr0
= 0x02010555;
1378 cpu
->pmceid0
= 0x00000000;
1379 cpu
->pmceid1
= 0x00000000;
1380 cpu
->id_afr0
= 0x00000000;
1381 cpu
->id_mmfr0
= 0x10101105;
1382 cpu
->id_mmfr1
= 0x40000000;
1383 cpu
->id_mmfr2
= 0x01240000;
1384 cpu
->id_mmfr3
= 0x02102211;
1385 cpu
->id_isar0
= 0x01101110;
1386 cpu
->id_isar1
= 0x13112111;
1387 cpu
->id_isar2
= 0x21232041;
1388 cpu
->id_isar3
= 0x11112131;
1389 cpu
->id_isar4
= 0x10011142;
1390 cpu
->dbgdidr
= 0x3515f005;
1391 cpu
->clidr
= 0x0a200023;
1392 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1393 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1394 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1395 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
1398 static void cortex_a15_initfn(Object
*obj
)
1400 ARMCPU
*cpu
= ARM_CPU(obj
);
1402 cpu
->dtb_compatible
= "arm,cortex-a15";
1403 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
1404 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1405 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1406 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1407 set_feature(&cpu
->env
, ARM_FEATURE_ARM_DIV
);
1408 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
1409 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1410 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
1411 set_feature(&cpu
->env
, ARM_FEATURE_LPAE
);
1412 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1413 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
1414 cpu
->midr
= 0x412fc0f1;
1415 cpu
->reset_fpsid
= 0x410430f0;
1416 cpu
->mvfr0
= 0x10110222;
1417 cpu
->mvfr1
= 0x11111111;
1418 cpu
->ctr
= 0x8444c004;
1419 cpu
->reset_sctlr
= 0x00c50078;
1420 cpu
->id_pfr0
= 0x00001131;
1421 cpu
->id_pfr1
= 0x00011011;
1422 cpu
->id_dfr0
= 0x02010555;
1423 cpu
->pmceid0
= 0x0000000;
1424 cpu
->pmceid1
= 0x00000000;
1425 cpu
->id_afr0
= 0x00000000;
1426 cpu
->id_mmfr0
= 0x10201105;
1427 cpu
->id_mmfr1
= 0x20000000;
1428 cpu
->id_mmfr2
= 0x01240000;
1429 cpu
->id_mmfr3
= 0x02102211;
1430 cpu
->id_isar0
= 0x02101110;
1431 cpu
->id_isar1
= 0x13112111;
1432 cpu
->id_isar2
= 0x21232041;
1433 cpu
->id_isar3
= 0x11112131;
1434 cpu
->id_isar4
= 0x10011142;
1435 cpu
->dbgdidr
= 0x3515f021;
1436 cpu
->clidr
= 0x0a200023;
1437 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
1438 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
1439 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
1440 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
1443 static void ti925t_initfn(Object
*obj
)
1445 ARMCPU
*cpu
= ARM_CPU(obj
);
1446 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
1447 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
1448 cpu
->midr
= ARM_CPUID_TI925T
;
1449 cpu
->ctr
= 0x5109149;
1450 cpu
->reset_sctlr
= 0x00000070;
1453 static void sa1100_initfn(Object
*obj
)
1455 ARMCPU
*cpu
= ARM_CPU(obj
);
1457 cpu
->dtb_compatible
= "intel,sa1100";
1458 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1459 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1460 cpu
->midr
= 0x4401A11B;
1461 cpu
->reset_sctlr
= 0x00000070;
1464 static void sa1110_initfn(Object
*obj
)
1466 ARMCPU
*cpu
= ARM_CPU(obj
);
1467 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
1468 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1469 cpu
->midr
= 0x6901B119;
1470 cpu
->reset_sctlr
= 0x00000070;
1473 static void pxa250_initfn(Object
*obj
)
1475 ARMCPU
*cpu
= ARM_CPU(obj
);
1477 cpu
->dtb_compatible
= "marvell,xscale";
1478 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1479 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1480 cpu
->midr
= 0x69052100;
1481 cpu
->ctr
= 0xd172172;
1482 cpu
->reset_sctlr
= 0x00000078;
1485 static void pxa255_initfn(Object
*obj
)
1487 ARMCPU
*cpu
= ARM_CPU(obj
);
1489 cpu
->dtb_compatible
= "marvell,xscale";
1490 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1491 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1492 cpu
->midr
= 0x69052d00;
1493 cpu
->ctr
= 0xd172172;
1494 cpu
->reset_sctlr
= 0x00000078;
1497 static void pxa260_initfn(Object
*obj
)
1499 ARMCPU
*cpu
= ARM_CPU(obj
);
1501 cpu
->dtb_compatible
= "marvell,xscale";
1502 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1503 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1504 cpu
->midr
= 0x69052903;
1505 cpu
->ctr
= 0xd172172;
1506 cpu
->reset_sctlr
= 0x00000078;
1509 static void pxa261_initfn(Object
*obj
)
1511 ARMCPU
*cpu
= ARM_CPU(obj
);
1513 cpu
->dtb_compatible
= "marvell,xscale";
1514 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1515 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1516 cpu
->midr
= 0x69052d05;
1517 cpu
->ctr
= 0xd172172;
1518 cpu
->reset_sctlr
= 0x00000078;
1521 static void pxa262_initfn(Object
*obj
)
1523 ARMCPU
*cpu
= ARM_CPU(obj
);
1525 cpu
->dtb_compatible
= "marvell,xscale";
1526 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1527 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1528 cpu
->midr
= 0x69052d06;
1529 cpu
->ctr
= 0xd172172;
1530 cpu
->reset_sctlr
= 0x00000078;
1533 static void pxa270a0_initfn(Object
*obj
)
1535 ARMCPU
*cpu
= ARM_CPU(obj
);
1537 cpu
->dtb_compatible
= "marvell,xscale";
1538 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1539 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1540 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1541 cpu
->midr
= 0x69054110;
1542 cpu
->ctr
= 0xd172172;
1543 cpu
->reset_sctlr
= 0x00000078;
1546 static void pxa270a1_initfn(Object
*obj
)
1548 ARMCPU
*cpu
= ARM_CPU(obj
);
1550 cpu
->dtb_compatible
= "marvell,xscale";
1551 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1552 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1553 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1554 cpu
->midr
= 0x69054111;
1555 cpu
->ctr
= 0xd172172;
1556 cpu
->reset_sctlr
= 0x00000078;
1559 static void pxa270b0_initfn(Object
*obj
)
1561 ARMCPU
*cpu
= ARM_CPU(obj
);
1563 cpu
->dtb_compatible
= "marvell,xscale";
1564 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1565 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1566 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1567 cpu
->midr
= 0x69054112;
1568 cpu
->ctr
= 0xd172172;
1569 cpu
->reset_sctlr
= 0x00000078;
1572 static void pxa270b1_initfn(Object
*obj
)
1574 ARMCPU
*cpu
= ARM_CPU(obj
);
1576 cpu
->dtb_compatible
= "marvell,xscale";
1577 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1578 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1579 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1580 cpu
->midr
= 0x69054113;
1581 cpu
->ctr
= 0xd172172;
1582 cpu
->reset_sctlr
= 0x00000078;
1585 static void pxa270c0_initfn(Object
*obj
)
1587 ARMCPU
*cpu
= ARM_CPU(obj
);
1589 cpu
->dtb_compatible
= "marvell,xscale";
1590 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1591 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1592 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1593 cpu
->midr
= 0x69054114;
1594 cpu
->ctr
= 0xd172172;
1595 cpu
->reset_sctlr
= 0x00000078;
1598 static void pxa270c5_initfn(Object
*obj
)
1600 ARMCPU
*cpu
= ARM_CPU(obj
);
1602 cpu
->dtb_compatible
= "marvell,xscale";
1603 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1604 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
1605 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
1606 cpu
->midr
= 0x69054117;
1607 cpu
->ctr
= 0xd172172;
1608 cpu
->reset_sctlr
= 0x00000078;
1611 #ifdef CONFIG_USER_ONLY
1612 static void arm_any_initfn(Object
*obj
)
1614 ARMCPU
*cpu
= ARM_CPU(obj
);
1615 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
1616 set_feature(&cpu
->env
, ARM_FEATURE_VFP4
);
1617 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
1618 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
1619 set_feature(&cpu
->env
, ARM_FEATURE_V8_AES
);
1620 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA1
);
1621 set_feature(&cpu
->env
, ARM_FEATURE_V8_SHA256
);
1622 set_feature(&cpu
->env
, ARM_FEATURE_V8_PMULL
);
1623 set_feature(&cpu
->env
, ARM_FEATURE_CRC
);
1624 cpu
->midr
= 0xffffffff;
1628 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1630 typedef struct ARMCPUInfo
{
1632 void (*initfn
)(Object
*obj
);
1633 void (*class_init
)(ObjectClass
*oc
, void *data
);
1636 static const ARMCPUInfo arm_cpus
[] = {
1637 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1638 { .name
= "arm926", .initfn
= arm926_initfn
},
1639 { .name
= "arm946", .initfn
= arm946_initfn
},
1640 { .name
= "arm1026", .initfn
= arm1026_initfn
},
1641 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1642 * older core than plain "arm1136". In particular this does not
1643 * have the v6K features.
1645 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
1646 { .name
= "arm1136", .initfn
= arm1136_initfn
},
1647 { .name
= "arm1176", .initfn
= arm1176_initfn
},
1648 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
1649 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
1650 .class_init
= arm_v7m_class_init
},
1651 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
1652 .class_init
= arm_v7m_class_init
},
1653 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
1654 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
1655 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
1656 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
1657 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
1658 { .name
= "ti925t", .initfn
= ti925t_initfn
},
1659 { .name
= "sa1100", .initfn
= sa1100_initfn
},
1660 { .name
= "sa1110", .initfn
= sa1110_initfn
},
1661 { .name
= "pxa250", .initfn
= pxa250_initfn
},
1662 { .name
= "pxa255", .initfn
= pxa255_initfn
},
1663 { .name
= "pxa260", .initfn
= pxa260_initfn
},
1664 { .name
= "pxa261", .initfn
= pxa261_initfn
},
1665 { .name
= "pxa262", .initfn
= pxa262_initfn
},
1666 /* "pxa270" is an alias for "pxa270-a0" */
1667 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
1668 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
1669 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
1670 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
1671 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
1672 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
1673 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
1674 #ifdef CONFIG_USER_ONLY
1675 { .name
= "any", .initfn
= arm_any_initfn
},
1681 static Property arm_cpu_properties
[] = {
1682 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
1683 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
1684 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
1685 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
1686 mp_affinity
, ARM64_AFFINITY_INVALID
),
1687 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
1688 DEFINE_PROP_END_OF_LIST()
1691 #ifdef CONFIG_USER_ONLY
1692 static int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int size
,
1693 int rw
, int mmu_idx
)
1695 ARMCPU
*cpu
= ARM_CPU(cs
);
1696 CPUARMState
*env
= &cpu
->env
;
1698 env
->exception
.vaddress
= address
;
1700 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
1702 cs
->exception_index
= EXCP_DATA_ABORT
;
1708 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
1710 ARMCPU
*cpu
= ARM_CPU(cs
);
1711 CPUARMState
*env
= &cpu
->env
;
1713 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
1714 return g_strdup("iwmmxt");
1716 return g_strdup("arm");
1719 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
1721 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1722 CPUClass
*cc
= CPU_CLASS(acc
);
1723 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1725 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
1726 &acc
->parent_realize
);
1727 dc
->props
= arm_cpu_properties
;
1729 acc
->parent_reset
= cc
->reset
;
1730 cc
->reset
= arm_cpu_reset
;
1732 cc
->class_by_name
= arm_cpu_class_by_name
;
1733 cc
->has_work
= arm_cpu_has_work
;
1734 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
1735 cc
->dump_state
= arm_cpu_dump_state
;
1736 cc
->set_pc
= arm_cpu_set_pc
;
1737 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
1738 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
1739 #ifdef CONFIG_USER_ONLY
1740 cc
->handle_mmu_fault
= arm_cpu_handle_mmu_fault
;
1742 cc
->do_interrupt
= arm_cpu_do_interrupt
;
1743 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
1744 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
1745 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
1746 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
1747 cc
->vmsd
= &vmstate_arm_cpu
;
1748 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
1749 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
1750 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
1752 cc
->gdb_num_core_regs
= 26;
1753 cc
->gdb_core_xml_file
= "arm-core.xml";
1754 cc
->gdb_arch_name
= arm_gdb_arch_name
;
1755 cc
->gdb_stop_before_watchpoint
= true;
1756 cc
->debug_excp_handler
= arm_debug_excp_handler
;
1757 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
1758 #if !defined(CONFIG_USER_ONLY)
1759 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
1762 cc
->disas_set_info
= arm_disas_set_info
;
1764 cc
->tcg_initialize
= arm_translate_init
;
1768 static void cpu_register(const ARMCPUInfo
*info
)
1770 TypeInfo type_info
= {
1771 .parent
= TYPE_ARM_CPU
,
1772 .instance_size
= sizeof(ARMCPU
),
1773 .instance_init
= info
->initfn
,
1774 .class_size
= sizeof(ARMCPUClass
),
1775 .class_init
= info
->class_init
,
1778 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1779 type_register(&type_info
);
1780 g_free((void *)type_info
.name
);
1783 static const TypeInfo arm_cpu_type_info
= {
1784 .name
= TYPE_ARM_CPU
,
1786 .instance_size
= sizeof(ARMCPU
),
1787 .instance_init
= arm_cpu_initfn
,
1788 .instance_post_init
= arm_cpu_post_init
,
1789 .instance_finalize
= arm_cpu_finalizefn
,
1791 .class_size
= sizeof(ARMCPUClass
),
1792 .class_init
= arm_cpu_class_init
,
1795 static void arm_cpu_register_types(void)
1797 const ARMCPUInfo
*info
= arm_cpus
;
1799 type_register_static(&arm_cpu_type_info
);
1801 while (info
->name
) {
1807 type_init(arm_cpu_register_types
)