2 * SD Association Host Standard Specification v2.0 controller emulation
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Mitsyanko Igor <i.mitsyanko@samsung.com>
6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com>
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
9 * by Alexey Merkulov and Vladimir Monakhov.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/osdep.h"
26 #include "qemu/error-report.h"
27 #include "qapi/error.h"
29 #include "sysemu/block-backend.h"
30 #include "sysemu/blockdev.h"
31 #include "sysemu/dma.h"
32 #include "qemu/timer.h"
33 #include "qemu/bitops.h"
34 #include "hw/sd/sdhci.h"
35 #include "sdhci-internal.h"
37 #include "qemu/cutils.h"
40 #define TYPE_SDHCI_BUS "sdhci-bus"
41 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS)
43 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val))
45 /* Default SD/MMC host controller features information, which will be
46 * presented in CAPABILITIES register of generic SD host controller at reset.
49 * - 3.3v and 1.8v voltages
52 * max host controller R/W buffers size: 512B
53 * max clock frequency for SDclock: 52 MHz
54 * timeout clock frequency: 52 MHz
61 #define SDHC_CAPAB_REG_DEFAULT 0x057834b4
63 static inline unsigned int sdhci_get_fifolen(SDHCIState
*s
)
65 return 1 << (9 + FIELD_EX32(s
->capareg
, SDHC_CAPAB
, MAXBLOCKLENGTH
));
68 /* return true on error */
69 static bool sdhci_check_capab_freq_range(SDHCIState
*s
, const char *desc
,
70 uint8_t freq
, Error
**errp
)
72 if (s
->sd_spec_version
>= 3) {
80 error_setg(errp
, "SD %s clock frequency can have value"
81 "in range 0-63 only", desc
);
87 static void sdhci_check_capareg(SDHCIState
*s
, Error
**errp
)
89 uint64_t msk
= s
->capareg
;
93 switch (s
->sd_spec_version
) {
95 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS64BIT_V4
);
96 trace_sdhci_capareg("64-bit system bus (v4)", val
);
97 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS64BIT_V4
, 0);
99 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, UHS_II
);
100 trace_sdhci_capareg("UHS-II", val
);
101 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, UHS_II
, 0);
103 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA3
);
104 trace_sdhci_capareg("ADMA3", val
);
105 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA3
, 0);
109 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ASYNC_INT
);
110 trace_sdhci_capareg("async interrupt", val
);
111 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ASYNC_INT
, 0);
113 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SLOT_TYPE
);
115 error_setg(errp
, "slot-type not supported");
118 trace_sdhci_capareg("slot type", val
);
119 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SLOT_TYPE
, 0);
122 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, EMBEDDED_8BIT
);
123 trace_sdhci_capareg("8-bit bus", val
);
125 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, EMBEDDED_8BIT
, 0);
127 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS_SPEED
);
128 trace_sdhci_capareg("bus speed mask", val
);
129 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS_SPEED
, 0);
131 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, DRIVER_STRENGTH
);
132 trace_sdhci_capareg("driver strength mask", val
);
133 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, DRIVER_STRENGTH
, 0);
135 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TIMER_RETUNING
);
136 trace_sdhci_capareg("timer re-tuning", val
);
137 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TIMER_RETUNING
, 0);
139 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SDR50_TUNING
);
140 trace_sdhci_capareg("use SDR50 tuning", val
);
141 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SDR50_TUNING
, 0);
143 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, RETUNING_MODE
);
144 trace_sdhci_capareg("re-tuning mode", val
);
145 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, RETUNING_MODE
, 0);
147 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, CLOCK_MULT
);
148 trace_sdhci_capareg("clock multiplier", val
);
149 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, CLOCK_MULT
, 0);
152 case 2: /* default version */
153 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA2
);
154 trace_sdhci_capareg("ADMA2", val
);
155 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA2
, 0);
157 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, ADMA1
);
158 trace_sdhci_capareg("ADMA1", val
);
159 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, ADMA1
, 0);
161 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BUS64BIT
);
162 trace_sdhci_capareg("64-bit system bus (v3)", val
);
163 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BUS64BIT
, 0);
167 y
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TOUNIT
);
168 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TOUNIT
, 0);
170 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, TOCLKFREQ
);
171 trace_sdhci_capareg(y
? "timeout (MHz)" : "Timeout (KHz)", val
);
172 if (sdhci_check_capab_freq_range(s
, "timeout", val
, errp
)) {
175 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, TOCLKFREQ
, 0);
177 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, BASECLKFREQ
);
178 trace_sdhci_capareg(y
? "base (MHz)" : "Base (KHz)", val
);
179 if (sdhci_check_capab_freq_range(s
, "base", val
, errp
)) {
182 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, BASECLKFREQ
, 0);
184 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, MAXBLOCKLENGTH
);
186 error_setg(errp
, "block size can be 512, 1024 or 2048 only");
189 trace_sdhci_capareg("max block length", sdhci_get_fifolen(s
));
190 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, MAXBLOCKLENGTH
, 0);
192 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, HIGHSPEED
);
193 trace_sdhci_capareg("high speed", val
);
194 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, HIGHSPEED
, 0);
196 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SDMA
);
197 trace_sdhci_capareg("SDMA", val
);
198 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SDMA
, 0);
200 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, SUSPRESUME
);
201 trace_sdhci_capareg("suspend/resume", val
);
202 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, SUSPRESUME
, 0);
204 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V33
);
205 trace_sdhci_capareg("3.3v", val
);
206 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V33
, 0);
208 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V30
);
209 trace_sdhci_capareg("3.0v", val
);
210 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V30
, 0);
212 val
= FIELD_EX64(s
->capareg
, SDHC_CAPAB
, V18
);
213 trace_sdhci_capareg("1.8v", val
);
214 msk
= FIELD_DP64(msk
, SDHC_CAPAB
, V18
, 0);
218 error_setg(errp
, "Unsupported spec version: %u", s
->sd_spec_version
);
221 qemu_log_mask(LOG_UNIMP
,
222 "SDHCI: unknown CAPAB mask: 0x%016" PRIx64
"\n", msk
);
226 static uint8_t sdhci_slotint(SDHCIState
*s
)
228 return (s
->norintsts
& s
->norintsigen
) || (s
->errintsts
& s
->errintsigen
) ||
229 ((s
->norintsts
& SDHC_NIS_INSERT
) && (s
->wakcon
& SDHC_WKUP_ON_INS
)) ||
230 ((s
->norintsts
& SDHC_NIS_REMOVE
) && (s
->wakcon
& SDHC_WKUP_ON_RMV
));
233 static inline void sdhci_update_irq(SDHCIState
*s
)
235 qemu_set_irq(s
->irq
, sdhci_slotint(s
));
238 static void sdhci_raise_insertion_irq(void *opaque
)
240 SDHCIState
*s
= (SDHCIState
*)opaque
;
242 if (s
->norintsts
& SDHC_NIS_REMOVE
) {
243 timer_mod(s
->insert_timer
,
244 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
246 s
->prnsts
= 0x1ff0000;
247 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
248 s
->norintsts
|= SDHC_NIS_INSERT
;
254 static void sdhci_set_inserted(DeviceState
*dev
, bool level
)
256 SDHCIState
*s
= (SDHCIState
*)dev
;
258 trace_sdhci_set_inserted(level
? "insert" : "eject");
259 if ((s
->norintsts
& SDHC_NIS_REMOVE
) && level
) {
260 /* Give target some time to notice card ejection */
261 timer_mod(s
->insert_timer
,
262 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_INSERTION_DELAY
);
265 s
->prnsts
= 0x1ff0000;
266 if (s
->norintstsen
& SDHC_NISEN_INSERT
) {
267 s
->norintsts
|= SDHC_NIS_INSERT
;
270 s
->prnsts
= 0x1fa0000;
271 s
->pwrcon
&= ~SDHC_POWER_ON
;
272 s
->clkcon
&= ~SDHC_CLOCK_SDCLK_EN
;
273 if (s
->norintstsen
& SDHC_NISEN_REMOVE
) {
274 s
->norintsts
|= SDHC_NIS_REMOVE
;
281 static void sdhci_set_readonly(DeviceState
*dev
, bool level
)
283 SDHCIState
*s
= (SDHCIState
*)dev
;
286 s
->prnsts
&= ~SDHC_WRITE_PROTECT
;
289 s
->prnsts
|= SDHC_WRITE_PROTECT
;
293 static void sdhci_reset(SDHCIState
*s
)
295 DeviceState
*dev
= DEVICE(s
);
297 timer_del(s
->insert_timer
);
298 timer_del(s
->transfer_timer
);
300 /* Set all registers to 0. Capabilities/Version registers are not cleared
301 * and assumed to always preserve their value, given to them during
303 memset(&s
->sdmasysad
, 0, (uintptr_t)&s
->capareg
- (uintptr_t)&s
->sdmasysad
);
305 /* Reset other state based on current card insertion/readonly status */
306 sdhci_set_inserted(dev
, sdbus_get_inserted(&s
->sdbus
));
307 sdhci_set_readonly(dev
, sdbus_get_readonly(&s
->sdbus
));
310 s
->stopped_state
= sdhc_not_stopped
;
311 s
->pending_insert_state
= false;
314 static void sdhci_poweron_reset(DeviceState
*dev
)
316 /* QOM (ie power-on) reset. This is identical to reset
317 * commanded via device register apart from handling of the
318 * 'pending insert on powerup' quirk.
320 SDHCIState
*s
= (SDHCIState
*)dev
;
324 if (s
->pending_insert_quirk
) {
325 s
->pending_insert_state
= true;
329 static void sdhci_data_transfer(void *opaque
);
331 static void sdhci_send_command(SDHCIState
*s
)
334 uint8_t response
[16];
339 request
.cmd
= s
->cmdreg
>> 8;
340 request
.arg
= s
->argument
;
342 trace_sdhci_send_command(request
.cmd
, request
.arg
);
343 rlen
= sdbus_do_command(&s
->sdbus
, &request
, response
);
345 if (s
->cmdreg
& SDHC_CMD_RESPONSE
) {
347 s
->rspreg
[0] = (response
[0] << 24) | (response
[1] << 16) |
348 (response
[2] << 8) | response
[3];
349 s
->rspreg
[1] = s
->rspreg
[2] = s
->rspreg
[3] = 0;
350 trace_sdhci_response4(s
->rspreg
[0]);
351 } else if (rlen
== 16) {
352 s
->rspreg
[0] = (response
[11] << 24) | (response
[12] << 16) |
353 (response
[13] << 8) | response
[14];
354 s
->rspreg
[1] = (response
[7] << 24) | (response
[8] << 16) |
355 (response
[9] << 8) | response
[10];
356 s
->rspreg
[2] = (response
[3] << 24) | (response
[4] << 16) |
357 (response
[5] << 8) | response
[6];
358 s
->rspreg
[3] = (response
[0] << 16) | (response
[1] << 8) |
360 trace_sdhci_response16(s
->rspreg
[3], s
->rspreg
[2],
361 s
->rspreg
[1], s
->rspreg
[0]);
363 trace_sdhci_error("timeout waiting for command response");
364 if (s
->errintstsen
& SDHC_EISEN_CMDTIMEOUT
) {
365 s
->errintsts
|= SDHC_EIS_CMDTIMEOUT
;
366 s
->norintsts
|= SDHC_NIS_ERR
;
370 if (!(s
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
) &&
371 (s
->norintstsen
& SDHC_NISEN_TRSCMP
) &&
372 (s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
) {
373 s
->norintsts
|= SDHC_NIS_TRSCMP
;
377 if (s
->norintstsen
& SDHC_NISEN_CMDCMP
) {
378 s
->norintsts
|= SDHC_NIS_CMDCMP
;
383 if (s
->blksize
&& (s
->cmdreg
& SDHC_CMD_DATA_PRESENT
)) {
385 sdhci_data_transfer(s
);
389 static void sdhci_end_transfer(SDHCIState
*s
)
391 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */
392 if ((s
->trnmod
& SDHC_TRNS_ACMD12
) != 0) {
394 uint8_t response
[16];
398 trace_sdhci_end_transfer(request
.cmd
, request
.arg
);
399 sdbus_do_command(&s
->sdbus
, &request
, response
);
400 /* Auto CMD12 response goes to the upper Response register */
401 s
->rspreg
[3] = (response
[0] << 24) | (response
[1] << 16) |
402 (response
[2] << 8) | response
[3];
405 s
->prnsts
&= ~(SDHC_DOING_READ
| SDHC_DOING_WRITE
|
406 SDHC_DAT_LINE_ACTIVE
| SDHC_DATA_INHIBIT
|
407 SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
);
409 if (s
->norintstsen
& SDHC_NISEN_TRSCMP
) {
410 s
->norintsts
|= SDHC_NIS_TRSCMP
;
417 * Programmed i/o data transfer
419 #define BLOCK_SIZE_MASK (4 * K_BYTE - 1)
421 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */
422 static void sdhci_read_block_from_card(SDHCIState
*s
)
426 const uint16_t blk_size
= s
->blksize
& BLOCK_SIZE_MASK
;
428 if ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
429 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) {
433 for (index
= 0; index
< blk_size
; index
++) {
434 data
= sdbus_read_data(&s
->sdbus
);
435 if (!FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, EXECUTE_TUNING
)) {
436 /* Device is not in tunning */
437 s
->fifo_buffer
[index
] = data
;
441 if (FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, EXECUTE_TUNING
)) {
442 /* Device is in tunning */
443 s
->hostctl2
&= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK
;
444 s
->hostctl2
|= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK
;
445 s
->prnsts
&= ~(SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
|
450 /* New data now available for READ through Buffer Port Register */
451 s
->prnsts
|= SDHC_DATA_AVAILABLE
;
452 if (s
->norintstsen
& SDHC_NISEN_RBUFRDY
) {
453 s
->norintsts
|= SDHC_NIS_RBUFRDY
;
456 /* Clear DAT line active status if that was the last block */
457 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
458 ((s
->trnmod
& SDHC_TRNS_MULTI
) && s
->blkcnt
== 1)) {
459 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
462 /* If stop at block gap request was set and it's not the last block of
463 * data - generate Block Event interrupt */
464 if (s
->stopped_state
== sdhc_gap_read
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
466 s
->prnsts
&= ~SDHC_DAT_LINE_ACTIVE
;
467 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
468 s
->norintsts
|= SDHC_EIS_BLKGAP
;
476 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */
477 static uint32_t sdhci_read_dataport(SDHCIState
*s
, unsigned size
)
482 /* first check that a valid data exists in host controller input buffer */
483 if ((s
->prnsts
& SDHC_DATA_AVAILABLE
) == 0) {
484 trace_sdhci_error("read from empty buffer");
488 for (i
= 0; i
< size
; i
++) {
489 value
|= s
->fifo_buffer
[s
->data_count
] << i
* 8;
491 /* check if we've read all valid data (blksize bytes) from buffer */
492 if ((s
->data_count
) >= (s
->blksize
& BLOCK_SIZE_MASK
)) {
493 trace_sdhci_read_dataport(s
->data_count
);
494 s
->prnsts
&= ~SDHC_DATA_AVAILABLE
; /* no more data in a buffer */
495 s
->data_count
= 0; /* next buff read must start at position [0] */
497 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
501 /* if that was the last block of data */
502 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
503 ((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0)) ||
504 /* stop at gap request */
505 (s
->stopped_state
== sdhc_gap_read
&&
506 !(s
->prnsts
& SDHC_DAT_LINE_ACTIVE
))) {
507 sdhci_end_transfer(s
);
508 } else { /* if there are more data, read next block from card */
509 sdhci_read_block_from_card(s
);
518 /* Write data from host controller FIFO to card */
519 static void sdhci_write_block_to_card(SDHCIState
*s
)
523 if (s
->prnsts
& SDHC_SPACE_AVAILABLE
) {
524 if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
525 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
531 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
532 if (s
->blkcnt
== 0) {
539 for (index
= 0; index
< (s
->blksize
& BLOCK_SIZE_MASK
); index
++) {
540 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[index
]);
543 /* Next data can be written through BUFFER DATORT register */
544 s
->prnsts
|= SDHC_SPACE_AVAILABLE
;
546 /* Finish transfer if that was the last block of data */
547 if ((s
->trnmod
& SDHC_TRNS_MULTI
) == 0 ||
548 ((s
->trnmod
& SDHC_TRNS_MULTI
) &&
549 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) && (s
->blkcnt
== 0))) {
550 sdhci_end_transfer(s
);
551 } else if (s
->norintstsen
& SDHC_NISEN_WBUFRDY
) {
552 s
->norintsts
|= SDHC_NIS_WBUFRDY
;
555 /* Generate Block Gap Event if requested and if not the last block */
556 if (s
->stopped_state
== sdhc_gap_write
&& (s
->trnmod
& SDHC_TRNS_MULTI
) &&
558 s
->prnsts
&= ~SDHC_DOING_WRITE
;
559 if (s
->norintstsen
& SDHC_EISEN_BLKGAP
) {
560 s
->norintsts
|= SDHC_EIS_BLKGAP
;
562 sdhci_end_transfer(s
);
568 /* Write @size bytes of @value data to host controller @s Buffer Data Port
570 static void sdhci_write_dataport(SDHCIState
*s
, uint32_t value
, unsigned size
)
574 /* Check that there is free space left in a buffer */
575 if (!(s
->prnsts
& SDHC_SPACE_AVAILABLE
)) {
576 trace_sdhci_error("Can't write to data buffer: buffer full");
580 for (i
= 0; i
< size
; i
++) {
581 s
->fifo_buffer
[s
->data_count
] = value
& 0xFF;
584 if (s
->data_count
>= (s
->blksize
& BLOCK_SIZE_MASK
)) {
585 trace_sdhci_write_dataport(s
->data_count
);
587 s
->prnsts
&= ~SDHC_SPACE_AVAILABLE
;
588 if (s
->prnsts
& SDHC_DOING_WRITE
) {
589 sdhci_write_block_to_card(s
);
596 * Single DMA data transfer
599 /* Multi block SDMA transfer */
600 static void sdhci_sdma_transfer_multi_blocks(SDHCIState
*s
)
602 bool page_aligned
= false;
603 unsigned int n
, begin
;
604 const uint16_t block_size
= s
->blksize
& BLOCK_SIZE_MASK
;
605 uint32_t boundary_chk
= 1 << (((s
->blksize
& ~BLOCK_SIZE_MASK
) >> 12) + 12);
606 uint32_t boundary_count
= boundary_chk
- (s
->sdmasysad
% boundary_chk
);
608 if (!(s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) || !s
->blkcnt
) {
609 qemu_log_mask(LOG_UNIMP
, "infinite transfer is not supported\n");
613 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for
614 * possible stop at page boundary if initial address is not page aligned,
615 * allow them to work properly */
616 if ((s
->sdmasysad
% boundary_chk
) == 0) {
620 if (s
->trnmod
& SDHC_TRNS_READ
) {
621 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
622 SDHC_DAT_LINE_ACTIVE
;
624 if (s
->data_count
== 0) {
625 for (n
= 0; n
< block_size
; n
++) {
626 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
629 begin
= s
->data_count
;
630 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
631 s
->data_count
= boundary_count
+ begin
;
634 s
->data_count
= block_size
;
635 boundary_count
-= block_size
- begin
;
636 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
640 dma_memory_write(s
->dma_as
, s
->sdmasysad
,
641 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
642 s
->sdmasysad
+= s
->data_count
- begin
;
643 if (s
->data_count
== block_size
) {
646 if (page_aligned
&& boundary_count
== 0) {
651 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DATA_INHIBIT
|
652 SDHC_DAT_LINE_ACTIVE
;
654 begin
= s
->data_count
;
655 if (((boundary_count
+ begin
) < block_size
) && page_aligned
) {
656 s
->data_count
= boundary_count
+ begin
;
659 s
->data_count
= block_size
;
660 boundary_count
-= block_size
- begin
;
662 dma_memory_read(s
->dma_as
, s
->sdmasysad
,
663 &s
->fifo_buffer
[begin
], s
->data_count
- begin
);
664 s
->sdmasysad
+= s
->data_count
- begin
;
665 if (s
->data_count
== block_size
) {
666 for (n
= 0; n
< block_size
; n
++) {
667 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
670 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
674 if (page_aligned
&& boundary_count
== 0) {
680 if (s
->blkcnt
== 0) {
681 sdhci_end_transfer(s
);
683 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
684 s
->norintsts
|= SDHC_NIS_DMA
;
690 /* single block SDMA transfer */
691 static void sdhci_sdma_transfer_single_block(SDHCIState
*s
)
694 uint32_t datacnt
= s
->blksize
& BLOCK_SIZE_MASK
;
696 if (s
->trnmod
& SDHC_TRNS_READ
) {
697 for (n
= 0; n
< datacnt
; n
++) {
698 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
700 dma_memory_write(s
->dma_as
, s
->sdmasysad
, s
->fifo_buffer
, datacnt
);
702 dma_memory_read(s
->dma_as
, s
->sdmasysad
, s
->fifo_buffer
, datacnt
);
703 for (n
= 0; n
< datacnt
; n
++) {
704 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
709 sdhci_end_transfer(s
);
712 typedef struct ADMADescr
{
719 static void get_adma_description(SDHCIState
*s
, ADMADescr
*dscr
)
723 hwaddr entry_addr
= (hwaddr
)s
->admasysaddr
;
724 switch (SDHC_DMA_TYPE(s
->hostctl1
)) {
725 case SDHC_CTRL_ADMA2_32
:
726 dma_memory_read(s
->dma_as
, entry_addr
, (uint8_t *)&adma2
,
728 adma2
= le64_to_cpu(adma2
);
729 /* The spec does not specify endianness of descriptor table.
730 * We currently assume that it is LE.
732 dscr
->addr
= (hwaddr
)extract64(adma2
, 32, 32) & ~0x3ull
;
733 dscr
->length
= (uint16_t)extract64(adma2
, 16, 16);
734 dscr
->attr
= (uint8_t)extract64(adma2
, 0, 7);
737 case SDHC_CTRL_ADMA1_32
:
738 dma_memory_read(s
->dma_as
, entry_addr
, (uint8_t *)&adma1
,
740 adma1
= le32_to_cpu(adma1
);
741 dscr
->addr
= (hwaddr
)(adma1
& 0xFFFFF000);
742 dscr
->attr
= (uint8_t)extract32(adma1
, 0, 7);
744 if ((dscr
->attr
& SDHC_ADMA_ATTR_ACT_MASK
) == SDHC_ADMA_ATTR_SET_LEN
) {
745 dscr
->length
= (uint16_t)extract32(adma1
, 12, 16);
750 case SDHC_CTRL_ADMA2_64
:
751 dma_memory_read(s
->dma_as
, entry_addr
,
752 (uint8_t *)(&dscr
->attr
), 1);
753 dma_memory_read(s
->dma_as
, entry_addr
+ 2,
754 (uint8_t *)(&dscr
->length
), 2);
755 dscr
->length
= le16_to_cpu(dscr
->length
);
756 dma_memory_read(s
->dma_as
, entry_addr
+ 4,
757 (uint8_t *)(&dscr
->addr
), 8);
758 dscr
->addr
= le64_to_cpu(dscr
->addr
);
759 dscr
->attr
&= (uint8_t) ~0xC0;
765 /* Advanced DMA data transfer */
767 static void sdhci_do_adma(SDHCIState
*s
)
769 unsigned int n
, begin
, length
;
770 const uint16_t block_size
= s
->blksize
& BLOCK_SIZE_MASK
;
774 for (i
= 0; i
< SDHC_ADMA_DESCS_PER_DELAY
; ++i
) {
775 s
->admaerr
&= ~SDHC_ADMAERR_LENGTH_MISMATCH
;
777 get_adma_description(s
, &dscr
);
778 trace_sdhci_adma_loop(dscr
.addr
, dscr
.length
, dscr
.attr
);
780 if ((dscr
.attr
& SDHC_ADMA_ATTR_VALID
) == 0) {
781 /* Indicate that error occurred in ST_FDS state */
782 s
->admaerr
&= ~SDHC_ADMAERR_STATE_MASK
;
783 s
->admaerr
|= SDHC_ADMAERR_STATE_ST_FDS
;
785 /* Generate ADMA error interrupt */
786 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
787 s
->errintsts
|= SDHC_EIS_ADMAERR
;
788 s
->norintsts
|= SDHC_NIS_ERR
;
795 length
= dscr
.length
? dscr
.length
: 65536;
797 switch (dscr
.attr
& SDHC_ADMA_ATTR_ACT_MASK
) {
798 case SDHC_ADMA_ATTR_ACT_TRAN
: /* data transfer */
800 if (s
->trnmod
& SDHC_TRNS_READ
) {
802 if (s
->data_count
== 0) {
803 for (n
= 0; n
< block_size
; n
++) {
804 s
->fifo_buffer
[n
] = sdbus_read_data(&s
->sdbus
);
807 begin
= s
->data_count
;
808 if ((length
+ begin
) < block_size
) {
809 s
->data_count
= length
+ begin
;
812 s
->data_count
= block_size
;
813 length
-= block_size
- begin
;
815 dma_memory_write(s
->dma_as
, dscr
.addr
,
816 &s
->fifo_buffer
[begin
],
817 s
->data_count
- begin
);
818 dscr
.addr
+= s
->data_count
- begin
;
819 if (s
->data_count
== block_size
) {
821 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
823 if (s
->blkcnt
== 0) {
831 begin
= s
->data_count
;
832 if ((length
+ begin
) < block_size
) {
833 s
->data_count
= length
+ begin
;
836 s
->data_count
= block_size
;
837 length
-= block_size
- begin
;
839 dma_memory_read(s
->dma_as
, dscr
.addr
,
840 &s
->fifo_buffer
[begin
],
841 s
->data_count
- begin
);
842 dscr
.addr
+= s
->data_count
- begin
;
843 if (s
->data_count
== block_size
) {
844 for (n
= 0; n
< block_size
; n
++) {
845 sdbus_write_data(&s
->sdbus
, s
->fifo_buffer
[n
]);
848 if (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) {
850 if (s
->blkcnt
== 0) {
857 s
->admasysaddr
+= dscr
.incr
;
859 case SDHC_ADMA_ATTR_ACT_LINK
: /* link to next descriptor table */
860 s
->admasysaddr
= dscr
.addr
;
861 trace_sdhci_adma("link", s
->admasysaddr
);
864 s
->admasysaddr
+= dscr
.incr
;
868 if (dscr
.attr
& SDHC_ADMA_ATTR_INT
) {
869 trace_sdhci_adma("interrupt", s
->admasysaddr
);
870 if (s
->norintstsen
& SDHC_NISEN_DMA
) {
871 s
->norintsts
|= SDHC_NIS_DMA
;
877 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */
878 if (((s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
879 (s
->blkcnt
== 0)) || (dscr
.attr
& SDHC_ADMA_ATTR_END
)) {
880 trace_sdhci_adma_transfer_completed();
881 if (length
|| ((dscr
.attr
& SDHC_ADMA_ATTR_END
) &&
882 (s
->trnmod
& SDHC_TRNS_BLK_CNT_EN
) &&
884 trace_sdhci_error("SD/MMC host ADMA length mismatch");
885 s
->admaerr
|= SDHC_ADMAERR_LENGTH_MISMATCH
|
886 SDHC_ADMAERR_STATE_ST_TFR
;
887 if (s
->errintstsen
& SDHC_EISEN_ADMAERR
) {
888 trace_sdhci_error("Set ADMA error flag");
889 s
->errintsts
|= SDHC_EIS_ADMAERR
;
890 s
->norintsts
|= SDHC_NIS_ERR
;
895 sdhci_end_transfer(s
);
901 /* we have unfinished business - reschedule to continue ADMA */
902 timer_mod(s
->transfer_timer
,
903 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + SDHC_TRANSFER_DELAY
);
906 /* Perform data transfer according to controller configuration */
908 static void sdhci_data_transfer(void *opaque
)
910 SDHCIState
*s
= (SDHCIState
*)opaque
;
912 if (s
->trnmod
& SDHC_TRNS_DMA
) {
913 switch (SDHC_DMA_TYPE(s
->hostctl1
)) {
915 if ((s
->blkcnt
== 1) || !(s
->trnmod
& SDHC_TRNS_MULTI
)) {
916 sdhci_sdma_transfer_single_block(s
);
918 sdhci_sdma_transfer_multi_blocks(s
);
922 case SDHC_CTRL_ADMA1_32
:
923 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA1_MASK
)) {
924 trace_sdhci_error("ADMA1 not supported");
930 case SDHC_CTRL_ADMA2_32
:
931 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA2_MASK
)) {
932 trace_sdhci_error("ADMA2 not supported");
938 case SDHC_CTRL_ADMA2_64
:
939 if (!(s
->capareg
& R_SDHC_CAPAB_ADMA2_MASK
) ||
940 !(s
->capareg
& R_SDHC_CAPAB_BUS64BIT_MASK
)) {
941 trace_sdhci_error("64 bit ADMA not supported");
948 trace_sdhci_error("Unsupported DMA type");
952 if ((s
->trnmod
& SDHC_TRNS_READ
) && sdbus_data_ready(&s
->sdbus
)) {
953 s
->prnsts
|= SDHC_DOING_READ
| SDHC_DATA_INHIBIT
|
954 SDHC_DAT_LINE_ACTIVE
;
955 sdhci_read_block_from_card(s
);
957 s
->prnsts
|= SDHC_DOING_WRITE
| SDHC_DAT_LINE_ACTIVE
|
958 SDHC_SPACE_AVAILABLE
| SDHC_DATA_INHIBIT
;
959 sdhci_write_block_to_card(s
);
964 static bool sdhci_can_issue_command(SDHCIState
*s
)
966 if (!SDHC_CLOCK_IS_ON(s
->clkcon
) ||
967 (((s
->prnsts
& SDHC_DATA_INHIBIT
) || s
->stopped_state
) &&
968 ((s
->cmdreg
& SDHC_CMD_DATA_PRESENT
) ||
969 ((s
->cmdreg
& SDHC_CMD_RESPONSE
) == SDHC_CMD_RSP_WITH_BUSY
&&
970 !(SDHC_COMMAND_TYPE(s
->cmdreg
) == SDHC_CMD_ABORT
))))) {
977 /* The Buffer Data Port register must be accessed in sequential and
978 * continuous manner */
980 sdhci_buff_access_is_sequential(SDHCIState
*s
, unsigned byte_num
)
982 if ((s
->data_count
& 0x3) != byte_num
) {
983 trace_sdhci_error("Non-sequential access to Buffer Data Port register"
990 static uint64_t sdhci_read(void *opaque
, hwaddr offset
, unsigned size
)
992 SDHCIState
*s
= (SDHCIState
*)opaque
;
995 switch (offset
& ~0x3) {
1000 ret
= s
->blksize
| (s
->blkcnt
<< 16);
1006 ret
= s
->trnmod
| (s
->cmdreg
<< 16);
1008 case SDHC_RSPREG0
... SDHC_RSPREG3
:
1009 ret
= s
->rspreg
[((offset
& ~0x3) - SDHC_RSPREG0
) >> 2];
1012 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1013 ret
= sdhci_read_dataport(s
, size
);
1014 trace_sdhci_access("rd", size
<< 3, offset
, "->", ret
, ret
);
1020 ret
= FIELD_DP32(ret
, SDHC_PRNSTS
, DAT_LVL
,
1021 sdbus_get_dat_lines(&s
->sdbus
));
1022 ret
= FIELD_DP32(ret
, SDHC_PRNSTS
, CMD_LVL
,
1023 sdbus_get_cmd_line(&s
->sdbus
));
1026 ret
= s
->hostctl1
| (s
->pwrcon
<< 8) | (s
->blkgap
<< 16) |
1030 ret
= s
->clkcon
| (s
->timeoutcon
<< 16);
1032 case SDHC_NORINTSTS
:
1033 ret
= s
->norintsts
| (s
->errintsts
<< 16);
1035 case SDHC_NORINTSTSEN
:
1036 ret
= s
->norintstsen
| (s
->errintstsen
<< 16);
1038 case SDHC_NORINTSIGEN
:
1039 ret
= s
->norintsigen
| (s
->errintsigen
<< 16);
1041 case SDHC_ACMD12ERRSTS
:
1042 ret
= s
->acmd12errsts
| (s
->hostctl2
<< 16);
1045 ret
= (uint32_t)s
->capareg
;
1047 case SDHC_CAPAB
+ 4:
1048 ret
= (uint32_t)(s
->capareg
>> 32);
1051 ret
= (uint32_t)s
->maxcurr
;
1053 case SDHC_MAXCURR
+ 4:
1054 ret
= (uint32_t)(s
->maxcurr
>> 32);
1059 case SDHC_ADMASYSADDR
:
1060 ret
= (uint32_t)s
->admasysaddr
;
1062 case SDHC_ADMASYSADDR
+ 4:
1063 ret
= (uint32_t)(s
->admasysaddr
>> 32);
1065 case SDHC_SLOT_INT_STATUS
:
1066 ret
= (s
->version
<< 16) | sdhci_slotint(s
);
1069 qemu_log_mask(LOG_UNIMP
, "SDHC rd_%ub @0x%02" HWADDR_PRIx
" "
1070 "not implemented\n", size
, offset
);
1074 ret
>>= (offset
& 0x3) * 8;
1075 ret
&= (1ULL << (size
* 8)) - 1;
1076 trace_sdhci_access("rd", size
<< 3, offset
, "->", ret
, ret
);
1080 static inline void sdhci_blkgap_write(SDHCIState
*s
, uint8_t value
)
1082 if ((value
& SDHC_STOP_AT_GAP_REQ
) && (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
)) {
1085 s
->blkgap
= value
& SDHC_STOP_AT_GAP_REQ
;
1087 if ((value
& SDHC_CONTINUE_REQ
) && s
->stopped_state
&&
1088 (s
->blkgap
& SDHC_STOP_AT_GAP_REQ
) == 0) {
1089 if (s
->stopped_state
== sdhc_gap_read
) {
1090 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_READ
;
1091 sdhci_read_block_from_card(s
);
1093 s
->prnsts
|= SDHC_DAT_LINE_ACTIVE
| SDHC_DOING_WRITE
;
1094 sdhci_write_block_to_card(s
);
1096 s
->stopped_state
= sdhc_not_stopped
;
1097 } else if (!s
->stopped_state
&& (value
& SDHC_STOP_AT_GAP_REQ
)) {
1098 if (s
->prnsts
& SDHC_DOING_READ
) {
1099 s
->stopped_state
= sdhc_gap_read
;
1100 } else if (s
->prnsts
& SDHC_DOING_WRITE
) {
1101 s
->stopped_state
= sdhc_gap_write
;
1106 static inline void sdhci_reset_write(SDHCIState
*s
, uint8_t value
)
1109 case SDHC_RESET_ALL
:
1112 case SDHC_RESET_CMD
:
1113 s
->prnsts
&= ~SDHC_CMD_INHIBIT
;
1114 s
->norintsts
&= ~SDHC_NIS_CMDCMP
;
1116 case SDHC_RESET_DATA
:
1118 s
->prnsts
&= ~(SDHC_SPACE_AVAILABLE
| SDHC_DATA_AVAILABLE
|
1119 SDHC_DOING_READ
| SDHC_DOING_WRITE
|
1120 SDHC_DATA_INHIBIT
| SDHC_DAT_LINE_ACTIVE
);
1121 s
->blkgap
&= ~(SDHC_STOP_AT_GAP_REQ
| SDHC_CONTINUE_REQ
);
1122 s
->stopped_state
= sdhc_not_stopped
;
1123 s
->norintsts
&= ~(SDHC_NIS_WBUFRDY
| SDHC_NIS_RBUFRDY
|
1124 SDHC_NIS_DMA
| SDHC_NIS_TRSCMP
| SDHC_NIS_BLKGAP
);
1130 sdhci_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1132 SDHCIState
*s
= (SDHCIState
*)opaque
;
1133 unsigned shift
= 8 * (offset
& 0x3);
1134 uint32_t mask
= ~(((1ULL << (size
* 8)) - 1) << shift
);
1135 uint32_t value
= val
;
1138 switch (offset
& ~0x3) {
1140 s
->sdmasysad
= (s
->sdmasysad
& mask
) | value
;
1141 MASKED_WRITE(s
->sdmasysad
, mask
, value
);
1142 /* Writing to last byte of sdmasysad might trigger transfer */
1143 if (!(mask
& 0xFF000000) && TRANSFERRING_DATA(s
->prnsts
) && s
->blkcnt
&&
1144 s
->blksize
&& SDHC_DMA_TYPE(s
->hostctl1
) == SDHC_CTRL_SDMA
) {
1145 if (s
->trnmod
& SDHC_TRNS_MULTI
) {
1146 sdhci_sdma_transfer_multi_blocks(s
);
1148 sdhci_sdma_transfer_single_block(s
);
1153 if (!TRANSFERRING_DATA(s
->prnsts
)) {
1154 MASKED_WRITE(s
->blksize
, mask
, value
);
1155 MASKED_WRITE(s
->blkcnt
, mask
>> 16, value
>> 16);
1158 /* Limit block size to the maximum buffer size */
1159 if (extract32(s
->blksize
, 0, 12) > s
->buf_maxsz
) {
1160 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Size 0x%x is larger than " \
1161 "the maximum buffer 0x%x", __func__
, s
->blksize
,
1164 s
->blksize
= deposit32(s
->blksize
, 0, 12, s
->buf_maxsz
);
1169 MASKED_WRITE(s
->argument
, mask
, value
);
1172 /* DMA can be enabled only if it is supported as indicated by
1173 * capabilities register */
1174 if (!(s
->capareg
& R_SDHC_CAPAB_SDMA_MASK
)) {
1175 value
&= ~SDHC_TRNS_DMA
;
1177 MASKED_WRITE(s
->trnmod
, mask
, value
& SDHC_TRNMOD_MASK
);
1178 MASKED_WRITE(s
->cmdreg
, mask
>> 16, value
>> 16);
1180 /* Writing to the upper byte of CMDREG triggers SD command generation */
1181 if ((mask
& 0xFF000000) || !sdhci_can_issue_command(s
)) {
1185 sdhci_send_command(s
);
1188 if (sdhci_buff_access_is_sequential(s
, offset
- SDHC_BDATA
)) {
1189 sdhci_write_dataport(s
, value
>> shift
, size
);
1193 if (!(mask
& 0xFF0000)) {
1194 sdhci_blkgap_write(s
, value
>> 16);
1196 MASKED_WRITE(s
->hostctl1
, mask
, value
);
1197 MASKED_WRITE(s
->pwrcon
, mask
>> 8, value
>> 8);
1198 MASKED_WRITE(s
->wakcon
, mask
>> 24, value
>> 24);
1199 if (!(s
->prnsts
& SDHC_CARD_PRESENT
) || ((s
->pwrcon
>> 1) & 0x7) < 5 ||
1200 !(s
->capareg
& (1 << (31 - ((s
->pwrcon
>> 1) & 0x7))))) {
1201 s
->pwrcon
&= ~SDHC_POWER_ON
;
1205 if (!(mask
& 0xFF000000)) {
1206 sdhci_reset_write(s
, value
>> 24);
1208 MASKED_WRITE(s
->clkcon
, mask
, value
);
1209 MASKED_WRITE(s
->timeoutcon
, mask
>> 16, value
>> 16);
1210 if (s
->clkcon
& SDHC_CLOCK_INT_EN
) {
1211 s
->clkcon
|= SDHC_CLOCK_INT_STABLE
;
1213 s
->clkcon
&= ~SDHC_CLOCK_INT_STABLE
;
1216 case SDHC_NORINTSTS
:
1217 if (s
->norintstsen
& SDHC_NISEN_CARDINT
) {
1218 value
&= ~SDHC_NIS_CARDINT
;
1220 s
->norintsts
&= mask
| ~value
;
1221 s
->errintsts
&= (mask
>> 16) | ~(value
>> 16);
1223 s
->norintsts
|= SDHC_NIS_ERR
;
1225 s
->norintsts
&= ~SDHC_NIS_ERR
;
1227 sdhci_update_irq(s
);
1229 case SDHC_NORINTSTSEN
:
1230 MASKED_WRITE(s
->norintstsen
, mask
, value
);
1231 MASKED_WRITE(s
->errintstsen
, mask
>> 16, value
>> 16);
1232 s
->norintsts
&= s
->norintstsen
;
1233 s
->errintsts
&= s
->errintstsen
;
1235 s
->norintsts
|= SDHC_NIS_ERR
;
1237 s
->norintsts
&= ~SDHC_NIS_ERR
;
1239 /* Quirk for Raspberry Pi: pending card insert interrupt
1240 * appears when first enabled after power on */
1241 if ((s
->norintstsen
& SDHC_NISEN_INSERT
) && s
->pending_insert_state
) {
1242 assert(s
->pending_insert_quirk
);
1243 s
->norintsts
|= SDHC_NIS_INSERT
;
1244 s
->pending_insert_state
= false;
1246 sdhci_update_irq(s
);
1248 case SDHC_NORINTSIGEN
:
1249 MASKED_WRITE(s
->norintsigen
, mask
, value
);
1250 MASKED_WRITE(s
->errintsigen
, mask
>> 16, value
>> 16);
1251 sdhci_update_irq(s
);
1254 MASKED_WRITE(s
->admaerr
, mask
, value
);
1256 case SDHC_ADMASYSADDR
:
1257 s
->admasysaddr
= (s
->admasysaddr
& (0xFFFFFFFF00000000ULL
|
1258 (uint64_t)mask
)) | (uint64_t)value
;
1260 case SDHC_ADMASYSADDR
+ 4:
1261 s
->admasysaddr
= (s
->admasysaddr
& (0x00000000FFFFFFFFULL
|
1262 ((uint64_t)mask
<< 32))) | ((uint64_t)value
<< 32);
1265 s
->acmd12errsts
|= value
;
1266 s
->errintsts
|= (value
>> 16) & s
->errintstsen
;
1267 if (s
->acmd12errsts
) {
1268 s
->errintsts
|= SDHC_EIS_CMD12ERR
;
1271 s
->norintsts
|= SDHC_NIS_ERR
;
1273 sdhci_update_irq(s
);
1275 case SDHC_ACMD12ERRSTS
:
1276 MASKED_WRITE(s
->acmd12errsts
, mask
, value
& UINT16_MAX
);
1277 if (s
->uhs_mode
>= UHS_I
) {
1278 MASKED_WRITE(s
->hostctl2
, mask
>> 16, value
>> 16);
1280 if (FIELD_EX32(s
->hostctl2
, SDHC_HOSTCTL2
, V18_ENA
)) {
1281 sdbus_set_voltage(&s
->sdbus
, SD_VOLTAGE_1_8V
);
1283 sdbus_set_voltage(&s
->sdbus
, SD_VOLTAGE_3_3V
);
1289 case SDHC_CAPAB
+ 4:
1291 case SDHC_MAXCURR
+ 4:
1292 qemu_log_mask(LOG_GUEST_ERROR
, "SDHC wr_%ub @0x%02" HWADDR_PRIx
1293 " <- 0x%08x read-only\n", size
, offset
, value
>> shift
);
1297 qemu_log_mask(LOG_UNIMP
, "SDHC wr_%ub @0x%02" HWADDR_PRIx
" <- 0x%08x "
1298 "not implemented\n", size
, offset
, value
>> shift
);
1301 trace_sdhci_access("wr", size
<< 3, offset
, "<-",
1302 value
>> shift
, value
>> shift
);
1305 static const MemoryRegionOps sdhci_mmio_ops
= {
1307 .write
= sdhci_write
,
1309 .min_access_size
= 1,
1310 .max_access_size
= 4,
1313 .endianness
= DEVICE_LITTLE_ENDIAN
,
1316 static void sdhci_init_readonly_registers(SDHCIState
*s
, Error
**errp
)
1318 Error
*local_err
= NULL
;
1320 switch (s
->sd_spec_version
) {
1324 error_setg(errp
, "Only Spec v2/v3 are supported");
1327 s
->version
= (SDHC_HCVER_VENDOR
<< 8) | (s
->sd_spec_version
- 1);
1329 sdhci_check_capareg(s
, &local_err
);
1331 error_propagate(errp
, local_err
);
1336 /* --- qdev common --- */
1338 #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
1339 DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
1340 DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
1342 /* Capabilities registers provide information on supported
1343 * features of this specific host controller implementation */ \
1344 DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
1345 DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
1347 static void sdhci_initfn(SDHCIState
*s
)
1349 qbus_create_inplace(&s
->sdbus
, sizeof(s
->sdbus
),
1350 TYPE_SDHCI_BUS
, DEVICE(s
), "sd-bus");
1352 s
->insert_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_raise_insertion_irq
, s
);
1353 s
->transfer_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, sdhci_data_transfer
, s
);
1355 s
->io_ops
= &sdhci_mmio_ops
;
1358 static void sdhci_uninitfn(SDHCIState
*s
)
1360 timer_del(s
->insert_timer
);
1361 timer_free(s
->insert_timer
);
1362 timer_del(s
->transfer_timer
);
1363 timer_free(s
->transfer_timer
);
1365 g_free(s
->fifo_buffer
);
1366 s
->fifo_buffer
= NULL
;
1369 static void sdhci_common_realize(SDHCIState
*s
, Error
**errp
)
1371 Error
*local_err
= NULL
;
1373 sdhci_init_readonly_registers(s
, &local_err
);
1375 error_propagate(errp
, local_err
);
1378 s
->buf_maxsz
= sdhci_get_fifolen(s
);
1379 s
->fifo_buffer
= g_malloc0(s
->buf_maxsz
);
1381 memory_region_init_io(&s
->iomem
, OBJECT(s
), &sdhci_mmio_ops
, s
, "sdhci",
1382 SDHC_REGISTERS_MAP_SIZE
);
1385 static void sdhci_common_unrealize(SDHCIState
*s
, Error
**errp
)
1387 /* This function is expected to be called only once for each class:
1388 * - SysBus: via DeviceClass->unrealize(),
1389 * - PCI: via PCIDeviceClass->exit().
1390 * However to avoid double-free and/or use-after-free we still nullify
1391 * this variable (better safe than sorry!). */
1392 g_free(s
->fifo_buffer
);
1393 s
->fifo_buffer
= NULL
;
1396 static bool sdhci_pending_insert_vmstate_needed(void *opaque
)
1398 SDHCIState
*s
= opaque
;
1400 return s
->pending_insert_state
;
1403 static const VMStateDescription sdhci_pending_insert_vmstate
= {
1404 .name
= "sdhci/pending-insert",
1406 .minimum_version_id
= 1,
1407 .needed
= sdhci_pending_insert_vmstate_needed
,
1408 .fields
= (VMStateField
[]) {
1409 VMSTATE_BOOL(pending_insert_state
, SDHCIState
),
1410 VMSTATE_END_OF_LIST()
1414 const VMStateDescription sdhci_vmstate
= {
1417 .minimum_version_id
= 1,
1418 .fields
= (VMStateField
[]) {
1419 VMSTATE_UINT32(sdmasysad
, SDHCIState
),
1420 VMSTATE_UINT16(blksize
, SDHCIState
),
1421 VMSTATE_UINT16(blkcnt
, SDHCIState
),
1422 VMSTATE_UINT32(argument
, SDHCIState
),
1423 VMSTATE_UINT16(trnmod
, SDHCIState
),
1424 VMSTATE_UINT16(cmdreg
, SDHCIState
),
1425 VMSTATE_UINT32_ARRAY(rspreg
, SDHCIState
, 4),
1426 VMSTATE_UINT32(prnsts
, SDHCIState
),
1427 VMSTATE_UINT8(hostctl1
, SDHCIState
),
1428 VMSTATE_UINT8(pwrcon
, SDHCIState
),
1429 VMSTATE_UINT8(blkgap
, SDHCIState
),
1430 VMSTATE_UINT8(wakcon
, SDHCIState
),
1431 VMSTATE_UINT16(clkcon
, SDHCIState
),
1432 VMSTATE_UINT8(timeoutcon
, SDHCIState
),
1433 VMSTATE_UINT8(admaerr
, SDHCIState
),
1434 VMSTATE_UINT16(norintsts
, SDHCIState
),
1435 VMSTATE_UINT16(errintsts
, SDHCIState
),
1436 VMSTATE_UINT16(norintstsen
, SDHCIState
),
1437 VMSTATE_UINT16(errintstsen
, SDHCIState
),
1438 VMSTATE_UINT16(norintsigen
, SDHCIState
),
1439 VMSTATE_UINT16(errintsigen
, SDHCIState
),
1440 VMSTATE_UINT16(acmd12errsts
, SDHCIState
),
1441 VMSTATE_UINT16(data_count
, SDHCIState
),
1442 VMSTATE_UINT64(admasysaddr
, SDHCIState
),
1443 VMSTATE_UINT8(stopped_state
, SDHCIState
),
1444 VMSTATE_VBUFFER_UINT32(fifo_buffer
, SDHCIState
, 1, NULL
, buf_maxsz
),
1445 VMSTATE_TIMER_PTR(insert_timer
, SDHCIState
),
1446 VMSTATE_TIMER_PTR(transfer_timer
, SDHCIState
),
1447 VMSTATE_END_OF_LIST()
1449 .subsections
= (const VMStateDescription
*[]) {
1450 &sdhci_pending_insert_vmstate
,
1455 static void sdhci_common_class_init(ObjectClass
*klass
, void *data
)
1457 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1459 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
1460 dc
->vmsd
= &sdhci_vmstate
;
1461 dc
->reset
= sdhci_poweron_reset
;
1464 /* --- qdev PCI --- */
1466 static Property sdhci_pci_properties
[] = {
1467 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState
),
1468 DEFINE_PROP_END_OF_LIST(),
1471 static void sdhci_pci_realize(PCIDevice
*dev
, Error
**errp
)
1473 SDHCIState
*s
= PCI_SDHCI(dev
);
1474 Error
*local_err
= NULL
;
1477 sdhci_common_realize(s
, errp
);
1479 error_propagate(errp
, local_err
);
1483 dev
->config
[PCI_CLASS_PROG
] = 0x01; /* Standard Host supported DMA */
1484 dev
->config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin A */
1485 s
->irq
= pci_allocate_irq(dev
);
1486 s
->dma_as
= pci_get_address_space(dev
);
1487 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->iomem
);
1490 static void sdhci_pci_exit(PCIDevice
*dev
)
1492 SDHCIState
*s
= PCI_SDHCI(dev
);
1494 sdhci_common_unrealize(s
, &error_abort
);
1498 static void sdhci_pci_class_init(ObjectClass
*klass
, void *data
)
1500 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1501 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1503 k
->realize
= sdhci_pci_realize
;
1504 k
->exit
= sdhci_pci_exit
;
1505 k
->vendor_id
= PCI_VENDOR_ID_REDHAT
;
1506 k
->device_id
= PCI_DEVICE_ID_REDHAT_SDHCI
;
1507 k
->class_id
= PCI_CLASS_SYSTEM_SDHCI
;
1508 dc
->props
= sdhci_pci_properties
;
1510 sdhci_common_class_init(klass
, data
);
1513 static const TypeInfo sdhci_pci_info
= {
1514 .name
= TYPE_PCI_SDHCI
,
1515 .parent
= TYPE_PCI_DEVICE
,
1516 .instance_size
= sizeof(SDHCIState
),
1517 .class_init
= sdhci_pci_class_init
,
1518 .interfaces
= (InterfaceInfo
[]) {
1519 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
1524 /* --- qdev SysBus --- */
1526 static Property sdhci_sysbus_properties
[] = {
1527 DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState
),
1528 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState
, pending_insert_quirk
,
1530 DEFINE_PROP_LINK("dma", SDHCIState
,
1531 dma_mr
, TYPE_MEMORY_REGION
, MemoryRegion
*),
1532 DEFINE_PROP_END_OF_LIST(),
1535 static void sdhci_sysbus_init(Object
*obj
)
1537 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1542 static void sdhci_sysbus_finalize(Object
*obj
)
1544 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1547 object_unparent(OBJECT(s
->dma_mr
));
1553 static void sdhci_sysbus_realize(DeviceState
*dev
, Error
** errp
)
1555 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1556 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1557 Error
*local_err
= NULL
;
1559 sdhci_common_realize(s
, errp
);
1561 error_propagate(errp
, local_err
);
1566 s
->dma_as
= &s
->sysbus_dma_as
;
1567 address_space_init(s
->dma_as
, s
->dma_mr
, "sdhci-dma");
1569 /* use system_memory() if property "dma" not set */
1570 s
->dma_as
= &address_space_memory
;
1573 sysbus_init_irq(sbd
, &s
->irq
);
1575 memory_region_init_io(&s
->iomem
, OBJECT(s
), s
->io_ops
, s
, "sdhci",
1576 SDHC_REGISTERS_MAP_SIZE
);
1578 sysbus_init_mmio(sbd
, &s
->iomem
);
1581 static void sdhci_sysbus_unrealize(DeviceState
*dev
, Error
**errp
)
1583 SDHCIState
*s
= SYSBUS_SDHCI(dev
);
1585 sdhci_common_unrealize(s
, &error_abort
);
1588 address_space_destroy(s
->dma_as
);
1592 static void sdhci_sysbus_class_init(ObjectClass
*klass
, void *data
)
1594 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1596 dc
->props
= sdhci_sysbus_properties
;
1597 dc
->realize
= sdhci_sysbus_realize
;
1598 dc
->unrealize
= sdhci_sysbus_unrealize
;
1600 sdhci_common_class_init(klass
, data
);
1603 static const TypeInfo sdhci_sysbus_info
= {
1604 .name
= TYPE_SYSBUS_SDHCI
,
1605 .parent
= TYPE_SYS_BUS_DEVICE
,
1606 .instance_size
= sizeof(SDHCIState
),
1607 .instance_init
= sdhci_sysbus_init
,
1608 .instance_finalize
= sdhci_sysbus_finalize
,
1609 .class_init
= sdhci_sysbus_class_init
,
1612 /* --- qdev bus master --- */
1614 static void sdhci_bus_class_init(ObjectClass
*klass
, void *data
)
1616 SDBusClass
*sbc
= SD_BUS_CLASS(klass
);
1618 sbc
->set_inserted
= sdhci_set_inserted
;
1619 sbc
->set_readonly
= sdhci_set_readonly
;
1622 static const TypeInfo sdhci_bus_info
= {
1623 .name
= TYPE_SDHCI_BUS
,
1624 .parent
= TYPE_SD_BUS
,
1625 .instance_size
= sizeof(SDBus
),
1626 .class_init
= sdhci_bus_class_init
,
1629 static uint64_t usdhc_read(void *opaque
, hwaddr offset
, unsigned size
)
1631 SDHCIState
*s
= SYSBUS_SDHCI(opaque
);
1637 return sdhci_read(opaque
, offset
, size
);
1641 * For a detailed explanation on the following bit
1642 * manipulation code see comments in a similar part of
1645 hostctl1
= SDHC_DMA_TYPE(s
->hostctl1
) << (8 - 3);
1647 if (s
->hostctl1
& SDHC_CTRL_8BITBUS
) {
1648 hostctl1
|= ESDHC_CTRL_8BITBUS
;
1651 if (s
->hostctl1
& SDHC_CTRL_4BITBUS
) {
1652 hostctl1
|= ESDHC_CTRL_4BITBUS
;
1656 ret
|= (uint32_t)s
->blkgap
<< 16;
1657 ret
|= (uint32_t)s
->wakcon
<< 24;
1661 case ESDHC_DLL_CTRL
:
1662 case ESDHC_TUNE_CTRL_STATUS
:
1663 case ESDHC_UNDOCUMENTED_REG27
:
1664 case ESDHC_TUNING_CTRL
:
1665 case ESDHC_VENDOR_SPEC
:
1666 case ESDHC_MIX_CTRL
:
1667 case ESDHC_WTMK_LVL
:
1676 usdhc_write(void *opaque
, hwaddr offset
, uint64_t val
, unsigned size
)
1678 SDHCIState
*s
= SYSBUS_SDHCI(opaque
);
1680 uint32_t value
= (uint32_t)val
;
1683 case ESDHC_DLL_CTRL
:
1684 case ESDHC_TUNE_CTRL_STATUS
:
1685 case ESDHC_UNDOCUMENTED_REG27
:
1686 case ESDHC_TUNING_CTRL
:
1687 case ESDHC_WTMK_LVL
:
1688 case ESDHC_VENDOR_SPEC
:
1693 * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL)
1696 * |-----------+--------+--------+-----------+----------+---------|
1697 * | Card | Card | Endian | DATA3 | Data | Led |
1698 * | Detect | Detect | Mode | as Card | Transfer | Control |
1699 * | Signal | Test | | Detection | Width | |
1700 * | Selection | Level | | Pin | | |
1701 * |-----------+--------+--------+-----------+----------+---------|
1706 * |----------+------|
1707 * | Reserved | DMA |
1710 * |----------+------|
1712 * and here's what SDCHI spec expects those offsets to be:
1714 * 0x28 (Host Control Register)
1717 * |--------+--------+----------+------+--------+----------+---------|
1718 * | Card | Card | Extended | DMA | High | Data | LED |
1719 * | Detect | Detect | Data | Sel. | Speed | Transfer | Control |
1720 * | Signal | Test | Transfer | | Enable | Width | |
1721 * | Sel. | Level | Width | | | | |
1722 * |--------+--------+----------+------+--------+----------+---------|
1724 * and 0x29 (Power Control Register)
1726 * |----------------------------------|
1727 * | Power Control Register |
1729 * | Description omitted, |
1730 * | since it has no analog in ESDHCI |
1732 * |----------------------------------|
1734 * Since offsets 0x2A and 0x2B should be compatible between
1735 * both IP specs we only need to reconcile least 16-bit of the
1736 * word we've been given.
1740 * First, save bits 7 6 and 0 since they are identical
1742 hostctl1
= value
& (SDHC_CTRL_LED
|
1743 SDHC_CTRL_CDTEST_INS
|
1744 SDHC_CTRL_CDTEST_EN
);
1746 * Second, split "Data Transfer Width" from bits 2 and 1 in to
1749 if (value
& ESDHC_CTRL_8BITBUS
) {
1750 hostctl1
|= SDHC_CTRL_8BITBUS
;
1753 if (value
& ESDHC_CTRL_4BITBUS
) {
1754 hostctl1
|= ESDHC_CTRL_4BITBUS
;
1758 * Third, move DMA select from bits 9 and 8 to bits 4 and 3
1760 hostctl1
|= SDHC_DMA_TYPE(value
>> (8 - 3));
1763 * Now place the corrected value into low 16-bit of the value
1764 * we are going to give standard SDHCI write function
1766 * NOTE: This transformation should be the inverse of what can
1767 * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux
1770 value
&= ~UINT16_MAX
;
1772 value
|= (uint16_t)s
->pwrcon
<< 8;
1774 sdhci_write(opaque
, offset
, value
, size
);
1777 case ESDHC_MIX_CTRL
:
1779 * So, when SD/MMC stack in Linux tries to write to "Transfer
1780 * Mode Register", ESDHC i.MX quirk code will translate it
1781 * into a write to ESDHC_MIX_CTRL, so we do the opposite in
1782 * order to get where we started
1784 * Note that Auto CMD23 Enable bit is located in a wrong place
1785 * on i.MX, but since it is not used by QEMU we do not care.
1787 * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...)
1788 * here becuase it will result in a call to
1789 * sdhci_send_command(s) which we don't want.
1792 s
->trnmod
= value
& UINT16_MAX
;
1796 * Similar to above, but this time a write to "Command
1797 * Register" will be translated into a 4-byte write to
1798 * "Transfer Mode register" where lower 16-bit of value would
1799 * be set to zero. So what we do is fill those bits with
1800 * cached value from s->trnmod and let the SDHCI
1801 * infrastructure handle the rest
1803 sdhci_write(opaque
, offset
, val
| s
->trnmod
, size
);
1807 * ESDHCI does not implement "Host SDMA Buffer Boundary", and
1808 * Linux driver will try to zero this field out which will
1809 * break the rest of SDHCI emulation.
1811 * Linux defaults to maximum possible setting (512K boundary)
1812 * and it seems to be the only option that i.MX IP implements,
1813 * so we artificially set it to that value.
1818 sdhci_write(opaque
, offset
, val
, size
);
1824 static const MemoryRegionOps usdhc_mmio_ops
= {
1826 .write
= usdhc_write
,
1828 .min_access_size
= 1,
1829 .max_access_size
= 4,
1832 .endianness
= DEVICE_LITTLE_ENDIAN
,
1835 static void imx_usdhc_init(Object
*obj
)
1837 SDHCIState
*s
= SYSBUS_SDHCI(obj
);
1839 s
->io_ops
= &usdhc_mmio_ops
;
1840 s
->quirks
= SDHCI_QUIRK_NO_BUSY_IRQ
;
1843 static const TypeInfo imx_usdhc_info
= {
1844 .name
= TYPE_IMX_USDHC
,
1845 .parent
= TYPE_SYSBUS_SDHCI
,
1846 .instance_init
= imx_usdhc_init
,
1849 static void sdhci_register_types(void)
1851 type_register_static(&sdhci_pci_info
);
1852 type_register_static(&sdhci_sysbus_info
);
1853 type_register_static(&sdhci_bus_info
);
1854 type_register_static(&imx_usdhc_info
);
1857 type_init(sdhci_register_types
)