hw/pci-bridge/xio3130_upstream.c

   1 /*
   2  * xio3130_upstream.c
   3  * TI X3130 pci express upstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/pci/pci_ids.h"
  24 #include "hw/pci/msi.h"
  25 #include "hw/pci/pcie.h"
  26 #include "xio3130_upstream.h"
  27 #include "qapi/error.h"
  28
  29 #define PCI_DEVICE_ID_TI_XIO3130U       0x8232  /* upstream port */
  30 #define XIO3130_REVISION                0x2
  31 #define XIO3130_MSI_OFFSET              0x70
  32 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  33 #define XIO3130_MSI_NR_VECTOR           1
  34 #define XIO3130_SSVID_OFFSET            0x80
  35 #define XIO3130_SSVID_SVID              0
  36 #define XIO3130_SSVID_SSID              0
  37 #define XIO3130_EXP_OFFSET              0x90
  38 #define XIO3130_AER_OFFSET              0x100
  39
  40 static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
  41                                           uint32_t val, int len)
  42 {
  43     pci_bridge_write_config(d, address, val, len);
  44     pcie_cap_flr_write_config(d, address, val, len);
  45     pcie_aer_write_config(d, address, val, len);
  46 }
  47
  48 static void xio3130_upstream_reset(DeviceState *qdev)
  49 {
  50     PCIDevice *d = PCI_DEVICE(qdev);
  51
  52     pci_bridge_reset(qdev);
  53     pcie_cap_deverr_reset(d);
  54 }
  55
  56 static int xio3130_upstream_initfn(PCIDevice *d)
  57 {
  58     PCIEPort *p = PCIE_PORT(d);
  59     int rc;
  60     Error *err = NULL;
  61
  62     pci_bridge_initfn(d, TYPE_PCIE_BUS);
  63     pcie_port_init_reg(d);
  64
  65     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  66                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  67                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, &err);
  68     if (rc < 0) {
  69         assert(rc == -ENOTSUP);
  70         error_report_err(err);
  71         goto err_bridge;
  72     }
  73
  74     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  75                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  76     if (rc < 0) {
  77         goto err_bridge;
  78     }
  79
  80     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
  81                        p->port);
  82     if (rc < 0) {
  83         goto err_msi;
  84     }
  85     pcie_cap_flr_init(d);
  86     pcie_cap_deverr_init(d);
  87
  88     rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
  89     if (rc < 0) {
  90         error_report_err(err);
  91         goto err;
  92     }
  93
  94     return 0;
  95
  96 err:
  97     pcie_cap_exit(d);
  98 err_msi:
  99     msi_uninit(d);
 100 err_bridge:
 101     pci_bridge_exitfn(d);
 102     return rc;
 103 }
 104
 105 static void xio3130_upstream_exitfn(PCIDevice *d)
 106 {
 107     pcie_aer_exit(d);
 108     pcie_cap_exit(d);
 109     msi_uninit(d);
 110     pci_bridge_exitfn(d);
 111 }
 112
 113 PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
 114                              const char *bus_name, pci_map_irq_fn map_irq,
 115                              uint8_t port)
 116 {
 117     PCIDevice *d;
 118     PCIBridge *br;
 119     DeviceState *qdev;
 120
 121     d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
 122     if (!d) {
 123         return NULL;
 124     }
 125     br = PCI_BRIDGE(d);
 126
 127     qdev = DEVICE(d);
 128     pci_bridge_map_irq(br, bus_name, map_irq);
 129     qdev_prop_set_uint8(qdev, "port", port);
 130     qdev_init_nofail(qdev);
 131
 132     return PCIE_PORT(d);
 133 }
 134
 135 static const VMStateDescription vmstate_xio3130_upstream = {
 136     .name = "xio3130-express-upstream-port",
 137     .version_id = 1,
 138     .minimum_version_id = 1,
 139     .fields = (VMStateField[]) {
 140         VMSTATE_PCIE_DEVICE(parent_obj.parent_obj, PCIEPort),
 141         VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0,
 142                        vmstate_pcie_aer_log, PCIEAERLog),
 143         VMSTATE_END_OF_LIST()
 144     }
 145 };
 146
 147 static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
 148 {
 149     DeviceClass *dc = DEVICE_CLASS(klass);
 150     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 151
 152     k->is_express = 1;
 153     k->is_bridge = 1;
 154     k->config_write = xio3130_upstream_write_config;
 155     k->init = xio3130_upstream_initfn;
 156     k->exit = xio3130_upstream_exitfn;
 157     k->vendor_id = PCI_VENDOR_ID_TI;
 158     k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
 159     k->revision = XIO3130_REVISION;
 160     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 161     dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
 162     dc->reset = xio3130_upstream_reset;
 163     dc->vmsd = &vmstate_xio3130_upstream;
 164 }
 165
 166 static const TypeInfo xio3130_upstream_info = {
 167     .name          = "x3130-upstream",
 168     .parent        = TYPE_PCIE_PORT,
 169     .class_init    = xio3130_upstream_class_init,
 170 };
 171
 172 static void xio3130_upstream_register_types(void)
 173 {
 174     type_register_static(&xio3130_upstream_info);
 175 }
 176
 177 type_init(xio3130_upstream_register_types)