target-ppc/cpu.h

   1 /*
   2  *  PowerPC emulation cpu definitions for qemu.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #if !defined (__CPU_PPC_H__)
  20 #define __CPU_PPC_H__
  21
  22 #include "qemu-common.h"
  23
  24 //#define PPC_EMULATE_32BITS_HYPV
  25
  26 #if defined (TARGET_PPC64)
  27 /* PowerPC 64 definitions */
  28 #define TARGET_LONG_BITS 64
  29 #define TARGET_PAGE_BITS 12
  30
  31 /* Note that the official physical address space bits is 62-M where M
  32    is implementation dependent.  I've not looked up M for the set of
  33    cpus we emulate at the system level.  */
  34 #define TARGET_PHYS_ADDR_SPACE_BITS 62
  35
  36 /* Note that the PPC environment architecture talks about 80 bit virtual
  37    addresses, with segmentation.  Obviously that's not all visible to a
  38    single process, which is all we're concerned with here.  */
  39 #ifdef TARGET_ABI32
  40 # define TARGET_VIRT_ADDR_SPACE_BITS 32
  41 #else
  42 # define TARGET_VIRT_ADDR_SPACE_BITS 64
  43 #endif
  44
  45 #define TARGET_PAGE_BITS_64K 16
  46 #define TARGET_PAGE_BITS_16M 24
  47
  48 #else /* defined (TARGET_PPC64) */
  49 /* PowerPC 32 definitions */
  50 #define TARGET_LONG_BITS 32
  51
  52 #if defined(TARGET_PPCEMB)
  53 /* Specific definitions for PowerPC embedded */
  54 /* BookE have 36 bits physical address space */
  55 #if defined(CONFIG_USER_ONLY)
  56 /* It looks like a lot of Linux programs assume page size
  57  * is 4kB long. This is evil, but we have to deal with it...
  58  */
  59 #define TARGET_PAGE_BITS 12
  60 #else /* defined(CONFIG_USER_ONLY) */
  61 /* Pages can be 1 kB small */
  62 #define TARGET_PAGE_BITS 10
  63 #endif /* defined(CONFIG_USER_ONLY) */
  64 #else /* defined(TARGET_PPCEMB) */
  65 /* "standard" PowerPC 32 definitions */
  66 #define TARGET_PAGE_BITS 12
  67 #endif /* defined(TARGET_PPCEMB) */
  68
  69 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  70 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  71
  72 #endif /* defined (TARGET_PPC64) */
  73
  74 #define CPUArchState struct CPUPPCState
  75
  76 #include "exec/cpu-defs.h"
  77 #include "cpu-qom.h"
  78 #include "fpu/softfloat.h"
  79
  80 #if defined (TARGET_PPC64)
  81 #define PPC_ELF_MACHINE     EM_PPC64
  82 #else
  83 #define PPC_ELF_MACHINE     EM_PPC
  84 #endif
  85
  86 /*****************************************************************************/
  87 /* Exception vectors definitions                                             */
  88 enum {
  89     POWERPC_EXCP_NONE    = -1,
  90     /* The 64 first entries are used by the PowerPC embedded specification   */
  91     POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */
  92     POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */
  93     POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */
  94     POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */
  95     POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */
  96     POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */
  97     POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */
  98     POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */
  99     POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */
 100     POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */
 101     POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */
 102     POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */
 103     POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */
 104     POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */
 105     POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */
 106     POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */
 107     /* Vectors 16 to 31 are reserved                                         */
 108     POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */
 109     POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */
 110     POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */
 111     POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */
 112     POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */
 113     POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */
 114     POWERPC_EXCP_GDOORI   = 38, /* Embedded guest doorbell interrupt         */
 115     POWERPC_EXCP_GDOORCI  = 39, /* Embedded guest doorbell critical interrupt*/
 116     POWERPC_EXCP_HYPPRIV  = 41, /* Embedded hypervisor priv instruction      */
 117     /* Vectors 42 to 63 are reserved                                         */
 118     /* Exceptions defined in the PowerPC server specification                */
 119     /* Server doorbell variants */
 120 #define POWERPC_EXCP_SDOOR      POWERPC_EXCP_GDOORI
 121 #define POWERPC_EXCP_SDOOR_HV   POWERPC_EXCP_DOORI
 122     POWERPC_EXCP_RESET    = 64, /* System reset exception                    */
 123     POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */
 124     POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */
 125     POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */
 126     POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */
 127     POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */
 128     POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */
 129     POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */
 130     POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */
 131     POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */
 132     /* 40x specific exceptions                                               */
 133     POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */
 134     /* 601 specific exceptions                                               */
 135     POWERPC_EXCP_IO       = 75, /* IO error exception                        */
 136     POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */
 137     /* 602 specific exceptions                                               */
 138     POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */
 139     /* 602/603 specific exceptions                                           */
 140     POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */
 141     POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */
 142     POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */
 143     /* Exceptions available on most PowerPC                                  */
 144     POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */
 145     POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */
 146     POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */
 147     POWERPC_EXCP_SMI      = 84, /* System management interrupt               */
 148     POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */
 149     /* 7xx/74xx specific exceptions                                          */
 150     POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */
 151     /* 74xx specific exceptions                                              */
 152     POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */
 153     /* 970FX specific exceptions                                             */
 154     POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */
 155     POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */
 156     /* Freescale embedded cores specific exceptions                          */
 157     POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */
 158     POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */
 159     POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */
 160     POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */
 161     /* VSX Unavailable (Power ISA 2.06 and later)                            */
 162     POWERPC_EXCP_VSXU     = 94, /* VSX Unavailable                           */
 163     POWERPC_EXCP_FU       = 95, /* Facility Unavailable                      */
 164     /* Additional ISA 2.06 and later server exceptions                       */
 165     POWERPC_EXCP_HV_EMU   = 96, /* HV emulation assistance                   */
 166     POWERPC_EXCP_HV_MAINT = 97, /* HMI                                       */
 167     POWERPC_EXCP_HV_FU    = 98, /* Hypervisor Facility unavailable           */
 168     /* EOL                                                                   */
 169     POWERPC_EXCP_NB       = 99,
 170     /* QEMU exceptions: used internally during code translation              */
 171     POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */
 172     POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */
 173     /* QEMU exceptions: special cases we want to stop translation            */
 174     POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */
 175     POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */
 176     POWERPC_EXCP_STCX         = 0x204 /* Conditional stores in user mode     */
 177 };
 178
 179 /* Exceptions error codes                                                    */
 180 enum {
 181     /* Exception subtypes for POWERPC_EXCP_ALIGN                             */
 182     POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */
 183     POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */
 184     POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */
 185     POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */
 186     POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */
 187     POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */
 188     /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */
 189     /* FP exceptions                                                         */
 190     POWERPC_EXCP_FP            = 0x10,
 191     POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */
 192     POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */
 193     POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */
 194     POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */
 195     POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */
 196     POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */
 197     POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */
 198     POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */
 199     POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */
 200     POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */
 201     POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */
 202     POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */
 203     POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */
 204     /* Invalid instruction                                                   */
 205     POWERPC_EXCP_INVAL         = 0x20,
 206     POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */
 207     POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */
 208     POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */
 209     POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */
 210     /* Privileged instruction                                                */
 211     POWERPC_EXCP_PRIV          = 0x30,
 212     POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */
 213     POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */
 214     /* Trap                                                                  */
 215     POWERPC_EXCP_TRAP          = 0x40,
 216 };
 217
 218 #define PPC_INPUT(env) (env->bus_model)
 219
 220 /*****************************************************************************/
 221 typedef struct opc_handler_t opc_handler_t;
 222
 223 /*****************************************************************************/
 224 /* Types used to describe some PowerPC registers */
 225 typedef struct DisasContext DisasContext;
 226 typedef struct ppc_spr_t ppc_spr_t;
 227 typedef union ppc_avr_t ppc_avr_t;
 228 typedef union ppc_tlb_t ppc_tlb_t;
 229
 230 /* SPR access micro-ops generations callbacks */
 231 struct ppc_spr_t {
 232     void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 233     void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 234 #if !defined(CONFIG_USER_ONLY)
 235     void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 236     void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 237     void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
 238     void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
 239 #endif
 240     const char *name;
 241     target_ulong default_value;
 242 #ifdef CONFIG_KVM
 243     /* We (ab)use the fact that all the SPRs will have ids for the
 244      * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
 245      * don't sync this */
 246     uint64_t one_reg_id;
 247 #endif
 248 };
 249
 250 /* Altivec registers (128 bits) */
 251 union ppc_avr_t {
 252     float32 f[4];
 253     uint8_t u8[16];
 254     uint16_t u16[8];
 255     uint32_t u32[4];
 256     int8_t s8[16];
 257     int16_t s16[8];
 258     int32_t s32[4];
 259     uint64_t u64[2];
 260     int64_t s64[2];
 261 #ifdef CONFIG_INT128
 262     __uint128_t u128;
 263 #endif
 264 };
 265
 266 #if !defined(CONFIG_USER_ONLY)
 267 /* Software TLB cache */
 268 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 269 struct ppc6xx_tlb_t {
 270     target_ulong pte0;
 271     target_ulong pte1;
 272     target_ulong EPN;
 273 };
 274
 275 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
 276 struct ppcemb_tlb_t {
 277     uint64_t RPN;
 278     target_ulong EPN;
 279     target_ulong PID;
 280     target_ulong size;
 281     uint32_t prot;
 282     uint32_t attr; /* Storage attributes */
 283 };
 284
 285 typedef struct ppcmas_tlb_t {
 286      uint32_t mas8;
 287      uint32_t mas1;
 288      uint64_t mas2;
 289      uint64_t mas7_3;
 290 } ppcmas_tlb_t;
 291
 292 union ppc_tlb_t {
 293     ppc6xx_tlb_t *tlb6;
 294     ppcemb_tlb_t *tlbe;
 295     ppcmas_tlb_t *tlbm;
 296 };
 297
 298 /* possible TLB variants */
 299 #define TLB_NONE               0
 300 #define TLB_6XX                1
 301 #define TLB_EMB                2
 302 #define TLB_MAS                3
 303 #endif
 304
 305 #define SDR_32_HTABORG         0xFFFF0000UL
 306 #define SDR_32_HTABMASK        0x000001FFUL
 307
 308 #if defined(TARGET_PPC64)
 309 #define SDR_64_HTABORG         0xFFFFFFFFFFFC0000ULL
 310 #define SDR_64_HTABSIZE        0x000000000000001FULL
 311 #endif /* defined(TARGET_PPC64 */
 312
 313 typedef struct ppc_slb_t ppc_slb_t;
 314 struct ppc_slb_t {
 315     uint64_t esid;
 316     uint64_t vsid;
 317     const struct ppc_one_seg_page_size *sps;
 318 };
 319
 320 #define MAX_SLB_ENTRIES         64
 321 #define SEGMENT_SHIFT_256M      28
 322 #define SEGMENT_MASK_256M       (~((1ULL << SEGMENT_SHIFT_256M) - 1))
 323
 324 #define SEGMENT_SHIFT_1T        40
 325 #define SEGMENT_MASK_1T         (~((1ULL << SEGMENT_SHIFT_1T) - 1))
 326
 327
 328 /*****************************************************************************/
 329 /* Machine state register bits definition                                    */
 330 #define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
 331 #define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */
 332 #define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
 333 #define MSR_SHV  60 /* hypervisor state                               hflags */
 334 #define MSR_TS0  34 /* Transactional state, 2 bits (Book3s)                  */
 335 #define MSR_TS1  33
 336 #define MSR_TM   32 /* Transactional Memory Available (Book3s)               */
 337 #define MSR_CM   31 /* Computation mode for BookE                     hflags */
 338 #define MSR_ICM  30 /* Interrupt computation mode for BookE                  */
 339 #define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */
 340 #define MSR_GS   28 /* guest state for BookE                                 */
 341 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */
 342 #define MSR_VR   25 /* altivec available                            x hflags */
 343 #define MSR_SPE  25 /* SPE enable for BookE                         x hflags */
 344 #define MSR_AP   23 /* Access privilege state on 602                  hflags */
 345 #define MSR_VSX  23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
 346 #define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
 347 #define MSR_KEY  19 /* key bit on 603e                                       */
 348 #define MSR_POW  18 /* Power management                                      */
 349 #define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */
 350 #define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */
 351 #define MSR_ILE  16 /* Interrupt little-endian mode                          */
 352 #define MSR_EE   15 /* External interrupt enable                             */
 353 #define MSR_PR   14 /* Problem state                                  hflags */
 354 #define MSR_FP   13 /* Floating point available                       hflags */
 355 #define MSR_ME   12 /* Machine check interrupt enable                        */
 356 #define MSR_FE0  11 /* Floating point exception mode 0                hflags */
 357 #define MSR_SE   10 /* Single-step trace enable                     x hflags */
 358 #define MSR_DWE  10 /* Debug wait enable on 405                     x        */
 359 #define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */
 360 #define MSR_BE   9  /* Branch trace enable                          x hflags */
 361 #define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */
 362 #define MSR_FE1  8  /* Floating point exception mode 1                hflags */
 363 #define MSR_AL   7  /* AL bit on POWER                                       */
 364 #define MSR_EP   6  /* Exception prefix on 601                               */
 365 #define MSR_IR   5  /* Instruction relocate                                  */
 366 #define MSR_DR   4  /* Data relocate                                         */
 367 #define MSR_IS   5  /* Instruction address space (BookE)                     */
 368 #define MSR_DS   4  /* Data address space (BookE)                            */
 369 #define MSR_PE   3  /* Protection enable on 403                              */
 370 #define MSR_PX   2  /* Protection exclusive on 403                  x        */
 371 #define MSR_PMM  2  /* Performance monitor mark on POWER            x        */
 372 #define MSR_RI   1  /* Recoverable interrupt                        1        */
 373 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 374
 375 /* LPCR bits */
 376 #define LPCR_VPM0         (1ull << (63 - 0))
 377 #define LPCR_VPM1         (1ull << (63 - 1))
 378 #define LPCR_ISL          (1ull << (63 - 2))
 379 #define LPCR_KBV          (1ull << (63 - 3))
 380 #define LPCR_DPFD_SHIFT   (63 - 11)
 381 #define LPCR_DPFD         (0x3ull << LPCR_DPFD_SHIFT)
 382 #define LPCR_VRMASD_SHIFT (63 - 16)
 383 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 384 #define LPCR_RMLS_SHIFT   (63 - 37)
 385 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 386 #define LPCR_ILE          (1ull << (63 - 38))
 387 #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
 388 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
 389 #define LPCR_ONL          (1ull << (63 - 45))
 390 #define LPCR_P7_PECE0     (1ull << (63 - 49))
 391 #define LPCR_P7_PECE1     (1ull << (63 - 50))
 392 #define LPCR_P7_PECE2     (1ull << (63 - 51))
 393 #define LPCR_P8_PECE0     (1ull << (63 - 47))
 394 #define LPCR_P8_PECE1     (1ull << (63 - 48))
 395 #define LPCR_P8_PECE2     (1ull << (63 - 49))
 396 #define LPCR_P8_PECE3     (1ull << (63 - 50))
 397 #define LPCR_P8_PECE4     (1ull << (63 - 51))
 398 #define LPCR_MER          (1ull << (63 - 52))
 399 #define LPCR_TC           (1ull << (63 - 54))
 400 #define LPCR_LPES0        (1ull << (63 - 60))
 401 #define LPCR_LPES1        (1ull << (63 - 61))
 402 #define LPCR_RMI          (1ull << (63 - 62))
 403 #define LPCR_HDICE        (1ull << (63 - 63))
 404
 405 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 406 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
 407 #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
 408 #define msr_cm   ((env->msr >> MSR_CM)   & 1)
 409 #define msr_icm  ((env->msr >> MSR_ICM)  & 1)
 410 #define msr_thv  ((env->msr >> MSR_THV)  & 1)
 411 #define msr_gs   ((env->msr >> MSR_GS)   & 1)
 412 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
 413 #define msr_vr   ((env->msr >> MSR_VR)   & 1)
 414 #define msr_spe  ((env->msr >> MSR_SPE)  & 1)
 415 #define msr_ap   ((env->msr >> MSR_AP)   & 1)
 416 #define msr_vsx  ((env->msr >> MSR_VSX)  & 1)
 417 #define msr_sa   ((env->msr >> MSR_SA)   & 1)
 418 #define msr_key  ((env->msr >> MSR_KEY)  & 1)
 419 #define msr_pow  ((env->msr >> MSR_POW)  & 1)
 420 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
 421 #define msr_ce   ((env->msr >> MSR_CE)   & 1)
 422 #define msr_ile  ((env->msr >> MSR_ILE)  & 1)
 423 #define msr_ee   ((env->msr >> MSR_EE)   & 1)
 424 #define msr_pr   ((env->msr >> MSR_PR)   & 1)
 425 #define msr_fp   ((env->msr >> MSR_FP)   & 1)
 426 #define msr_me   ((env->msr >> MSR_ME)   & 1)
 427 #define msr_fe0  ((env->msr >> MSR_FE0)  & 1)
 428 #define msr_se   ((env->msr >> MSR_SE)   & 1)
 429 #define msr_dwe  ((env->msr >> MSR_DWE)  & 1)
 430 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
 431 #define msr_be   ((env->msr >> MSR_BE)   & 1)
 432 #define msr_de   ((env->msr >> MSR_DE)   & 1)
 433 #define msr_fe1  ((env->msr >> MSR_FE1)  & 1)
 434 #define msr_al   ((env->msr >> MSR_AL)   & 1)
 435 #define msr_ep   ((env->msr >> MSR_EP)   & 1)
 436 #define msr_ir   ((env->msr >> MSR_IR)   & 1)
 437 #define msr_dr   ((env->msr >> MSR_DR)   & 1)
 438 #define msr_is   ((env->msr >> MSR_IS)   & 1)
 439 #define msr_ds   ((env->msr >> MSR_DS)   & 1)
 440 #define msr_pe   ((env->msr >> MSR_PE)   & 1)
 441 #define msr_px   ((env->msr >> MSR_PX)   & 1)
 442 #define msr_pmm  ((env->msr >> MSR_PMM)  & 1)
 443 #define msr_ri   ((env->msr >> MSR_RI)   & 1)
 444 #define msr_le   ((env->msr >> MSR_LE)   & 1)
 445 #define msr_ts   ((env->msr >> MSR_TS1)  & 3)
 446 #define msr_tm   ((env->msr >> MSR_TM)   & 1)
 447
 448 /* Hypervisor bit is more specific */
 449 #if defined(TARGET_PPC64)
 450 #define MSR_HVB (1ULL << MSR_SHV)
 451 #define msr_hv  msr_shv
 452 #else
 453 #if defined(PPC_EMULATE_32BITS_HYPV)
 454 #define MSR_HVB (1ULL << MSR_THV)
 455 #define msr_hv  msr_thv
 456 #else
 457 #define MSR_HVB (0ULL)
 458 #define msr_hv  (0)
 459 #endif
 460 #endif
 461
 462 /* Facility Status and Control (FSCR) bits */
 463 #define FSCR_EBB        (63 - 56) /* Event-Based Branch Facility */
 464 #define FSCR_TAR        (63 - 55) /* Target Address Register */
 465 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
 466 #define FSCR_IC_MASK    (0xFFULL)
 467 #define FSCR_IC_POS     (63 - 7)
 468 #define FSCR_IC_DSCR_SPR3   2
 469 #define FSCR_IC_PMU         3
 470 #define FSCR_IC_BHRB        4
 471 #define FSCR_IC_TM          5
 472 #define FSCR_IC_EBB         7
 473 #define FSCR_IC_TAR         8
 474
 475 /* Exception state register bits definition                                  */
 476 #define ESR_PIL   (1 << (63 - 36)) /* Illegal Instruction                    */
 477 #define ESR_PPR   (1 << (63 - 37)) /* Privileged Instruction                 */
 478 #define ESR_PTR   (1 << (63 - 38)) /* Trap                                   */
 479 #define ESR_FP    (1 << (63 - 39)) /* Floating-Point Operation               */
 480 #define ESR_ST    (1 << (63 - 40)) /* Store Operation                        */
 481 #define ESR_AP    (1 << (63 - 44)) /* Auxiliary Processor Operation          */
 482 #define ESR_PUO   (1 << (63 - 45)) /* Unimplemented Operation                */
 483 #define ESR_BO    (1 << (63 - 46)) /* Byte Ordering                          */
 484 #define ESR_PIE   (1 << (63 - 47)) /* Imprecise exception                    */
 485 #define ESR_DATA  (1 << (63 - 53)) /* Data Access (Embedded page table)      */
 486 #define ESR_TLBI  (1 << (63 - 54)) /* TLB Ineligible (Embedded page table)   */
 487 #define ESR_PT    (1 << (63 - 55)) /* Page Table (Embedded page table)       */
 488 #define ESR_SPV   (1 << (63 - 56)) /* SPE/VMX operation                      */
 489 #define ESR_EPID  (1 << (63 - 57)) /* External Process ID operation          */
 490 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation                          */
 491 #define ESR_MIF   (1 << (63 - 62)) /* Misaligned instruction (VLE)           */
 492
 493 /* Transaction EXception And Summary Register bits                           */
 494 #define TEXASR_FAILURE_PERSISTENT                (63 - 7)
 495 #define TEXASR_DISALLOWED                        (63 - 8)
 496 #define TEXASR_NESTING_OVERFLOW                  (63 - 9)
 497 #define TEXASR_FOOTPRINT_OVERFLOW                (63 - 10)
 498 #define TEXASR_SELF_INDUCED_CONFLICT             (63 - 11)
 499 #define TEXASR_NON_TRANSACTIONAL_CONFLICT        (63 - 12)
 500 #define TEXASR_TRANSACTION_CONFLICT              (63 - 13)
 501 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
 502 #define TEXASR_IMPLEMENTATION_SPECIFIC           (63 - 15)
 503 #define TEXASR_INSTRUCTION_FETCH_CONFLICT        (63 - 16)
 504 #define TEXASR_ABORT                             (63 - 31)
 505 #define TEXASR_SUSPENDED                         (63 - 32)
 506 #define TEXASR_PRIVILEGE_HV                      (63 - 34)
 507 #define TEXASR_PRIVILEGE_PR                      (63 - 35)
 508 #define TEXASR_FAILURE_SUMMARY                   (63 - 36)
 509 #define TEXASR_TFIAR_EXACT                       (63 - 37)
 510 #define TEXASR_ROT                               (63 - 38)
 511 #define TEXASR_TRANSACTION_LEVEL                 (63 - 52) /* 12 bits */
 512
 513 enum {
 514     POWERPC_FLAG_NONE     = 0x00000000,
 515     /* Flag for MSR bit 25 signification (VRE/SPE)                           */
 516     POWERPC_FLAG_SPE      = 0x00000001,
 517     POWERPC_FLAG_VRE      = 0x00000002,
 518     /* Flag for MSR bit 17 signification (TGPR/CE)                           */
 519     POWERPC_FLAG_TGPR     = 0x00000004,
 520     POWERPC_FLAG_CE       = 0x00000008,
 521     /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */
 522     POWERPC_FLAG_SE       = 0x00000010,
 523     POWERPC_FLAG_DWE      = 0x00000020,
 524     POWERPC_FLAG_UBLE     = 0x00000040,
 525     /* Flag for MSR bit 9 signification (BE/DE)                              */
 526     POWERPC_FLAG_BE       = 0x00000080,
 527     POWERPC_FLAG_DE       = 0x00000100,
 528     /* Flag for MSR bit 2 signification (PX/PMM)                             */
 529     POWERPC_FLAG_PX       = 0x00000200,
 530     POWERPC_FLAG_PMM      = 0x00000400,
 531     /* Flag for special features                                             */
 532     /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */
 533     POWERPC_FLAG_RTC_CLK  = 0x00010000,
 534     POWERPC_FLAG_BUS_CLK  = 0x00020000,
 535     /* Has CFAR                                                              */
 536     POWERPC_FLAG_CFAR     = 0x00040000,
 537     /* Has VSX                                                               */
 538     POWERPC_FLAG_VSX      = 0x00080000,
 539     /* Has Transaction Memory (ISA 2.07)                                     */
 540     POWERPC_FLAG_TM       = 0x00100000,
 541 };
 542
 543 /*****************************************************************************/
 544 /* Floating point status and control register                                */
 545 #define FPSCR_FX     31 /* Floating-point exception summary                  */
 546 #define FPSCR_FEX    30 /* Floating-point enabled exception summary          */
 547 #define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */
 548 #define FPSCR_OX     28 /* Floating-point overflow exception                 */
 549 #define FPSCR_UX     27 /* Floating-point underflow exception                */
 550 #define FPSCR_ZX     26 /* Floating-point zero divide exception              */
 551 #define FPSCR_XX     25 /* Floating-point inexact exception                  */
 552 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
 553 #define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */
 554 #define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */
 555 #define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */
 556 #define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */
 557 #define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */
 558 #define FPSCR_FR     18 /* Floating-point fraction rounded                   */
 559 #define FPSCR_FI     17 /* Floating-point fraction inexact                   */
 560 #define FPSCR_C      16 /* Floating-point result class descriptor            */
 561 #define FPSCR_FL     15 /* Floating-point less than or negative              */
 562 #define FPSCR_FG     14 /* Floating-point greater than or negative           */
 563 #define FPSCR_FE     13 /* Floating-point equal or zero                      */
 564 #define FPSCR_FU     12 /* Floating-point unordered or NaN                   */
 565 #define FPSCR_FPCC   12 /* Floating-point condition code                     */
 566 #define FPSCR_FPRF   12 /* Floating-point result flags                       */
 567 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
 568 #define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */
 569 #define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */
 570 #define FPSCR_VE     7  /* Floating-point invalid operation exception enable */
 571 #define FPSCR_OE     6  /* Floating-point overflow exception enable          */
 572 #define FPSCR_UE     5  /* Floating-point undeflow exception enable          */
 573 #define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */
 574 #define FPSCR_XE     3  /* Floating-point inexact exception enable           */
 575 #define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */
 576 #define FPSCR_RN1    1
 577 #define FPSCR_RN     0  /* Floating-point rounding control                   */
 578 #define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)
 579 #define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)
 580 #define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)
 581 #define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)
 582 #define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)
 583 #define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)
 584 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
 585 #define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)
 586 #define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)
 587 #define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)
 588 #define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)
 589 #define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)
 590 #define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)
 591 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
 592 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
 593 #define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)
 594 #define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)
 595 #define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)
 596 #define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)
 597 #define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)
 598 #define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)
 599 #define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)
 600 #define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)
 601 /* Invalid operation exception summary */
 602 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \
 603                                   (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \
 604                                   (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \
 605                                   (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
 606                                   (1 << FPSCR_VXCVI)))
 607 /* exception summary */
 608 #define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)
 609 /* enabled exception summary */
 610 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \
 611                    0x1F)
 612
 613 #define FP_FX           (1ull << FPSCR_FX)
 614 #define FP_FEX          (1ull << FPSCR_FEX)
 615 #define FP_VX           (1ull << FPSCR_VX)
 616 #define FP_OX           (1ull << FPSCR_OX)
 617 #define FP_UX           (1ull << FPSCR_UX)
 618 #define FP_ZX           (1ull << FPSCR_ZX)
 619 #define FP_XX           (1ull << FPSCR_XX)
 620 #define FP_VXSNAN       (1ull << FPSCR_VXSNAN)
 621 #define FP_VXISI        (1ull << FPSCR_VXISI)
 622 #define FP_VXIDI        (1ull << FPSCR_VXIDI)
 623 #define FP_VXZDZ        (1ull << FPSCR_VXZDZ)
 624 #define FP_VXIMZ        (1ull << FPSCR_VXIMZ)
 625 #define FP_VXVC         (1ull << FPSCR_VXVC)
 626 #define FP_FR           (1ull << FSPCR_FR)
 627 #define FP_FI           (1ull << FPSCR_FI)
 628 #define FP_C            (1ull << FPSCR_C)
 629 #define FP_FL           (1ull << FPSCR_FL)
 630 #define FP_FG           (1ull << FPSCR_FG)
 631 #define FP_FE           (1ull << FPSCR_FE)
 632 #define FP_FU           (1ull << FPSCR_FU)
 633 #define FP_FPCC         (FP_FL | FP_FG | FP_FE | FP_FU)
 634 #define FP_FPRF         (FP_C  | FP_FL | FP_FG | FP_FE | FP_FU)
 635 #define FP_VXSOFT       (1ull << FPSCR_VXSOFT)
 636 #define FP_VXSQRT       (1ull << FPSCR_VXSQRT)
 637 #define FP_VXCVI        (1ull << FPSCR_VXCVI)
 638 #define FP_VE           (1ull << FPSCR_VE)
 639 #define FP_OE           (1ull << FPSCR_OE)
 640 #define FP_UE           (1ull << FPSCR_UE)
 641 #define FP_ZE           (1ull << FPSCR_ZE)
 642 #define FP_XE           (1ull << FPSCR_XE)
 643 #define FP_NI           (1ull << FPSCR_NI)
 644 #define FP_RN1          (1ull << FPSCR_RN1)
 645 #define FP_RN           (1ull << FPSCR_RN)
 646
 647 /* the exception bits which can be cleared by mcrfs - includes FX */
 648 #define FP_EX_CLEAR_BITS (FP_FX     | FP_OX     | FP_UX     | FP_ZX     | \
 649                           FP_XX     | FP_VXSNAN | FP_VXISI  | FP_VXIDI  | \
 650                           FP_VXZDZ  | FP_VXIMZ  | FP_VXVC   | FP_VXSOFT | \
 651                           FP_VXSQRT | FP_VXCVI)
 652
 653 /*****************************************************************************/
 654 /* Vector status and control register */
 655 #define VSCR_NJ         16 /* Vector non-java */
 656 #define VSCR_SAT        0 /* Vector saturation */
 657 #define vscr_nj         (((env->vscr) >> VSCR_NJ)       & 0x1)
 658 #define vscr_sat        (((env->vscr) >> VSCR_SAT)      & 0x1)
 659
 660 /*****************************************************************************/
 661 /* BookE e500 MMU registers */
 662
 663 #define MAS0_NV_SHIFT      0
 664 #define MAS0_NV_MASK       (0xfff << MAS0_NV_SHIFT)
 665
 666 #define MAS0_WQ_SHIFT      12
 667 #define MAS0_WQ_MASK       (3 << MAS0_WQ_SHIFT)
 668 /* Write TLB entry regardless of reservation */
 669 #define MAS0_WQ_ALWAYS     (0 << MAS0_WQ_SHIFT)
 670 /* Write TLB entry only already in use */
 671 #define MAS0_WQ_COND       (1 << MAS0_WQ_SHIFT)
 672 /* Clear TLB entry */
 673 #define MAS0_WQ_CLR_RSRV   (2 << MAS0_WQ_SHIFT)
 674
 675 #define MAS0_HES_SHIFT     14
 676 #define MAS0_HES           (1 << MAS0_HES_SHIFT)
 677
 678 #define MAS0_ESEL_SHIFT    16
 679 #define MAS0_ESEL_MASK     (0xfff << MAS0_ESEL_SHIFT)
 680
 681 #define MAS0_TLBSEL_SHIFT  28
 682 #define MAS0_TLBSEL_MASK   (3 << MAS0_TLBSEL_SHIFT)
 683 #define MAS0_TLBSEL_TLB0   (0 << MAS0_TLBSEL_SHIFT)
 684 #define MAS0_TLBSEL_TLB1   (1 << MAS0_TLBSEL_SHIFT)
 685 #define MAS0_TLBSEL_TLB2   (2 << MAS0_TLBSEL_SHIFT)
 686 #define MAS0_TLBSEL_TLB3   (3 << MAS0_TLBSEL_SHIFT)
 687
 688 #define MAS0_ATSEL_SHIFT   31
 689 #define MAS0_ATSEL         (1 << MAS0_ATSEL_SHIFT)
 690 #define MAS0_ATSEL_TLB     0
 691 #define MAS0_ATSEL_LRAT    MAS0_ATSEL
 692
 693 #define MAS1_TSIZE_SHIFT   7
 694 #define MAS1_TSIZE_MASK    (0x1f << MAS1_TSIZE_SHIFT)
 695
 696 #define MAS1_TS_SHIFT      12
 697 #define MAS1_TS            (1 << MAS1_TS_SHIFT)
 698
 699 #define MAS1_IND_SHIFT     13
 700 #define MAS1_IND           (1 << MAS1_IND_SHIFT)
 701
 702 #define MAS1_TID_SHIFT     16
 703 #define MAS1_TID_MASK      (0x3fff << MAS1_TID_SHIFT)
 704
 705 #define MAS1_IPROT_SHIFT   30
 706 #define MAS1_IPROT         (1 << MAS1_IPROT_SHIFT)
 707
 708 #define MAS1_VALID_SHIFT   31
 709 #define MAS1_VALID         0x80000000
 710
 711 #define MAS2_EPN_SHIFT     12
 712 #define MAS2_EPN_MASK      (~0ULL << MAS2_EPN_SHIFT)
 713
 714 #define MAS2_ACM_SHIFT     6
 715 #define MAS2_ACM           (1 << MAS2_ACM_SHIFT)
 716
 717 #define MAS2_VLE_SHIFT     5
 718 #define MAS2_VLE           (1 << MAS2_VLE_SHIFT)
 719
 720 #define MAS2_W_SHIFT       4
 721 #define MAS2_W             (1 << MAS2_W_SHIFT)
 722
 723 #define MAS2_I_SHIFT       3
 724 #define MAS2_I             (1 << MAS2_I_SHIFT)
 725
 726 #define MAS2_M_SHIFT       2
 727 #define MAS2_M             (1 << MAS2_M_SHIFT)
 728
 729 #define MAS2_G_SHIFT       1
 730 #define MAS2_G             (1 << MAS2_G_SHIFT)
 731
 732 #define MAS2_E_SHIFT       0
 733 #define MAS2_E             (1 << MAS2_E_SHIFT)
 734
 735 #define MAS3_RPN_SHIFT     12
 736 #define MAS3_RPN_MASK      (0xfffff << MAS3_RPN_SHIFT)
 737
 738 #define MAS3_U0                 0x00000200
 739 #define MAS3_U1                 0x00000100
 740 #define MAS3_U2                 0x00000080
 741 #define MAS3_U3                 0x00000040
 742 #define MAS3_UX                 0x00000020
 743 #define MAS3_SX                 0x00000010
 744 #define MAS3_UW                 0x00000008
 745 #define MAS3_SW                 0x00000004
 746 #define MAS3_UR                 0x00000002
 747 #define MAS3_SR                 0x00000001
 748 #define MAS3_SPSIZE_SHIFT       1
 749 #define MAS3_SPSIZE_MASK        (0x3e << MAS3_SPSIZE_SHIFT)
 750
 751 #define MAS4_TLBSELD_SHIFT      MAS0_TLBSEL_SHIFT
 752 #define MAS4_TLBSELD_MASK       MAS0_TLBSEL_MASK
 753 #define MAS4_TIDSELD_MASK       0x00030000
 754 #define MAS4_TIDSELD_PID0       0x00000000
 755 #define MAS4_TIDSELD_PID1       0x00010000
 756 #define MAS4_TIDSELD_PID2       0x00020000
 757 #define MAS4_TIDSELD_PIDZ       0x00030000
 758 #define MAS4_INDD               0x00008000      /* Default IND */
 759 #define MAS4_TSIZED_SHIFT       MAS1_TSIZE_SHIFT
 760 #define MAS4_TSIZED_MASK        MAS1_TSIZE_MASK
 761 #define MAS4_ACMD               0x00000040
 762 #define MAS4_VLED               0x00000020
 763 #define MAS4_WD                 0x00000010
 764 #define MAS4_ID                 0x00000008
 765 #define MAS4_MD                 0x00000004
 766 #define MAS4_GD                 0x00000002
 767 #define MAS4_ED                 0x00000001
 768 #define MAS4_WIMGED_MASK        0x0000001f      /* Default WIMGE */
 769 #define MAS4_WIMGED_SHIFT       0
 770
 771 #define MAS5_SGS                0x80000000
 772 #define MAS5_SLPID_MASK         0x00000fff
 773
 774 #define MAS6_SPID0              0x3fff0000
 775 #define MAS6_SPID1              0x00007ffe
 776 #define MAS6_ISIZE(x)           MAS1_TSIZE(x)
 777 #define MAS6_SAS                0x00000001
 778 #define MAS6_SPID               MAS6_SPID0
 779 #define MAS6_SIND               0x00000002      /* Indirect page */
 780 #define MAS6_SIND_SHIFT         1
 781 #define MAS6_SPID_MASK          0x3fff0000
 782 #define MAS6_SPID_SHIFT         16
 783 #define MAS6_ISIZE_MASK         0x00000f80
 784 #define MAS6_ISIZE_SHIFT        7
 785
 786 #define MAS7_RPN                0xffffffff
 787
 788 #define MAS8_TGS                0x80000000
 789 #define MAS8_VF                 0x40000000
 790 #define MAS8_TLBPID             0x00000fff
 791
 792 /* Bit definitions for MMUCFG */
 793 #define MMUCFG_MAVN     0x00000003      /* MMU Architecture Version Number */
 794 #define MMUCFG_MAVN_V1  0x00000000      /* v1.0 */
 795 #define MMUCFG_MAVN_V2  0x00000001      /* v2.0 */
 796 #define MMUCFG_NTLBS    0x0000000c      /* Number of TLBs */
 797 #define MMUCFG_PIDSIZE  0x000007c0      /* PID Reg Size */
 798 #define MMUCFG_TWC      0x00008000      /* TLB Write Conditional (v2.0) */
 799 #define MMUCFG_LRAT     0x00010000      /* LRAT Supported (v2.0) */
 800 #define MMUCFG_RASIZE   0x00fe0000      /* Real Addr Size */
 801 #define MMUCFG_LPIDSIZE 0x0f000000      /* LPID Reg Size */
 802
 803 /* Bit definitions for MMUCSR0 */
 804 #define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 805 #define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 806 #define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 807 #define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 808 #define MMUCSR0_TLBFI   (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
 809                          MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
 810 #define MMUCSR0_TLB0PS  0x00000780      /* TLB0 Page Size */
 811 #define MMUCSR0_TLB1PS  0x00007800      /* TLB1 Page Size */
 812 #define MMUCSR0_TLB2PS  0x00078000      /* TLB2 Page Size */
 813 #define MMUCSR0_TLB3PS  0x00780000      /* TLB3 Page Size */
 814
 815 /* TLBnCFG encoding */
 816 #define TLBnCFG_N_ENTRY         0x00000fff      /* number of entries */
 817 #define TLBnCFG_HES             0x00002000      /* HW select supported */
 818 #define TLBnCFG_AVAIL           0x00004000      /* variable page size */
 819 #define TLBnCFG_IPROT           0x00008000      /* IPROT supported */
 820 #define TLBnCFG_GTWE            0x00010000      /* Guest can write */
 821 #define TLBnCFG_IND             0x00020000      /* IND entries supported */
 822 #define TLBnCFG_PT              0x00040000      /* Can load from page table */
 823 #define TLBnCFG_MINSIZE         0x00f00000      /* Minimum Page Size (v1.0) */
 824 #define TLBnCFG_MINSIZE_SHIFT   20
 825 #define TLBnCFG_MAXSIZE         0x000f0000      /* Maximum Page Size (v1.0) */
 826 #define TLBnCFG_MAXSIZE_SHIFT   16
 827 #define TLBnCFG_ASSOC           0xff000000      /* Associativity */
 828 #define TLBnCFG_ASSOC_SHIFT     24
 829
 830 /* TLBnPS encoding */
 831 #define TLBnPS_4K               0x00000004
 832 #define TLBnPS_8K               0x00000008
 833 #define TLBnPS_16K              0x00000010
 834 #define TLBnPS_32K              0x00000020
 835 #define TLBnPS_64K              0x00000040
 836 #define TLBnPS_128K             0x00000080
 837 #define TLBnPS_256K             0x00000100
 838 #define TLBnPS_512K             0x00000200
 839 #define TLBnPS_1M               0x00000400
 840 #define TLBnPS_2M               0x00000800
 841 #define TLBnPS_4M               0x00001000
 842 #define TLBnPS_8M               0x00002000
 843 #define TLBnPS_16M              0x00004000
 844 #define TLBnPS_32M              0x00008000
 845 #define TLBnPS_64M              0x00010000
 846 #define TLBnPS_128M             0x00020000
 847 #define TLBnPS_256M             0x00040000
 848 #define TLBnPS_512M             0x00080000
 849 #define TLBnPS_1G               0x00100000
 850 #define TLBnPS_2G               0x00200000
 851 #define TLBnPS_4G               0x00400000
 852 #define TLBnPS_8G               0x00800000
 853 #define TLBnPS_16G              0x01000000
 854 #define TLBnPS_32G              0x02000000
 855 #define TLBnPS_64G              0x04000000
 856 #define TLBnPS_128G             0x08000000
 857 #define TLBnPS_256G             0x10000000
 858
 859 /* tlbilx action encoding */
 860 #define TLBILX_T_ALL                    0
 861 #define TLBILX_T_TID                    1
 862 #define TLBILX_T_FULLMATCH              3
 863 #define TLBILX_T_CLASS0                 4
 864 #define TLBILX_T_CLASS1                 5
 865 #define TLBILX_T_CLASS2                 6
 866 #define TLBILX_T_CLASS3                 7
 867
 868 /* BookE 2.06 helper defines */
 869
 870 #define BOOKE206_FLUSH_TLB0    (1 << 0)
 871 #define BOOKE206_FLUSH_TLB1    (1 << 1)
 872 #define BOOKE206_FLUSH_TLB2    (1 << 2)
 873 #define BOOKE206_FLUSH_TLB3    (1 << 3)
 874
 875 /* number of possible TLBs */
 876 #define BOOKE206_MAX_TLBN      4
 877
 878 /*****************************************************************************/
 879 /* Embedded.Processor Control */
 880
 881 #define DBELL_TYPE_SHIFT               27
 882 #define DBELL_TYPE_MASK                (0x1f << DBELL_TYPE_SHIFT)
 883 #define DBELL_TYPE_DBELL               (0x00 << DBELL_TYPE_SHIFT)
 884 #define DBELL_TYPE_DBELL_CRIT          (0x01 << DBELL_TYPE_SHIFT)
 885 #define DBELL_TYPE_G_DBELL             (0x02 << DBELL_TYPE_SHIFT)
 886 #define DBELL_TYPE_G_DBELL_CRIT        (0x03 << DBELL_TYPE_SHIFT)
 887 #define DBELL_TYPE_G_DBELL_MC          (0x04 << DBELL_TYPE_SHIFT)
 888
 889 #define DBELL_BRDCAST                  (1 << 26)
 890 #define DBELL_LPIDTAG_SHIFT            14
 891 #define DBELL_LPIDTAG_MASK             (0xfff << DBELL_LPIDTAG_SHIFT)
 892 #define DBELL_PIRTAG_MASK              0x3fff
 893
 894 /*****************************************************************************/
 895 /* Segment page size information, used by recent hash MMUs
 896  * The format of this structure mirrors kvm_ppc_smmu_info
 897  */
 898
 899 #define PPC_PAGE_SIZES_MAX_SZ   8
 900
 901 struct ppc_one_page_size {
 902     uint32_t page_shift;  /* Page shift (or 0) */
 903     uint32_t pte_enc;     /* Encoding in the HPTE (>>12) */
 904 };
 905
 906 struct ppc_one_seg_page_size {
 907     uint32_t page_shift;  /* Base page shift of segment (or 0) */
 908     uint32_t slb_enc;     /* SLB encoding for BookS */
 909     struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
 910 };
 911
 912 struct ppc_segment_page_sizes {
 913     struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
 914 };
 915
 916
 917 /*****************************************************************************/
 918 /* The whole PowerPC CPU context */
 919 #define NB_MMU_MODES    8
 920
 921 #define PPC_CPU_OPCODES_LEN          0x40
 922 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
 923
 924 struct CPUPPCState {
 925     /* First are the most commonly used resources
 926      * during translated code execution
 927      */
 928     /* general purpose registers */
 929     target_ulong gpr[32];
 930     /* Storage for GPR MSB, used by the SPE extension */
 931     target_ulong gprh[32];
 932     /* LR */
 933     target_ulong lr;
 934     /* CTR */
 935     target_ulong ctr;
 936     /* condition register */
 937     uint32_t crf[8];
 938 #if defined(TARGET_PPC64)
 939     /* CFAR */
 940     target_ulong cfar;
 941 #endif
 942     /* XER (with SO, OV, CA split out) */
 943     target_ulong xer;
 944     target_ulong so;
 945     target_ulong ov;
 946     target_ulong ca;
 947     /* Reservation address */
 948     target_ulong reserve_addr;
 949     /* Reservation value */
 950     target_ulong reserve_val;
 951     target_ulong reserve_val2;
 952     /* Reservation store address */
 953     target_ulong reserve_ea;
 954     /* Reserved store source register and size */
 955     target_ulong reserve_info;
 956
 957     /* Those ones are used in supervisor mode only */
 958     /* machine state register */
 959     target_ulong msr;
 960     /* temporary general purpose registers */
 961     target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
 962
 963     /* Floating point execution context */
 964     float_status fp_status;
 965     /* floating point registers */
 966     float64 fpr[32];
 967     /* floating point status and control register */
 968     target_ulong fpscr;
 969
 970     /* Next instruction pointer */
 971     target_ulong nip;
 972
 973     int access_type; /* when a memory exception occurs, the access
 974                         type is stored here */
 975
 976     CPU_COMMON
 977
 978     /* MMU context - only relevant for full system emulation */
 979 #if !defined(CONFIG_USER_ONLY)
 980 #if defined(TARGET_PPC64)
 981     /* PowerPC 64 SLB area */
 982     ppc_slb_t slb[MAX_SLB_ENTRIES];
 983     int32_t slb_nr;
 984     /* tcg TLB needs flush (deferred slb inval instruction typically) */
 985 #endif
 986     /* segment registers */
 987     hwaddr htab_base;
 988     /* mask used to normalize hash value to PTEG index */
 989     hwaddr htab_mask;
 990     target_ulong sr[32];
 991     /* externally stored hash table */
 992     uint8_t *external_htab;
 993     /* BATs */
 994     uint32_t nb_BATs;
 995     target_ulong DBAT[2][8];
 996     target_ulong IBAT[2][8];
 997     /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
 998     int32_t nb_tlb;      /* Total number of TLB                              */
 999     int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1000     int nb_ways;     /* Number of ways in the TLB set                        */
1001     int last_way;    /* Last used way used to allocate TLB in a LRU way      */
1002     int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
1003     int nb_pids;     /* Number of available PID registers                    */
1004     int tlb_type;    /* Type of TLB we're dealing with                       */
1005     ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */
1006     /* 403 dedicated access protection registers */
1007     target_ulong pb[4];
1008     bool tlb_dirty;   /* Set to non-zero when modifying TLB                  */
1009     bool kvm_sw_tlb;  /* non-zero if KVM SW TLB API is active                */
1010     uint32_t tlb_need_flush; /* Delayed flush needed */
1011 #endif
1012
1013     /* Other registers */
1014     /* Special purpose registers */
1015     target_ulong spr[1024];
1016     ppc_spr_t spr_cb[1024];
1017     /* Altivec registers */
1018     ppc_avr_t avr[32];
1019     uint32_t vscr;
1020     /* VSX registers */
1021     uint64_t vsr[32];
1022     /* SPE registers */
1023     uint64_t spe_acc;
1024     uint32_t spe_fscr;
1025     /* SPE and Altivec can share a status since they will never be used
1026      * simultaneously */
1027     float_status vec_status;
1028
1029     /* Internal devices resources */
1030     /* Time base and decrementer */
1031     ppc_tb_t *tb_env;
1032     /* Device control registers */
1033     ppc_dcr_t *dcr_env;
1034
1035     int dcache_line_size;
1036     int icache_line_size;
1037
1038     /* Those resources are used during exception processing */
1039     /* CPU model definition */
1040     target_ulong msr_mask;
1041     powerpc_mmu_t mmu_model;
1042     powerpc_excp_t excp_model;
1043     powerpc_input_t bus_model;
1044     int bfd_mach;
1045     uint32_t flags;
1046     uint64_t insns_flags;
1047     uint64_t insns_flags2;
1048 #if defined(TARGET_PPC64)
1049     struct ppc_segment_page_sizes sps;
1050     bool ci_large_pages;
1051 #endif
1052
1053 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1054     uint64_t vpa_addr;
1055     uint64_t slb_shadow_addr, slb_shadow_size;
1056     uint64_t dtl_addr, dtl_size;
1057 #endif /* TARGET_PPC64 */
1058
1059     int error_code;
1060     uint32_t pending_interrupts;
1061 #if !defined(CONFIG_USER_ONLY)
1062     /* This is the IRQ controller, which is implementation dependent
1063      * and only relevant when emulating a complete machine.
1064      */
1065     uint32_t irq_input_state;
1066     void **irq_inputs;
1067     /* Exception vectors */
1068     target_ulong excp_vectors[POWERPC_EXCP_NB];
1069     target_ulong excp_prefix;
1070     target_ulong ivor_mask;
1071     target_ulong ivpr_mask;
1072     target_ulong hreset_vector;
1073     hwaddr mpic_iack;
1074     /* true when the external proxy facility mode is enabled */
1075     bool mpic_proxy;
1076     /* set when the processor has an HV mode, thus HV priv
1077      * instructions and SPRs are diallowed if MSR:HV is 0
1078      */
1079     bool has_hv_mode;
1080     /* On P7/P8, set when in PM state, we need to handle resume
1081      * in a special way (such as routing some resume causes to
1082      * 0x100), so flag this here.
1083      */
1084     bool in_pm_state;
1085 #endif
1086
1087     /* Those resources are used only during code translation */
1088     /* opcode handlers */
1089     opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1090
1091     /* Those resources are used only in QEMU core */
1092     target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */
1093     target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1094     int immu_idx;         /* precomputed MMU index to speed up insn access */
1095     int dmmu_idx;         /* precomputed MMU index to speed up data accesses */
1096
1097     /* Power management */
1098     int (*check_pow)(CPUPPCState *env);
1099
1100 #if !defined(CONFIG_USER_ONLY)
1101     void *load_info;    /* Holds boot loading state.  */
1102 #endif
1103
1104     /* booke timers */
1105
1106     /* Specifies bit locations of the Time Base used to signal a fixed timer
1107      * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1108      *
1109      * 0 selects the least significant bit.
1110      * 63 selects the most significant bit.
1111      */
1112     uint8_t fit_period[4];
1113     uint8_t wdt_period[4];
1114
1115     /* Transactional memory state */
1116     target_ulong tm_gpr[32];
1117     ppc_avr_t tm_vsr[64];
1118     uint64_t tm_cr;
1119     uint64_t tm_lr;
1120     uint64_t tm_ctr;
1121     uint64_t tm_fpscr;
1122     uint64_t tm_amr;
1123     uint64_t tm_ppr;
1124     uint64_t tm_vrsave;
1125     uint32_t tm_vscr;
1126     uint64_t tm_dscr;
1127     uint64_t tm_tar;
1128 };
1129
1130 #define SET_FIT_PERIOD(a_, b_, c_, d_)          \
1131 do {                                            \
1132     env->fit_period[0] = (a_);                  \
1133     env->fit_period[1] = (b_);                  \
1134     env->fit_period[2] = (c_);                  \
1135     env->fit_period[3] = (d_);                  \
1136  } while (0)
1137
1138 #define SET_WDT_PERIOD(a_, b_, c_, d_)          \
1139 do {                                            \
1140     env->wdt_period[0] = (a_);                  \
1141     env->wdt_period[1] = (b_);                  \
1142     env->wdt_period[2] = (c_);                  \
1143     env->wdt_period[3] = (d_);                  \
1144  } while (0)
1145
1146 /**
1147  * PowerPCCPU:
1148  * @env: #CPUPPCState
1149  * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
1150  * @max_compat: Maximal supported logical PVR from the command line
1151  * @cpu_version: Current logical PVR, zero if in "raw" mode
1152  *
1153  * A PowerPC CPU.
1154  */
1155 struct PowerPCCPU {
1156     /*< private >*/
1157     CPUState parent_obj;
1158     /*< public >*/
1159
1160     CPUPPCState env;
1161     int cpu_dt_id;
1162     uint32_t max_compat;
1163     uint32_t cpu_version;
1164 };
1165
1166 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1167 {
1168     return container_of(env, PowerPCCPU, env);
1169 }
1170
1171 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1172
1173 #define ENV_OFFSET offsetof(PowerPCCPU, env)
1174
1175 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1176 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
1177
1178 void ppc_cpu_do_interrupt(CPUState *cpu);
1179 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1180 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1181                         int flags);
1182 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1183                              fprintf_function cpu_fprintf, int flags);
1184 int ppc_cpu_get_monitor_def(CPUState *cs, const char *name,
1185                             uint64_t *pval);
1186 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1187 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1188 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1189 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1190 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1191 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1192                                int cpuid, void *opaque);
1193 #ifndef CONFIG_USER_ONLY
1194 void ppc_cpu_do_system_reset(CPUState *cs);
1195 extern const struct VMStateDescription vmstate_ppc_cpu;
1196 #endif
1197
1198 /*****************************************************************************/
1199 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1200 void ppc_translate_init(void);
1201 void gen_update_current_nip(void *opaque);
1202 /* you can call this signal handler from your SIGBUS and SIGSEGV
1203    signal handlers to inform the virtual CPU of exceptions. non zero
1204    is returned if the signal was handled by the virtual CPU.  */
1205 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1206                             void *puc);
1207 #if defined(CONFIG_USER_ONLY)
1208 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1209                              int mmu_idx);
1210 #endif
1211
1212 #if !defined(CONFIG_USER_ONLY)
1213 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1214 #endif /* !defined(CONFIG_USER_ONLY) */
1215 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1216
1217 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1218 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1219 #if defined(TARGET_PPC64)
1220 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
1221 #endif
1222
1223 /* Time-base and decrementer management */
1224 #ifndef NO_CPU_IO_DEFS
1225 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1226 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1227 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1228 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1229 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1230 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1231 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1232 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1233 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1234 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1235 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1236 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1237 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1238 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1239 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1240 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1241 #if !defined(CONFIG_USER_ONLY)
1242 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1243 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1244 target_ulong load_40x_pit (CPUPPCState *env);
1245 void store_40x_pit (CPUPPCState *env, target_ulong val);
1246 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1247 void store_40x_sler (CPUPPCState *env, uint32_t val);
1248 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1249 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1250 void ppc_tlb_invalidate_all (CPUPPCState *env);
1251 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1252 void cpu_ppc_set_papr(PowerPCCPU *cpu);
1253 #endif
1254 #endif
1255
1256 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1257
1258 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1259 {
1260     uint64_t gprv;
1261
1262     gprv = env->gpr[gprn];
1263     if (env->flags & POWERPC_FLAG_SPE) {
1264         /* If the CPU implements the SPE extension, we have to get the
1265          * high bits of the GPR from the gprh storage area
1266          */
1267         gprv &= 0xFFFFFFFFULL;
1268         gprv |= (uint64_t)env->gprh[gprn] << 32;
1269     }
1270
1271     return gprv;
1272 }
1273
1274 /* Device control registers */
1275 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1276 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1277
1278 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1279
1280 #define cpu_signal_handler cpu_ppc_signal_handler
1281 #define cpu_list ppc_cpu_list
1282
1283 /* MMU modes definitions */
1284 #define MMU_USER_IDX 0
1285 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1286 {
1287     return ifetch ? env->immu_idx : env->dmmu_idx;
1288 }
1289
1290 #include "exec/cpu-all.h"
1291
1292 /*****************************************************************************/
1293 /* CRF definitions */
1294 #define CRF_LT        3
1295 #define CRF_GT        2
1296 #define CRF_EQ        1
1297 #define CRF_SO        0
1298 #define CRF_CH        (1 << CRF_LT)
1299 #define CRF_CL        (1 << CRF_GT)
1300 #define CRF_CH_OR_CL  (1 << CRF_EQ)
1301 #define CRF_CH_AND_CL (1 << CRF_SO)
1302
1303 /* XER definitions */
1304 #define XER_SO  31
1305 #define XER_OV  30
1306 #define XER_CA  29
1307 #define XER_CMP  8
1308 #define XER_BC   0
1309 #define xer_so  (env->so)
1310 #define xer_ov  (env->ov)
1311 #define xer_ca  (env->ca)
1312 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1313 #define xer_bc  ((env->xer >> XER_BC)  & 0x7F)
1314
1315 /* SPR definitions */
1316 #define SPR_MQ                (0x000)
1317 #define SPR_XER               (0x001)
1318 #define SPR_601_VRTCU         (0x004)
1319 #define SPR_601_VRTCL         (0x005)
1320 #define SPR_601_UDECR         (0x006)
1321 #define SPR_LR                (0x008)
1322 #define SPR_CTR               (0x009)
1323 #define SPR_UAMR              (0x00C)
1324 #define SPR_DSCR              (0x011)
1325 #define SPR_DSISR             (0x012)
1326 #define SPR_DAR               (0x013) /* DAE for PowerPC 601 */
1327 #define SPR_601_RTCU          (0x014)
1328 #define SPR_601_RTCL          (0x015)
1329 #define SPR_DECR              (0x016)
1330 #define SPR_SDR1              (0x019)
1331 #define SPR_SRR0              (0x01A)
1332 #define SPR_SRR1              (0x01B)
1333 #define SPR_CFAR              (0x01C)
1334 #define SPR_AMR               (0x01D)
1335 #define SPR_ACOP              (0x01F)
1336 #define SPR_BOOKE_PID         (0x030)
1337 #define SPR_BOOKS_PID         (0x030)
1338 #define SPR_BOOKE_DECAR       (0x036)
1339 #define SPR_BOOKE_CSRR0       (0x03A)
1340 #define SPR_BOOKE_CSRR1       (0x03B)
1341 #define SPR_BOOKE_DEAR        (0x03D)
1342 #define SPR_IAMR              (0x03D)
1343 #define SPR_BOOKE_ESR         (0x03E)
1344 #define SPR_BOOKE_IVPR        (0x03F)
1345 #define SPR_MPC_EIE           (0x050)
1346 #define SPR_MPC_EID           (0x051)
1347 #define SPR_MPC_NRI           (0x052)
1348 #define SPR_TFHAR             (0x080)
1349 #define SPR_TFIAR             (0x081)
1350 #define SPR_TEXASR            (0x082)
1351 #define SPR_TEXASRU           (0x083)
1352 #define SPR_UCTRL             (0x088)
1353 #define SPR_MPC_CMPA          (0x090)
1354 #define SPR_MPC_CMPB          (0x091)
1355 #define SPR_MPC_CMPC          (0x092)
1356 #define SPR_MPC_CMPD          (0x093)
1357 #define SPR_MPC_ECR           (0x094)
1358 #define SPR_MPC_DER           (0x095)
1359 #define SPR_MPC_COUNTA        (0x096)
1360 #define SPR_MPC_COUNTB        (0x097)
1361 #define SPR_CTRL              (0x098)
1362 #define SPR_MPC_CMPE          (0x098)
1363 #define SPR_MPC_CMPF          (0x099)
1364 #define SPR_FSCR              (0x099)
1365 #define SPR_MPC_CMPG          (0x09A)
1366 #define SPR_MPC_CMPH          (0x09B)
1367 #define SPR_MPC_LCTRL1        (0x09C)
1368 #define SPR_MPC_LCTRL2        (0x09D)
1369 #define SPR_UAMOR             (0x09D)
1370 #define SPR_MPC_ICTRL         (0x09E)
1371 #define SPR_MPC_BAR           (0x09F)
1372 #define SPR_PSPB              (0x09F)
1373 #define SPR_DAWR              (0x0B4)
1374 #define SPR_RPR               (0x0BA)
1375 #define SPR_CIABR             (0x0BB)
1376 #define SPR_DAWRX             (0x0BC)
1377 #define SPR_HFSCR             (0x0BE)
1378 #define SPR_VRSAVE            (0x100)
1379 #define SPR_USPRG0            (0x100)
1380 #define SPR_USPRG1            (0x101)
1381 #define SPR_USPRG2            (0x102)
1382 #define SPR_USPRG3            (0x103)
1383 #define SPR_USPRG4            (0x104)
1384 #define SPR_USPRG5            (0x105)
1385 #define SPR_USPRG6            (0x106)
1386 #define SPR_USPRG7            (0x107)
1387 #define SPR_VTBL              (0x10C)
1388 #define SPR_VTBU              (0x10D)
1389 #define SPR_SPRG0             (0x110)
1390 #define SPR_SPRG1             (0x111)
1391 #define SPR_SPRG2             (0x112)
1392 #define SPR_SPRG3             (0x113)
1393 #define SPR_SPRG4             (0x114)
1394 #define SPR_SCOMC             (0x114)
1395 #define SPR_SPRG5             (0x115)
1396 #define SPR_SCOMD             (0x115)
1397 #define SPR_SPRG6             (0x116)
1398 #define SPR_SPRG7             (0x117)
1399 #define SPR_ASR               (0x118)
1400 #define SPR_EAR               (0x11A)
1401 #define SPR_TBL               (0x11C)
1402 #define SPR_TBU               (0x11D)
1403 #define SPR_TBU40             (0x11E)
1404 #define SPR_SVR               (0x11E)
1405 #define SPR_BOOKE_PIR         (0x11E)
1406 #define SPR_PVR               (0x11F)
1407 #define SPR_HSPRG0            (0x130)
1408 #define SPR_BOOKE_DBSR        (0x130)
1409 #define SPR_HSPRG1            (0x131)
1410 #define SPR_HDSISR            (0x132)
1411 #define SPR_HDAR              (0x133)
1412 #define SPR_BOOKE_EPCR        (0x133)
1413 #define SPR_SPURR             (0x134)
1414 #define SPR_BOOKE_DBCR0       (0x134)
1415 #define SPR_IBCR              (0x135)
1416 #define SPR_PURR              (0x135)
1417 #define SPR_BOOKE_DBCR1       (0x135)
1418 #define SPR_DBCR              (0x136)
1419 #define SPR_HDEC              (0x136)
1420 #define SPR_BOOKE_DBCR2       (0x136)
1421 #define SPR_HIOR              (0x137)
1422 #define SPR_MBAR              (0x137)
1423 #define SPR_RMOR              (0x138)
1424 #define SPR_BOOKE_IAC1        (0x138)
1425 #define SPR_HRMOR             (0x139)
1426 #define SPR_BOOKE_IAC2        (0x139)
1427 #define SPR_HSRR0             (0x13A)
1428 #define SPR_BOOKE_IAC3        (0x13A)
1429 #define SPR_HSRR1             (0x13B)
1430 #define SPR_BOOKE_IAC4        (0x13B)
1431 #define SPR_BOOKE_DAC1        (0x13C)
1432 #define SPR_MMCRH             (0x13C)
1433 #define SPR_DABR2             (0x13D)
1434 #define SPR_BOOKE_DAC2        (0x13D)
1435 #define SPR_TFMR              (0x13D)
1436 #define SPR_BOOKE_DVC1        (0x13E)
1437 #define SPR_LPCR              (0x13E)
1438 #define SPR_BOOKE_DVC2        (0x13F)
1439 #define SPR_LPIDR             (0x13F)
1440 #define SPR_BOOKE_TSR         (0x150)
1441 #define SPR_HMER              (0x150)
1442 #define SPR_HMEER             (0x151)
1443 #define SPR_PCR               (0x152)
1444 #define SPR_BOOKE_LPIDR       (0x152)
1445 #define SPR_BOOKE_TCR         (0x154)
1446 #define SPR_BOOKE_TLB0PS      (0x158)
1447 #define SPR_BOOKE_TLB1PS      (0x159)
1448 #define SPR_BOOKE_TLB2PS      (0x15A)
1449 #define SPR_BOOKE_TLB3PS      (0x15B)
1450 #define SPR_AMOR              (0x15D)
1451 #define SPR_BOOKE_MAS7_MAS3   (0x174)
1452 #define SPR_BOOKE_IVOR0       (0x190)
1453 #define SPR_BOOKE_IVOR1       (0x191)
1454 #define SPR_BOOKE_IVOR2       (0x192)
1455 #define SPR_BOOKE_IVOR3       (0x193)
1456 #define SPR_BOOKE_IVOR4       (0x194)
1457 #define SPR_BOOKE_IVOR5       (0x195)
1458 #define SPR_BOOKE_IVOR6       (0x196)
1459 #define SPR_BOOKE_IVOR7       (0x197)
1460 #define SPR_BOOKE_IVOR8       (0x198)
1461 #define SPR_BOOKE_IVOR9       (0x199)
1462 #define SPR_BOOKE_IVOR10      (0x19A)
1463 #define SPR_BOOKE_IVOR11      (0x19B)
1464 #define SPR_BOOKE_IVOR12      (0x19C)
1465 #define SPR_BOOKE_IVOR13      (0x19D)
1466 #define SPR_BOOKE_IVOR14      (0x19E)
1467 #define SPR_BOOKE_IVOR15      (0x19F)
1468 #define SPR_BOOKE_IVOR38      (0x1B0)
1469 #define SPR_BOOKE_IVOR39      (0x1B1)
1470 #define SPR_BOOKE_IVOR40      (0x1B2)
1471 #define SPR_BOOKE_IVOR41      (0x1B3)
1472 #define SPR_BOOKE_IVOR42      (0x1B4)
1473 #define SPR_BOOKE_GIVOR2      (0x1B8)
1474 #define SPR_BOOKE_GIVOR3      (0x1B9)
1475 #define SPR_BOOKE_GIVOR4      (0x1BA)
1476 #define SPR_BOOKE_GIVOR8      (0x1BB)
1477 #define SPR_BOOKE_GIVOR13     (0x1BC)
1478 #define SPR_BOOKE_GIVOR14     (0x1BD)
1479 #define SPR_TIR               (0x1BE)
1480 #define SPR_BOOKE_SPEFSCR     (0x200)
1481 #define SPR_Exxx_BBEAR        (0x201)
1482 #define SPR_Exxx_BBTAR        (0x202)
1483 #define SPR_Exxx_L1CFG0       (0x203)
1484 #define SPR_Exxx_L1CFG1       (0x204)
1485 #define SPR_Exxx_NPIDR        (0x205)
1486 #define SPR_ATBL              (0x20E)
1487 #define SPR_ATBU              (0x20F)
1488 #define SPR_IBAT0U            (0x210)
1489 #define SPR_BOOKE_IVOR32      (0x210)
1490 #define SPR_RCPU_MI_GRA       (0x210)
1491 #define SPR_IBAT0L            (0x211)
1492 #define SPR_BOOKE_IVOR33      (0x211)
1493 #define SPR_IBAT1U            (0x212)
1494 #define SPR_BOOKE_IVOR34      (0x212)
1495 #define SPR_IBAT1L            (0x213)
1496 #define SPR_BOOKE_IVOR35      (0x213)
1497 #define SPR_IBAT2U            (0x214)
1498 #define SPR_BOOKE_IVOR36      (0x214)
1499 #define SPR_IBAT2L            (0x215)
1500 #define SPR_BOOKE_IVOR37      (0x215)
1501 #define SPR_IBAT3U            (0x216)
1502 #define SPR_IBAT3L            (0x217)
1503 #define SPR_DBAT0U            (0x218)
1504 #define SPR_RCPU_L2U_GRA      (0x218)
1505 #define SPR_DBAT0L            (0x219)
1506 #define SPR_DBAT1U            (0x21A)
1507 #define SPR_DBAT1L            (0x21B)
1508 #define SPR_DBAT2U            (0x21C)
1509 #define SPR_DBAT2L            (0x21D)
1510 #define SPR_DBAT3U            (0x21E)
1511 #define SPR_DBAT3L            (0x21F)
1512 #define SPR_IBAT4U            (0x230)
1513 #define SPR_RPCU_BBCMCR       (0x230)
1514 #define SPR_MPC_IC_CST        (0x230)
1515 #define SPR_Exxx_CTXCR        (0x230)
1516 #define SPR_IBAT4L            (0x231)
1517 #define SPR_MPC_IC_ADR        (0x231)
1518 #define SPR_Exxx_DBCR3        (0x231)
1519 #define SPR_IBAT5U            (0x232)
1520 #define SPR_MPC_IC_DAT        (0x232)
1521 #define SPR_Exxx_DBCNT        (0x232)
1522 #define SPR_IBAT5L            (0x233)
1523 #define SPR_IBAT6U            (0x234)
1524 #define SPR_IBAT6L            (0x235)
1525 #define SPR_IBAT7U            (0x236)
1526 #define SPR_IBAT7L            (0x237)
1527 #define SPR_DBAT4U            (0x238)
1528 #define SPR_RCPU_L2U_MCR      (0x238)
1529 #define SPR_MPC_DC_CST        (0x238)
1530 #define SPR_Exxx_ALTCTXCR     (0x238)
1531 #define SPR_DBAT4L            (0x239)
1532 #define SPR_MPC_DC_ADR        (0x239)
1533 #define SPR_DBAT5U            (0x23A)
1534 #define SPR_BOOKE_MCSRR0      (0x23A)
1535 #define SPR_MPC_DC_DAT        (0x23A)
1536 #define SPR_DBAT5L            (0x23B)
1537 #define SPR_BOOKE_MCSRR1      (0x23B)
1538 #define SPR_DBAT6U            (0x23C)
1539 #define SPR_BOOKE_MCSR        (0x23C)
1540 #define SPR_DBAT6L            (0x23D)
1541 #define SPR_Exxx_MCAR         (0x23D)
1542 #define SPR_DBAT7U            (0x23E)
1543 #define SPR_BOOKE_DSRR0       (0x23E)
1544 #define SPR_DBAT7L            (0x23F)
1545 #define SPR_BOOKE_DSRR1       (0x23F)
1546 #define SPR_BOOKE_SPRG8       (0x25C)
1547 #define SPR_BOOKE_SPRG9       (0x25D)
1548 #define SPR_BOOKE_MAS0        (0x270)
1549 #define SPR_BOOKE_MAS1        (0x271)
1550 #define SPR_BOOKE_MAS2        (0x272)
1551 #define SPR_BOOKE_MAS3        (0x273)
1552 #define SPR_BOOKE_MAS4        (0x274)
1553 #define SPR_BOOKE_MAS5        (0x275)
1554 #define SPR_BOOKE_MAS6        (0x276)
1555 #define SPR_BOOKE_PID1        (0x279)
1556 #define SPR_BOOKE_PID2        (0x27A)
1557 #define SPR_MPC_DPDR          (0x280)
1558 #define SPR_MPC_IMMR          (0x288)
1559 #define SPR_BOOKE_TLB0CFG     (0x2B0)
1560 #define SPR_BOOKE_TLB1CFG     (0x2B1)
1561 #define SPR_BOOKE_TLB2CFG     (0x2B2)
1562 #define SPR_BOOKE_TLB3CFG     (0x2B3)
1563 #define SPR_BOOKE_EPR         (0x2BE)
1564 #define SPR_PERF0             (0x300)
1565 #define SPR_RCPU_MI_RBA0      (0x300)
1566 #define SPR_MPC_MI_CTR        (0x300)
1567 #define SPR_POWER_USIER       (0x300)
1568 #define SPR_PERF1             (0x301)
1569 #define SPR_RCPU_MI_RBA1      (0x301)
1570 #define SPR_POWER_UMMCR2      (0x301)
1571 #define SPR_PERF2             (0x302)
1572 #define SPR_RCPU_MI_RBA2      (0x302)
1573 #define SPR_MPC_MI_AP         (0x302)
1574 #define SPR_POWER_UMMCRA      (0x302)
1575 #define SPR_PERF3             (0x303)
1576 #define SPR_RCPU_MI_RBA3      (0x303)
1577 #define SPR_MPC_MI_EPN        (0x303)
1578 #define SPR_POWER_UPMC1       (0x303)
1579 #define SPR_PERF4             (0x304)
1580 #define SPR_POWER_UPMC2       (0x304)
1581 #define SPR_PERF5             (0x305)
1582 #define SPR_MPC_MI_TWC        (0x305)
1583 #define SPR_POWER_UPMC3       (0x305)
1584 #define SPR_PERF6             (0x306)
1585 #define SPR_MPC_MI_RPN        (0x306)
1586 #define SPR_POWER_UPMC4       (0x306)
1587 #define SPR_PERF7             (0x307)
1588 #define SPR_POWER_UPMC5       (0x307)
1589 #define SPR_PERF8             (0x308)
1590 #define SPR_RCPU_L2U_RBA0     (0x308)
1591 #define SPR_MPC_MD_CTR        (0x308)
1592 #define SPR_POWER_UPMC6       (0x308)
1593 #define SPR_PERF9             (0x309)
1594 #define SPR_RCPU_L2U_RBA1     (0x309)
1595 #define SPR_MPC_MD_CASID      (0x309)
1596 #define SPR_970_UPMC7         (0X309)
1597 #define SPR_PERFA             (0x30A)
1598 #define SPR_RCPU_L2U_RBA2     (0x30A)
1599 #define SPR_MPC_MD_AP         (0x30A)
1600 #define SPR_970_UPMC8         (0X30A)
1601 #define SPR_PERFB             (0x30B)
1602 #define SPR_RCPU_L2U_RBA3     (0x30B)
1603 #define SPR_MPC_MD_EPN        (0x30B)
1604 #define SPR_POWER_UMMCR0      (0X30B)
1605 #define SPR_PERFC             (0x30C)
1606 #define SPR_MPC_MD_TWB        (0x30C)
1607 #define SPR_POWER_USIAR       (0X30C)
1608 #define SPR_PERFD             (0x30D)
1609 #define SPR_MPC_MD_TWC        (0x30D)
1610 #define SPR_POWER_USDAR       (0X30D)
1611 #define SPR_PERFE             (0x30E)
1612 #define SPR_MPC_MD_RPN        (0x30E)
1613 #define SPR_POWER_UMMCR1      (0X30E)
1614 #define SPR_PERFF             (0x30F)
1615 #define SPR_MPC_MD_TW         (0x30F)
1616 #define SPR_UPERF0            (0x310)
1617 #define SPR_POWER_SIER        (0x310)
1618 #define SPR_UPERF1            (0x311)
1619 #define SPR_POWER_MMCR2       (0x311)
1620 #define SPR_UPERF2            (0x312)
1621 #define SPR_POWER_MMCRA       (0X312)
1622 #define SPR_UPERF3            (0x313)
1623 #define SPR_POWER_PMC1        (0X313)
1624 #define SPR_UPERF4            (0x314)
1625 #define SPR_POWER_PMC2        (0X314)
1626 #define SPR_UPERF5            (0x315)
1627 #define SPR_POWER_PMC3        (0X315)
1628 #define SPR_UPERF6            (0x316)
1629 #define SPR_POWER_PMC4        (0X316)
1630 #define SPR_UPERF7            (0x317)
1631 #define SPR_POWER_PMC5        (0X317)
1632 #define SPR_UPERF8            (0x318)
1633 #define SPR_POWER_PMC6        (0X318)
1634 #define SPR_UPERF9            (0x319)
1635 #define SPR_970_PMC7          (0X319)
1636 #define SPR_UPERFA            (0x31A)
1637 #define SPR_970_PMC8          (0X31A)
1638 #define SPR_UPERFB            (0x31B)
1639 #define SPR_POWER_MMCR0       (0X31B)
1640 #define SPR_UPERFC            (0x31C)
1641 #define SPR_POWER_SIAR        (0X31C)
1642 #define SPR_UPERFD            (0x31D)
1643 #define SPR_POWER_SDAR        (0X31D)
1644 #define SPR_UPERFE            (0x31E)
1645 #define SPR_POWER_MMCR1       (0X31E)
1646 #define SPR_UPERFF            (0x31F)
1647 #define SPR_RCPU_MI_RA0       (0x320)
1648 #define SPR_MPC_MI_DBCAM      (0x320)
1649 #define SPR_BESCRS            (0x320)
1650 #define SPR_RCPU_MI_RA1       (0x321)
1651 #define SPR_MPC_MI_DBRAM0     (0x321)
1652 #define SPR_BESCRSU           (0x321)
1653 #define SPR_RCPU_MI_RA2       (0x322)
1654 #define SPR_MPC_MI_DBRAM1     (0x322)
1655 #define SPR_BESCRR            (0x322)
1656 #define SPR_RCPU_MI_RA3       (0x323)
1657 #define SPR_BESCRRU           (0x323)
1658 #define SPR_EBBHR             (0x324)
1659 #define SPR_EBBRR             (0x325)
1660 #define SPR_BESCR             (0x326)
1661 #define SPR_RCPU_L2U_RA0      (0x328)
1662 #define SPR_MPC_MD_DBCAM      (0x328)
1663 #define SPR_RCPU_L2U_RA1      (0x329)
1664 #define SPR_MPC_MD_DBRAM0     (0x329)
1665 #define SPR_RCPU_L2U_RA2      (0x32A)
1666 #define SPR_MPC_MD_DBRAM1     (0x32A)
1667 #define SPR_RCPU_L2U_RA3      (0x32B)
1668 #define SPR_TAR               (0x32F)
1669 #define SPR_IC                (0x350)
1670 #define SPR_VTB               (0x351)
1671 #define SPR_MMCRC             (0x353)
1672 #define SPR_440_INV0          (0x370)
1673 #define SPR_440_INV1          (0x371)
1674 #define SPR_440_INV2          (0x372)
1675 #define SPR_440_INV3          (0x373)
1676 #define SPR_440_ITV0          (0x374)
1677 #define SPR_440_ITV1          (0x375)
1678 #define SPR_440_ITV2          (0x376)
1679 #define SPR_440_ITV3          (0x377)
1680 #define SPR_440_CCR1          (0x378)
1681 #define SPR_TACR              (0x378)
1682 #define SPR_TCSCR             (0x379)
1683 #define SPR_CSIGR             (0x37a)
1684 #define SPR_DCRIPR            (0x37B)
1685 #define SPR_POWER_SPMC1       (0x37C)
1686 #define SPR_POWER_SPMC2       (0x37D)
1687 #define SPR_POWER_MMCRS       (0x37E)
1688 #define SPR_WORT              (0x37F)
1689 #define SPR_PPR               (0x380)
1690 #define SPR_750_GQR0          (0x390)
1691 #define SPR_440_DNV0          (0x390)
1692 #define SPR_750_GQR1          (0x391)
1693 #define SPR_440_DNV1          (0x391)
1694 #define SPR_750_GQR2          (0x392)
1695 #define SPR_440_DNV2          (0x392)
1696 #define SPR_750_GQR3          (0x393)
1697 #define SPR_440_DNV3          (0x393)
1698 #define SPR_750_GQR4          (0x394)
1699 #define SPR_440_DTV0          (0x394)
1700 #define SPR_750_GQR5          (0x395)
1701 #define SPR_440_DTV1          (0x395)
1702 #define SPR_750_GQR6          (0x396)
1703 #define SPR_440_DTV2          (0x396)
1704 #define SPR_750_GQR7          (0x397)
1705 #define SPR_440_DTV3          (0x397)
1706 #define SPR_750_THRM4         (0x398)
1707 #define SPR_750CL_HID2        (0x398)
1708 #define SPR_440_DVLIM         (0x398)
1709 #define SPR_750_WPAR          (0x399)
1710 #define SPR_440_IVLIM         (0x399)
1711 #define SPR_TSCR              (0x399)
1712 #define SPR_750_DMAU          (0x39A)
1713 #define SPR_750_DMAL          (0x39B)
1714 #define SPR_440_RSTCFG        (0x39B)
1715 #define SPR_BOOKE_DCDBTRL     (0x39C)
1716 #define SPR_BOOKE_DCDBTRH     (0x39D)
1717 #define SPR_BOOKE_ICDBTRL     (0x39E)
1718 #define SPR_BOOKE_ICDBTRH     (0x39F)
1719 #define SPR_74XX_UMMCR2       (0x3A0)
1720 #define SPR_7XX_UPMC5         (0x3A1)
1721 #define SPR_7XX_UPMC6         (0x3A2)
1722 #define SPR_UBAMR             (0x3A7)
1723 #define SPR_7XX_UMMCR0        (0x3A8)
1724 #define SPR_7XX_UPMC1         (0x3A9)
1725 #define SPR_7XX_UPMC2         (0x3AA)
1726 #define SPR_7XX_USIAR         (0x3AB)
1727 #define SPR_7XX_UMMCR1        (0x3AC)
1728 #define SPR_7XX_UPMC3         (0x3AD)
1729 #define SPR_7XX_UPMC4         (0x3AE)
1730 #define SPR_USDA              (0x3AF)
1731 #define SPR_40x_ZPR           (0x3B0)
1732 #define SPR_BOOKE_MAS7        (0x3B0)
1733 #define SPR_74XX_MMCR2        (0x3B0)
1734 #define SPR_7XX_PMC5          (0x3B1)
1735 #define SPR_40x_PID           (0x3B1)
1736 #define SPR_7XX_PMC6          (0x3B2)
1737 #define SPR_440_MMUCR         (0x3B2)
1738 #define SPR_4xx_CCR0          (0x3B3)
1739 #define SPR_BOOKE_EPLC        (0x3B3)
1740 #define SPR_405_IAC3          (0x3B4)
1741 #define SPR_BOOKE_EPSC        (0x3B4)
1742 #define SPR_405_IAC4          (0x3B5)
1743 #define SPR_405_DVC1          (0x3B6)
1744 #define SPR_405_DVC2          (0x3B7)
1745 #define SPR_BAMR              (0x3B7)
1746 #define SPR_7XX_MMCR0         (0x3B8)
1747 #define SPR_7XX_PMC1          (0x3B9)
1748 #define SPR_40x_SGR           (0x3B9)
1749 #define SPR_7XX_PMC2          (0x3BA)
1750 #define SPR_40x_DCWR          (0x3BA)
1751 #define SPR_7XX_SIAR          (0x3BB)
1752 #define SPR_405_SLER          (0x3BB)
1753 #define SPR_7XX_MMCR1         (0x3BC)
1754 #define SPR_405_SU0R          (0x3BC)
1755 #define SPR_401_SKR           (0x3BC)
1756 #define SPR_7XX_PMC3          (0x3BD)
1757 #define SPR_405_DBCR1         (0x3BD)
1758 #define SPR_7XX_PMC4          (0x3BE)
1759 #define SPR_SDA               (0x3BF)
1760 #define SPR_403_VTBL          (0x3CC)
1761 #define SPR_403_VTBU          (0x3CD)
1762 #define SPR_DMISS             (0x3D0)
1763 #define SPR_DCMP              (0x3D1)
1764 #define SPR_HASH1             (0x3D2)
1765 #define SPR_HASH2             (0x3D3)
1766 #define SPR_BOOKE_ICDBDR      (0x3D3)
1767 #define SPR_TLBMISS           (0x3D4)
1768 #define SPR_IMISS             (0x3D4)
1769 #define SPR_40x_ESR           (0x3D4)
1770 #define SPR_PTEHI             (0x3D5)
1771 #define SPR_ICMP              (0x3D5)
1772 #define SPR_40x_DEAR          (0x3D5)
1773 #define SPR_PTELO             (0x3D6)
1774 #define SPR_RPA               (0x3D6)
1775 #define SPR_40x_EVPR          (0x3D6)
1776 #define SPR_L3PM              (0x3D7)
1777 #define SPR_403_CDBCR         (0x3D7)
1778 #define SPR_L3ITCR0           (0x3D8)
1779 #define SPR_TCR               (0x3D8)
1780 #define SPR_40x_TSR           (0x3D8)
1781 #define SPR_IBR               (0x3DA)
1782 #define SPR_40x_TCR           (0x3DA)
1783 #define SPR_ESASRR            (0x3DB)
1784 #define SPR_40x_PIT           (0x3DB)
1785 #define SPR_403_TBL           (0x3DC)
1786 #define SPR_403_TBU           (0x3DD)
1787 #define SPR_SEBR              (0x3DE)
1788 #define SPR_40x_SRR2          (0x3DE)
1789 #define SPR_SER               (0x3DF)
1790 #define SPR_40x_SRR3          (0x3DF)
1791 #define SPR_L3OHCR            (0x3E8)
1792 #define SPR_L3ITCR1           (0x3E9)
1793 #define SPR_L3ITCR2           (0x3EA)
1794 #define SPR_L3ITCR3           (0x3EB)
1795 #define SPR_HID0              (0x3F0)
1796 #define SPR_40x_DBSR          (0x3F0)
1797 #define SPR_HID1              (0x3F1)
1798 #define SPR_IABR              (0x3F2)
1799 #define SPR_40x_DBCR0         (0x3F2)
1800 #define SPR_601_HID2          (0x3F2)
1801 #define SPR_Exxx_L1CSR0       (0x3F2)
1802 #define SPR_ICTRL             (0x3F3)
1803 #define SPR_HID2              (0x3F3)
1804 #define SPR_750CL_HID4        (0x3F3)
1805 #define SPR_Exxx_L1CSR1       (0x3F3)
1806 #define SPR_440_DBDR          (0x3F3)
1807 #define SPR_LDSTDB            (0x3F4)
1808 #define SPR_750_TDCL          (0x3F4)
1809 #define SPR_40x_IAC1          (0x3F4)
1810 #define SPR_MMUCSR0           (0x3F4)
1811 #define SPR_970_HID4          (0x3F4)
1812 #define SPR_DABR              (0x3F5)
1813 #define DABR_MASK (~(target_ulong)0x7)
1814 #define SPR_Exxx_BUCSR        (0x3F5)
1815 #define SPR_40x_IAC2          (0x3F5)
1816 #define SPR_601_HID5          (0x3F5)
1817 #define SPR_40x_DAC1          (0x3F6)
1818 #define SPR_MSSCR0            (0x3F6)
1819 #define SPR_970_HID5          (0x3F6)
1820 #define SPR_MSSSR0            (0x3F7)
1821 #define SPR_MSSCR1            (0x3F7)
1822 #define SPR_DABRX             (0x3F7)
1823 #define SPR_40x_DAC2          (0x3F7)
1824 #define SPR_MMUCFG            (0x3F7)
1825 #define SPR_LDSTCR            (0x3F8)
1826 #define SPR_L2PMCR            (0x3F8)
1827 #define SPR_750FX_HID2        (0x3F8)
1828 #define SPR_Exxx_L1FINV0      (0x3F8)
1829 #define SPR_L2CR              (0x3F9)
1830 #define SPR_L3CR              (0x3FA)
1831 #define SPR_750_TDCH          (0x3FA)
1832 #define SPR_IABR2             (0x3FA)
1833 #define SPR_40x_DCCR          (0x3FA)
1834 #define SPR_ICTC              (0x3FB)
1835 #define SPR_40x_ICCR          (0x3FB)
1836 #define SPR_THRM1             (0x3FC)
1837 #define SPR_403_PBL1          (0x3FC)
1838 #define SPR_SP                (0x3FD)
1839 #define SPR_THRM2             (0x3FD)
1840 #define SPR_403_PBU1          (0x3FD)
1841 #define SPR_604_HID13         (0x3FD)
1842 #define SPR_LT                (0x3FE)
1843 #define SPR_THRM3             (0x3FE)
1844 #define SPR_RCPU_FPECR        (0x3FE)
1845 #define SPR_403_PBL2          (0x3FE)
1846 #define SPR_PIR               (0x3FF)
1847 #define SPR_403_PBU2          (0x3FF)
1848 #define SPR_601_HID15         (0x3FF)
1849 #define SPR_604_HID15         (0x3FF)
1850 #define SPR_E500_SVR          (0x3FF)
1851
1852 /* Disable MAS Interrupt Updates for Hypervisor */
1853 #define EPCR_DMIUH            (1 << 22)
1854 /* Disable Guest TLB Management Instructions */
1855 #define EPCR_DGTMI            (1 << 23)
1856 /* Guest Interrupt Computation Mode */
1857 #define EPCR_GICM             (1 << 24)
1858 /* Interrupt Computation Mode */
1859 #define EPCR_ICM              (1 << 25)
1860 /* Disable Embedded Hypervisor Debug */
1861 #define EPCR_DUVD             (1 << 26)
1862 /* Instruction Storage Interrupt Directed to Guest State */
1863 #define EPCR_ISIGS            (1 << 27)
1864 /* Data Storage Interrupt Directed to Guest State */
1865 #define EPCR_DSIGS            (1 << 28)
1866 /* Instruction TLB Error Interrupt Directed to Guest State */
1867 #define EPCR_ITLBGS           (1 << 29)
1868 /* Data TLB Error Interrupt Directed to Guest State */
1869 #define EPCR_DTLBGS           (1 << 30)
1870 /* External Input Interrupt Directed to Guest State */
1871 #define EPCR_EXTGS            (1 << 31)
1872
1873 #define   L1CSR0_CPE            0x00010000      /* Data Cache Parity Enable */
1874 #define   L1CSR0_CUL            0x00000400      /* (D-)Cache Unable to Lock */
1875 #define   L1CSR0_DCLFR          0x00000100      /* D-Cache Lock Flash Reset */
1876 #define   L1CSR0_DCFI           0x00000002      /* Data Cache Flash Invalidate */
1877 #define   L1CSR0_DCE            0x00000001      /* Data Cache Enable */
1878
1879 #define   L1CSR1_CPE            0x00010000      /* Instruction Cache Parity Enable */
1880 #define   L1CSR1_ICUL           0x00000400      /* I-Cache Unable to Lock */
1881 #define   L1CSR1_ICLFR          0x00000100      /* I-Cache Lock Flash Reset */
1882 #define   L1CSR1_ICFI           0x00000002      /* Instruction Cache Flash Invalidate */
1883 #define   L1CSR1_ICE            0x00000001      /* Instruction Cache Enable */
1884
1885 /* HID0 bits */
1886 #define HID0_DEEPNAP        (1 << 24)           /* pre-2.06 */
1887 #define HID0_DOZE           (1 << 23)           /* pre-2.06 */
1888 #define HID0_NAP            (1 << 22)           /* pre-2.06 */
1889 #define HID0_HILE           (1ull << (63 - 19)) /* POWER8 */
1890
1891 /*****************************************************************************/
1892 /* PowerPC Instructions types definitions                                    */
1893 enum {
1894     PPC_NONE           = 0x0000000000000000ULL,
1895     /* PowerPC base instructions set                                         */
1896     PPC_INSNS_BASE     = 0x0000000000000001ULL,
1897     /*   integer operations instructions                                     */
1898 #define PPC_INTEGER PPC_INSNS_BASE
1899     /*   flow control instructions                                           */
1900 #define PPC_FLOW    PPC_INSNS_BASE
1901     /*   virtual memory instructions                                         */
1902 #define PPC_MEM     PPC_INSNS_BASE
1903     /*   ld/st with reservation instructions                                 */
1904 #define PPC_RES     PPC_INSNS_BASE
1905     /*   spr/msr access instructions                                         */
1906 #define PPC_MISC    PPC_INSNS_BASE
1907     /* Deprecated instruction sets                                           */
1908     /*   Original POWER instruction set                                      */
1909     PPC_POWER          = 0x0000000000000002ULL,
1910     /*   POWER2 instruction set extension                                    */
1911     PPC_POWER2         = 0x0000000000000004ULL,
1912     /*   Power RTC support                                                   */
1913     PPC_POWER_RTC      = 0x0000000000000008ULL,
1914     /*   Power-to-PowerPC bridge (601)                                       */
1915     PPC_POWER_BR       = 0x0000000000000010ULL,
1916     /* 64 bits PowerPC instruction set                                       */
1917     PPC_64B            = 0x0000000000000020ULL,
1918     /*   New 64 bits extensions (PowerPC 2.0x)                               */
1919     PPC_64BX           = 0x0000000000000040ULL,
1920     /*   64 bits hypervisor extensions                                       */
1921     PPC_64H            = 0x0000000000000080ULL,
1922     /*   New wait instruction (PowerPC 2.0x)                                 */
1923     PPC_WAIT           = 0x0000000000000100ULL,
1924     /*   Time base mftb instruction                                          */
1925     PPC_MFTB           = 0x0000000000000200ULL,
1926
1927     /* Fixed-point unit extensions                                           */
1928     /*   PowerPC 602 specific                                                */
1929     PPC_602_SPEC       = 0x0000000000000400ULL,
1930     /*   isel instruction                                                    */
1931     PPC_ISEL           = 0x0000000000000800ULL,
1932     /*   popcntb instruction                                                 */
1933     PPC_POPCNTB        = 0x0000000000001000ULL,
1934     /*   string load / store                                                 */
1935     PPC_STRING         = 0x0000000000002000ULL,
1936     /*   real mode cache inhibited load / store                              */
1937     PPC_CILDST         = 0x0000000000004000ULL,
1938
1939     /* Floating-point unit extensions                                        */
1940     /*   Optional floating point instructions                                */
1941     PPC_FLOAT          = 0x0000000000010000ULL,
1942     /* New floating-point extensions (PowerPC 2.0x)                          */
1943     PPC_FLOAT_EXT      = 0x0000000000020000ULL,
1944     PPC_FLOAT_FSQRT    = 0x0000000000040000ULL,
1945     PPC_FLOAT_FRES     = 0x0000000000080000ULL,
1946     PPC_FLOAT_FRSQRTE  = 0x0000000000100000ULL,
1947     PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1948     PPC_FLOAT_FSEL     = 0x0000000000400000ULL,
1949     PPC_FLOAT_STFIWX   = 0x0000000000800000ULL,
1950
1951     /* Vector/SIMD extensions                                                */
1952     /*   Altivec support                                                     */
1953     PPC_ALTIVEC        = 0x0000000001000000ULL,
1954     /*   PowerPC 2.03 SPE extension                                          */
1955     PPC_SPE            = 0x0000000002000000ULL,
1956     /*   PowerPC 2.03 SPE single-precision floating-point extension          */
1957     PPC_SPE_SINGLE     = 0x0000000004000000ULL,
1958     /*   PowerPC 2.03 SPE double-precision floating-point extension          */
1959     PPC_SPE_DOUBLE     = 0x0000000008000000ULL,
1960
1961     /* Optional memory control instructions                                  */
1962     PPC_MEM_TLBIA      = 0x0000000010000000ULL,
1963     PPC_MEM_TLBIE      = 0x0000000020000000ULL,
1964     PPC_MEM_TLBSYNC    = 0x0000000040000000ULL,
1965     /*   sync instruction                                                    */
1966     PPC_MEM_SYNC       = 0x0000000080000000ULL,
1967     /*   eieio instruction                                                   */
1968     PPC_MEM_EIEIO      = 0x0000000100000000ULL,
1969
1970     /* Cache control instructions                                            */
1971     PPC_CACHE          = 0x0000000200000000ULL,
1972     /*   icbi instruction                                                    */
1973     PPC_CACHE_ICBI     = 0x0000000400000000ULL,
1974     /*   dcbz instruction                                                    */
1975     PPC_CACHE_DCBZ     = 0x0000000800000000ULL,
1976     /*   dcba instruction                                                    */
1977     PPC_CACHE_DCBA     = 0x0000002000000000ULL,
1978     /*   Freescale cache locking instructions                                */
1979     PPC_CACHE_LOCK     = 0x0000004000000000ULL,
1980
1981     /* MMU related extensions                                                */
1982     /*   external control instructions                                       */
1983     PPC_EXTERN         = 0x0000010000000000ULL,
1984     /*   segment register access instructions                                */
1985     PPC_SEGMENT        = 0x0000020000000000ULL,
1986     /*   PowerPC 6xx TLB management instructions                             */
1987     PPC_6xx_TLB        = 0x0000040000000000ULL,
1988     /* PowerPC 74xx TLB management instructions                              */
1989     PPC_74xx_TLB       = 0x0000080000000000ULL,
1990     /*   PowerPC 40x TLB management instructions                             */
1991     PPC_40x_TLB        = 0x0000100000000000ULL,
1992     /*   segment register access instructions for PowerPC 64 "bridge"        */
1993     PPC_SEGMENT_64B    = 0x0000200000000000ULL,
1994     /*   SLB management                                                      */
1995     PPC_SLBI           = 0x0000400000000000ULL,
1996
1997     /* Embedded PowerPC dedicated instructions                               */
1998     PPC_WRTEE          = 0x0001000000000000ULL,
1999     /* PowerPC 40x exception model                                           */
2000     PPC_40x_EXCP       = 0x0002000000000000ULL,
2001     /* PowerPC 405 Mac instructions                                          */
2002     PPC_405_MAC        = 0x0004000000000000ULL,
2003     /* PowerPC 440 specific instructions                                     */
2004     PPC_440_SPEC       = 0x0008000000000000ULL,
2005     /* BookE (embedded) PowerPC specification                                */
2006     PPC_BOOKE          = 0x0010000000000000ULL,
2007     /* mfapidi instruction                                                   */
2008     PPC_MFAPIDI        = 0x0020000000000000ULL,
2009     /* tlbiva instruction                                                    */
2010     PPC_TLBIVA         = 0x0040000000000000ULL,
2011     /* tlbivax instruction                                                   */
2012     PPC_TLBIVAX        = 0x0080000000000000ULL,
2013     /* PowerPC 4xx dedicated instructions                                    */
2014     PPC_4xx_COMMON     = 0x0100000000000000ULL,
2015     /* PowerPC 40x ibct instructions                                         */
2016     PPC_40x_ICBT       = 0x0200000000000000ULL,
2017     /* rfmci is not implemented in all BookE PowerPC                         */
2018     PPC_RFMCI          = 0x0400000000000000ULL,
2019     /* rfdi instruction                                                      */
2020     PPC_RFDI           = 0x0800000000000000ULL,
2021     /* DCR accesses                                                          */
2022     PPC_DCR            = 0x1000000000000000ULL,
2023     /* DCR extended accesse                                                  */
2024     PPC_DCRX           = 0x2000000000000000ULL,
2025     /* user-mode DCR access, implemented in PowerPC 460                      */
2026     PPC_DCRUX          = 0x4000000000000000ULL,
2027     /* popcntw and popcntd instructions                                      */
2028     PPC_POPCNTWD       = 0x8000000000000000ULL,
2029
2030 #define PPC_TCG_INSNS  (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2031                         | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2032                         | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2033                         | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2034                         | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2035                         | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2036                         | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2037                         | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2038                         | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2039                         | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2040                         | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2041                         | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2042                         | PPC_CACHE | PPC_CACHE_ICBI \
2043                         | PPC_CACHE_DCBZ \
2044                         | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2045                         | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2046                         | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2047                         | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2048                         | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2049                         | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2050                         | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2051                         | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2052                         | PPC_POPCNTWD | PPC_CILDST)
2053
2054     /* extended type values */
2055
2056     /* BookE 2.06 PowerPC specification                                      */
2057     PPC2_BOOKE206      = 0x0000000000000001ULL,
2058     /* VSX (extensions to Altivec / VMX)                                     */
2059     PPC2_VSX           = 0x0000000000000002ULL,
2060     /* Decimal Floating Point (DFP)                                          */
2061     PPC2_DFP           = 0x0000000000000004ULL,
2062     /* Embedded.Processor Control                                            */
2063     PPC2_PRCNTL        = 0x0000000000000008ULL,
2064     /* Byte-reversed, indexed, double-word load and store                    */
2065     PPC2_DBRX          = 0x0000000000000010ULL,
2066     /* Book I 2.05 PowerPC specification                                     */
2067     PPC2_ISA205        = 0x0000000000000020ULL,
2068     /* VSX additions in ISA 2.07                                             */
2069     PPC2_VSX207        = 0x0000000000000040ULL,
2070     /* ISA 2.06B bpermd                                                      */
2071     PPC2_PERM_ISA206   = 0x0000000000000080ULL,
2072     /* ISA 2.06B divide extended variants                                    */
2073     PPC2_DIVE_ISA206   = 0x0000000000000100ULL,
2074     /* ISA 2.06B larx/stcx. instructions                                     */
2075     PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2076     /* ISA 2.06B floating point integer conversion                           */
2077     PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2078     /* ISA 2.06B floating point test instructions                            */
2079     PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2080     /* ISA 2.07 bctar instruction                                            */
2081     PPC2_BCTAR_ISA207  = 0x0000000000001000ULL,
2082     /* ISA 2.07 load/store quadword                                          */
2083     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
2084     /* ISA 2.07 Altivec                                                      */
2085     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
2086     /* PowerISA 2.07 Book3s specification                                    */
2087     PPC2_ISA207S       = 0x0000000000008000ULL,
2088     /* Double precision floating point conversion for signed integer 64      */
2089     PPC2_FP_CVT_S64    = 0x0000000000010000ULL,
2090     /* Transactional Memory (ISA 2.07, Book II)                              */
2091     PPC2_TM            = 0x0000000000020000ULL,
2092     /* Server PM instructgions (ISA 2.06, Book III)                          */
2093     PPC2_PM_ISA206     = 0x0000000000040000ULL,
2094
2095 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2096                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2097                         PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2098                         PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2099                         PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2100                         PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2101                         PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206)
2102 };
2103
2104 /*****************************************************************************/
2105 /* Memory access type :
2106  * may be needed for precise access rights control and precise exceptions.
2107  */
2108 enum {
2109     /* 1 bit to define user level / supervisor access */
2110     ACCESS_USER  = 0x00,
2111     ACCESS_SUPER = 0x01,
2112     /* Type of instruction that generated the access */
2113     ACCESS_CODE  = 0x10, /* Code fetch access                */
2114     ACCESS_INT   = 0x20, /* Integer load/store access        */
2115     ACCESS_FLOAT = 0x30, /* floating point load/store access */
2116     ACCESS_RES   = 0x40, /* load/store with reservation      */
2117     ACCESS_EXT   = 0x50, /* external access                  */
2118     ACCESS_CACHE = 0x60, /* Cache manipulation               */
2119 };
2120
2121 /* Hardware interruption sources:
2122  * all those exception can be raised simulteaneously
2123  */
2124 /* Input pins definitions */
2125 enum {
2126     /* 6xx bus input pins */
2127     PPC6xx_INPUT_HRESET     = 0,
2128     PPC6xx_INPUT_SRESET     = 1,
2129     PPC6xx_INPUT_CKSTP_IN   = 2,
2130     PPC6xx_INPUT_MCP        = 3,
2131     PPC6xx_INPUT_SMI        = 4,
2132     PPC6xx_INPUT_INT        = 5,
2133     PPC6xx_INPUT_TBEN       = 6,
2134     PPC6xx_INPUT_WAKEUP     = 7,
2135     PPC6xx_INPUT_NB,
2136 };
2137
2138 enum {
2139     /* Embedded PowerPC input pins */
2140     PPCBookE_INPUT_HRESET     = 0,
2141     PPCBookE_INPUT_SRESET     = 1,
2142     PPCBookE_INPUT_CKSTP_IN   = 2,
2143     PPCBookE_INPUT_MCP        = 3,
2144     PPCBookE_INPUT_SMI        = 4,
2145     PPCBookE_INPUT_INT        = 5,
2146     PPCBookE_INPUT_CINT       = 6,
2147     PPCBookE_INPUT_NB,
2148 };
2149
2150 enum {
2151     /* PowerPC E500 input pins */
2152     PPCE500_INPUT_RESET_CORE = 0,
2153     PPCE500_INPUT_MCK        = 1,
2154     PPCE500_INPUT_CINT       = 3,
2155     PPCE500_INPUT_INT        = 4,
2156     PPCE500_INPUT_DEBUG      = 6,
2157     PPCE500_INPUT_NB,
2158 };
2159
2160 enum {
2161     /* PowerPC 40x input pins */
2162     PPC40x_INPUT_RESET_CORE = 0,
2163     PPC40x_INPUT_RESET_CHIP = 1,
2164     PPC40x_INPUT_RESET_SYS  = 2,
2165     PPC40x_INPUT_CINT       = 3,
2166     PPC40x_INPUT_INT        = 4,
2167     PPC40x_INPUT_HALT       = 5,
2168     PPC40x_INPUT_DEBUG      = 6,
2169     PPC40x_INPUT_NB,
2170 };
2171
2172 enum {
2173     /* RCPU input pins */
2174     PPCRCPU_INPUT_PORESET   = 0,
2175     PPCRCPU_INPUT_HRESET    = 1,
2176     PPCRCPU_INPUT_SRESET    = 2,
2177     PPCRCPU_INPUT_IRQ0      = 3,
2178     PPCRCPU_INPUT_IRQ1      = 4,
2179     PPCRCPU_INPUT_IRQ2      = 5,
2180     PPCRCPU_INPUT_IRQ3      = 6,
2181     PPCRCPU_INPUT_IRQ4      = 7,
2182     PPCRCPU_INPUT_IRQ5      = 8,
2183     PPCRCPU_INPUT_IRQ6      = 9,
2184     PPCRCPU_INPUT_IRQ7      = 10,
2185     PPCRCPU_INPUT_NB,
2186 };
2187
2188 #if defined(TARGET_PPC64)
2189 enum {
2190     /* PowerPC 970 input pins */
2191     PPC970_INPUT_HRESET     = 0,
2192     PPC970_INPUT_SRESET     = 1,
2193     PPC970_INPUT_CKSTP      = 2,
2194     PPC970_INPUT_TBEN       = 3,
2195     PPC970_INPUT_MCP        = 4,
2196     PPC970_INPUT_INT        = 5,
2197     PPC970_INPUT_THINT      = 6,
2198     PPC970_INPUT_NB,
2199 };
2200
2201 enum {
2202     /* POWER7 input pins */
2203     POWER7_INPUT_INT        = 0,
2204     /* POWER7 probably has other inputs, but we don't care about them
2205      * for any existing machine.  We can wire these up when we need
2206      * them */
2207     POWER7_INPUT_NB,
2208 };
2209 #endif
2210
2211 /* Hardware exceptions definitions */
2212 enum {
2213     /* External hardware exception sources */
2214     PPC_INTERRUPT_RESET     = 0,  /* Reset exception                      */
2215     PPC_INTERRUPT_WAKEUP,         /* Wakeup exception                     */
2216     PPC_INTERRUPT_MCK,            /* Machine check exception              */
2217     PPC_INTERRUPT_EXT,            /* External interrupt                   */
2218     PPC_INTERRUPT_SMI,            /* System management interrupt          */
2219     PPC_INTERRUPT_CEXT,           /* Critical external interrupt          */
2220     PPC_INTERRUPT_DEBUG,          /* External debug exception             */
2221     PPC_INTERRUPT_THERM,          /* Thermal exception                    */
2222     /* Internal hardware exception sources */
2223     PPC_INTERRUPT_DECR,           /* Decrementer exception                */
2224     PPC_INTERRUPT_HDECR,          /* Hypervisor decrementer exception     */
2225     PPC_INTERRUPT_PIT,            /* Programmable inteval timer interrupt */
2226     PPC_INTERRUPT_FIT,            /* Fixed interval timer interrupt       */
2227     PPC_INTERRUPT_WDT,            /* Watchdog timer interrupt             */
2228     PPC_INTERRUPT_CDOORBELL,      /* Critical doorbell interrupt          */
2229     PPC_INTERRUPT_DOORBELL,       /* Doorbell interrupt                   */
2230     PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */
2231     PPC_INTERRUPT_HMI,            /* Hypervisor Maintainance interrupt    */
2232     PPC_INTERRUPT_HDOORBELL,      /* Hypervisor Doorbell interrupt        */
2233 };
2234
2235 /* Processor Compatibility mask (PCR) */
2236 enum {
2237     PCR_COMPAT_2_05     = 1ull << (63-62),
2238     PCR_COMPAT_2_06     = 1ull << (63-61),
2239     PCR_COMPAT_2_07     = 1ull << (63-60),
2240     PCR_VEC_DIS         = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2241     PCR_VSX_DIS         = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2242     PCR_TM_DIS          = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2243 };
2244
2245 /* HMER/HMEER */
2246 enum {
2247     HMER_MALFUNCTION_ALERT      = 1ull << (63 - 0),
2248     HMER_PROC_RECV_DONE         = 1ull << (63 - 2),
2249     HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2250     HMER_TFAC_ERROR             = 1ull << (63 - 4),
2251     HMER_TFMR_PARITY_ERROR      = 1ull << (63 - 5),
2252     HMER_XSCOM_FAIL             = 1ull << (63 - 8),
2253     HMER_XSCOM_DONE             = 1ull << (63 - 9),
2254     HMER_PROC_RECV_AGAIN        = 1ull << (63 - 11),
2255     HMER_WARN_RISE              = 1ull << (63 - 14),
2256     HMER_WARN_FALL              = 1ull << (63 - 15),
2257     HMER_SCOM_FIR_HMI           = 1ull << (63 - 16),
2258     HMER_TRIG_FIR_HMI           = 1ull << (63 - 17),
2259     HMER_HYP_RESOURCE_ERR       = 1ull << (63 - 20),
2260     HMER_XSCOM_STATUS_MASK      = 7ull << (63 - 23),
2261     HMER_XSCOM_STATUS_LSH       = (63 - 23),
2262 };
2263
2264 /* Alternate Interrupt Location (AIL) */
2265 enum {
2266     AIL_NONE                = 0,
2267     AIL_RESERVED            = 1,
2268     AIL_0001_8000           = 2,
2269     AIL_C000_0000_0000_4000 = 3,
2270 };
2271
2272 /*****************************************************************************/
2273
2274 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2275 {
2276     return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2277 }
2278
2279 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2280 {
2281     env->so = (xer >> XER_SO) & 1;
2282     env->ov = (xer >> XER_OV) & 1;
2283     env->ca = (xer >> XER_CA) & 1;
2284     env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2285 }
2286
2287 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2288                                         target_ulong *cs_base, uint32_t *flags)
2289 {
2290     *pc = env->nip;
2291     *cs_base = 0;
2292     *flags = env->hflags;
2293 }
2294
2295 #if !defined(CONFIG_USER_ONLY)
2296 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2297 {
2298     uintptr_t tlbml = (uintptr_t)tlbm;
2299     uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2300
2301     return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2302 }
2303
2304 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2305 {
2306     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2307     int r = tlbncfg & TLBnCFG_N_ENTRY;
2308     return r;
2309 }
2310
2311 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2312 {
2313     uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2314     int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2315     return r;
2316 }
2317
2318 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2319 {
2320     int id = booke206_tlbm_id(env, tlbm);
2321     int end = 0;
2322     int i;
2323
2324     for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2325         end += booke206_tlb_size(env, i);
2326         if (id < end) {
2327             return i;
2328         }
2329     }
2330
2331     cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2332     return 0;
2333 }
2334
2335 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2336 {
2337     int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2338     int tlbid = booke206_tlbm_id(env, tlb);
2339     return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2340 }
2341
2342 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2343                                               target_ulong ea, int way)
2344 {
2345     int r;
2346     uint32_t ways = booke206_tlb_ways(env, tlbn);
2347     int ways_bits = ctz32(ways);
2348     int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2349     int i;
2350
2351     way &= ways - 1;
2352     ea >>= MAS2_EPN_SHIFT;
2353     ea &= (1 << (tlb_bits - ways_bits)) - 1;
2354     r = (ea << ways_bits) | way;
2355
2356     if (r >= booke206_tlb_size(env, tlbn)) {
2357         return NULL;
2358     }
2359
2360     /* bump up to tlbn index */
2361     for (i = 0; i < tlbn; i++) {
2362         r += booke206_tlb_size(env, i);
2363     }
2364
2365     return &env->tlb.tlbm[r];
2366 }
2367
2368 /* returns bitmap of supported page sizes for a given TLB */
2369 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2370 {
2371     bool mav2 = false;
2372     uint32_t ret = 0;
2373
2374     if (mav2) {
2375         ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2376     } else {
2377         uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2378         uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2379         uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2380         int i;
2381         for (i = min; i <= max; i++) {
2382             ret |= (1 << (i << 1));
2383         }
2384     }
2385
2386     return ret;
2387 }
2388
2389 #endif
2390
2391 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2392 {
2393     if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2394         return msr & (1ULL << MSR_CM);
2395     }
2396
2397     return msr & (1ULL << MSR_SF);
2398 }
2399
2400 /**
2401  * Check whether register rx is in the range between start and
2402  * start + nregs (as needed by the LSWX and LSWI instructions)
2403  */
2404 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2405 {
2406     return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2407            (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2408 }
2409
2410 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2411
2412 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2413
2414 /**
2415  * ppc_get_vcpu_dt_id:
2416  * @cs: a PowerPCCPU struct.
2417  *
2418  * Returns a device-tree ID for a CPU.
2419  */
2420 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2421
2422 /**
2423  * ppc_get_vcpu_by_dt_id:
2424  * @cpu_dt_id: a device tree id
2425  *
2426  * Searches for a CPU by @cpu_dt_id.
2427  *
2428  * Returns: a PowerPCCPU struct
2429  */
2430 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2431
2432 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2433 #endif /* !defined (__CPU_PPC_H__) */