hw/scsi/mptsas.h

   1 #ifndef MPTSAS_H
   2 #define MPTSAS_H
   3
   4 #include "mpi.h"
   5
   6 #define MPTSAS_NUM_PORTS 8
   7 #define MPTSAS_MAX_FRAMES 2048     /* Firmware limit at 65535 */
   8
   9 #define MPTSAS_REQUEST_QUEUE_DEPTH 128
  10 #define MPTSAS_REPLY_QUEUE_DEPTH   128
  11
  12 #define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22
  13
  14 typedef struct MPTSASState MPTSASState;
  15 typedef struct MPTSASRequest MPTSASRequest;
  16
  17 enum {
  18     DOORBELL_NONE,
  19     DOORBELL_WRITE,
  20     DOORBELL_READ
  21 };
  22
  23 struct MPTSASState {
  24     PCIDevice dev;
  25     MemoryRegion mmio_io;
  26     MemoryRegion port_io;
  27     MemoryRegion diag_io;
  28     QEMUBH *request_bh;
  29
  30     /* properties */
  31     OnOffAuto msi;
  32     uint64_t sas_addr;
  33
  34     /* Doorbell register */
  35     uint32_t state;
  36     uint8_t who_init;
  37     uint8_t doorbell_state;
  38
  39     /* Buffer for requests that are sent through the doorbell register.  */
  40     uint32_t doorbell_msg[256];
  41     int doorbell_idx;
  42     int doorbell_cnt;
  43
  44     uint16_t doorbell_reply[256];
  45     int doorbell_reply_idx;
  46     int doorbell_reply_size;
  47
  48     /* Other registers */
  49     uint8_t diagnostic_idx;
  50     uint32_t diagnostic;
  51     uint32_t intr_mask;
  52     uint32_t intr_status;
  53
  54     /* Request queues */
  55     uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1];
  56     uint16_t request_post_head;
  57     uint16_t request_post_tail;
  58
  59     uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1];
  60     uint16_t reply_post_head;
  61     uint16_t reply_post_tail;
  62
  63     uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1];
  64     uint16_t reply_free_head;
  65     uint16_t reply_free_tail;
  66
  67     /* IOC Facts */
  68     hwaddr host_mfa_high_addr;
  69     hwaddr sense_buffer_high_addr;
  70     uint16_t max_devices;
  71     uint16_t max_buses;
  72     uint16_t reply_frame_size;
  73
  74     SCSIBus bus;
  75     QTAILQ_HEAD(, MPTSASRequest) pending;
  76 };
  77
  78 void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req);
  79 void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply);
  80 void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req);
  81 void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply);
  82 void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req);
  83 void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply);
  84 void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req);
  85 void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply);
  86 void mptsas_fix_config_endianness(MPIMsgConfig *req);
  87 void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply);
  88 void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req);
  89 void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply);
  90 void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req);
  91 void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply);
  92 void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req);
  93 void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply);
  94
  95 void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply);
  96
  97 void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req);
  98
  99 #endif /* MPTSAS_H */