hw/arm/fsl-imx25.c

   1 /*
   2  * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
   3  *
   4  * i.MX25 SOC emulation.
   5  *
   6  * Based on hw/arm/xlnx-zynqmp.c
   7  *
   8  * Copyright (C) 2015 Xilinx Inc
   9  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the
  13  *  Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  19  *  for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along
  22  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu-common.h"
  28 #include "cpu.h"
  29 #include "hw/arm/fsl-imx25.h"
  30 #include "sysemu/sysemu.h"
  31 #include "exec/address-spaces.h"
  32 #include "hw/boards.h"
  33 #include "chardev/char.h"
  34
  35 static void fsl_imx25_init(Object *obj)
  36 {
  37     FslIMX25State *s = FSL_IMX25(obj);
  38     int i;
  39
  40     object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
  41
  42     object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC);
  43     qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default());
  44
  45     object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX25_CCM);
  46     qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default());
  47
  48     for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
  49         object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL);
  50         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
  51     }
  52
  53     for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
  54         object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX25_GPT);
  55         qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
  56     }
  57
  58     for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
  59         object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT);
  60         qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default());
  61     }
  62
  63     object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC);
  64     qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default());
  65
  66     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
  67         object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C);
  68         qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default());
  69     }
  70
  71     for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
  72         object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO);
  73         qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default());
  74     }
  75 }
  76
  77 static void fsl_imx25_realize(DeviceState *dev, Error **errp)
  78 {
  79     FslIMX25State *s = FSL_IMX25(dev);
  80     uint8_t i;
  81     Error *err = NULL;
  82
  83     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  84     if (err) {
  85         error_propagate(errp, err);
  86         return;
  87     }
  88
  89     object_property_set_bool(OBJECT(&s->avic), true, "realized", &err);
  90     if (err) {
  91         error_propagate(errp, err);
  92         return;
  93     }
  94     sysbus_mmio_map(SYS_BUS_DEVICE(&s->avic), 0, FSL_IMX25_AVIC_ADDR);
  95     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 0,
  96                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
  97     sysbus_connect_irq(SYS_BUS_DEVICE(&s->avic), 1,
  98                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
  99
 100     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &err);
 101     if (err) {
 102         error_propagate(errp, err);
 103         return;
 104     }
 105     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX25_CCM_ADDR);
 106
 107     /* Initialize all UARTs */
 108     for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) {
 109         static const struct {
 110             hwaddr addr;
 111             unsigned int irq;
 112         } serial_table[FSL_IMX25_NUM_UARTS] = {
 113             { FSL_IMX25_UART1_ADDR, FSL_IMX25_UART1_IRQ },
 114             { FSL_IMX25_UART2_ADDR, FSL_IMX25_UART2_IRQ },
 115             { FSL_IMX25_UART3_ADDR, FSL_IMX25_UART3_IRQ },
 116             { FSL_IMX25_UART4_ADDR, FSL_IMX25_UART4_IRQ },
 117             { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ }
 118         };
 119
 120         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 121
 122         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err);
 123         if (err) {
 124             error_propagate(errp, err);
 125             return;
 126         }
 127         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
 128         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
 129                            qdev_get_gpio_in(DEVICE(&s->avic),
 130                                             serial_table[i].irq));
 131     }
 132
 133     /* Initialize all GPT timers */
 134     for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
 135         static const struct {
 136             hwaddr addr;
 137             unsigned int irq;
 138         } gpt_table[FSL_IMX25_NUM_GPTS] = {
 139             { FSL_IMX25_GPT1_ADDR, FSL_IMX25_GPT1_IRQ },
 140             { FSL_IMX25_GPT2_ADDR, FSL_IMX25_GPT2_IRQ },
 141             { FSL_IMX25_GPT3_ADDR, FSL_IMX25_GPT3_IRQ },
 142             { FSL_IMX25_GPT4_ADDR, FSL_IMX25_GPT4_IRQ }
 143         };
 144
 145         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 146
 147         object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized", &err);
 148         if (err) {
 149             error_propagate(errp, err);
 150             return;
 151         }
 152         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, gpt_table[i].addr);
 153         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
 154                            qdev_get_gpio_in(DEVICE(&s->avic),
 155                                             gpt_table[i].irq));
 156     }
 157
 158     /* Initialize all EPIT timers */
 159     for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) {
 160         static const struct {
 161             hwaddr addr;
 162             unsigned int irq;
 163         } epit_table[FSL_IMX25_NUM_EPITS] = {
 164             { FSL_IMX25_EPIT1_ADDR, FSL_IMX25_EPIT1_IRQ },
 165             { FSL_IMX25_EPIT2_ADDR, FSL_IMX25_EPIT2_IRQ }
 166         };
 167
 168         s->epit[i].ccm = IMX_CCM(&s->ccm);
 169
 170         object_property_set_bool(OBJECT(&s->epit[i]), true, "realized", &err);
 171         if (err) {
 172             error_propagate(errp, err);
 173             return;
 174         }
 175         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
 176         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
 177                            qdev_get_gpio_in(DEVICE(&s->avic),
 178                                             epit_table[i].irq));
 179     }
 180
 181     qdev_set_nic_properties(DEVICE(&s->fec), &nd_table[0]);
 182
 183     object_property_set_bool(OBJECT(&s->fec), true, "realized", &err);
 184     if (err) {
 185         error_propagate(errp, err);
 186         return;
 187     }
 188     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fec), 0, FSL_IMX25_FEC_ADDR);
 189     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fec), 0,
 190                        qdev_get_gpio_in(DEVICE(&s->avic), FSL_IMX25_FEC_IRQ));
 191
 192
 193     /* Initialize all I2C */
 194     for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) {
 195         static const struct {
 196             hwaddr addr;
 197             unsigned int irq;
 198         } i2c_table[FSL_IMX25_NUM_I2CS] = {
 199             { FSL_IMX25_I2C1_ADDR, FSL_IMX25_I2C1_IRQ },
 200             { FSL_IMX25_I2C2_ADDR, FSL_IMX25_I2C2_IRQ },
 201             { FSL_IMX25_I2C3_ADDR, FSL_IMX25_I2C3_IRQ }
 202         };
 203
 204         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized", &err);
 205         if (err) {
 206             error_propagate(errp, err);
 207             return;
 208         }
 209         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
 210         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 211                            qdev_get_gpio_in(DEVICE(&s->avic),
 212                                             i2c_table[i].irq));
 213     }
 214
 215     /* Initialize all GPIOs */
 216     for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) {
 217         static const struct {
 218             hwaddr addr;
 219             unsigned int irq;
 220         } gpio_table[FSL_IMX25_NUM_GPIOS] = {
 221             { FSL_IMX25_GPIO1_ADDR, FSL_IMX25_GPIO1_IRQ },
 222             { FSL_IMX25_GPIO2_ADDR, FSL_IMX25_GPIO2_IRQ },
 223             { FSL_IMX25_GPIO3_ADDR, FSL_IMX25_GPIO3_IRQ },
 224             { FSL_IMX25_GPIO4_ADDR, FSL_IMX25_GPIO4_IRQ }
 225         };
 226
 227         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized", &err);
 228         if (err) {
 229             error_propagate(errp, err);
 230             return;
 231         }
 232         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
 233         /* Connect GPIO IRQ to PIC */
 234         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
 235                            qdev_get_gpio_in(DEVICE(&s->avic),
 236                                             gpio_table[i].irq));
 237     }
 238
 239     /* initialize 2 x 16 KB ROM */
 240     memory_region_init_rom(&s->rom[0], NULL,
 241                            "imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
 242     if (err) {
 243         error_propagate(errp, err);
 244         return;
 245     }
 246     memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR,
 247                                 &s->rom[0]);
 248     memory_region_init_rom(&s->rom[1], NULL,
 249                            "imx25.rom1", FSL_IMX25_ROM1_SIZE, &err);
 250     if (err) {
 251         error_propagate(errp, err);
 252         return;
 253     }
 254     memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR,
 255                                 &s->rom[1]);
 256
 257     /* initialize internal RAM (128 KB) */
 258     memory_region_init_ram(&s->iram, NULL, "imx25.iram", FSL_IMX25_IRAM_SIZE,
 259                            &err);
 260     if (err) {
 261         error_propagate(errp, err);
 262         return;
 263     }
 264     memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR,
 265                                 &s->iram);
 266
 267     /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
 268     memory_region_init_alias(&s->iram_alias, NULL, "imx25.iram_alias",
 269                              &s->iram, 0, FSL_IMX25_IRAM_ALIAS_SIZE);
 270     memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR,
 271                                 &s->iram_alias);
 272 }
 273
 274 static void fsl_imx25_class_init(ObjectClass *oc, void *data)
 275 {
 276     DeviceClass *dc = DEVICE_CLASS(oc);
 277
 278     dc->realize = fsl_imx25_realize;
 279     dc->desc = "i.MX25 SOC";
 280     /*
 281      * Reason: uses serial_hd in realize and the imx25 board does not
 282      * support multiple CPUs
 283      */
 284     dc->user_creatable = false;
 285 }
 286
 287 static const TypeInfo fsl_imx25_type_info = {
 288     .name = TYPE_FSL_IMX25,
 289     .parent = TYPE_DEVICE,
 290     .instance_size = sizeof(FslIMX25State),
 291     .instance_init = fsl_imx25_init,
 292     .class_init = fsl_imx25_class_init,
 293 };
 294
 295 static void fsl_imx25_register_types(void)
 296 {
 297     type_register_static(&fsl_imx25_type_info);
 298 }
 299
 300 type_init(fsl_imx25_register_types)