hw/arm/aspeed_soc.c

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  * Jeremy Kerr <jk@ozlabs.org>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "qemu-common.h"
  16 #include "cpu.h"
  17 #include "exec/address-spaces.h"
  18 #include "hw/arm/aspeed_soc.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "hw/i2c/aspeed_i2c.h"
  22
  23 #define ASPEED_SOC_UART_5_BASE      0x00184000
  24 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
  25 #define ASPEED_SOC_IOMEM_BASE       0x1E600000
  26 #define ASPEED_SOC_FMC_BASE         0x1E620000
  27 #define ASPEED_SOC_SPI_BASE         0x1E630000
  28 #define ASPEED_SOC_SPI2_BASE        0x1E631000
  29 #define ASPEED_SOC_VIC_BASE         0x1E6C0000
  30 #define ASPEED_SOC_SDMC_BASE        0x1E6E0000
  31 #define ASPEED_SOC_SCU_BASE         0x1E6E2000
  32 #define ASPEED_SOC_SRAM_BASE        0x1E720000
  33 #define ASPEED_SOC_TIMER_BASE       0x1E782000
  34 #define ASPEED_SOC_I2C_BASE         0x1E78A000
  35
  36 static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
  37 static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
  38
  39 #define AST2400_SDRAM_BASE       0x40000000
  40 #define AST2500_SDRAM_BASE       0x80000000
  41
  42 static const hwaddr aspeed_soc_ast2400_spi_bases[] = { ASPEED_SOC_SPI_BASE };
  43 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
  44
  45 static const hwaddr aspeed_soc_ast2500_spi_bases[] = { ASPEED_SOC_SPI_BASE,
  46                                                        ASPEED_SOC_SPI2_BASE};
  47 static const char *aspeed_soc_ast2500_typenames[] = {
  48     "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
  49
  50 static const AspeedSoCInfo aspeed_socs[] = {
  51     {
  52         .name         = "ast2400-a0",
  53         .cpu_model    = "arm926",
  54         .silicon_rev  = AST2400_A0_SILICON_REV,
  55         .sdram_base   = AST2400_SDRAM_BASE,
  56         .sram_size    = 0x8000,
  57         .spis_num     = 1,
  58         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  59         .fmc_typename = "aspeed.smc.fmc",
  60         .spi_typename = aspeed_soc_ast2400_typenames,
  61     }, {
  62         .name         = "ast2400-a1",
  63         .cpu_model    = "arm926",
  64         .silicon_rev  = AST2400_A1_SILICON_REV,
  65         .sdram_base   = AST2400_SDRAM_BASE,
  66         .sram_size    = 0x8000,
  67         .spis_num     = 1,
  68         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  69         .fmc_typename = "aspeed.smc.fmc",
  70         .spi_typename = aspeed_soc_ast2400_typenames,
  71     }, {
  72         .name         = "ast2400",
  73         .cpu_model    = "arm926",
  74         .silicon_rev  = AST2400_A0_SILICON_REV,
  75         .sdram_base   = AST2400_SDRAM_BASE,
  76         .sram_size    = 0x8000,
  77         .spis_num     = 1,
  78         .spi_bases    = aspeed_soc_ast2400_spi_bases,
  79         .fmc_typename = "aspeed.smc.fmc",
  80         .spi_typename = aspeed_soc_ast2400_typenames,
  81     }, {
  82         .name         = "ast2500-a1",
  83         .cpu_model    = "arm1176",
  84         .silicon_rev  = AST2500_A1_SILICON_REV,
  85         .sdram_base   = AST2500_SDRAM_BASE,
  86         .sram_size    = 0x9000,
  87         .spis_num     = 2,
  88         .spi_bases    = aspeed_soc_ast2500_spi_bases,
  89         .fmc_typename = "aspeed.smc.ast2500-fmc",
  90         .spi_typename = aspeed_soc_ast2500_typenames,
  91     },
  92 };
  93
  94 /*
  95  * IO handlers: simply catch any reads/writes to IO addresses that aren't
  96  * handled by a device mapping.
  97  */
  98
  99 static uint64_t aspeed_soc_io_read(void *p, hwaddr offset, unsigned size)
 100 {
 101     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
 102                   __func__, offset, size);
 103     return 0;
 104 }
 105
 106 static void aspeed_soc_io_write(void *opaque, hwaddr offset, uint64_t value,
 107                 unsigned size)
 108 {
 109     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
 110                   __func__, offset, value, size);
 111 }
 112
 113 static const MemoryRegionOps aspeed_soc_io_ops = {
 114     .read = aspeed_soc_io_read,
 115     .write = aspeed_soc_io_write,
 116     .endianness = DEVICE_LITTLE_ENDIAN,
 117 };
 118
 119 static void aspeed_soc_init(Object *obj)
 120 {
 121     AspeedSoCState *s = ASPEED_SOC(obj);
 122     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 123     char *cpu_typename;
 124     int i;
 125
 126     cpu_typename = g_strdup_printf("%s-" TYPE_ARM_CPU, sc->info->cpu_model);
 127     object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);
 128     object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL);
 129     g_free(cpu_typename);
 130
 131     object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);
 132     object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL);
 133     qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default());
 134
 135     object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
 136     object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL);
 137     qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default());
 138
 139     object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
 140     object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
 141     qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
 142
 143     object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
 144     object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
 145     qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
 146     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
 147                          sc->info->silicon_rev);
 148     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
 149                               "hw-strap1", &error_abort);
 150     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
 151                               "hw-strap2", &error_abort);
 152
 153     object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename);
 154     object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL);
 155     qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default());
 156     object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
 157                               &error_abort);
 158
 159     for (i = 0; i < sc->info->spis_num; i++) {
 160         object_initialize(&s->spi[i], sizeof(s->spi[i]),
 161                           sc->info->spi_typename[i]);
 162         object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL);
 163         qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
 164     }
 165
 166     object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC);
 167     object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL);
 168     qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
 169     qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
 170                          sc->info->silicon_rev);
 171     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
 172                               "ram-size", &error_abort);
 173 }
 174
 175 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 176 {
 177     int i;
 178     AspeedSoCState *s = ASPEED_SOC(dev);
 179     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 180     Error *err = NULL, *local_err = NULL;
 181
 182     /* IO space */
 183     memory_region_init_io(&s->iomem, NULL, &aspeed_soc_io_ops, NULL,
 184             "aspeed_soc.io", ASPEED_SOC_IOMEM_SIZE);
 185     memory_region_add_subregion_overlap(get_system_memory(),
 186                                         ASPEED_SOC_IOMEM_BASE, &s->iomem, -1);
 187
 188     /* CPU */
 189     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
 190     if (err) {
 191         error_propagate(errp, err);
 192         return;
 193     }
 194
 195     /* SRAM */
 196     memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
 197                            sc->info->sram_size, &err);
 198     if (err) {
 199         error_propagate(errp, err);
 200         return;
 201     }
 202     vmstate_register_ram_global(&s->sram);
 203     memory_region_add_subregion(get_system_memory(), ASPEED_SOC_SRAM_BASE,
 204                                 &s->sram);
 205
 206     /* VIC */
 207     object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
 208     if (err) {
 209         error_propagate(errp, err);
 210         return;
 211     }
 212     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, ASPEED_SOC_VIC_BASE);
 213     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 214                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 215     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 216                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 217
 218     /* Timer */
 219     object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
 220     if (err) {
 221         error_propagate(errp, err);
 222         return;
 223     }
 224     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0, ASPEED_SOC_TIMER_BASE);
 225     for (i = 0; i < ARRAY_SIZE(timer_irqs); i++) {
 226         qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->vic), timer_irqs[i]);
 227         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 228     }
 229
 230     /* SCU */
 231     object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
 232     if (err) {
 233         error_propagate(errp, err);
 234         return;
 235     }
 236     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE);
 237
 238     /* UART - attach an 8250 to the IO space as our UART5 */
 239     if (serial_hds[0]) {
 240         qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
 241         serial_mm_init(&s->iomem, ASPEED_SOC_UART_5_BASE, 2,
 242                        uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN);
 243     }
 244
 245     /* I2C */
 246     object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
 247     if (err) {
 248         error_propagate(errp, err);
 249         return;
 250     }
 251     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, ASPEED_SOC_I2C_BASE);
 252     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 253                        qdev_get_gpio_in(DEVICE(&s->vic), 12));
 254
 255     /* FMC, The number of CS is set at the board level */
 256     object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
 257     if (err) {
 258         error_propagate(errp, err);
 259         return;
 260     }
 261     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, ASPEED_SOC_FMC_BASE);
 262     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
 263                     s->fmc.ctrl->flash_window_base);
 264     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
 265                        qdev_get_gpio_in(DEVICE(&s->vic), 19));
 266
 267     /* SPI */
 268     for (i = 0; i < sc->info->spis_num; i++) {
 269         object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
 270         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 271                                  &local_err);
 272         error_propagate(&err, local_err);
 273         if (err) {
 274             error_propagate(errp, err);
 275             return;
 276         }
 277         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sc->info->spi_bases[i]);
 278         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
 279                         s->spi[i].ctrl->flash_window_base);
 280     }
 281
 282     /* SDMC - SDRAM Memory Controller */
 283     object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
 284     if (err) {
 285         error_propagate(errp, err);
 286         return;
 287     }
 288     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
 289 }
 290
 291 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 292 {
 293     DeviceClass *dc = DEVICE_CLASS(oc);
 294     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 295
 296     sc->info = (AspeedSoCInfo *) data;
 297     dc->realize = aspeed_soc_realize;
 298 }
 299
 300 static const TypeInfo aspeed_soc_type_info = {
 301     .name           = TYPE_ASPEED_SOC,
 302     .parent         = TYPE_DEVICE,
 303     .instance_init  = aspeed_soc_init,
 304     .instance_size  = sizeof(AspeedSoCState),
 305     .class_size     = sizeof(AspeedSoCClass),
 306     .abstract       = true,
 307 };
 308
 309 static void aspeed_soc_register_types(void)
 310 {
 311     int i;
 312
 313     type_register_static(&aspeed_soc_type_info);
 314     for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
 315         TypeInfo ti = {
 316             .name       = aspeed_socs[i].name,
 317             .parent     = TYPE_ASPEED_SOC,
 318             .class_init = aspeed_soc_class_init,
 319             .class_data = (void *) &aspeed_socs[i],
 320         };
 321         type_register(&ti);
 322     }
 323 }
 324
 325 type_init(aspeed_soc_register_types)