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Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
[qemu/ar7.git] / target-i386 / kvm.c
blob9697e16fddc3393d10d304fb6f2f68c3a26f924c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38 #include "hw/i386/intel_iommu.h"
39 #include "hw/i386/x86-iommu.h"
40
41 #include "exec/ioport.h"
42 #include "standard-headers/asm-x86/hyperv.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "migration/migration.h"
46 #include "exec/memattrs.h"
47 #include "trace.h"
48
49 //#define DEBUG_KVM
50
51 #ifdef DEBUG_KVM
52 #define DPRINTF(fmt, ...) \
53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54 #else
55 #define DPRINTF(fmt, ...) \
56 do { } while (0)
57 #endif
58
59 #define MSR_KVM_WALL_CLOCK 0x11
60 #define MSR_KVM_SYSTEM_TIME 0x12
61
62 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64 #define MSR_BUF_SIZE 4096
65
66 #ifndef BUS_MCEERR_AR
67 #define BUS_MCEERR_AR 4
68 #endif
69 #ifndef BUS_MCEERR_AO
70 #define BUS_MCEERR_AO 5
71 #endif
72
73 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR),
75 KVM_CAP_INFO(EXT_CPUID),
76 KVM_CAP_INFO(MP_STATE),
77 KVM_CAP_LAST_INFO
78 };
79
80 static bool has_msr_star;
81 static bool has_msr_hsave_pa;
82 static bool has_msr_tsc_aux;
83 static bool has_msr_tsc_adjust;
84 static bool has_msr_tsc_deadline;
85 static bool has_msr_feature_control;
86 static bool has_msr_async_pf_en;
87 static bool has_msr_pv_eoi_en;
88 static bool has_msr_misc_enable;
89 static bool has_msr_smbase;
90 static bool has_msr_bndcfgs;
91 static bool has_msr_kvm_steal_time;
92 static int lm_capable_kernel;
93 static bool has_msr_hv_hypercall;
94 static bool has_msr_hv_vapic;
95 static bool has_msr_hv_tsc;
96 static bool has_msr_hv_crash;
97 static bool has_msr_hv_reset;
98 static bool has_msr_hv_vpindex;
99 static bool has_msr_hv_runtime;
100 static bool has_msr_hv_synic;
101 static bool has_msr_hv_stimer;
102 static bool has_msr_mtrr;
103 static bool has_msr_xss;
104
105 static bool has_msr_architectural_pmu;
106 static uint32_t num_architectural_pmu_counters;
107
108 static int has_xsave;
109 static int has_xcrs;
110 static int has_pit_state2;
111
112 static bool has_msr_mcg_ext_ctl;
113
114 static struct kvm_cpuid2 *cpuid_cache;
115
116 int kvm_has_pit_state2(void)
117 {
118 return has_pit_state2;
119 }
120
121 bool kvm_has_smm(void)
122 {
123 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
124 }
125
126 bool kvm_allows_irq0_override(void)
127 {
128 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
129 }
130
131 static int kvm_get_tsc(CPUState *cs)
132 {
133 X86CPU *cpu = X86_CPU(cs);
134 CPUX86State *env = &cpu->env;
135 struct {
136 struct kvm_msrs info;
137 struct kvm_msr_entry entries[1];
138 } msr_data;
139 int ret;
140
141 if (env->tsc_valid) {
142 return 0;
143 }
144
145 msr_data.info.nmsrs = 1;
146 msr_data.entries[0].index = MSR_IA32_TSC;
147 env->tsc_valid = !runstate_is_running();
148
149 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
150 if (ret < 0) {
151 return ret;
152 }
153
154 assert(ret == 1);
155 env->tsc = msr_data.entries[0].data;
156 return 0;
157 }
158
159 static inline void do_kvm_synchronize_tsc(void *arg)
160 {
161 CPUState *cpu = arg;
162
163 kvm_get_tsc(cpu);
164 }
165
166 void kvm_synchronize_all_tsc(void)
167 {
168 CPUState *cpu;
169
170 if (kvm_enabled()) {
171 CPU_FOREACH(cpu) {
172 run_on_cpu(cpu, do_kvm_synchronize_tsc, cpu);
173 }
174 }
175 }
176
177 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
178 {
179 struct kvm_cpuid2 *cpuid;
180 int r, size;
181
182 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
183 cpuid = g_malloc0(size);
184 cpuid->nent = max;
185 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
186 if (r == 0 && cpuid->nent >= max) {
187 r = -E2BIG;
188 }
189 if (r < 0) {
190 if (r == -E2BIG) {
191 g_free(cpuid);
192 return NULL;
193 } else {
194 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
195 strerror(-r));
196 exit(1);
197 }
198 }
199 return cpuid;
200 }
201
202 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
203 * for all entries.
204 */
205 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
206 {
207 struct kvm_cpuid2 *cpuid;
208 int max = 1;
209
210 if (cpuid_cache != NULL) {
211 return cpuid_cache;
212 }
213 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
214 max *= 2;
215 }
216 cpuid_cache = cpuid;
217 return cpuid;
218 }
219
220 static const struct kvm_para_features {
221 int cap;
222 int feature;
223 } para_features[] = {
224 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
225 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
226 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
227 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
228 };
229
230 static int get_para_features(KVMState *s)
231 {
232 int i, features = 0;
233
234 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
235 if (kvm_check_extension(s, para_features[i].cap)) {
236 features |= (1 << para_features[i].feature);
237 }
238 }
239
240 return features;
241 }
242
243
244 /* Returns the value for a specific register on the cpuid entry
245 */
246 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
247 {
248 uint32_t ret = 0;
249 switch (reg) {
250 case R_EAX:
251 ret = entry->eax;
252 break;
253 case R_EBX:
254 ret = entry->ebx;
255 break;
256 case R_ECX:
257 ret = entry->ecx;
258 break;
259 case R_EDX:
260 ret = entry->edx;
261 break;
262 }
263 return ret;
264 }
265
266 /* Find matching entry for function/index on kvm_cpuid2 struct
267 */
268 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
269 uint32_t function,
270 uint32_t index)
271 {
272 int i;
273 for (i = 0; i < cpuid->nent; ++i) {
274 if (cpuid->entries[i].function == function &&
275 cpuid->entries[i].index == index) {
276 return &cpuid->entries[i];
277 }
278 }
279 /* not found: */
280 return NULL;
281 }
282
283 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
284 uint32_t index, int reg)
285 {
286 struct kvm_cpuid2 *cpuid;
287 uint32_t ret = 0;
288 uint32_t cpuid_1_edx;
289 bool found = false;
290
291 cpuid = get_supported_cpuid(s);
292
293 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
294 if (entry) {
295 found = true;
296 ret = cpuid_entry_get_reg(entry, reg);
297 }
298
299 /* Fixups for the data returned by KVM, below */
300
301 if (function == 1 && reg == R_EDX) {
302 /* KVM before 2.6.30 misreports the following features */
303 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
304 } else if (function == 1 && reg == R_ECX) {
305 /* We can set the hypervisor flag, even if KVM does not return it on
306 * GET_SUPPORTED_CPUID
307 */
308 ret |= CPUID_EXT_HYPERVISOR;
309 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
310 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
311 * and the irqchip is in the kernel.
312 */
313 if (kvm_irqchip_in_kernel() &&
314 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
315 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
316 }
317
318 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
319 * without the in-kernel irqchip
320 */
321 if (!kvm_irqchip_in_kernel()) {
322 ret &= ~CPUID_EXT_X2APIC;
323 }
324 } else if (function == 6 && reg == R_EAX) {
325 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
326 } else if (function == 0x80000001 && reg == R_EDX) {
327 /* On Intel, kvm returns cpuid according to the Intel spec,
328 * so add missing bits according to the AMD spec:
329 */
330 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
331 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
332 }
333
334 /* fallback for older kernels */
335 if ((function == KVM_CPUID_FEATURES) && !found) {
336 ret = get_para_features(s);
337 }
338
339 return ret;
340 }
341
342 typedef struct HWPoisonPage {
343 ram_addr_t ram_addr;
344 QLIST_ENTRY(HWPoisonPage) list;
345 } HWPoisonPage;
346
347 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
348 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
349
350 static void kvm_unpoison_all(void *param)
351 {
352 HWPoisonPage *page, *next_page;
353
354 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
355 QLIST_REMOVE(page, list);
356 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
357 g_free(page);
358 }
359 }
360
361 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
362 {
363 HWPoisonPage *page;
364
365 QLIST_FOREACH(page, &hwpoison_page_list, list) {
366 if (page->ram_addr == ram_addr) {
367 return;
368 }
369 }
370 page = g_new(HWPoisonPage, 1);
371 page->ram_addr = ram_addr;
372 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
373 }
374
375 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
376 int *max_banks)
377 {
378 int r;
379
380 r = kvm_check_extension(s, KVM_CAP_MCE);
381 if (r > 0) {
382 *max_banks = r;
383 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
384 }
385 return -ENOSYS;
386 }
387
388 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
389 {
390 CPUState *cs = CPU(cpu);
391 CPUX86State *env = &cpu->env;
392 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
393 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
394 uint64_t mcg_status = MCG_STATUS_MCIP;
395 int flags = 0;
396
397 if (code == BUS_MCEERR_AR) {
398 status |= MCI_STATUS_AR | 0x134;
399 mcg_status |= MCG_STATUS_EIPV;
400 } else {
401 status |= 0xc0;
402 mcg_status |= MCG_STATUS_RIPV;
403 }
404
405 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
406 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
407 * guest kernel back into env->mcg_ext_ctl.
408 */
409 cpu_synchronize_state(cs);
410 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
411 mcg_status |= MCG_STATUS_LMCE;
412 flags = 0;
413 }
414
415 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
416 (MCM_ADDR_PHYS << 6) | 0xc, flags);
417 }
418
419 static void hardware_memory_error(void)
420 {
421 fprintf(stderr, "Hardware memory error!\n");
422 exit(1);
423 }
424
425 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
426 {
427 X86CPU *cpu = X86_CPU(c);
428 CPUX86State *env = &cpu->env;
429 ram_addr_t ram_addr;
430 hwaddr paddr;
431
432 if ((env->mcg_cap & MCG_SER_P) && addr
433 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
434 ram_addr = qemu_ram_addr_from_host(addr);
435 if (ram_addr == RAM_ADDR_INVALID ||
436 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
437 fprintf(stderr, "Hardware memory error for memory used by "
438 "QEMU itself instead of guest system!\n");
439 /* Hope we are lucky for AO MCE */
440 if (code == BUS_MCEERR_AO) {
441 return 0;
442 } else {
443 hardware_memory_error();
444 }
445 }
446 kvm_hwpoison_page_add(ram_addr);
447 kvm_mce_inject(cpu, paddr, code);
448 } else {
449 if (code == BUS_MCEERR_AO) {
450 return 0;
451 } else if (code == BUS_MCEERR_AR) {
452 hardware_memory_error();
453 } else {
454 return 1;
455 }
456 }
457 return 0;
458 }
459
460 int kvm_arch_on_sigbus(int code, void *addr)
461 {
462 X86CPU *cpu = X86_CPU(first_cpu);
463
464 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
465 ram_addr_t ram_addr;
466 hwaddr paddr;
467
468 /* Hope we are lucky for AO MCE */
469 ram_addr = qemu_ram_addr_from_host(addr);
470 if (ram_addr == RAM_ADDR_INVALID ||
471 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
472 addr, &paddr)) {
473 fprintf(stderr, "Hardware memory error for memory used by "
474 "QEMU itself instead of guest system!: %p\n", addr);
475 return 0;
476 }
477 kvm_hwpoison_page_add(ram_addr);
478 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
479 } else {
480 if (code == BUS_MCEERR_AO) {
481 return 0;
482 } else if (code == BUS_MCEERR_AR) {
483 hardware_memory_error();
484 } else {
485 return 1;
486 }
487 }
488 return 0;
489 }
490
491 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
492 {
493 CPUX86State *env = &cpu->env;
494
495 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
496 unsigned int bank, bank_num = env->mcg_cap & 0xff;
497 struct kvm_x86_mce mce;
498
499 env->exception_injected = -1;
500
501 /*
502 * There must be at least one bank in use if an MCE is pending.
503 * Find it and use its values for the event injection.
504 */
505 for (bank = 0; bank < bank_num; bank++) {
506 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
507 break;
508 }
509 }
510 assert(bank < bank_num);
511
512 mce.bank = bank;
513 mce.status = env->mce_banks[bank * 4 + 1];
514 mce.mcg_status = env->mcg_status;
515 mce.addr = env->mce_banks[bank * 4 + 2];
516 mce.misc = env->mce_banks[bank * 4 + 3];
517
518 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
519 }
520 return 0;
521 }
522
523 static void cpu_update_state(void *opaque, int running, RunState state)
524 {
525 CPUX86State *env = opaque;
526
527 if (running) {
528 env->tsc_valid = false;
529 }
530 }
531
532 unsigned long kvm_arch_vcpu_id(CPUState *cs)
533 {
534 X86CPU *cpu = X86_CPU(cs);
535 return cpu->apic_id;
536 }
537
538 #ifndef KVM_CPUID_SIGNATURE_NEXT
539 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
540 #endif
541
542 static bool hyperv_hypercall_available(X86CPU *cpu)
543 {
544 return cpu->hyperv_vapic ||
545 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
546 }
547
548 static bool hyperv_enabled(X86CPU *cpu)
549 {
550 CPUState *cs = CPU(cpu);
551 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
552 (hyperv_hypercall_available(cpu) ||
553 cpu->hyperv_time ||
554 cpu->hyperv_relaxed_timing ||
555 cpu->hyperv_crash ||
556 cpu->hyperv_reset ||
557 cpu->hyperv_vpindex ||
558 cpu->hyperv_runtime ||
559 cpu->hyperv_synic ||
560 cpu->hyperv_stimer);
561 }
562
563 static int kvm_arch_set_tsc_khz(CPUState *cs)
564 {
565 X86CPU *cpu = X86_CPU(cs);
566 CPUX86State *env = &cpu->env;
567 int r;
568
569 if (!env->tsc_khz) {
570 return 0;
571 }
572
573 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
574 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
575 -ENOTSUP;
576 if (r < 0) {
577 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
578 * TSC frequency doesn't match the one we want.
579 */
580 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
581 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
582 -ENOTSUP;
583 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
584 error_report("warning: TSC frequency mismatch between "
585 "VM (%" PRId64 " kHz) and host (%d kHz), "
586 "and TSC scaling unavailable",
587 env->tsc_khz, cur_freq);
588 return r;
589 }
590 }
591
592 return 0;
593 }
594
595 static int hyperv_handle_properties(CPUState *cs)
596 {
597 X86CPU *cpu = X86_CPU(cs);
598 CPUX86State *env = &cpu->env;
599
600 if (cpu->hyperv_relaxed_timing) {
601 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
602 }
603 if (cpu->hyperv_vapic) {
604 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
605 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
606 has_msr_hv_vapic = true;
607 }
608 if (cpu->hyperv_time &&
609 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
610 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
611 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
612 env->features[FEAT_HYPERV_EAX] |= 0x200;
613 has_msr_hv_tsc = true;
614 }
615 if (cpu->hyperv_crash && has_msr_hv_crash) {
616 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
617 }
618 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
619 if (cpu->hyperv_reset && has_msr_hv_reset) {
620 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
621 }
622 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
623 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
624 }
625 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
626 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
627 }
628 if (cpu->hyperv_synic) {
629 int sint;
630
631 if (!has_msr_hv_synic ||
632 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
633 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
634 return -ENOSYS;
635 }
636
637 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
638 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
639 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
640 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
641 }
642 }
643 if (cpu->hyperv_stimer) {
644 if (!has_msr_hv_stimer) {
645 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
646 return -ENOSYS;
647 }
648 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
649 }
650 return 0;
651 }
652
653 static Error *invtsc_mig_blocker;
654
655 #define KVM_MAX_CPUID_ENTRIES 100
656
657 int kvm_arch_init_vcpu(CPUState *cs)
658 {
659 struct {
660 struct kvm_cpuid2 cpuid;
661 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
662 } QEMU_PACKED cpuid_data;
663 X86CPU *cpu = X86_CPU(cs);
664 CPUX86State *env = &cpu->env;
665 uint32_t limit, i, j, cpuid_i;
666 uint32_t unused;
667 struct kvm_cpuid_entry2 *c;
668 uint32_t signature[3];
669 int kvm_base = KVM_CPUID_SIGNATURE;
670 int r;
671
672 memset(&cpuid_data, 0, sizeof(cpuid_data));
673
674 cpuid_i = 0;
675
676 /* Paravirtualization CPUIDs */
677 if (hyperv_enabled(cpu)) {
678 c = &cpuid_data.entries[cpuid_i++];
679 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
680 if (!cpu->hyperv_vendor_id) {
681 memcpy(signature, "Microsoft Hv", 12);
682 } else {
683 size_t len = strlen(cpu->hyperv_vendor_id);
684
685 if (len > 12) {
686 error_report("hv-vendor-id truncated to 12 characters");
687 len = 12;
688 }
689 memset(signature, 0, 12);
690 memcpy(signature, cpu->hyperv_vendor_id, len);
691 }
692 c->eax = HYPERV_CPUID_MIN;
693 c->ebx = signature[0];
694 c->ecx = signature[1];
695 c->edx = signature[2];
696
697 c = &cpuid_data.entries[cpuid_i++];
698 c->function = HYPERV_CPUID_INTERFACE;
699 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
700 c->eax = signature[0];
701 c->ebx = 0;
702 c->ecx = 0;
703 c->edx = 0;
704
705 c = &cpuid_data.entries[cpuid_i++];
706 c->function = HYPERV_CPUID_VERSION;
707 c->eax = 0x00001bbc;
708 c->ebx = 0x00060001;
709
710 c = &cpuid_data.entries[cpuid_i++];
711 c->function = HYPERV_CPUID_FEATURES;
712 r = hyperv_handle_properties(cs);
713 if (r) {
714 return r;
715 }
716 c->eax = env->features[FEAT_HYPERV_EAX];
717 c->ebx = env->features[FEAT_HYPERV_EBX];
718 c->edx = env->features[FEAT_HYPERV_EDX];
719
720 c = &cpuid_data.entries[cpuid_i++];
721 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
722 if (cpu->hyperv_relaxed_timing) {
723 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
724 }
725 if (has_msr_hv_vapic) {
726 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
727 }
728 c->ebx = cpu->hyperv_spinlock_attempts;
729
730 c = &cpuid_data.entries[cpuid_i++];
731 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
732 c->eax = 0x40;
733 c->ebx = 0x40;
734
735 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
736 has_msr_hv_hypercall = true;
737 }
738
739 if (cpu->expose_kvm) {
740 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
741 c = &cpuid_data.entries[cpuid_i++];
742 c->function = KVM_CPUID_SIGNATURE | kvm_base;
743 c->eax = KVM_CPUID_FEATURES | kvm_base;
744 c->ebx = signature[0];
745 c->ecx = signature[1];
746 c->edx = signature[2];
747
748 c = &cpuid_data.entries[cpuid_i++];
749 c->function = KVM_CPUID_FEATURES | kvm_base;
750 c->eax = env->features[FEAT_KVM];
751
752 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
753
754 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
755
756 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
757 }
758
759 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
760
761 for (i = 0; i <= limit; i++) {
762 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
763 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
764 abort();
765 }
766 c = &cpuid_data.entries[cpuid_i++];
767
768 switch (i) {
769 case 2: {
770 /* Keep reading function 2 till all the input is received */
771 int times;
772
773 c->function = i;
774 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
775 KVM_CPUID_FLAG_STATE_READ_NEXT;
776 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
777 times = c->eax & 0xff;
778
779 for (j = 1; j < times; ++j) {
780 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
781 fprintf(stderr, "cpuid_data is full, no space for "
782 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
783 abort();
784 }
785 c = &cpuid_data.entries[cpuid_i++];
786 c->function = i;
787 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
788 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
789 }
790 break;
791 }
792 case 4:
793 case 0xb:
794 case 0xd:
795 for (j = 0; ; j++) {
796 if (i == 0xd && j == 64) {
797 break;
798 }
799 c->function = i;
800 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
801 c->index = j;
802 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
803
804 if (i == 4 && c->eax == 0) {
805 break;
806 }
807 if (i == 0xb && !(c->ecx & 0xff00)) {
808 break;
809 }
810 if (i == 0xd && c->eax == 0) {
811 continue;
812 }
813 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
814 fprintf(stderr, "cpuid_data is full, no space for "
815 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
816 abort();
817 }
818 c = &cpuid_data.entries[cpuid_i++];
819 }
820 break;
821 default:
822 c->function = i;
823 c->flags = 0;
824 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
825 break;
826 }
827 }
828
829 if (limit >= 0x0a) {
830 uint32_t ver;
831
832 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
833 if ((ver & 0xff) > 0) {
834 has_msr_architectural_pmu = true;
835 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
836
837 /* Shouldn't be more than 32, since that's the number of bits
838 * available in EBX to tell us _which_ counters are available.
839 * Play it safe.
840 */
841 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
842 num_architectural_pmu_counters = MAX_GP_COUNTERS;
843 }
844 }
845 }
846
847 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
848
849 for (i = 0x80000000; i <= limit; i++) {
850 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
851 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
852 abort();
853 }
854 c = &cpuid_data.entries[cpuid_i++];
855
856 c->function = i;
857 c->flags = 0;
858 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
859 }
860
861 /* Call Centaur's CPUID instructions they are supported. */
862 if (env->cpuid_xlevel2 > 0) {
863 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
864
865 for (i = 0xC0000000; i <= limit; i++) {
866 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
867 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
868 abort();
869 }
870 c = &cpuid_data.entries[cpuid_i++];
871
872 c->function = i;
873 c->flags = 0;
874 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
875 }
876 }
877
878 cpuid_data.cpuid.nent = cpuid_i;
879
880 if (((env->cpuid_version >> 8)&0xF) >= 6
881 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
882 (CPUID_MCE | CPUID_MCA)
883 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
884 uint64_t mcg_cap, unsupported_caps;
885 int banks;
886 int ret;
887
888 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
889 if (ret < 0) {
890 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
891 return ret;
892 }
893
894 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
895 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
896 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
897 return -ENOTSUP;
898 }
899
900 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
901 if (unsupported_caps) {
902 if (unsupported_caps & MCG_LMCE_P) {
903 error_report("kvm: LMCE not supported");
904 return -ENOTSUP;
905 }
906 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
907 unsupported_caps);
908 }
909
910 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
911 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
912 if (ret < 0) {
913 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
914 return ret;
915 }
916 }
917
918 qemu_add_vm_change_state_handler(cpu_update_state, env);
919
920 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
921 if (c) {
922 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
923 !!(c->ecx & CPUID_EXT_SMX);
924 }
925
926 if (env->mcg_cap & MCG_LMCE_P) {
927 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
928 }
929
930 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
931 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
932 /* for migration */
933 error_setg(&invtsc_mig_blocker,
934 "State blocked by non-migratable CPU device"
935 " (invtsc flag)");
936 migrate_add_blocker(invtsc_mig_blocker);
937 /* for savevm */
938 vmstate_x86_cpu.unmigratable = 1;
939 }
940
941 cpuid_data.cpuid.padding = 0;
942 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
943 if (r) {
944 return r;
945 }
946
947 r = kvm_arch_set_tsc_khz(cs);
948 if (r < 0) {
949 return r;
950 }
951
952 /* vcpu's TSC frequency is either specified by user, or following
953 * the value used by KVM if the former is not present. In the
954 * latter case, we query it from KVM and record in env->tsc_khz,
955 * so that vcpu's TSC frequency can be migrated later via this field.
956 */
957 if (!env->tsc_khz) {
958 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
959 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
960 -ENOTSUP;
961 if (r > 0) {
962 env->tsc_khz = r;
963 }
964 }
965
966 if (has_xsave) {
967 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
968 }
969 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
970
971 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
972 has_msr_mtrr = true;
973 }
974 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
975 has_msr_tsc_aux = false;
976 }
977
978 return 0;
979 }
980
981 void kvm_arch_reset_vcpu(X86CPU *cpu)
982 {
983 CPUX86State *env = &cpu->env;
984
985 env->exception_injected = -1;
986 env->interrupt_injected = -1;
987 env->xcr0 = 1;
988 if (kvm_irqchip_in_kernel()) {
989 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
990 KVM_MP_STATE_UNINITIALIZED;
991 } else {
992 env->mp_state = KVM_MP_STATE_RUNNABLE;
993 }
994 }
995
996 void kvm_arch_do_init_vcpu(X86CPU *cpu)
997 {
998 CPUX86State *env = &cpu->env;
999
1000 /* APs get directly into wait-for-SIPI state. */
1001 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1002 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1003 }
1004 }
1005
1006 static int kvm_get_supported_msrs(KVMState *s)
1007 {
1008 static int kvm_supported_msrs;
1009 int ret = 0;
1010
1011 /* first time */
1012 if (kvm_supported_msrs == 0) {
1013 struct kvm_msr_list msr_list, *kvm_msr_list;
1014
1015 kvm_supported_msrs = -1;
1016
1017 /* Obtain MSR list from KVM. These are the MSRs that we must
1018 * save/restore */
1019 msr_list.nmsrs = 0;
1020 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1021 if (ret < 0 && ret != -E2BIG) {
1022 return ret;
1023 }
1024 /* Old kernel modules had a bug and could write beyond the provided
1025 memory. Allocate at least a safe amount of 1K. */
1026 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1027 msr_list.nmsrs *
1028 sizeof(msr_list.indices[0])));
1029
1030 kvm_msr_list->nmsrs = msr_list.nmsrs;
1031 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1032 if (ret >= 0) {
1033 int i;
1034
1035 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1036 if (kvm_msr_list->indices[i] == MSR_STAR) {
1037 has_msr_star = true;
1038 continue;
1039 }
1040 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1041 has_msr_hsave_pa = true;
1042 continue;
1043 }
1044 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1045 has_msr_tsc_aux = true;
1046 continue;
1047 }
1048 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1049 has_msr_tsc_adjust = true;
1050 continue;
1051 }
1052 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1053 has_msr_tsc_deadline = true;
1054 continue;
1055 }
1056 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1057 has_msr_smbase = true;
1058 continue;
1059 }
1060 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1061 has_msr_misc_enable = true;
1062 continue;
1063 }
1064 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1065 has_msr_bndcfgs = true;
1066 continue;
1067 }
1068 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1069 has_msr_xss = true;
1070 continue;
1071 }
1072 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1073 has_msr_hv_crash = true;
1074 continue;
1075 }
1076 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1077 has_msr_hv_reset = true;
1078 continue;
1079 }
1080 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1081 has_msr_hv_vpindex = true;
1082 continue;
1083 }
1084 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1085 has_msr_hv_runtime = true;
1086 continue;
1087 }
1088 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1089 has_msr_hv_synic = true;
1090 continue;
1091 }
1092 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1093 has_msr_hv_stimer = true;
1094 continue;
1095 }
1096 }
1097 }
1098
1099 g_free(kvm_msr_list);
1100 }
1101
1102 return ret;
1103 }
1104
1105 static Notifier smram_machine_done;
1106 static KVMMemoryListener smram_listener;
1107 static AddressSpace smram_address_space;
1108 static MemoryRegion smram_as_root;
1109 static MemoryRegion smram_as_mem;
1110
1111 static void register_smram_listener(Notifier *n, void *unused)
1112 {
1113 MemoryRegion *smram =
1114 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1115
1116 /* Outer container... */
1117 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1118 memory_region_set_enabled(&smram_as_root, true);
1119
1120 /* ... with two regions inside: normal system memory with low
1121 * priority, and...
1122 */
1123 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1124 get_system_memory(), 0, ~0ull);
1125 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1126 memory_region_set_enabled(&smram_as_mem, true);
1127
1128 if (smram) {
1129 /* ... SMRAM with higher priority */
1130 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1131 memory_region_set_enabled(smram, true);
1132 }
1133
1134 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1135 kvm_memory_listener_register(kvm_state, &smram_listener,
1136 &smram_address_space, 1);
1137 }
1138
1139 int kvm_arch_init(MachineState *ms, KVMState *s)
1140 {
1141 uint64_t identity_base = 0xfffbc000;
1142 uint64_t shadow_mem;
1143 int ret;
1144 struct utsname utsname;
1145
1146 #ifdef KVM_CAP_XSAVE
1147 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1148 #endif
1149
1150 #ifdef KVM_CAP_XCRS
1151 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1152 #endif
1153
1154 #ifdef KVM_CAP_PIT_STATE2
1155 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1156 #endif
1157
1158 ret = kvm_get_supported_msrs(s);
1159 if (ret < 0) {
1160 return ret;
1161 }
1162
1163 uname(&utsname);
1164 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1165
1166 /*
1167 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1168 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1169 * Since these must be part of guest physical memory, we need to allocate
1170 * them, both by setting their start addresses in the kernel and by
1171 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1172 *
1173 * Older KVM versions may not support setting the identity map base. In
1174 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1175 * size.
1176 */
1177 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1178 /* Allows up to 16M BIOSes. */
1179 identity_base = 0xfeffc000;
1180
1181 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1182 if (ret < 0) {
1183 return ret;
1184 }
1185 }
1186
1187 /* Set TSS base one page after EPT identity map. */
1188 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1189 if (ret < 0) {
1190 return ret;
1191 }
1192
1193 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1194 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1195 if (ret < 0) {
1196 fprintf(stderr, "e820_add_entry() table is full\n");
1197 return ret;
1198 }
1199 qemu_register_reset(kvm_unpoison_all, NULL);
1200
1201 shadow_mem = machine_kvm_shadow_mem(ms);
1202 if (shadow_mem != -1) {
1203 shadow_mem /= 4096;
1204 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1205 if (ret < 0) {
1206 return ret;
1207 }
1208 }
1209
1210 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1211 smram_machine_done.notify = register_smram_listener;
1212 qemu_add_machine_init_done_notifier(&smram_machine_done);
1213 }
1214 return 0;
1215 }
1216
1217 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1218 {
1219 lhs->selector = rhs->selector;
1220 lhs->base = rhs->base;
1221 lhs->limit = rhs->limit;
1222 lhs->type = 3;
1223 lhs->present = 1;
1224 lhs->dpl = 3;
1225 lhs->db = 0;
1226 lhs->s = 1;
1227 lhs->l = 0;
1228 lhs->g = 0;
1229 lhs->avl = 0;
1230 lhs->unusable = 0;
1231 }
1232
1233 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1234 {
1235 unsigned flags = rhs->flags;
1236 lhs->selector = rhs->selector;
1237 lhs->base = rhs->base;
1238 lhs->limit = rhs->limit;
1239 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1240 lhs->present = (flags & DESC_P_MASK) != 0;
1241 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1242 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1243 lhs->s = (flags & DESC_S_MASK) != 0;
1244 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1245 lhs->g = (flags & DESC_G_MASK) != 0;
1246 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1247 lhs->unusable = !lhs->present;
1248 lhs->padding = 0;
1249 }
1250
1251 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1252 {
1253 lhs->selector = rhs->selector;
1254 lhs->base = rhs->base;
1255 lhs->limit = rhs->limit;
1256 if (rhs->unusable) {
1257 lhs->flags = 0;
1258 } else {
1259 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1260 (rhs->present * DESC_P_MASK) |
1261 (rhs->dpl << DESC_DPL_SHIFT) |
1262 (rhs->db << DESC_B_SHIFT) |
1263 (rhs->s * DESC_S_MASK) |
1264 (rhs->l << DESC_L_SHIFT) |
1265 (rhs->g * DESC_G_MASK) |
1266 (rhs->avl * DESC_AVL_MASK);
1267 }
1268 }
1269
1270 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1271 {
1272 if (set) {
1273 *kvm_reg = *qemu_reg;
1274 } else {
1275 *qemu_reg = *kvm_reg;
1276 }
1277 }
1278
1279 static int kvm_getput_regs(X86CPU *cpu, int set)
1280 {
1281 CPUX86State *env = &cpu->env;
1282 struct kvm_regs regs;
1283 int ret = 0;
1284
1285 if (!set) {
1286 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1287 if (ret < 0) {
1288 return ret;
1289 }
1290 }
1291
1292 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1293 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1294 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1295 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1296 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1297 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1298 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1299 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1300 #ifdef TARGET_X86_64
1301 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1302 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1303 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1304 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1305 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1306 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1307 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1308 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1309 #endif
1310
1311 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1312 kvm_getput_reg(&regs.rip, &env->eip, set);
1313
1314 if (set) {
1315 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1316 }
1317
1318 return ret;
1319 }
1320
1321 static int kvm_put_fpu(X86CPU *cpu)
1322 {
1323 CPUX86State *env = &cpu->env;
1324 struct kvm_fpu fpu;
1325 int i;
1326
1327 memset(&fpu, 0, sizeof fpu);
1328 fpu.fsw = env->fpus & ~(7 << 11);
1329 fpu.fsw |= (env->fpstt & 7) << 11;
1330 fpu.fcw = env->fpuc;
1331 fpu.last_opcode = env->fpop;
1332 fpu.last_ip = env->fpip;
1333 fpu.last_dp = env->fpdp;
1334 for (i = 0; i < 8; ++i) {
1335 fpu.ftwx |= (!env->fptags[i]) << i;
1336 }
1337 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1338 for (i = 0; i < CPU_NB_REGS; i++) {
1339 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1340 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1341 }
1342 fpu.mxcsr = env->mxcsr;
1343
1344 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1345 }
1346
1347 #define XSAVE_FCW_FSW 0
1348 #define XSAVE_FTW_FOP 1
1349 #define XSAVE_CWD_RIP 2
1350 #define XSAVE_CWD_RDP 4
1351 #define XSAVE_MXCSR 6
1352 #define XSAVE_ST_SPACE 8
1353 #define XSAVE_XMM_SPACE 40
1354 #define XSAVE_XSTATE_BV 128
1355 #define XSAVE_YMMH_SPACE 144
1356 #define XSAVE_BNDREGS 240
1357 #define XSAVE_BNDCSR 256
1358 #define XSAVE_OPMASK 272
1359 #define XSAVE_ZMM_Hi256 288
1360 #define XSAVE_Hi16_ZMM 416
1361 #define XSAVE_PKRU 672
1362
1363 #define XSAVE_BYTE_OFFSET(word_offset) \
1364 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1365
1366 #define ASSERT_OFFSET(word_offset, field) \
1367 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1368 offsetof(X86XSaveArea, field))
1369
1370 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1371 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1372 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1373 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1374 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1375 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1376 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1377 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1378 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1379 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1380 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1381 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1382 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1383 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1384 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1385
1386 static int kvm_put_xsave(X86CPU *cpu)
1387 {
1388 CPUX86State *env = &cpu->env;
1389 X86XSaveArea *xsave = env->kvm_xsave_buf;
1390 uint16_t cwd, swd, twd;
1391 int i;
1392
1393 if (!has_xsave) {
1394 return kvm_put_fpu(cpu);
1395 }
1396
1397 memset(xsave, 0, sizeof(struct kvm_xsave));
1398 twd = 0;
1399 swd = env->fpus & ~(7 << 11);
1400 swd |= (env->fpstt & 7) << 11;
1401 cwd = env->fpuc;
1402 for (i = 0; i < 8; ++i) {
1403 twd |= (!env->fptags[i]) << i;
1404 }
1405 xsave->legacy.fcw = cwd;
1406 xsave->legacy.fsw = swd;
1407 xsave->legacy.ftw = twd;
1408 xsave->legacy.fpop = env->fpop;
1409 xsave->legacy.fpip = env->fpip;
1410 xsave->legacy.fpdp = env->fpdp;
1411 memcpy(&xsave->legacy.fpregs, env->fpregs,
1412 sizeof env->fpregs);
1413 xsave->legacy.mxcsr = env->mxcsr;
1414 xsave->header.xstate_bv = env->xstate_bv;
1415 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1416 sizeof env->bnd_regs);
1417 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1418 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1419 sizeof env->opmask_regs);
1420
1421 for (i = 0; i < CPU_NB_REGS; i++) {
1422 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1423 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1424 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1425 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1426 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1427 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1428 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1429 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1430 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1431 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1432 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1433 }
1434
1435 #ifdef TARGET_X86_64
1436 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1437 16 * sizeof env->xmm_regs[16]);
1438 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1439 #endif
1440 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1441 }
1442
1443 static int kvm_put_xcrs(X86CPU *cpu)
1444 {
1445 CPUX86State *env = &cpu->env;
1446 struct kvm_xcrs xcrs = {};
1447
1448 if (!has_xcrs) {
1449 return 0;
1450 }
1451
1452 xcrs.nr_xcrs = 1;
1453 xcrs.flags = 0;
1454 xcrs.xcrs[0].xcr = 0;
1455 xcrs.xcrs[0].value = env->xcr0;
1456 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1457 }
1458
1459 static int kvm_put_sregs(X86CPU *cpu)
1460 {
1461 CPUX86State *env = &cpu->env;
1462 struct kvm_sregs sregs;
1463
1464 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1465 if (env->interrupt_injected >= 0) {
1466 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1467 (uint64_t)1 << (env->interrupt_injected % 64);
1468 }
1469
1470 if ((env->eflags & VM_MASK)) {
1471 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1472 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1473 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1474 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1475 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1476 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1477 } else {
1478 set_seg(&sregs.cs, &env->segs[R_CS]);
1479 set_seg(&sregs.ds, &env->segs[R_DS]);
1480 set_seg(&sregs.es, &env->segs[R_ES]);
1481 set_seg(&sregs.fs, &env->segs[R_FS]);
1482 set_seg(&sregs.gs, &env->segs[R_GS]);
1483 set_seg(&sregs.ss, &env->segs[R_SS]);
1484 }
1485
1486 set_seg(&sregs.tr, &env->tr);
1487 set_seg(&sregs.ldt, &env->ldt);
1488
1489 sregs.idt.limit = env->idt.limit;
1490 sregs.idt.base = env->idt.base;
1491 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1492 sregs.gdt.limit = env->gdt.limit;
1493 sregs.gdt.base = env->gdt.base;
1494 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1495
1496 sregs.cr0 = env->cr[0];
1497 sregs.cr2 = env->cr[2];
1498 sregs.cr3 = env->cr[3];
1499 sregs.cr4 = env->cr[4];
1500
1501 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1502 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1503
1504 sregs.efer = env->efer;
1505
1506 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1507 }
1508
1509 static void kvm_msr_buf_reset(X86CPU *cpu)
1510 {
1511 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1512 }
1513
1514 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1515 {
1516 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1517 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1518 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1519
1520 assert((void *)(entry + 1) <= limit);
1521
1522 entry->index = index;
1523 entry->reserved = 0;
1524 entry->data = value;
1525 msrs->nmsrs++;
1526 }
1527
1528 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1529 {
1530 CPUX86State *env = &cpu->env;
1531 int ret;
1532
1533 if (!has_msr_tsc_deadline) {
1534 return 0;
1535 }
1536
1537 kvm_msr_buf_reset(cpu);
1538 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1539
1540 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1541 if (ret < 0) {
1542 return ret;
1543 }
1544
1545 assert(ret == 1);
1546 return 0;
1547 }
1548
1549 /*
1550 * Provide a separate write service for the feature control MSR in order to
1551 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1552 * before writing any other state because forcibly leaving nested mode
1553 * invalidates the VCPU state.
1554 */
1555 static int kvm_put_msr_feature_control(X86CPU *cpu)
1556 {
1557 int ret;
1558
1559 if (!has_msr_feature_control) {
1560 return 0;
1561 }
1562
1563 kvm_msr_buf_reset(cpu);
1564 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL,
1565 cpu->env.msr_ia32_feature_control);
1566
1567 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1568 if (ret < 0) {
1569 return ret;
1570 }
1571
1572 assert(ret == 1);
1573 return 0;
1574 }
1575
1576 static int kvm_put_msrs(X86CPU *cpu, int level)
1577 {
1578 CPUX86State *env = &cpu->env;
1579 int i;
1580 int ret;
1581
1582 kvm_msr_buf_reset(cpu);
1583
1584 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1585 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1586 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1587 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1588 if (has_msr_star) {
1589 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1590 }
1591 if (has_msr_hsave_pa) {
1592 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1593 }
1594 if (has_msr_tsc_aux) {
1595 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1596 }
1597 if (has_msr_tsc_adjust) {
1598 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1599 }
1600 if (has_msr_misc_enable) {
1601 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1602 env->msr_ia32_misc_enable);
1603 }
1604 if (has_msr_smbase) {
1605 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1606 }
1607 if (has_msr_bndcfgs) {
1608 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1609 }
1610 if (has_msr_xss) {
1611 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1612 }
1613 #ifdef TARGET_X86_64
1614 if (lm_capable_kernel) {
1615 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1616 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1617 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1618 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1619 }
1620 #endif
1621 /*
1622 * The following MSRs have side effects on the guest or are too heavy
1623 * for normal writeback. Limit them to reset or full state updates.
1624 */
1625 if (level >= KVM_PUT_RESET_STATE) {
1626 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1627 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1628 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1629 if (has_msr_async_pf_en) {
1630 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1631 }
1632 if (has_msr_pv_eoi_en) {
1633 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1634 }
1635 if (has_msr_kvm_steal_time) {
1636 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1637 }
1638 if (has_msr_architectural_pmu) {
1639 /* Stop the counter. */
1640 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1641 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1642
1643 /* Set the counter values. */
1644 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1645 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1646 env->msr_fixed_counters[i]);
1647 }
1648 for (i = 0; i < num_architectural_pmu_counters; i++) {
1649 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1650 env->msr_gp_counters[i]);
1651 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1652 env->msr_gp_evtsel[i]);
1653 }
1654 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1655 env->msr_global_status);
1656 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1657 env->msr_global_ovf_ctrl);
1658
1659 /* Now start the PMU. */
1660 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1661 env->msr_fixed_ctr_ctrl);
1662 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1663 env->msr_global_ctrl);
1664 }
1665 if (has_msr_hv_hypercall) {
1666 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1667 env->msr_hv_guest_os_id);
1668 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1669 env->msr_hv_hypercall);
1670 }
1671 if (has_msr_hv_vapic) {
1672 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1673 env->msr_hv_vapic);
1674 }
1675 if (has_msr_hv_tsc) {
1676 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1677 }
1678 if (has_msr_hv_crash) {
1679 int j;
1680
1681 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1682 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1683 env->msr_hv_crash_params[j]);
1684
1685 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1686 HV_X64_MSR_CRASH_CTL_NOTIFY);
1687 }
1688 if (has_msr_hv_runtime) {
1689 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1690 }
1691 if (cpu->hyperv_synic) {
1692 int j;
1693
1694 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1695 env->msr_hv_synic_control);
1696 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1697 env->msr_hv_synic_version);
1698 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1699 env->msr_hv_synic_evt_page);
1700 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1701 env->msr_hv_synic_msg_page);
1702
1703 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1704 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1705 env->msr_hv_synic_sint[j]);
1706 }
1707 }
1708 if (has_msr_hv_stimer) {
1709 int j;
1710
1711 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1712 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1713 env->msr_hv_stimer_config[j]);
1714 }
1715
1716 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1717 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1718 env->msr_hv_stimer_count[j]);
1719 }
1720 }
1721 if (has_msr_mtrr) {
1722 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1723
1724 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1725 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1726 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1727 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1728 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1729 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1730 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1731 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1732 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1733 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1734 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1735 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1736 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1737 /* The CPU GPs if we write to a bit above the physical limit of
1738 * the host CPU (and KVM emulates that)
1739 */
1740 uint64_t mask = env->mtrr_var[i].mask;
1741 mask &= phys_mask;
1742
1743 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1744 env->mtrr_var[i].base);
1745 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1746 }
1747 }
1748
1749 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1750 * kvm_put_msr_feature_control. */
1751 }
1752 if (env->mcg_cap) {
1753 int i;
1754
1755 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1756 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1757 if (has_msr_mcg_ext_ctl) {
1758 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1759 }
1760 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1761 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1762 }
1763 }
1764
1765 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1766 if (ret < 0) {
1767 return ret;
1768 }
1769
1770 assert(ret == cpu->kvm_msr_buf->nmsrs);
1771 return 0;
1772 }
1773
1774
1775 static int kvm_get_fpu(X86CPU *cpu)
1776 {
1777 CPUX86State *env = &cpu->env;
1778 struct kvm_fpu fpu;
1779 int i, ret;
1780
1781 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1782 if (ret < 0) {
1783 return ret;
1784 }
1785
1786 env->fpstt = (fpu.fsw >> 11) & 7;
1787 env->fpus = fpu.fsw;
1788 env->fpuc = fpu.fcw;
1789 env->fpop = fpu.last_opcode;
1790 env->fpip = fpu.last_ip;
1791 env->fpdp = fpu.last_dp;
1792 for (i = 0; i < 8; ++i) {
1793 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1794 }
1795 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1796 for (i = 0; i < CPU_NB_REGS; i++) {
1797 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1798 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1799 }
1800 env->mxcsr = fpu.mxcsr;
1801
1802 return 0;
1803 }
1804
1805 static int kvm_get_xsave(X86CPU *cpu)
1806 {
1807 CPUX86State *env = &cpu->env;
1808 X86XSaveArea *xsave = env->kvm_xsave_buf;
1809 int ret, i;
1810 uint16_t cwd, swd, twd;
1811
1812 if (!has_xsave) {
1813 return kvm_get_fpu(cpu);
1814 }
1815
1816 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1817 if (ret < 0) {
1818 return ret;
1819 }
1820
1821 cwd = xsave->legacy.fcw;
1822 swd = xsave->legacy.fsw;
1823 twd = xsave->legacy.ftw;
1824 env->fpop = xsave->legacy.fpop;
1825 env->fpstt = (swd >> 11) & 7;
1826 env->fpus = swd;
1827 env->fpuc = cwd;
1828 for (i = 0; i < 8; ++i) {
1829 env->fptags[i] = !((twd >> i) & 1);
1830 }
1831 env->fpip = xsave->legacy.fpip;
1832 env->fpdp = xsave->legacy.fpdp;
1833 env->mxcsr = xsave->legacy.mxcsr;
1834 memcpy(env->fpregs, &xsave->legacy.fpregs,
1835 sizeof env->fpregs);
1836 env->xstate_bv = xsave->header.xstate_bv;
1837 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1838 sizeof env->bnd_regs);
1839 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1840 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1841 sizeof env->opmask_regs);
1842
1843 for (i = 0; i < CPU_NB_REGS; i++) {
1844 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1845 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1846 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1847 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1848 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1849 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1850 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1851 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1852 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1853 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1854 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1855 }
1856
1857 #ifdef TARGET_X86_64
1858 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1859 16 * sizeof env->xmm_regs[16]);
1860 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1861 #endif
1862 return 0;
1863 }
1864
1865 static int kvm_get_xcrs(X86CPU *cpu)
1866 {
1867 CPUX86State *env = &cpu->env;
1868 int i, ret;
1869 struct kvm_xcrs xcrs;
1870
1871 if (!has_xcrs) {
1872 return 0;
1873 }
1874
1875 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1876 if (ret < 0) {
1877 return ret;
1878 }
1879
1880 for (i = 0; i < xcrs.nr_xcrs; i++) {
1881 /* Only support xcr0 now */
1882 if (xcrs.xcrs[i].xcr == 0) {
1883 env->xcr0 = xcrs.xcrs[i].value;
1884 break;
1885 }
1886 }
1887 return 0;
1888 }
1889
1890 static int kvm_get_sregs(X86CPU *cpu)
1891 {
1892 CPUX86State *env = &cpu->env;
1893 struct kvm_sregs sregs;
1894 uint32_t hflags;
1895 int bit, i, ret;
1896
1897 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1898 if (ret < 0) {
1899 return ret;
1900 }
1901
1902 /* There can only be one pending IRQ set in the bitmap at a time, so try
1903 to find it and save its number instead (-1 for none). */
1904 env->interrupt_injected = -1;
1905 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1906 if (sregs.interrupt_bitmap[i]) {
1907 bit = ctz64(sregs.interrupt_bitmap[i]);
1908 env->interrupt_injected = i * 64 + bit;
1909 break;
1910 }
1911 }
1912
1913 get_seg(&env->segs[R_CS], &sregs.cs);
1914 get_seg(&env->segs[R_DS], &sregs.ds);
1915 get_seg(&env->segs[R_ES], &sregs.es);
1916 get_seg(&env->segs[R_FS], &sregs.fs);
1917 get_seg(&env->segs[R_GS], &sregs.gs);
1918 get_seg(&env->segs[R_SS], &sregs.ss);
1919
1920 get_seg(&env->tr, &sregs.tr);
1921 get_seg(&env->ldt, &sregs.ldt);
1922
1923 env->idt.limit = sregs.idt.limit;
1924 env->idt.base = sregs.idt.base;
1925 env->gdt.limit = sregs.gdt.limit;
1926 env->gdt.base = sregs.gdt.base;
1927
1928 env->cr[0] = sregs.cr0;
1929 env->cr[2] = sregs.cr2;
1930 env->cr[3] = sregs.cr3;
1931 env->cr[4] = sregs.cr4;
1932
1933 env->efer = sregs.efer;
1934
1935 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1936
1937 #define HFLAG_COPY_MASK \
1938 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1939 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1940 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1941 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1942
1943 hflags = env->hflags & HFLAG_COPY_MASK;
1944 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1945 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1946 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1947 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1948 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1949
1950 if (env->cr[4] & CR4_OSFXSR_MASK) {
1951 hflags |= HF_OSFXSR_MASK;
1952 }
1953
1954 if (env->efer & MSR_EFER_LMA) {
1955 hflags |= HF_LMA_MASK;
1956 }
1957
1958 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1959 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1960 } else {
1961 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1962 (DESC_B_SHIFT - HF_CS32_SHIFT);
1963 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1964 (DESC_B_SHIFT - HF_SS32_SHIFT);
1965 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1966 !(hflags & HF_CS32_MASK)) {
1967 hflags |= HF_ADDSEG_MASK;
1968 } else {
1969 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1970 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1971 }
1972 }
1973 env->hflags = hflags;
1974
1975 return 0;
1976 }
1977
1978 static int kvm_get_msrs(X86CPU *cpu)
1979 {
1980 CPUX86State *env = &cpu->env;
1981 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
1982 int ret, i;
1983 uint64_t mtrr_top_bits;
1984
1985 kvm_msr_buf_reset(cpu);
1986
1987 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1988 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1989 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1990 kvm_msr_entry_add(cpu, MSR_PAT, 0);
1991 if (has_msr_star) {
1992 kvm_msr_entry_add(cpu, MSR_STAR, 0);
1993 }
1994 if (has_msr_hsave_pa) {
1995 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
1996 }
1997 if (has_msr_tsc_aux) {
1998 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
1999 }
2000 if (has_msr_tsc_adjust) {
2001 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2002 }
2003 if (has_msr_tsc_deadline) {
2004 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2005 }
2006 if (has_msr_misc_enable) {
2007 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2008 }
2009 if (has_msr_smbase) {
2010 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2011 }
2012 if (has_msr_feature_control) {
2013 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2014 }
2015 if (has_msr_bndcfgs) {
2016 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2017 }
2018 if (has_msr_xss) {
2019 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2020 }
2021
2022
2023 if (!env->tsc_valid) {
2024 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2025 env->tsc_valid = !runstate_is_running();
2026 }
2027
2028 #ifdef TARGET_X86_64
2029 if (lm_capable_kernel) {
2030 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2031 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2032 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2033 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2034 }
2035 #endif
2036 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2037 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2038 if (has_msr_async_pf_en) {
2039 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2040 }
2041 if (has_msr_pv_eoi_en) {
2042 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2043 }
2044 if (has_msr_kvm_steal_time) {
2045 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2046 }
2047 if (has_msr_architectural_pmu) {
2048 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2049 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2050 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2051 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2052 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2053 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2054 }
2055 for (i = 0; i < num_architectural_pmu_counters; i++) {
2056 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2057 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2058 }
2059 }
2060
2061 if (env->mcg_cap) {
2062 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2063 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2064 if (has_msr_mcg_ext_ctl) {
2065 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2066 }
2067 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2068 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2069 }
2070 }
2071
2072 if (has_msr_hv_hypercall) {
2073 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2074 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2075 }
2076 if (has_msr_hv_vapic) {
2077 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2078 }
2079 if (has_msr_hv_tsc) {
2080 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2081 }
2082 if (has_msr_hv_crash) {
2083 int j;
2084
2085 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2086 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2087 }
2088 }
2089 if (has_msr_hv_runtime) {
2090 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2091 }
2092 if (cpu->hyperv_synic) {
2093 uint32_t msr;
2094
2095 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2096 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2097 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2098 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2099 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2100 kvm_msr_entry_add(cpu, msr, 0);
2101 }
2102 }
2103 if (has_msr_hv_stimer) {
2104 uint32_t msr;
2105
2106 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2107 msr++) {
2108 kvm_msr_entry_add(cpu, msr, 0);
2109 }
2110 }
2111 if (has_msr_mtrr) {
2112 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2113 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2114 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2115 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2116 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2117 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2118 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2119 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2120 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2121 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2122 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2123 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2124 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2125 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2126 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2127 }
2128 }
2129
2130 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2131 if (ret < 0) {
2132 return ret;
2133 }
2134
2135 assert(ret == cpu->kvm_msr_buf->nmsrs);
2136 /*
2137 * MTRR masks: Each mask consists of 5 parts
2138 * a 10..0: must be zero
2139 * b 11 : valid bit
2140 * c n-1.12: actual mask bits
2141 * d 51..n: reserved must be zero
2142 * e 63.52: reserved must be zero
2143 *
2144 * 'n' is the number of physical bits supported by the CPU and is
2145 * apparently always <= 52. We know our 'n' but don't know what
2146 * the destinations 'n' is; it might be smaller, in which case
2147 * it masks (c) on loading. It might be larger, in which case
2148 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2149 * we're migrating to.
2150 */
2151
2152 if (cpu->fill_mtrr_mask) {
2153 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2154 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2155 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2156 } else {
2157 mtrr_top_bits = 0;
2158 }
2159
2160 for (i = 0; i < ret; i++) {
2161 uint32_t index = msrs[i].index;
2162 switch (index) {
2163 case MSR_IA32_SYSENTER_CS:
2164 env->sysenter_cs = msrs[i].data;
2165 break;
2166 case MSR_IA32_SYSENTER_ESP:
2167 env->sysenter_esp = msrs[i].data;
2168 break;
2169 case MSR_IA32_SYSENTER_EIP:
2170 env->sysenter_eip = msrs[i].data;
2171 break;
2172 case MSR_PAT:
2173 env->pat = msrs[i].data;
2174 break;
2175 case MSR_STAR:
2176 env->star = msrs[i].data;
2177 break;
2178 #ifdef TARGET_X86_64
2179 case MSR_CSTAR:
2180 env->cstar = msrs[i].data;
2181 break;
2182 case MSR_KERNELGSBASE:
2183 env->kernelgsbase = msrs[i].data;
2184 break;
2185 case MSR_FMASK:
2186 env->fmask = msrs[i].data;
2187 break;
2188 case MSR_LSTAR:
2189 env->lstar = msrs[i].data;
2190 break;
2191 #endif
2192 case MSR_IA32_TSC:
2193 env->tsc = msrs[i].data;
2194 break;
2195 case MSR_TSC_AUX:
2196 env->tsc_aux = msrs[i].data;
2197 break;
2198 case MSR_TSC_ADJUST:
2199 env->tsc_adjust = msrs[i].data;
2200 break;
2201 case MSR_IA32_TSCDEADLINE:
2202 env->tsc_deadline = msrs[i].data;
2203 break;
2204 case MSR_VM_HSAVE_PA:
2205 env->vm_hsave = msrs[i].data;
2206 break;
2207 case MSR_KVM_SYSTEM_TIME:
2208 env->system_time_msr = msrs[i].data;
2209 break;
2210 case MSR_KVM_WALL_CLOCK:
2211 env->wall_clock_msr = msrs[i].data;
2212 break;
2213 case MSR_MCG_STATUS:
2214 env->mcg_status = msrs[i].data;
2215 break;
2216 case MSR_MCG_CTL:
2217 env->mcg_ctl = msrs[i].data;
2218 break;
2219 case MSR_MCG_EXT_CTL:
2220 env->mcg_ext_ctl = msrs[i].data;
2221 break;
2222 case MSR_IA32_MISC_ENABLE:
2223 env->msr_ia32_misc_enable = msrs[i].data;
2224 break;
2225 case MSR_IA32_SMBASE:
2226 env->smbase = msrs[i].data;
2227 break;
2228 case MSR_IA32_FEATURE_CONTROL:
2229 env->msr_ia32_feature_control = msrs[i].data;
2230 break;
2231 case MSR_IA32_BNDCFGS:
2232 env->msr_bndcfgs = msrs[i].data;
2233 break;
2234 case MSR_IA32_XSS:
2235 env->xss = msrs[i].data;
2236 break;
2237 default:
2238 if (msrs[i].index >= MSR_MC0_CTL &&
2239 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2240 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2241 }
2242 break;
2243 case MSR_KVM_ASYNC_PF_EN:
2244 env->async_pf_en_msr = msrs[i].data;
2245 break;
2246 case MSR_KVM_PV_EOI_EN:
2247 env->pv_eoi_en_msr = msrs[i].data;
2248 break;
2249 case MSR_KVM_STEAL_TIME:
2250 env->steal_time_msr = msrs[i].data;
2251 break;
2252 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2253 env->msr_fixed_ctr_ctrl = msrs[i].data;
2254 break;
2255 case MSR_CORE_PERF_GLOBAL_CTRL:
2256 env->msr_global_ctrl = msrs[i].data;
2257 break;
2258 case MSR_CORE_PERF_GLOBAL_STATUS:
2259 env->msr_global_status = msrs[i].data;
2260 break;
2261 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2262 env->msr_global_ovf_ctrl = msrs[i].data;
2263 break;
2264 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2265 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2266 break;
2267 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2268 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2269 break;
2270 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2271 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2272 break;
2273 case HV_X64_MSR_HYPERCALL:
2274 env->msr_hv_hypercall = msrs[i].data;
2275 break;
2276 case HV_X64_MSR_GUEST_OS_ID:
2277 env->msr_hv_guest_os_id = msrs[i].data;
2278 break;
2279 case HV_X64_MSR_APIC_ASSIST_PAGE:
2280 env->msr_hv_vapic = msrs[i].data;
2281 break;
2282 case HV_X64_MSR_REFERENCE_TSC:
2283 env->msr_hv_tsc = msrs[i].data;
2284 break;
2285 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2286 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2287 break;
2288 case HV_X64_MSR_VP_RUNTIME:
2289 env->msr_hv_runtime = msrs[i].data;
2290 break;
2291 case HV_X64_MSR_SCONTROL:
2292 env->msr_hv_synic_control = msrs[i].data;
2293 break;
2294 case HV_X64_MSR_SVERSION:
2295 env->msr_hv_synic_version = msrs[i].data;
2296 break;
2297 case HV_X64_MSR_SIEFP:
2298 env->msr_hv_synic_evt_page = msrs[i].data;
2299 break;
2300 case HV_X64_MSR_SIMP:
2301 env->msr_hv_synic_msg_page = msrs[i].data;
2302 break;
2303 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2304 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2305 break;
2306 case HV_X64_MSR_STIMER0_CONFIG:
2307 case HV_X64_MSR_STIMER1_CONFIG:
2308 case HV_X64_MSR_STIMER2_CONFIG:
2309 case HV_X64_MSR_STIMER3_CONFIG:
2310 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2311 msrs[i].data;
2312 break;
2313 case HV_X64_MSR_STIMER0_COUNT:
2314 case HV_X64_MSR_STIMER1_COUNT:
2315 case HV_X64_MSR_STIMER2_COUNT:
2316 case HV_X64_MSR_STIMER3_COUNT:
2317 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2318 msrs[i].data;
2319 break;
2320 case MSR_MTRRdefType:
2321 env->mtrr_deftype = msrs[i].data;
2322 break;
2323 case MSR_MTRRfix64K_00000:
2324 env->mtrr_fixed[0] = msrs[i].data;
2325 break;
2326 case MSR_MTRRfix16K_80000:
2327 env->mtrr_fixed[1] = msrs[i].data;
2328 break;
2329 case MSR_MTRRfix16K_A0000:
2330 env->mtrr_fixed[2] = msrs[i].data;
2331 break;
2332 case MSR_MTRRfix4K_C0000:
2333 env->mtrr_fixed[3] = msrs[i].data;
2334 break;
2335 case MSR_MTRRfix4K_C8000:
2336 env->mtrr_fixed[4] = msrs[i].data;
2337 break;
2338 case MSR_MTRRfix4K_D0000:
2339 env->mtrr_fixed[5] = msrs[i].data;
2340 break;
2341 case MSR_MTRRfix4K_D8000:
2342 env->mtrr_fixed[6] = msrs[i].data;
2343 break;
2344 case MSR_MTRRfix4K_E0000:
2345 env->mtrr_fixed[7] = msrs[i].data;
2346 break;
2347 case MSR_MTRRfix4K_E8000:
2348 env->mtrr_fixed[8] = msrs[i].data;
2349 break;
2350 case MSR_MTRRfix4K_F0000:
2351 env->mtrr_fixed[9] = msrs[i].data;
2352 break;
2353 case MSR_MTRRfix4K_F8000:
2354 env->mtrr_fixed[10] = msrs[i].data;
2355 break;
2356 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2357 if (index & 1) {
2358 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2359 mtrr_top_bits;
2360 } else {
2361 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2362 }
2363 break;
2364 }
2365 }
2366
2367 return 0;
2368 }
2369
2370 static int kvm_put_mp_state(X86CPU *cpu)
2371 {
2372 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2373
2374 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2375 }
2376
2377 static int kvm_get_mp_state(X86CPU *cpu)
2378 {
2379 CPUState *cs = CPU(cpu);
2380 CPUX86State *env = &cpu->env;
2381 struct kvm_mp_state mp_state;
2382 int ret;
2383
2384 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2385 if (ret < 0) {
2386 return ret;
2387 }
2388 env->mp_state = mp_state.mp_state;
2389 if (kvm_irqchip_in_kernel()) {
2390 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2391 }
2392 return 0;
2393 }
2394
2395 static int kvm_get_apic(X86CPU *cpu)
2396 {
2397 DeviceState *apic = cpu->apic_state;
2398 struct kvm_lapic_state kapic;
2399 int ret;
2400
2401 if (apic && kvm_irqchip_in_kernel()) {
2402 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2403 if (ret < 0) {
2404 return ret;
2405 }
2406
2407 kvm_get_apic_state(apic, &kapic);
2408 }
2409 return 0;
2410 }
2411
2412 static int kvm_put_apic(X86CPU *cpu)
2413 {
2414 DeviceState *apic = cpu->apic_state;
2415 struct kvm_lapic_state kapic;
2416
2417 if (apic && kvm_irqchip_in_kernel()) {
2418 kvm_put_apic_state(apic, &kapic);
2419
2420 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
2421 }
2422 return 0;
2423 }
2424
2425 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2426 {
2427 CPUState *cs = CPU(cpu);
2428 CPUX86State *env = &cpu->env;
2429 struct kvm_vcpu_events events = {};
2430
2431 if (!kvm_has_vcpu_events()) {
2432 return 0;
2433 }
2434
2435 events.exception.injected = (env->exception_injected >= 0);
2436 events.exception.nr = env->exception_injected;
2437 events.exception.has_error_code = env->has_error_code;
2438 events.exception.error_code = env->error_code;
2439 events.exception.pad = 0;
2440
2441 events.interrupt.injected = (env->interrupt_injected >= 0);
2442 events.interrupt.nr = env->interrupt_injected;
2443 events.interrupt.soft = env->soft_interrupt;
2444
2445 events.nmi.injected = env->nmi_injected;
2446 events.nmi.pending = env->nmi_pending;
2447 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2448 events.nmi.pad = 0;
2449
2450 events.sipi_vector = env->sipi_vector;
2451
2452 if (has_msr_smbase) {
2453 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2454 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2455 if (kvm_irqchip_in_kernel()) {
2456 /* As soon as these are moved to the kernel, remove them
2457 * from cs->interrupt_request.
2458 */
2459 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2460 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2461 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2462 } else {
2463 /* Keep these in cs->interrupt_request. */
2464 events.smi.pending = 0;
2465 events.smi.latched_init = 0;
2466 }
2467 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2468 }
2469
2470 events.flags = 0;
2471 if (level >= KVM_PUT_RESET_STATE) {
2472 events.flags |=
2473 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2474 }
2475
2476 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2477 }
2478
2479 static int kvm_get_vcpu_events(X86CPU *cpu)
2480 {
2481 CPUX86State *env = &cpu->env;
2482 struct kvm_vcpu_events events;
2483 int ret;
2484
2485 if (!kvm_has_vcpu_events()) {
2486 return 0;
2487 }
2488
2489 memset(&events, 0, sizeof(events));
2490 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2491 if (ret < 0) {
2492 return ret;
2493 }
2494 env->exception_injected =
2495 events.exception.injected ? events.exception.nr : -1;
2496 env->has_error_code = events.exception.has_error_code;
2497 env->error_code = events.exception.error_code;
2498
2499 env->interrupt_injected =
2500 events.interrupt.injected ? events.interrupt.nr : -1;
2501 env->soft_interrupt = events.interrupt.soft;
2502
2503 env->nmi_injected = events.nmi.injected;
2504 env->nmi_pending = events.nmi.pending;
2505 if (events.nmi.masked) {
2506 env->hflags2 |= HF2_NMI_MASK;
2507 } else {
2508 env->hflags2 &= ~HF2_NMI_MASK;
2509 }
2510
2511 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2512 if (events.smi.smm) {
2513 env->hflags |= HF_SMM_MASK;
2514 } else {
2515 env->hflags &= ~HF_SMM_MASK;
2516 }
2517 if (events.smi.pending) {
2518 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2519 } else {
2520 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2521 }
2522 if (events.smi.smm_inside_nmi) {
2523 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2524 } else {
2525 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2526 }
2527 if (events.smi.latched_init) {
2528 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2529 } else {
2530 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2531 }
2532 }
2533
2534 env->sipi_vector = events.sipi_vector;
2535
2536 return 0;
2537 }
2538
2539 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2540 {
2541 CPUState *cs = CPU(cpu);
2542 CPUX86State *env = &cpu->env;
2543 int ret = 0;
2544 unsigned long reinject_trap = 0;
2545
2546 if (!kvm_has_vcpu_events()) {
2547 if (env->exception_injected == 1) {
2548 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2549 } else if (env->exception_injected == 3) {
2550 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2551 }
2552 env->exception_injected = -1;
2553 }
2554
2555 /*
2556 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2557 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2558 * by updating the debug state once again if single-stepping is on.
2559 * Another reason to call kvm_update_guest_debug here is a pending debug
2560 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2561 * reinject them via SET_GUEST_DEBUG.
2562 */
2563 if (reinject_trap ||
2564 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2565 ret = kvm_update_guest_debug(cs, reinject_trap);
2566 }
2567 return ret;
2568 }
2569
2570 static int kvm_put_debugregs(X86CPU *cpu)
2571 {
2572 CPUX86State *env = &cpu->env;
2573 struct kvm_debugregs dbgregs;
2574 int i;
2575
2576 if (!kvm_has_debugregs()) {
2577 return 0;
2578 }
2579
2580 for (i = 0; i < 4; i++) {
2581 dbgregs.db[i] = env->dr[i];
2582 }
2583 dbgregs.dr6 = env->dr[6];
2584 dbgregs.dr7 = env->dr[7];
2585 dbgregs.flags = 0;
2586
2587 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2588 }
2589
2590 static int kvm_get_debugregs(X86CPU *cpu)
2591 {
2592 CPUX86State *env = &cpu->env;
2593 struct kvm_debugregs dbgregs;
2594 int i, ret;
2595
2596 if (!kvm_has_debugregs()) {
2597 return 0;
2598 }
2599
2600 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2601 if (ret < 0) {
2602 return ret;
2603 }
2604 for (i = 0; i < 4; i++) {
2605 env->dr[i] = dbgregs.db[i];
2606 }
2607 env->dr[4] = env->dr[6] = dbgregs.dr6;
2608 env->dr[5] = env->dr[7] = dbgregs.dr7;
2609
2610 return 0;
2611 }
2612
2613 int kvm_arch_put_registers(CPUState *cpu, int level)
2614 {
2615 X86CPU *x86_cpu = X86_CPU(cpu);
2616 int ret;
2617
2618 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2619
2620 if (level >= KVM_PUT_RESET_STATE) {
2621 ret = kvm_put_msr_feature_control(x86_cpu);
2622 if (ret < 0) {
2623 return ret;
2624 }
2625 }
2626
2627 if (level == KVM_PUT_FULL_STATE) {
2628 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2629 * because TSC frequency mismatch shouldn't abort migration,
2630 * unless the user explicitly asked for a more strict TSC
2631 * setting (e.g. using an explicit "tsc-freq" option).
2632 */
2633 kvm_arch_set_tsc_khz(cpu);
2634 }
2635
2636 ret = kvm_getput_regs(x86_cpu, 1);
2637 if (ret < 0) {
2638 return ret;
2639 }
2640 ret = kvm_put_xsave(x86_cpu);
2641 if (ret < 0) {
2642 return ret;
2643 }
2644 ret = kvm_put_xcrs(x86_cpu);
2645 if (ret < 0) {
2646 return ret;
2647 }
2648 ret = kvm_put_sregs(x86_cpu);
2649 if (ret < 0) {
2650 return ret;
2651 }
2652 /* must be before kvm_put_msrs */
2653 ret = kvm_inject_mce_oldstyle(x86_cpu);
2654 if (ret < 0) {
2655 return ret;
2656 }
2657 ret = kvm_put_msrs(x86_cpu, level);
2658 if (ret < 0) {
2659 return ret;
2660 }
2661 if (level >= KVM_PUT_RESET_STATE) {
2662 ret = kvm_put_mp_state(x86_cpu);
2663 if (ret < 0) {
2664 return ret;
2665 }
2666 ret = kvm_put_apic(x86_cpu);
2667 if (ret < 0) {
2668 return ret;
2669 }
2670 }
2671
2672 ret = kvm_put_tscdeadline_msr(x86_cpu);
2673 if (ret < 0) {
2674 return ret;
2675 }
2676
2677 ret = kvm_put_vcpu_events(x86_cpu, level);
2678 if (ret < 0) {
2679 return ret;
2680 }
2681 ret = kvm_put_debugregs(x86_cpu);
2682 if (ret < 0) {
2683 return ret;
2684 }
2685 /* must be last */
2686 ret = kvm_guest_debug_workarounds(x86_cpu);
2687 if (ret < 0) {
2688 return ret;
2689 }
2690 return 0;
2691 }
2692
2693 int kvm_arch_get_registers(CPUState *cs)
2694 {
2695 X86CPU *cpu = X86_CPU(cs);
2696 int ret;
2697
2698 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2699
2700 ret = kvm_getput_regs(cpu, 0);
2701 if (ret < 0) {
2702 goto out;
2703 }
2704 ret = kvm_get_xsave(cpu);
2705 if (ret < 0) {
2706 goto out;
2707 }
2708 ret = kvm_get_xcrs(cpu);
2709 if (ret < 0) {
2710 goto out;
2711 }
2712 ret = kvm_get_sregs(cpu);
2713 if (ret < 0) {
2714 goto out;
2715 }
2716 ret = kvm_get_msrs(cpu);
2717 if (ret < 0) {
2718 goto out;
2719 }
2720 ret = kvm_get_mp_state(cpu);
2721 if (ret < 0) {
2722 goto out;
2723 }
2724 ret = kvm_get_apic(cpu);
2725 if (ret < 0) {
2726 goto out;
2727 }
2728 ret = kvm_get_vcpu_events(cpu);
2729 if (ret < 0) {
2730 goto out;
2731 }
2732 ret = kvm_get_debugregs(cpu);
2733 if (ret < 0) {
2734 goto out;
2735 }
2736 ret = 0;
2737 out:
2738 cpu_sync_bndcs_hflags(&cpu->env);
2739 return ret;
2740 }
2741
2742 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2743 {
2744 X86CPU *x86_cpu = X86_CPU(cpu);
2745 CPUX86State *env = &x86_cpu->env;
2746 int ret;
2747
2748 /* Inject NMI */
2749 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2750 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2751 qemu_mutex_lock_iothread();
2752 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2753 qemu_mutex_unlock_iothread();
2754 DPRINTF("injected NMI\n");
2755 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2756 if (ret < 0) {
2757 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2758 strerror(-ret));
2759 }
2760 }
2761 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2762 qemu_mutex_lock_iothread();
2763 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2764 qemu_mutex_unlock_iothread();
2765 DPRINTF("injected SMI\n");
2766 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2767 if (ret < 0) {
2768 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2769 strerror(-ret));
2770 }
2771 }
2772 }
2773
2774 if (!kvm_pic_in_kernel()) {
2775 qemu_mutex_lock_iothread();
2776 }
2777
2778 /* Force the VCPU out of its inner loop to process any INIT requests
2779 * or (for userspace APIC, but it is cheap to combine the checks here)
2780 * pending TPR access reports.
2781 */
2782 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2783 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2784 !(env->hflags & HF_SMM_MASK)) {
2785 cpu->exit_request = 1;
2786 }
2787 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2788 cpu->exit_request = 1;
2789 }
2790 }
2791
2792 if (!kvm_pic_in_kernel()) {
2793 /* Try to inject an interrupt if the guest can accept it */
2794 if (run->ready_for_interrupt_injection &&
2795 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2796 (env->eflags & IF_MASK)) {
2797 int irq;
2798
2799 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2800 irq = cpu_get_pic_interrupt(env);
2801 if (irq >= 0) {
2802 struct kvm_interrupt intr;
2803
2804 intr.irq = irq;
2805 DPRINTF("injected interrupt %d\n", irq);
2806 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2807 if (ret < 0) {
2808 fprintf(stderr,
2809 "KVM: injection failed, interrupt lost (%s)\n",
2810 strerror(-ret));
2811 }
2812 }
2813 }
2814
2815 /* If we have an interrupt but the guest is not ready to receive an
2816 * interrupt, request an interrupt window exit. This will
2817 * cause a return to userspace as soon as the guest is ready to
2818 * receive interrupts. */
2819 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2820 run->request_interrupt_window = 1;
2821 } else {
2822 run->request_interrupt_window = 0;
2823 }
2824
2825 DPRINTF("setting tpr\n");
2826 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2827
2828 qemu_mutex_unlock_iothread();
2829 }
2830 }
2831
2832 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2833 {
2834 X86CPU *x86_cpu = X86_CPU(cpu);
2835 CPUX86State *env = &x86_cpu->env;
2836
2837 if (run->flags & KVM_RUN_X86_SMM) {
2838 env->hflags |= HF_SMM_MASK;
2839 } else {
2840 env->hflags &= HF_SMM_MASK;
2841 }
2842 if (run->if_flag) {
2843 env->eflags |= IF_MASK;
2844 } else {
2845 env->eflags &= ~IF_MASK;
2846 }
2847
2848 /* We need to protect the apic state against concurrent accesses from
2849 * different threads in case the userspace irqchip is used. */
2850 if (!kvm_irqchip_in_kernel()) {
2851 qemu_mutex_lock_iothread();
2852 }
2853 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2854 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2855 if (!kvm_irqchip_in_kernel()) {
2856 qemu_mutex_unlock_iothread();
2857 }
2858 return cpu_get_mem_attrs(env);
2859 }
2860
2861 int kvm_arch_process_async_events(CPUState *cs)
2862 {
2863 X86CPU *cpu = X86_CPU(cs);
2864 CPUX86State *env = &cpu->env;
2865
2866 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2867 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2868 assert(env->mcg_cap);
2869
2870 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2871
2872 kvm_cpu_synchronize_state(cs);
2873
2874 if (env->exception_injected == EXCP08_DBLE) {
2875 /* this means triple fault */
2876 qemu_system_reset_request();
2877 cs->exit_request = 1;
2878 return 0;
2879 }
2880 env->exception_injected = EXCP12_MCHK;
2881 env->has_error_code = 0;
2882
2883 cs->halted = 0;
2884 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2885 env->mp_state = KVM_MP_STATE_RUNNABLE;
2886 }
2887 }
2888
2889 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2890 !(env->hflags & HF_SMM_MASK)) {
2891 kvm_cpu_synchronize_state(cs);
2892 do_cpu_init(cpu);
2893 }
2894
2895 if (kvm_irqchip_in_kernel()) {
2896 return 0;
2897 }
2898
2899 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2900 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2901 apic_poll_irq(cpu->apic_state);
2902 }
2903 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2904 (env->eflags & IF_MASK)) ||
2905 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2906 cs->halted = 0;
2907 }
2908 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2909 kvm_cpu_synchronize_state(cs);
2910 do_cpu_sipi(cpu);
2911 }
2912 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2913 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2914 kvm_cpu_synchronize_state(cs);
2915 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2916 env->tpr_access_type);
2917 }
2918
2919 return cs->halted;
2920 }
2921
2922 static int kvm_handle_halt(X86CPU *cpu)
2923 {
2924 CPUState *cs = CPU(cpu);
2925 CPUX86State *env = &cpu->env;
2926
2927 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2928 (env->eflags & IF_MASK)) &&
2929 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2930 cs->halted = 1;
2931 return EXCP_HLT;
2932 }
2933
2934 return 0;
2935 }
2936
2937 static int kvm_handle_tpr_access(X86CPU *cpu)
2938 {
2939 CPUState *cs = CPU(cpu);
2940 struct kvm_run *run = cs->kvm_run;
2941
2942 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2943 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2944 : TPR_ACCESS_READ);
2945 return 1;
2946 }
2947
2948 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2949 {
2950 static const uint8_t int3 = 0xcc;
2951
2952 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2953 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2954 return -EINVAL;
2955 }
2956 return 0;
2957 }
2958
2959 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2960 {
2961 uint8_t int3;
2962
2963 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2964 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2965 return -EINVAL;
2966 }
2967 return 0;
2968 }
2969
2970 static struct {
2971 target_ulong addr;
2972 int len;
2973 int type;
2974 } hw_breakpoint[4];
2975
2976 static int nb_hw_breakpoint;
2977
2978 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2979 {
2980 int n;
2981
2982 for (n = 0; n < nb_hw_breakpoint; n++) {
2983 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2984 (hw_breakpoint[n].len == len || len == -1)) {
2985 return n;
2986 }
2987 }
2988 return -1;
2989 }
2990
2991 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2992 target_ulong len, int type)
2993 {
2994 switch (type) {
2995 case GDB_BREAKPOINT_HW:
2996 len = 1;
2997 break;
2998 case GDB_WATCHPOINT_WRITE:
2999 case GDB_WATCHPOINT_ACCESS:
3000 switch (len) {
3001 case 1:
3002 break;
3003 case 2:
3004 case 4:
3005 case 8:
3006 if (addr & (len - 1)) {
3007 return -EINVAL;
3008 }
3009 break;
3010 default:
3011 return -EINVAL;
3012 }
3013 break;
3014 default:
3015 return -ENOSYS;
3016 }
3017
3018 if (nb_hw_breakpoint == 4) {
3019 return -ENOBUFS;
3020 }
3021 if (find_hw_breakpoint(addr, len, type) >= 0) {
3022 return -EEXIST;
3023 }
3024 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3025 hw_breakpoint[nb_hw_breakpoint].len = len;
3026 hw_breakpoint[nb_hw_breakpoint].type = type;
3027 nb_hw_breakpoint++;
3028
3029 return 0;
3030 }
3031
3032 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3033 target_ulong len, int type)
3034 {
3035 int n;
3036
3037 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3038 if (n < 0) {
3039 return -ENOENT;
3040 }
3041 nb_hw_breakpoint--;
3042 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3043
3044 return 0;
3045 }
3046
3047 void kvm_arch_remove_all_hw_breakpoints(void)
3048 {
3049 nb_hw_breakpoint = 0;
3050 }
3051
3052 static CPUWatchpoint hw_watchpoint;
3053
3054 static int kvm_handle_debug(X86CPU *cpu,
3055 struct kvm_debug_exit_arch *arch_info)
3056 {
3057 CPUState *cs = CPU(cpu);
3058 CPUX86State *env = &cpu->env;
3059 int ret = 0;
3060 int n;
3061
3062 if (arch_info->exception == 1) {
3063 if (arch_info->dr6 & (1 << 14)) {
3064 if (cs->singlestep_enabled) {
3065 ret = EXCP_DEBUG;
3066 }
3067 } else {
3068 for (n = 0; n < 4; n++) {
3069 if (arch_info->dr6 & (1 << n)) {
3070 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3071 case 0x0:
3072 ret = EXCP_DEBUG;
3073 break;
3074 case 0x1:
3075 ret = EXCP_DEBUG;
3076 cs->watchpoint_hit = &hw_watchpoint;
3077 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3078 hw_watchpoint.flags = BP_MEM_WRITE;
3079 break;
3080 case 0x3:
3081 ret = EXCP_DEBUG;
3082 cs->watchpoint_hit = &hw_watchpoint;
3083 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3084 hw_watchpoint.flags = BP_MEM_ACCESS;
3085 break;
3086 }
3087 }
3088 }
3089 }
3090 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3091 ret = EXCP_DEBUG;
3092 }
3093 if (ret == 0) {
3094 cpu_synchronize_state(cs);
3095 assert(env->exception_injected == -1);
3096
3097 /* pass to guest */
3098 env->exception_injected = arch_info->exception;
3099 env->has_error_code = 0;
3100 }
3101
3102 return ret;
3103 }
3104
3105 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3106 {
3107 const uint8_t type_code[] = {
3108 [GDB_BREAKPOINT_HW] = 0x0,
3109 [GDB_WATCHPOINT_WRITE] = 0x1,
3110 [GDB_WATCHPOINT_ACCESS] = 0x3
3111 };
3112 const uint8_t len_code[] = {
3113 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3114 };
3115 int n;
3116
3117 if (kvm_sw_breakpoints_active(cpu)) {
3118 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3119 }
3120 if (nb_hw_breakpoint > 0) {
3121 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3122 dbg->arch.debugreg[7] = 0x0600;
3123 for (n = 0; n < nb_hw_breakpoint; n++) {
3124 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3125 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3126 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3127 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3128 }
3129 }
3130 }
3131
3132 static bool host_supports_vmx(void)
3133 {
3134 uint32_t ecx, unused;
3135
3136 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3137 return ecx & CPUID_EXT_VMX;
3138 }
3139
3140 #define VMX_INVALID_GUEST_STATE 0x80000021
3141
3142 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3143 {
3144 X86CPU *cpu = X86_CPU(cs);
3145 uint64_t code;
3146 int ret;
3147
3148 switch (run->exit_reason) {
3149 case KVM_EXIT_HLT:
3150 DPRINTF("handle_hlt\n");
3151 qemu_mutex_lock_iothread();
3152 ret = kvm_handle_halt(cpu);
3153 qemu_mutex_unlock_iothread();
3154 break;
3155 case KVM_EXIT_SET_TPR:
3156 ret = 0;
3157 break;
3158 case KVM_EXIT_TPR_ACCESS:
3159 qemu_mutex_lock_iothread();
3160 ret = kvm_handle_tpr_access(cpu);
3161 qemu_mutex_unlock_iothread();
3162 break;
3163 case KVM_EXIT_FAIL_ENTRY:
3164 code = run->fail_entry.hardware_entry_failure_reason;
3165 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3166 code);
3167 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3168 fprintf(stderr,
3169 "\nIf you're running a guest on an Intel machine without "
3170 "unrestricted mode\n"
3171 "support, the failure can be most likely due to the guest "
3172 "entering an invalid\n"
3173 "state for Intel VT. For example, the guest maybe running "
3174 "in big real mode\n"
3175 "which is not supported on less recent Intel processors."
3176 "\n\n");
3177 }
3178 ret = -1;
3179 break;
3180 case KVM_EXIT_EXCEPTION:
3181 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3182 run->ex.exception, run->ex.error_code);
3183 ret = -1;
3184 break;
3185 case KVM_EXIT_DEBUG:
3186 DPRINTF("kvm_exit_debug\n");
3187 qemu_mutex_lock_iothread();
3188 ret = kvm_handle_debug(cpu, &run->debug.arch);
3189 qemu_mutex_unlock_iothread();
3190 break;
3191 case KVM_EXIT_HYPERV:
3192 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3193 break;
3194 case KVM_EXIT_IOAPIC_EOI:
3195 ioapic_eoi_broadcast(run->eoi.vector);
3196 ret = 0;
3197 break;
3198 default:
3199 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3200 ret = -1;
3201 break;
3202 }
3203
3204 return ret;
3205 }
3206
3207 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3208 {
3209 X86CPU *cpu = X86_CPU(cs);
3210 CPUX86State *env = &cpu->env;
3211
3212 kvm_cpu_synchronize_state(cs);
3213 return !(env->cr[0] & CR0_PE_MASK) ||
3214 ((env->segs[R_CS].selector & 3) != 3);
3215 }
3216
3217 void kvm_arch_init_irq_routing(KVMState *s)
3218 {
3219 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3220 /* If kernel can't do irq routing, interrupt source
3221 * override 0->2 cannot be set up as required by HPET.
3222 * So we have to disable it.
3223 */
3224 no_hpet = 1;
3225 }
3226 /* We know at this point that we're using the in-kernel
3227 * irqchip, so we can use irqfds, and on x86 we know
3228 * we can use msi via irqfd and GSI routing.
3229 */
3230 kvm_msi_via_irqfd_allowed = true;
3231 kvm_gsi_routing_allowed = true;
3232
3233 if (kvm_irqchip_is_split()) {
3234 int i;
3235
3236 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3237 MSI routes for signaling interrupts to the local apics. */
3238 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3239 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3240 error_report("Could not enable split IRQ mode.");
3241 exit(1);
3242 }
3243 }
3244 }
3245 }
3246
3247 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3248 {
3249 int ret;
3250 if (machine_kernel_irqchip_split(ms)) {
3251 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3252 if (ret) {
3253 error_report("Could not enable split irqchip mode: %s\n",
3254 strerror(-ret));
3255 exit(1);
3256 } else {
3257 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3258 kvm_split_irqchip = true;
3259 return 1;
3260 }
3261 } else {
3262 return 0;
3263 }
3264 }
3265
3266 /* Classic KVM device assignment interface. Will remain x86 only. */
3267 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3268 uint32_t flags, uint32_t *dev_id)
3269 {
3270 struct kvm_assigned_pci_dev dev_data = {
3271 .segnr = dev_addr->domain,
3272 .busnr = dev_addr->bus,
3273 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3274 .flags = flags,
3275 };
3276 int ret;
3277
3278 dev_data.assigned_dev_id =
3279 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3280
3281 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3282 if (ret < 0) {
3283 return ret;
3284 }
3285
3286 *dev_id = dev_data.assigned_dev_id;
3287
3288 return 0;
3289 }
3290
3291 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3292 {
3293 struct kvm_assigned_pci_dev dev_data = {
3294 .assigned_dev_id = dev_id,
3295 };
3296
3297 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3298 }
3299
3300 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3301 uint32_t irq_type, uint32_t guest_irq)
3302 {
3303 struct kvm_assigned_irq assigned_irq = {
3304 .assigned_dev_id = dev_id,
3305 .guest_irq = guest_irq,
3306 .flags = irq_type,
3307 };
3308
3309 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3310 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3311 } else {
3312 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3313 }
3314 }
3315
3316 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3317 uint32_t guest_irq)
3318 {
3319 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3320 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3321
3322 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3323 }
3324
3325 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3326 {
3327 struct kvm_assigned_pci_dev dev_data = {
3328 .assigned_dev_id = dev_id,
3329 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3330 };
3331
3332 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3333 }
3334
3335 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3336 uint32_t type)
3337 {
3338 struct kvm_assigned_irq assigned_irq = {
3339 .assigned_dev_id = dev_id,
3340 .flags = type,
3341 };
3342
3343 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3344 }
3345
3346 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3347 {
3348 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3349 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3350 }
3351
3352 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3353 {
3354 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3355 KVM_DEV_IRQ_GUEST_MSI, virq);
3356 }
3357
3358 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3359 {
3360 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3361 KVM_DEV_IRQ_HOST_MSI);
3362 }
3363
3364 bool kvm_device_msix_supported(KVMState *s)
3365 {
3366 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3367 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3368 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3369 }
3370
3371 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3372 uint32_t nr_vectors)
3373 {
3374 struct kvm_assigned_msix_nr msix_nr = {
3375 .assigned_dev_id = dev_id,
3376 .entry_nr = nr_vectors,
3377 };
3378
3379 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3380 }
3381
3382 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3383 int virq)
3384 {
3385 struct kvm_assigned_msix_entry msix_entry = {
3386 .assigned_dev_id = dev_id,
3387 .gsi = virq,
3388 .entry = vector,
3389 };
3390
3391 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3392 }
3393
3394 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3395 {
3396 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3397 KVM_DEV_IRQ_GUEST_MSIX, 0);
3398 }
3399
3400 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3401 {
3402 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3403 KVM_DEV_IRQ_HOST_MSIX);
3404 }
3405
3406 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3407 uint64_t address, uint32_t data, PCIDevice *dev)
3408 {
3409 X86IOMMUState *iommu = x86_iommu_get_default();
3410
3411 if (iommu) {
3412 int ret;
3413 MSIMessage src, dst;
3414 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3415
3416 src.address = route->u.msi.address_hi;
3417 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3418 src.address |= route->u.msi.address_lo;
3419 src.data = route->u.msi.data;
3420
3421 ret = class->int_remap(iommu, &src, &dst, dev ? \
3422 pci_requester_id(dev) : \
3423 X86_IOMMU_SID_INVALID);
3424 if (ret) {
3425 trace_kvm_x86_fixup_msi_error(route->gsi);
3426 return 1;
3427 }
3428
3429 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3430 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3431 route->u.msi.data = dst.data;
3432 }
3433
3434 return 0;
3435 }
3436
3437 typedef struct MSIRouteEntry MSIRouteEntry;
3438
3439 struct MSIRouteEntry {
3440 PCIDevice *dev; /* Device pointer */
3441 int vector; /* MSI/MSIX vector index */
3442 int virq; /* Virtual IRQ index */
3443 QLIST_ENTRY(MSIRouteEntry) list;
3444 };
3445
3446 /* List of used GSI routes */
3447 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3448 QLIST_HEAD_INITIALIZER(msi_route_list);
3449
3450 static void kvm_update_msi_routes_all(void *private, bool global,
3451 uint32_t index, uint32_t mask)
3452 {
3453 int cnt = 0;
3454 MSIRouteEntry *entry;
3455 MSIMessage msg;
3456 /* TODO: explicit route update */
3457 QLIST_FOREACH(entry, &msi_route_list, list) {
3458 cnt++;
3459 msg = pci_get_msi_message(entry->dev, entry->vector);
3460 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3461 msg, entry->dev);
3462 }
3463 kvm_irqchip_commit_routes(kvm_state);
3464 trace_kvm_x86_update_msi_routes(cnt);
3465 }
3466
3467 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3468 int vector, PCIDevice *dev)
3469 {
3470 static bool notify_list_inited = false;
3471 MSIRouteEntry *entry;
3472
3473 if (!dev) {
3474 /* These are (possibly) IOAPIC routes only used for split
3475 * kernel irqchip mode, while what we are housekeeping are
3476 * PCI devices only. */
3477 return 0;
3478 }
3479
3480 entry = g_new0(MSIRouteEntry, 1);
3481 entry->dev = dev;
3482 entry->vector = vector;
3483 entry->virq = route->gsi;
3484 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3485
3486 trace_kvm_x86_add_msi_route(route->gsi);
3487
3488 if (!notify_list_inited) {
3489 /* For the first time we do add route, add ourselves into
3490 * IOMMU's IEC notify list if needed. */
3491 X86IOMMUState *iommu = x86_iommu_get_default();
3492 if (iommu) {
3493 x86_iommu_iec_register_notifier(iommu,
3494 kvm_update_msi_routes_all,
3495 NULL);
3496 }
3497 notify_list_inited = true;
3498 }
3499 return 0;
3500 }
3501
3502 int kvm_arch_release_virq_post(int virq)
3503 {
3504 MSIRouteEntry *entry, *next;
3505 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3506 if (entry->virq == virq) {
3507 trace_kvm_x86_remove_msi_route(virq);
3508 QLIST_REMOVE(entry, list);
3509 break;
3510 }
3511 }
3512 return 0;
3513 }
3514
3515 int kvm_arch_msi_data_to_gsi(uint32_t data)
3516 {
3517 abort();
3518 }
AR7 emulation for QEMU