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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / hw / pci / pci.c
blobc1806a730c6b554aae15f87e76c3e1c0876d8eb3
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/pci_bridge.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pci_host.h"
30 #include "monitor/monitor.h"
31 #include "net/net.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/loader.h"
34 #include "qemu/error-report.h"
35 #include "qemu/range.h"
36 #include "qmp-commands.h"
37 #include "trace.h"
38 #include "hw/pci/msi.h"
39 #include "hw/pci/msix.h"
40 #include "exec/address-spaces.h"
41 #include "hw/hotplug.h"
42 #include "hw/boards.h"
43 #include "qemu/cutils.h"
44
45 //#define DEBUG_PCI
46 #ifdef DEBUG_PCI
47 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
48 #else
49 # define PCI_DPRINTF(format, ...) do { } while (0)
50 #endif
51
52 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
53 static char *pcibus_get_dev_path(DeviceState *dev);
54 static char *pcibus_get_fw_dev_path(DeviceState *dev);
55 static void pcibus_reset(BusState *qbus);
56
57 static Property pci_props[] = {
58 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
59 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
60 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
61 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
62 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
63 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
64 QEMU_PCI_CAP_SERR_BITNR, true),
65 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present,
66 QEMU_PCIE_LNKSTA_DLLLA_BITNR, true),
67 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present,
68 QEMU_PCIE_EXTCAP_INIT_BITNR, true),
69 DEFINE_PROP_END_OF_LIST()
70 };
71
72 static const VMStateDescription vmstate_pcibus = {
73 .name = "PCIBUS",
74 .version_id = 1,
75 .minimum_version_id = 1,
76 .fields = (VMStateField[]) {
77 VMSTATE_INT32_EQUAL(nirq, PCIBus),
78 VMSTATE_VARRAY_INT32(irq_count, PCIBus,
79 nirq, 0, vmstate_info_int32,
80 int32_t),
81 VMSTATE_END_OF_LIST()
82 }
83 };
84
85 static void pci_init_bus_master(PCIDevice *pci_dev)
86 {
87 AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev);
88
89 memory_region_init_alias(&pci_dev->bus_master_enable_region,
90 OBJECT(pci_dev), "bus master",
91 dma_as->root, 0, memory_region_size(dma_as->root));
92 memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
93 memory_region_add_subregion(&pci_dev->bus_master_container_region, 0,
94 &pci_dev->bus_master_enable_region);
95 }
96
97 static void pcibus_machine_done(Notifier *notifier, void *data)
98 {
99 PCIBus *bus = container_of(notifier, PCIBus, machine_done);
100 int i;
101
102 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
103 if (bus->devices[i]) {
104 pci_init_bus_master(bus->devices[i]);
105 }
106 }
107 }
108
109 static void pci_bus_realize(BusState *qbus, Error **errp)
110 {
111 PCIBus *bus = PCI_BUS(qbus);
112
113 bus->machine_done.notify = pcibus_machine_done;
114 qemu_add_machine_init_done_notifier(&bus->machine_done);
115
116 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
117 }
118
119 static void pci_bus_unrealize(BusState *qbus, Error **errp)
120 {
121 PCIBus *bus = PCI_BUS(qbus);
122
123 qemu_remove_machine_init_done_notifier(&bus->machine_done);
124
125 vmstate_unregister(NULL, &vmstate_pcibus, bus);
126 }
127
128 static bool pcibus_is_root(PCIBus *bus)
129 {
130 return !bus->parent_dev;
131 }
132
133 static int pcibus_num(PCIBus *bus)
134 {
135 if (pcibus_is_root(bus)) {
136 return 0; /* pci host bridge */
137 }
138 return bus->parent_dev->config[PCI_SECONDARY_BUS];
139 }
140
141 static uint16_t pcibus_numa_node(PCIBus *bus)
142 {
143 return NUMA_NODE_UNASSIGNED;
144 }
145
146 static void pci_bus_class_init(ObjectClass *klass, void *data)
147 {
148 BusClass *k = BUS_CLASS(klass);
149 PCIBusClass *pbc = PCI_BUS_CLASS(klass);
150
151 k->print_dev = pcibus_dev_print;
152 k->get_dev_path = pcibus_get_dev_path;
153 k->get_fw_dev_path = pcibus_get_fw_dev_path;
154 k->realize = pci_bus_realize;
155 k->unrealize = pci_bus_unrealize;
156 k->reset = pcibus_reset;
157
158 pbc->is_root = pcibus_is_root;
159 pbc->bus_num = pcibus_num;
160 pbc->numa_node = pcibus_numa_node;
161 }
162
163 static const TypeInfo pci_bus_info = {
164 .name = TYPE_PCI_BUS,
165 .parent = TYPE_BUS,
166 .instance_size = sizeof(PCIBus),
167 .class_size = sizeof(PCIBusClass),
168 .class_init = pci_bus_class_init,
169 };
170
171 static const TypeInfo pcie_bus_info = {
172 .name = TYPE_PCIE_BUS,
173 .parent = TYPE_PCI_BUS,
174 };
175
176 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
177 static void pci_update_mappings(PCIDevice *d);
178 static void pci_irq_handler(void *opaque, int irq_num, int level);
179 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
180 static void pci_del_option_rom(PCIDevice *pdev);
181
182 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
183 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
184
185 static QLIST_HEAD(, PCIHostState) pci_host_bridges;
186
187 int pci_bar(PCIDevice *d, int reg)
188 {
189 uint8_t type;
190
191 if (reg != PCI_ROM_SLOT)
192 return PCI_BASE_ADDRESS_0 + reg * 4;
193
194 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
195 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
196 }
197
198 static inline int pci_irq_state(PCIDevice *d, int irq_num)
199 {
200 return (d->irq_state >> irq_num) & 0x1;
201 }
202
203 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
204 {
205 d->irq_state &= ~(0x1 << irq_num);
206 d->irq_state |= level << irq_num;
207 }
208
209 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
210 {
211 PCIBus *bus;
212 for (;;) {
213 bus = pci_dev->bus;
214 irq_num = bus->map_irq(pci_dev, irq_num);
215 if (bus->set_irq)
216 break;
217 pci_dev = bus->parent_dev;
218 }
219 bus->irq_count[irq_num] += change;
220 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
221 }
222
223 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
224 {
225 assert(irq_num >= 0);
226 assert(irq_num < bus->nirq);
227 return !!bus->irq_count[irq_num];
228 }
229
230 /* Update interrupt status bit in config space on interrupt
231 * state change. */
232 static void pci_update_irq_status(PCIDevice *dev)
233 {
234 if (dev->irq_state) {
235 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
236 } else {
237 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
238 }
239 }
240
241 void pci_device_deassert_intx(PCIDevice *dev)
242 {
243 int i;
244 for (i = 0; i < PCI_NUM_PINS; ++i) {
245 pci_irq_handler(dev, i, 0);
246 }
247 }
248
249 static void pci_do_device_reset(PCIDevice *dev)
250 {
251 int r;
252
253 pci_device_deassert_intx(dev);
254 assert(dev->irq_state == 0);
255
256 /* Clear all writable bits */
257 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
258 pci_get_word(dev->wmask + PCI_COMMAND) |
259 pci_get_word(dev->w1cmask + PCI_COMMAND));
260 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
261 pci_get_word(dev->wmask + PCI_STATUS) |
262 pci_get_word(dev->w1cmask + PCI_STATUS));
263 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
264 dev->config[PCI_INTERRUPT_LINE] = 0x0;
265 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
266 PCIIORegion *region = &dev->io_regions[r];
267 if (!region->size) {
268 continue;
269 }
270
271 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
272 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
273 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
274 } else {
275 pci_set_long(dev->config + pci_bar(dev, r), region->type);
276 }
277 }
278 pci_update_mappings(dev);
279
280 msi_reset(dev);
281 msix_reset(dev);
282 }
283
284 /*
285 * This function is called on #RST and FLR.
286 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
287 */
288 void pci_device_reset(PCIDevice *dev)
289 {
290 qdev_reset_all(&dev->qdev);
291 pci_do_device_reset(dev);
292 }
293
294 /*
295 * Trigger pci bus reset under a given bus.
296 * Called via qbus_reset_all on RST# assert, after the devices
297 * have been reset qdev_reset_all-ed already.
298 */
299 static void pcibus_reset(BusState *qbus)
300 {
301 PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus);
302 int i;
303
304 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
305 if (bus->devices[i]) {
306 pci_do_device_reset(bus->devices[i]);
307 }
308 }
309
310 for (i = 0; i < bus->nirq; i++) {
311 assert(bus->irq_count[i] == 0);
312 }
313 }
314
315 static void pci_host_bus_register(DeviceState *host)
316 {
317 PCIHostState *host_bridge = PCI_HOST_BRIDGE(host);
318
319 QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next);
320 }
321
322 PCIBus *pci_find_primary_bus(void)
323 {
324 PCIBus *primary_bus = NULL;
325 PCIHostState *host;
326
327 QLIST_FOREACH(host, &pci_host_bridges, next) {
328 if (primary_bus) {
329 /* We have multiple root buses, refuse to select a primary */
330 return NULL;
331 }
332 primary_bus = host->bus;
333 }
334
335 return primary_bus;
336 }
337
338 PCIBus *pci_device_root_bus(const PCIDevice *d)
339 {
340 PCIBus *bus = d->bus;
341
342 while (!pci_bus_is_root(bus)) {
343 d = bus->parent_dev;
344 assert(d != NULL);
345
346 bus = d->bus;
347 }
348
349 return bus;
350 }
351
352 const char *pci_root_bus_path(PCIDevice *dev)
353 {
354 PCIBus *rootbus = pci_device_root_bus(dev);
355 PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
356 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge);
357
358 assert(host_bridge->bus == rootbus);
359
360 if (hc->root_bus_path) {
361 return (*hc->root_bus_path)(host_bridge, rootbus);
362 }
363
364 return rootbus->qbus.name;
365 }
366
367 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
368 MemoryRegion *address_space_mem,
369 MemoryRegion *address_space_io,
370 uint8_t devfn_min)
371 {
372 assert(PCI_FUNC(devfn_min) == 0);
373 bus->devfn_min = devfn_min;
374 bus->address_space_mem = address_space_mem;
375 bus->address_space_io = address_space_io;
376
377 /* host bridge */
378 QLIST_INIT(&bus->child);
379
380 pci_host_bus_register(parent);
381 }
382
383 bool pci_bus_is_express(PCIBus *bus)
384 {
385 return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
386 }
387
388 bool pci_bus_is_root(PCIBus *bus)
389 {
390 return PCI_BUS_GET_CLASS(bus)->is_root(bus);
391 }
392
393 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
394 const char *name,
395 MemoryRegion *address_space_mem,
396 MemoryRegion *address_space_io,
397 uint8_t devfn_min, const char *typename)
398 {
399 qbus_create_inplace(bus, bus_size, typename, parent, name);
400 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
401 }
402
403 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
404 MemoryRegion *address_space_mem,
405 MemoryRegion *address_space_io,
406 uint8_t devfn_min, const char *typename)
407 {
408 PCIBus *bus;
409
410 bus = PCI_BUS(qbus_create(typename, parent, name));
411 pci_bus_init(bus, parent, address_space_mem, address_space_io, devfn_min);
412 return bus;
413 }
414
415 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
416 void *irq_opaque, int nirq)
417 {
418 bus->set_irq = set_irq;
419 bus->map_irq = map_irq;
420 bus->irq_opaque = irq_opaque;
421 bus->nirq = nirq;
422 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
423 }
424
425 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
426 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
427 void *irq_opaque,
428 MemoryRegion *address_space_mem,
429 MemoryRegion *address_space_io,
430 uint8_t devfn_min, int nirq, const char *typename)
431 {
432 PCIBus *bus;
433
434 bus = pci_bus_new(parent, name, address_space_mem,
435 address_space_io, devfn_min, typename);
436 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
437 return bus;
438 }
439
440 int pci_bus_num(PCIBus *s)
441 {
442 return PCI_BUS_GET_CLASS(s)->bus_num(s);
443 }
444
445 int pci_bus_numa_node(PCIBus *bus)
446 {
447 return PCI_BUS_GET_CLASS(bus)->numa_node(bus);
448 }
449
450 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size,
451 VMStateField *field)
452 {
453 PCIDevice *s = container_of(pv, PCIDevice, config);
454 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s);
455 uint8_t *config;
456 int i;
457
458 assert(size == pci_config_size(s));
459 config = g_malloc(size);
460
461 qemu_get_buffer(f, config, size);
462 for (i = 0; i < size; ++i) {
463 if ((config[i] ^ s->config[i]) &
464 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
465 error_report("%s: Bad config data: i=0x%x read: %x device: %x "
466 "cmask: %x wmask: %x w1cmask:%x", __func__,
467 i, config[i], s->config[i],
468 s->cmask[i], s->wmask[i], s->w1cmask[i]);
469 g_free(config);
470 return -EINVAL;
471 }
472 }
473 memcpy(s->config, config, size);
474
475 pci_update_mappings(s);
476 if (pc->is_bridge) {
477 PCIBridge *b = PCI_BRIDGE(s);
478 pci_bridge_update_mappings(b);
479 }
480
481 memory_region_set_enabled(&s->bus_master_enable_region,
482 pci_get_word(s->config + PCI_COMMAND)
483 & PCI_COMMAND_MASTER);
484
485 g_free(config);
486 return 0;
487 }
488
489 /* just put buffer */
490 static int put_pci_config_device(QEMUFile *f, void *pv, size_t size,
491 VMStateField *field, QJSON *vmdesc)
492 {
493 const uint8_t **v = pv;
494 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
495 qemu_put_buffer(f, *v, size);
496
497 return 0;
498 }
499
500 static VMStateInfo vmstate_info_pci_config = {
501 .name = "pci config",
502 .get = get_pci_config_device,
503 .put = put_pci_config_device,
504 };
505
506 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size,
507 VMStateField *field)
508 {
509 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
510 uint32_t irq_state[PCI_NUM_PINS];
511 int i;
512 for (i = 0; i < PCI_NUM_PINS; ++i) {
513 irq_state[i] = qemu_get_be32(f);
514 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
515 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
516 irq_state[i]);
517 return -EINVAL;
518 }
519 }
520
521 for (i = 0; i < PCI_NUM_PINS; ++i) {
522 pci_set_irq_state(s, i, irq_state[i]);
523 }
524
525 return 0;
526 }
527
528 static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size,
529 VMStateField *field, QJSON *vmdesc)
530 {
531 int i;
532 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
533
534 for (i = 0; i < PCI_NUM_PINS; ++i) {
535 qemu_put_be32(f, pci_irq_state(s, i));
536 }
537
538 return 0;
539 }
540
541 static VMStateInfo vmstate_info_pci_irq_state = {
542 .name = "pci irq state",
543 .get = get_pci_irq_state,
544 .put = put_pci_irq_state,
545 };
546
547 static bool migrate_is_pcie(void *opaque, int version_id)
548 {
549 return pci_is_express((PCIDevice *)opaque);
550 }
551
552 static bool migrate_is_not_pcie(void *opaque, int version_id)
553 {
554 return !pci_is_express((PCIDevice *)opaque);
555 }
556
557 const VMStateDescription vmstate_pci_device = {
558 .name = "PCIDevice",
559 .version_id = 2,
560 .minimum_version_id = 1,
561 .fields = (VMStateField[]) {
562 VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice),
563 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
564 migrate_is_not_pcie,
565 0, vmstate_info_pci_config,
566 PCI_CONFIG_SPACE_SIZE),
567 VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice,
568 migrate_is_pcie,
569 0, vmstate_info_pci_config,
570 PCIE_CONFIG_SPACE_SIZE),
571 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
572 vmstate_info_pci_irq_state,
573 PCI_NUM_PINS * sizeof(int32_t)),
574 VMSTATE_END_OF_LIST()
575 }
576 };
577
578
579 void pci_device_save(PCIDevice *s, QEMUFile *f)
580 {
581 /* Clear interrupt status bit: it is implicit
582 * in irq_state which we are saving.
583 * This makes us compatible with old devices
584 * which never set or clear this bit. */
585 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
586 vmstate_save_state(f, &vmstate_pci_device, s, NULL);
587 /* Restore the interrupt status bit. */
588 pci_update_irq_status(s);
589 }
590
591 int pci_device_load(PCIDevice *s, QEMUFile *f)
592 {
593 int ret;
594 ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id);
595 /* Restore the interrupt status bit. */
596 pci_update_irq_status(s);
597 return ret;
598 }
599
600 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
601 {
602 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
603 pci_default_sub_vendor_id);
604 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
605 pci_default_sub_device_id);
606 }
607
608 /*
609 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
610 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
611 */
612 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
613 unsigned int *slotp, unsigned int *funcp)
614 {
615 const char *p;
616 char *e;
617 unsigned long val;
618 unsigned long dom = 0, bus = 0;
619 unsigned int slot = 0;
620 unsigned int func = 0;
621
622 p = addr;
623 val = strtoul(p, &e, 16);
624 if (e == p)
625 return -1;
626 if (*e == ':') {
627 bus = val;
628 p = e + 1;
629 val = strtoul(p, &e, 16);
630 if (e == p)
631 return -1;
632 if (*e == ':') {
633 dom = bus;
634 bus = val;
635 p = e + 1;
636 val = strtoul(p, &e, 16);
637 if (e == p)
638 return -1;
639 }
640 }
641
642 slot = val;
643
644 if (funcp != NULL) {
645 if (*e != '.')
646 return -1;
647
648 p = e + 1;
649 val = strtoul(p, &e, 16);
650 if (e == p)
651 return -1;
652
653 func = val;
654 }
655
656 /* if funcp == NULL func is 0 */
657 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
658 return -1;
659
660 if (*e)
661 return -1;
662
663 *domp = dom;
664 *busp = bus;
665 *slotp = slot;
666 if (funcp != NULL)
667 *funcp = func;
668 return 0;
669 }
670
671 static PCIBus *pci_get_bus_devfn(int *devfnp, PCIBus *root,
672 const char *devaddr)
673 {
674 int dom, bus;
675 unsigned slot;
676
677 if (!root) {
678 fprintf(stderr, "No primary PCI bus\n");
679 return NULL;
680 }
681
682 assert(!root->parent_dev);
683
684 if (!devaddr) {
685 *devfnp = -1;
686 return pci_find_bus_nr(root, 0);
687 }
688
689 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
690 return NULL;
691 }
692
693 if (dom != 0) {
694 fprintf(stderr, "No support for non-zero PCI domains\n");
695 return NULL;
696 }
697
698 *devfnp = PCI_DEVFN(slot, 0);
699 return pci_find_bus_nr(root, bus);
700 }
701
702 static void pci_init_cmask(PCIDevice *dev)
703 {
704 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
705 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
706 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
707 dev->cmask[PCI_REVISION_ID] = 0xff;
708 dev->cmask[PCI_CLASS_PROG] = 0xff;
709 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
710 dev->cmask[PCI_HEADER_TYPE] = 0xff;
711 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
712 }
713
714 static void pci_init_wmask(PCIDevice *dev)
715 {
716 int config_size = pci_config_size(dev);
717
718 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
719 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
720 pci_set_word(dev->wmask + PCI_COMMAND,
721 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
722 PCI_COMMAND_INTX_DISABLE);
723 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
724 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
725 }
726
727 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
728 config_size - PCI_CONFIG_HEADER_SIZE);
729 }
730
731 static void pci_init_w1cmask(PCIDevice *dev)
732 {
733 /*
734 * Note: It's okay to set w1cmask even for readonly bits as
735 * long as their value is hardwired to 0.
736 */
737 pci_set_word(dev->w1cmask + PCI_STATUS,
738 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
739 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
740 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
741 }
742
743 static void pci_init_mask_bridge(PCIDevice *d)
744 {
745 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
746 PCI_SEC_LETENCY_TIMER */
747 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
748
749 /* base and limit */
750 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
751 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
752 pci_set_word(d->wmask + PCI_MEMORY_BASE,
753 PCI_MEMORY_RANGE_MASK & 0xffff);
754 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
755 PCI_MEMORY_RANGE_MASK & 0xffff);
756 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
757 PCI_PREF_RANGE_MASK & 0xffff);
758 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
759 PCI_PREF_RANGE_MASK & 0xffff);
760
761 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
762 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
763
764 /* Supported memory and i/o types */
765 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
766 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
767 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
768 PCI_PREF_RANGE_TYPE_64);
769 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
770 PCI_PREF_RANGE_TYPE_64);
771
772 /*
773 * TODO: Bridges default to 10-bit VGA decoding but we currently only
774 * implement 16-bit decoding (no alias support).
775 */
776 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
777 PCI_BRIDGE_CTL_PARITY |
778 PCI_BRIDGE_CTL_SERR |
779 PCI_BRIDGE_CTL_ISA |
780 PCI_BRIDGE_CTL_VGA |
781 PCI_BRIDGE_CTL_VGA_16BIT |
782 PCI_BRIDGE_CTL_MASTER_ABORT |
783 PCI_BRIDGE_CTL_BUS_RESET |
784 PCI_BRIDGE_CTL_FAST_BACK |
785 PCI_BRIDGE_CTL_DISCARD |
786 PCI_BRIDGE_CTL_SEC_DISCARD |
787 PCI_BRIDGE_CTL_DISCARD_SERR);
788 /* Below does not do anything as we never set this bit, put here for
789 * completeness. */
790 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
791 PCI_BRIDGE_CTL_DISCARD_STATUS);
792 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
793 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
794 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
795 PCI_PREF_RANGE_TYPE_MASK);
796 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
797 PCI_PREF_RANGE_TYPE_MASK);
798 }
799
800 static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp)
801 {
802 uint8_t slot = PCI_SLOT(dev->devfn);
803 uint8_t func;
804
805 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
806 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
807 }
808
809 /*
810 * multifunction bit is interpreted in two ways as follows.
811 * - all functions must set the bit to 1.
812 * Example: Intel X53
813 * - function 0 must set the bit, but the rest function (> 0)
814 * is allowed to leave the bit to 0.
815 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
816 *
817 * So OS (at least Linux) checks the bit of only function 0,
818 * and doesn't see the bit of function > 0.
819 *
820 * The below check allows both interpretation.
821 */
822 if (PCI_FUNC(dev->devfn)) {
823 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
824 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
825 /* function 0 should set multifunction bit */
826 error_setg(errp, "PCI: single function device can't be populated "
827 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
828 return;
829 }
830 return;
831 }
832
833 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
834 return;
835 }
836 /* function 0 indicates single function, so function > 0 must be NULL */
837 for (func = 1; func < PCI_FUNC_MAX; ++func) {
838 if (bus->devices[PCI_DEVFN(slot, func)]) {
839 error_setg(errp, "PCI: %x.0 indicates single function, "
840 "but %x.%x is already populated.",
841 slot, slot, func);
842 return;
843 }
844 }
845 }
846
847 static void pci_config_alloc(PCIDevice *pci_dev)
848 {
849 int config_size = pci_config_size(pci_dev);
850
851 pci_dev->config = g_malloc0(config_size);
852 pci_dev->cmask = g_malloc0(config_size);
853 pci_dev->wmask = g_malloc0(config_size);
854 pci_dev->w1cmask = g_malloc0(config_size);
855 pci_dev->used = g_malloc0(config_size);
856 }
857
858 static void pci_config_free(PCIDevice *pci_dev)
859 {
860 g_free(pci_dev->config);
861 g_free(pci_dev->cmask);
862 g_free(pci_dev->wmask);
863 g_free(pci_dev->w1cmask);
864 g_free(pci_dev->used);
865 }
866
867 static void do_pci_unregister_device(PCIDevice *pci_dev)
868 {
869 pci_dev->bus->devices[pci_dev->devfn] = NULL;
870 pci_config_free(pci_dev);
871
872 memory_region_del_subregion(&pci_dev->bus_master_container_region,
873 &pci_dev->bus_master_enable_region);
874 address_space_destroy(&pci_dev->bus_master_as);
875 }
876
877 /* Extract PCIReqIDCache into BDF format */
878 static uint16_t pci_req_id_cache_extract(PCIReqIDCache *cache)
879 {
880 uint8_t bus_n;
881 uint16_t result;
882
883 switch (cache->type) {
884 case PCI_REQ_ID_BDF:
885 result = pci_get_bdf(cache->dev);
886 break;
887 case PCI_REQ_ID_SECONDARY_BUS:
888 bus_n = pci_bus_num(cache->dev->bus);
889 result = PCI_BUILD_BDF(bus_n, 0);
890 break;
891 default:
892 error_printf("Invalid PCI requester ID cache type: %d\n",
893 cache->type);
894 exit(1);
895 break;
896 }
897
898 return result;
899 }
900
901 /* Parse bridges up to the root complex and return requester ID
902 * cache for specific device. For full PCIe topology, the cache
903 * result would be exactly the same as getting BDF of the device.
904 * However, several tricks are required when system mixed up with
905 * legacy PCI devices and PCIe-to-PCI bridges.
906 *
907 * Here we cache the proxy device (and type) not requester ID since
908 * bus number might change from time to time.
909 */
910 static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev)
911 {
912 PCIDevice *parent;
913 PCIReqIDCache cache = {
914 .dev = dev,
915 .type = PCI_REQ_ID_BDF,
916 };
917
918 while (!pci_bus_is_root(dev->bus)) {
919 /* We are under PCI/PCIe bridges */
920 parent = dev->bus->parent_dev;
921 if (pci_is_express(parent)) {
922 if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) {
923 /* When we pass through PCIe-to-PCI/PCIX bridges, we
924 * override the requester ID using secondary bus
925 * number of parent bridge with zeroed devfn
926 * (pcie-to-pci bridge spec chap 2.3). */
927 cache.type = PCI_REQ_ID_SECONDARY_BUS;
928 cache.dev = dev;
929 }
930 } else {
931 /* Legacy PCI, override requester ID with the bridge's
932 * BDF upstream. When the root complex connects to
933 * legacy PCI devices (including buses), it can only
934 * obtain requester ID info from directly attached
935 * devices. If devices are attached under bridges, only
936 * the requester ID of the bridge that is directly
937 * attached to the root complex can be recognized. */
938 cache.type = PCI_REQ_ID_BDF;
939 cache.dev = parent;
940 }
941 dev = parent;
942 }
943
944 return cache;
945 }
946
947 uint16_t pci_requester_id(PCIDevice *dev)
948 {
949 return pci_req_id_cache_extract(&dev->requester_id_cache);
950 }
951
952 /* -1 for devfn means auto assign */
953 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
954 const char *name, int devfn,
955 Error **errp)
956 {
957 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
958 PCIConfigReadFunc *config_read = pc->config_read;
959 PCIConfigWriteFunc *config_write = pc->config_write;
960 Error *local_err = NULL;
961 DeviceState *dev = DEVICE(pci_dev);
962
963 pci_dev->bus = bus;
964 /* Only pci bridges can be attached to extra PCI root buses */
965 if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) {
966 error_setg(errp,
967 "PCI: Only PCI/PCIe bridges can be plugged into %s",
968 bus->parent_dev->name);
969 return NULL;
970 }
971
972 if (devfn < 0) {
973 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
974 devfn += PCI_FUNC_MAX) {
975 if (!bus->devices[devfn])
976 goto found;
977 }
978 error_setg(errp, "PCI: no slot/function available for %s, all in use",
979 name);
980 return NULL;
981 found: ;
982 } else if (bus->devices[devfn]) {
983 error_setg(errp, "PCI: slot %d function %d not available for %s,"
984 " in use by %s",
985 PCI_SLOT(devfn), PCI_FUNC(devfn), name,
986 bus->devices[devfn]->name);
987 return NULL;
988 } else if (dev->hotplugged &&
989 pci_get_function_0(pci_dev)) {
990 error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s,"
991 " new func %s cannot be exposed to guest.",
992 PCI_SLOT(pci_get_function_0(pci_dev)->devfn),
993 pci_get_function_0(pci_dev)->name,
994 name);
995
996 return NULL;
997 }
998
999 pci_dev->devfn = devfn;
1000 pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev);
1001
1002 memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
1003 "bus master container", UINT64_MAX);
1004 address_space_init(&pci_dev->bus_master_as,
1005 &pci_dev->bus_master_container_region, pci_dev->name);
1006
1007 if (qdev_hotplug) {
1008 pci_init_bus_master(pci_dev);
1009 }
1010 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
1011 pci_dev->irq_state = 0;
1012 pci_config_alloc(pci_dev);
1013
1014 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
1015 pci_config_set_device_id(pci_dev->config, pc->device_id);
1016 pci_config_set_revision(pci_dev->config, pc->revision);
1017 pci_config_set_class(pci_dev->config, pc->class_id);
1018
1019 if (!pc->is_bridge) {
1020 if (pc->subsystem_vendor_id || pc->subsystem_id) {
1021 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1022 pc->subsystem_vendor_id);
1023 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1024 pc->subsystem_id);
1025 } else {
1026 pci_set_default_subsystem_id(pci_dev);
1027 }
1028 } else {
1029 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
1030 assert(!pc->subsystem_vendor_id);
1031 assert(!pc->subsystem_id);
1032 }
1033 pci_init_cmask(pci_dev);
1034 pci_init_wmask(pci_dev);
1035 pci_init_w1cmask(pci_dev);
1036 if (pc->is_bridge) {
1037 pci_init_mask_bridge(pci_dev);
1038 }
1039 pci_init_multifunction(bus, pci_dev, &local_err);
1040 if (local_err) {
1041 error_propagate(errp, local_err);
1042 do_pci_unregister_device(pci_dev);
1043 return NULL;
1044 }
1045
1046 if (!config_read)
1047 config_read = pci_default_read_config;
1048 if (!config_write)
1049 config_write = pci_default_write_config;
1050 pci_dev->config_read = config_read;
1051 pci_dev->config_write = config_write;
1052 bus->devices[devfn] = pci_dev;
1053 pci_dev->version_id = 2; /* Current pci device vmstate version */
1054 return pci_dev;
1055 }
1056
1057 static void pci_unregister_io_regions(PCIDevice *pci_dev)
1058 {
1059 PCIIORegion *r;
1060 int i;
1061
1062 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1063 r = &pci_dev->io_regions[i];
1064 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
1065 continue;
1066 memory_region_del_subregion(r->address_space, r->memory);
1067 }
1068
1069 pci_unregister_vga(pci_dev);
1070 }
1071
1072 static void pci_qdev_unrealize(DeviceState *dev, Error **errp)
1073 {
1074 PCIDevice *pci_dev = PCI_DEVICE(dev);
1075 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1076
1077 pci_unregister_io_regions(pci_dev);
1078 pci_del_option_rom(pci_dev);
1079
1080 if (pc->exit) {
1081 pc->exit(pci_dev);
1082 }
1083
1084 do_pci_unregister_device(pci_dev);
1085 }
1086
1087 void pci_register_bar(PCIDevice *pci_dev, int region_num,
1088 uint8_t type, MemoryRegion *memory)
1089 {
1090 PCIIORegion *r;
1091 uint32_t addr; /* offset in pci config space */
1092 uint64_t wmask;
1093 pcibus_t size = memory_region_size(memory);
1094
1095 g_assert(region_num >= 0);
1096 g_assert(region_num < PCI_NUM_REGIONS);
1097 if (size & (size-1)) {
1098 fprintf(stderr, "ERROR: PCI region size must be pow2 "
1099 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
1100 exit(1);
1101 }
1102
1103 r = &pci_dev->io_regions[region_num];
1104 r->addr = PCI_BAR_UNMAPPED;
1105 r->size = size;
1106 r->type = type;
1107 r->memory = memory;
1108 r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO
1109 ? pci_dev->bus->address_space_io
1110 : pci_dev->bus->address_space_mem;
1111
1112 wmask = ~(size - 1);
1113 if (region_num == PCI_ROM_SLOT) {
1114 /* ROM enable bit is writable */
1115 wmask |= PCI_ROM_ADDRESS_ENABLE;
1116 }
1117
1118 addr = pci_bar(pci_dev, region_num);
1119 pci_set_long(pci_dev->config + addr, type);
1120
1121 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
1122 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1123 pci_set_quad(pci_dev->wmask + addr, wmask);
1124 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
1125 } else {
1126 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
1127 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
1128 }
1129 }
1130
1131 static void pci_update_vga(PCIDevice *pci_dev)
1132 {
1133 uint16_t cmd;
1134
1135 if (!pci_dev->has_vga) {
1136 return;
1137 }
1138
1139 cmd = pci_get_word(pci_dev->config + PCI_COMMAND);
1140
1141 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM],
1142 cmd & PCI_COMMAND_MEMORY);
1143 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO],
1144 cmd & PCI_COMMAND_IO);
1145 memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI],
1146 cmd & PCI_COMMAND_IO);
1147 }
1148
1149 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
1150 MemoryRegion *io_lo, MemoryRegion *io_hi)
1151 {
1152 assert(!pci_dev->has_vga);
1153
1154 assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE);
1155 pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem;
1156 memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem,
1157 QEMU_PCI_VGA_MEM_BASE, mem, 1);
1158
1159 assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE);
1160 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo;
1161 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1162 QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
1163
1164 assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE);
1165 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi;
1166 memory_region_add_subregion_overlap(pci_dev->bus->address_space_io,
1167 QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
1168 pci_dev->has_vga = true;
1169
1170 pci_update_vga(pci_dev);
1171 }
1172
1173 void pci_unregister_vga(PCIDevice *pci_dev)
1174 {
1175 if (!pci_dev->has_vga) {
1176 return;
1177 }
1178
1179 memory_region_del_subregion(pci_dev->bus->address_space_mem,
1180 pci_dev->vga_regions[QEMU_PCI_VGA_MEM]);
1181 memory_region_del_subregion(pci_dev->bus->address_space_io,
1182 pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]);
1183 memory_region_del_subregion(pci_dev->bus->address_space_io,
1184 pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]);
1185 pci_dev->has_vga = false;
1186 }
1187
1188 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
1189 {
1190 return pci_dev->io_regions[region_num].addr;
1191 }
1192
1193 static pcibus_t pci_bar_address(PCIDevice *d,
1194 int reg, uint8_t type, pcibus_t size)
1195 {
1196 pcibus_t new_addr, last_addr;
1197 int bar = pci_bar(d, reg);
1198 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
1199 Object *machine = qdev_get_machine();
1200 ObjectClass *oc = object_get_class(machine);
1201 MachineClass *mc = MACHINE_CLASS(oc);
1202 bool allow_0_address = mc->pci_allow_0_address;
1203
1204 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
1205 if (!(cmd & PCI_COMMAND_IO)) {
1206 return PCI_BAR_UNMAPPED;
1207 }
1208 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
1209 last_addr = new_addr + size - 1;
1210 /* Check if 32 bit BAR wraps around explicitly.
1211 * TODO: make priorities correct and remove this work around.
1212 */
1213 if (last_addr <= new_addr || last_addr >= UINT32_MAX ||
1214 (!allow_0_address && new_addr == 0)) {
1215 return PCI_BAR_UNMAPPED;
1216 }
1217 return new_addr;
1218 }
1219
1220 if (!(cmd & PCI_COMMAND_MEMORY)) {
1221 return PCI_BAR_UNMAPPED;
1222 }
1223 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1224 new_addr = pci_get_quad(d->config + bar);
1225 } else {
1226 new_addr = pci_get_long(d->config + bar);
1227 }
1228 /* the ROM slot has a specific enable bit */
1229 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
1230 return PCI_BAR_UNMAPPED;
1231 }
1232 new_addr &= ~(size - 1);
1233 last_addr = new_addr + size - 1;
1234 /* NOTE: we do not support wrapping */
1235 /* XXX: as we cannot support really dynamic
1236 mappings, we handle specific values as invalid
1237 mappings. */
1238 if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED ||
1239 (!allow_0_address && new_addr == 0)) {
1240 return PCI_BAR_UNMAPPED;
1241 }
1242
1243 /* Now pcibus_t is 64bit.
1244 * Check if 32 bit BAR wraps around explicitly.
1245 * Without this, PC ide doesn't work well.
1246 * TODO: remove this work around.
1247 */
1248 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
1249 return PCI_BAR_UNMAPPED;
1250 }
1251
1252 /*
1253 * OS is allowed to set BAR beyond its addressable
1254 * bits. For example, 32 bit OS can set 64bit bar
1255 * to >4G. Check it. TODO: we might need to support
1256 * it in the future for e.g. PAE.
1257 */
1258 if (last_addr >= HWADDR_MAX) {
1259 return PCI_BAR_UNMAPPED;
1260 }
1261
1262 return new_addr;
1263 }
1264
1265 static void pci_update_mappings(PCIDevice *d)
1266 {
1267 PCIIORegion *r;
1268 int i;
1269 pcibus_t new_addr;
1270
1271 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1272 r = &d->io_regions[i];
1273
1274 /* this region isn't registered */
1275 if (!r->size)
1276 continue;
1277
1278 new_addr = pci_bar_address(d, i, r->type, r->size);
1279
1280 /* This bar isn't changed */
1281 if (new_addr == r->addr)
1282 continue;
1283
1284 /* now do the real mapping */
1285 if (r->addr != PCI_BAR_UNMAPPED) {
1286 trace_pci_update_mappings_del(d, pci_bus_num(d->bus),
1287 PCI_SLOT(d->devfn),
1288 PCI_FUNC(d->devfn),
1289 i, r->addr, r->size);
1290 memory_region_del_subregion(r->address_space, r->memory);
1291 }
1292 r->addr = new_addr;
1293 if (r->addr != PCI_BAR_UNMAPPED) {
1294 trace_pci_update_mappings_add(d, pci_bus_num(d->bus),
1295 PCI_SLOT(d->devfn),
1296 PCI_FUNC(d->devfn),
1297 i, r->addr, r->size);
1298 memory_region_add_subregion_overlap(r->address_space,
1299 r->addr, r->memory, 1);
1300 }
1301 }
1302
1303 pci_update_vga(d);
1304 }
1305
1306 static inline int pci_irq_disabled(PCIDevice *d)
1307 {
1308 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1309 }
1310
1311 /* Called after interrupt disabled field update in config space,
1312 * assert/deassert interrupts if necessary.
1313 * Gets original interrupt disable bit value (before update). */
1314 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1315 {
1316 int i, disabled = pci_irq_disabled(d);
1317 if (disabled == was_irq_disabled)
1318 return;
1319 for (i = 0; i < PCI_NUM_PINS; ++i) {
1320 int state = pci_irq_state(d, i);
1321 pci_change_irq_level(d, i, disabled ? -state : state);
1322 }
1323 }
1324
1325 uint32_t pci_default_read_config(PCIDevice *d,
1326 uint32_t address, int len)
1327 {
1328 uint32_t val = 0;
1329
1330 memcpy(&val, d->config + address, len);
1331 return le32_to_cpu(val);
1332 }
1333
1334 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l)
1335 {
1336 int i, was_irq_disabled = pci_irq_disabled(d);
1337 uint32_t val = val_in;
1338
1339 for (i = 0; i < l; val >>= 8, ++i) {
1340 uint8_t wmask = d->wmask[addr + i];
1341 uint8_t w1cmask = d->w1cmask[addr + i];
1342 assert(!(wmask & w1cmask));
1343 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1344 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1345 }
1346 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1347 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1348 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1349 range_covers_byte(addr, l, PCI_COMMAND))
1350 pci_update_mappings(d);
1351
1352 if (range_covers_byte(addr, l, PCI_COMMAND)) {
1353 pci_update_irq_disabled(d, was_irq_disabled);
1354 memory_region_set_enabled(&d->bus_master_enable_region,
1355 pci_get_word(d->config + PCI_COMMAND)
1356 & PCI_COMMAND_MASTER);
1357 }
1358
1359 msi_write_config(d, addr, val_in, l);
1360 msix_write_config(d, addr, val_in, l);
1361 }
1362
1363 /***********************************************************/
1364 /* generic PCI irq support */
1365
1366 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1367 static void pci_irq_handler(void *opaque, int irq_num, int level)
1368 {
1369 PCIDevice *pci_dev = opaque;
1370 int change;
1371
1372 change = level - pci_irq_state(pci_dev, irq_num);
1373 if (!change)
1374 return;
1375
1376 pci_set_irq_state(pci_dev, irq_num, level);
1377 pci_update_irq_status(pci_dev);
1378 if (pci_irq_disabled(pci_dev))
1379 return;
1380 pci_change_irq_level(pci_dev, irq_num, change);
1381 }
1382
1383 static inline int pci_intx(PCIDevice *pci_dev)
1384 {
1385 return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
1386 }
1387
1388 qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
1389 {
1390 int intx = pci_intx(pci_dev);
1391
1392 return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
1393 }
1394
1395 void pci_set_irq(PCIDevice *pci_dev, int level)
1396 {
1397 int intx = pci_intx(pci_dev);
1398 pci_irq_handler(pci_dev, intx, level);
1399 }
1400
1401 /* Special hooks used by device assignment */
1402 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
1403 {
1404 assert(pci_bus_is_root(bus));
1405 bus->route_intx_to_irq = route_intx_to_irq;
1406 }
1407
1408 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
1409 {
1410 PCIBus *bus;
1411
1412 do {
1413 bus = dev->bus;
1414 pin = bus->map_irq(dev, pin);
1415 dev = bus->parent_dev;
1416 } while (dev);
1417
1418 if (!bus->route_intx_to_irq) {
1419 error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
1420 object_get_typename(OBJECT(bus->qbus.parent)));
1421 return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 };
1422 }
1423
1424 return bus->route_intx_to_irq(bus->irq_opaque, pin);
1425 }
1426
1427 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
1428 {
1429 return old->mode != new->mode || old->irq != new->irq;
1430 }
1431
1432 void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
1433 {
1434 PCIDevice *dev;
1435 PCIBus *sec;
1436 int i;
1437
1438 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1439 dev = bus->devices[i];
1440 if (dev && dev->intx_routing_notifier) {
1441 dev->intx_routing_notifier(dev);
1442 }
1443 }
1444
1445 QLIST_FOREACH(sec, &bus->child, sibling) {
1446 pci_bus_fire_intx_routing_notifier(sec);
1447 }
1448 }
1449
1450 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
1451 PCIINTxRoutingNotifier notifier)
1452 {
1453 dev->intx_routing_notifier = notifier;
1454 }
1455
1456 /*
1457 * PCI-to-PCI bridge specification
1458 * 9.1: Interrupt routing. Table 9-1
1459 *
1460 * the PCI Express Base Specification, Revision 2.1
1461 * 2.2.8.1: INTx interrutp signaling - Rules
1462 * the Implementation Note
1463 * Table 2-20
1464 */
1465 /*
1466 * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
1467 * 0-origin unlike PCI interrupt pin register.
1468 */
1469 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
1470 {
1471 return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
1472 }
1473
1474 /***********************************************************/
1475 /* monitor info on PCI */
1476
1477 typedef struct {
1478 uint16_t class;
1479 const char *desc;
1480 const char *fw_name;
1481 uint16_t fw_ign_bits;
1482 } pci_class_desc;
1483
1484 static const pci_class_desc pci_class_descriptions[] =
1485 {
1486 { 0x0001, "VGA controller", "display"},
1487 { 0x0100, "SCSI controller", "scsi"},
1488 { 0x0101, "IDE controller", "ide"},
1489 { 0x0102, "Floppy controller", "fdc"},
1490 { 0x0103, "IPI controller", "ipi"},
1491 { 0x0104, "RAID controller", "raid"},
1492 { 0x0106, "SATA controller"},
1493 { 0x0107, "SAS controller"},
1494 { 0x0180, "Storage controller"},
1495 { 0x0200, "Ethernet controller", "ethernet"},
1496 { 0x0201, "Token Ring controller", "token-ring"},
1497 { 0x0202, "FDDI controller", "fddi"},
1498 { 0x0203, "ATM controller", "atm"},
1499 { 0x0280, "Network controller"},
1500 { 0x0300, "VGA controller", "display", 0x00ff},
1501 { 0x0301, "XGA controller"},
1502 { 0x0302, "3D controller"},
1503 { 0x0380, "Display controller"},
1504 { 0x0400, "Video controller", "video"},
1505 { 0x0401, "Audio controller", "sound"},
1506 { 0x0402, "Phone"},
1507 { 0x0403, "Audio controller", "sound"},
1508 { 0x0480, "Multimedia controller"},
1509 { 0x0500, "RAM controller", "memory"},
1510 { 0x0501, "Flash controller", "flash"},
1511 { 0x0580, "Memory controller"},
1512 { 0x0600, "Host bridge", "host"},
1513 { 0x0601, "ISA bridge", "isa"},
1514 { 0x0602, "EISA bridge", "eisa"},
1515 { 0x0603, "MC bridge", "mca"},
1516 { 0x0604, "PCI bridge", "pci-bridge"},
1517 { 0x0605, "PCMCIA bridge", "pcmcia"},
1518 { 0x0606, "NUBUS bridge", "nubus"},
1519 { 0x0607, "CARDBUS bridge", "cardbus"},
1520 { 0x0608, "RACEWAY bridge"},
1521 { 0x0680, "Bridge"},
1522 { 0x0700, "Serial port", "serial"},
1523 { 0x0701, "Parallel port", "parallel"},
1524 { 0x0800, "Interrupt controller", "interrupt-controller"},
1525 { 0x0801, "DMA controller", "dma-controller"},
1526 { 0x0802, "Timer", "timer"},
1527 { 0x0803, "RTC", "rtc"},
1528 { 0x0900, "Keyboard", "keyboard"},
1529 { 0x0901, "Pen", "pen"},
1530 { 0x0902, "Mouse", "mouse"},
1531 { 0x0A00, "Dock station", "dock", 0x00ff},
1532 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1533 { 0x0c00, "Fireware contorller", "fireware"},
1534 { 0x0c01, "Access bus controller", "access-bus"},
1535 { 0x0c02, "SSA controller", "ssa"},
1536 { 0x0c03, "USB controller", "usb"},
1537 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1538 { 0x0c05, "SMBus"},
1539 { 0, NULL}
1540 };
1541
1542 static void pci_for_each_device_under_bus_reverse(PCIBus *bus,
1543 void (*fn)(PCIBus *b,
1544 PCIDevice *d,
1545 void *opaque),
1546 void *opaque)
1547 {
1548 PCIDevice *d;
1549 int devfn;
1550
1551 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1552 d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn];
1553 if (d) {
1554 fn(bus, d, opaque);
1555 }
1556 }
1557 }
1558
1559 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
1560 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1561 void *opaque)
1562 {
1563 bus = pci_find_bus_nr(bus, bus_num);
1564
1565 if (bus) {
1566 pci_for_each_device_under_bus_reverse(bus, fn, opaque);
1567 }
1568 }
1569
1570 static void pci_for_each_device_under_bus(PCIBus *bus,
1571 void (*fn)(PCIBus *b, PCIDevice *d,
1572 void *opaque),
1573 void *opaque)
1574 {
1575 PCIDevice *d;
1576 int devfn;
1577
1578 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1579 d = bus->devices[devfn];
1580 if (d) {
1581 fn(bus, d, opaque);
1582 }
1583 }
1584 }
1585
1586 void pci_for_each_device(PCIBus *bus, int bus_num,
1587 void (*fn)(PCIBus *b, PCIDevice *d, void *opaque),
1588 void *opaque)
1589 {
1590 bus = pci_find_bus_nr(bus, bus_num);
1591
1592 if (bus) {
1593 pci_for_each_device_under_bus(bus, fn, opaque);
1594 }
1595 }
1596
1597 static const pci_class_desc *get_class_desc(int class)
1598 {
1599 const pci_class_desc *desc;
1600
1601 desc = pci_class_descriptions;
1602 while (desc->desc && class != desc->class) {
1603 desc++;
1604 }
1605
1606 return desc;
1607 }
1608
1609 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1610
1611 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1612 {
1613 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1614 int i;
1615
1616 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1617 const PCIIORegion *r = &dev->io_regions[i];
1618 PciMemoryRegionList *region;
1619
1620 if (!r->size) {
1621 continue;
1622 }
1623
1624 region = g_malloc0(sizeof(*region));
1625 region->value = g_malloc0(sizeof(*region->value));
1626
1627 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1628 region->value->type = g_strdup("io");
1629 } else {
1630 region->value->type = g_strdup("memory");
1631 region->value->has_prefetch = true;
1632 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1633 region->value->has_mem_type_64 = true;
1634 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1635 }
1636
1637 region->value->bar = i;
1638 region->value->address = r->addr;
1639 region->value->size = r->size;
1640
1641 /* XXX: waiting for the qapi to support GSList */
1642 if (!cur_item) {
1643 head = cur_item = region;
1644 } else {
1645 cur_item->next = region;
1646 cur_item = region;
1647 }
1648 }
1649
1650 return head;
1651 }
1652
1653 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1654 int bus_num)
1655 {
1656 PciBridgeInfo *info;
1657 PciMemoryRange *range;
1658
1659 info = g_new0(PciBridgeInfo, 1);
1660
1661 info->bus = g_new0(PciBusInfo, 1);
1662 info->bus->number = dev->config[PCI_PRIMARY_BUS];
1663 info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
1664 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
1665
1666 range = info->bus->io_range = g_new0(PciMemoryRange, 1);
1667 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1668 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1669
1670 range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
1671 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1672 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1673
1674 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
1675 range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1676 range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1677
1678 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1679 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1680 if (child_bus) {
1681 info->has_devices = true;
1682 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1683 }
1684 }
1685
1686 return info;
1687 }
1688
1689 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1690 int bus_num)
1691 {
1692 const pci_class_desc *desc;
1693 PciDeviceInfo *info;
1694 uint8_t type;
1695 int class;
1696
1697 info = g_new0(PciDeviceInfo, 1);
1698 info->bus = bus_num;
1699 info->slot = PCI_SLOT(dev->devfn);
1700 info->function = PCI_FUNC(dev->devfn);
1701
1702 info->class_info = g_new0(PciDeviceClass, 1);
1703 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1704 info->class_info->q_class = class;
1705 desc = get_class_desc(class);
1706 if (desc->desc) {
1707 info->class_info->has_desc = true;
1708 info->class_info->desc = g_strdup(desc->desc);
1709 }
1710
1711 info->id = g_new0(PciDeviceId, 1);
1712 info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1713 info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
1714 info->regions = qmp_query_pci_regions(dev);
1715 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1716
1717 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1718 info->has_irq = true;
1719 info->irq = dev->config[PCI_INTERRUPT_LINE];
1720 }
1721
1722 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1723 if (type == PCI_HEADER_TYPE_BRIDGE) {
1724 info->has_pci_bridge = true;
1725 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1726 }
1727
1728 return info;
1729 }
1730
1731 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1732 {
1733 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1734 PCIDevice *dev;
1735 int devfn;
1736
1737 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1738 dev = bus->devices[devfn];
1739 if (dev) {
1740 info = g_malloc0(sizeof(*info));
1741 info->value = qmp_query_pci_device(dev, bus, bus_num);
1742
1743 /* XXX: waiting for the qapi to support GSList */
1744 if (!cur_item) {
1745 head = cur_item = info;
1746 } else {
1747 cur_item->next = info;
1748 cur_item = info;
1749 }
1750 }
1751 }
1752
1753 return head;
1754 }
1755
1756 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1757 {
1758 PciInfo *info = NULL;
1759
1760 bus = pci_find_bus_nr(bus, bus_num);
1761 if (bus) {
1762 info = g_malloc0(sizeof(*info));
1763 info->bus = bus_num;
1764 info->devices = qmp_query_pci_devices(bus, bus_num);
1765 }
1766
1767 return info;
1768 }
1769
1770 PciInfoList *qmp_query_pci(Error **errp)
1771 {
1772 PciInfoList *info, *head = NULL, *cur_item = NULL;
1773 PCIHostState *host_bridge;
1774
1775 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
1776 info = g_malloc0(sizeof(*info));
1777 info->value = qmp_query_pci_bus(host_bridge->bus,
1778 pci_bus_num(host_bridge->bus));
1779
1780 /* XXX: waiting for the qapi to support GSList */
1781 if (!cur_item) {
1782 head = cur_item = info;
1783 } else {
1784 cur_item->next = info;
1785 cur_item = info;
1786 }
1787 }
1788
1789 return head;
1790 }
1791
1792 static const char * const pci_nic_models[] = {
1793 #if !defined(CONFIG_WIN32)
1794 "atheros_wlan",
1795 #endif
1796 "dp83816",
1797 "e100",
1798 "ne2k_pci",
1799 "i82551",
1800 "i82557a",
1801 "i82557b",
1802 "i82557c",
1803 "i82558b",
1804 "i82559c",
1805 "i82559er",
1806 "i82801",
1807 "rtl8139",
1808 "e1000",
1809 "pcnet",
1810 "tnetw1130",
1811 "virtio",
1812 NULL
1813 };
1814
1815 static const char * const pci_nic_names[] = {
1816 #if !defined(CONFIG_WIN32)
1817 "atheros_wlan",
1818 #endif
1819 "dp83816",
1820 "e100",
1821 "ne2k_pci",
1822 "i82551",
1823 "i82557a",
1824 "i82557b",
1825 "i82557c",
1826 "i82558b",
1827 "i82559c",
1828 "i82559er",
1829 "i82801",
1830 "rtl8139",
1831 "e1000",
1832 "pcnet",
1833 "tnetw1130",
1834 "virtio-net-pci",
1835 NULL
1836 };
1837
1838 /* Initialize a PCI NIC. */
1839 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
1840 const char *default_model,
1841 const char *default_devaddr)
1842 {
1843 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1844 PCIBus *bus;
1845 PCIDevice *pci_dev;
1846 DeviceState *dev;
1847 int devfn;
1848 int i;
1849
1850 if (qemu_show_nic_models(nd->model, pci_nic_models)) {
1851 exit(0);
1852 }
1853
1854 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1855 if (i < 0) {
1856 exit(1);
1857 }
1858
1859 bus = pci_get_bus_devfn(&devfn, rootbus, devaddr);
1860 if (!bus) {
1861 error_report("Invalid PCI device address %s for device %s",
1862 devaddr, pci_nic_names[i]);
1863 exit(1);
1864 }
1865
1866 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1867 dev = &pci_dev->qdev;
1868 qdev_set_nic_properties(dev, nd);
1869 qdev_init_nofail(dev);
1870
1871 return pci_dev;
1872 }
1873
1874 PCIDevice *pci_vga_init(PCIBus *bus)
1875 {
1876 switch (vga_interface_type) {
1877 case VGA_CIRRUS:
1878 return pci_create_simple(bus, -1, "cirrus-vga");
1879 case VGA_QXL:
1880 return pci_create_simple(bus, -1, "qxl-vga");
1881 case VGA_STD:
1882 return pci_create_simple(bus, -1, "VGA");
1883 case VGA_VMWARE:
1884 return pci_create_simple(bus, -1, "vmware-svga");
1885 case VGA_VIRTIO:
1886 return pci_create_simple(bus, -1, "virtio-vga");
1887 case VGA_NONE:
1888 default: /* Other non-PCI types. Checking for unsupported types is already
1889 done in vl.c. */
1890 return NULL;
1891 }
1892 }
1893
1894 /* Whether a given bus number is in range of the secondary
1895 * bus of the given bridge device. */
1896 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1897 {
1898 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1899 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1900 dev->config[PCI_SECONDARY_BUS] <= bus_num &&
1901 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1902 }
1903
1904 /* Whether a given bus number is in a range of a root bus */
1905 static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
1906 {
1907 int i;
1908
1909 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
1910 PCIDevice *dev = bus->devices[i];
1911
1912 if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) {
1913 if (pci_secondary_bus_in_range(dev, bus_num)) {
1914 return true;
1915 }
1916 }
1917 }
1918
1919 return false;
1920 }
1921
1922 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1923 {
1924 PCIBus *sec;
1925
1926 if (!bus) {
1927 return NULL;
1928 }
1929
1930 if (pci_bus_num(bus) == bus_num) {
1931 return bus;
1932 }
1933
1934 /* Consider all bus numbers in range for the host pci bridge. */
1935 if (!pci_bus_is_root(bus) &&
1936 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1937 return NULL;
1938 }
1939
1940 /* try child bus */
1941 for (; bus; bus = sec) {
1942 QLIST_FOREACH(sec, &bus->child, sibling) {
1943 if (pci_bus_num(sec) == bus_num) {
1944 return sec;
1945 }
1946 /* PXB buses assumed to be children of bus 0 */
1947 if (pci_bus_is_root(sec)) {
1948 if (pci_root_bus_in_range(sec, bus_num)) {
1949 break;
1950 }
1951 } else {
1952 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1953 break;
1954 }
1955 }
1956 }
1957 }
1958
1959 return NULL;
1960 }
1961
1962 void pci_for_each_bus_depth_first(PCIBus *bus,
1963 void *(*begin)(PCIBus *bus, void *parent_state),
1964 void (*end)(PCIBus *bus, void *state),
1965 void *parent_state)
1966 {
1967 PCIBus *sec;
1968 void *state;
1969
1970 if (!bus) {
1971 return;
1972 }
1973
1974 if (begin) {
1975 state = begin(bus, parent_state);
1976 } else {
1977 state = parent_state;
1978 }
1979
1980 QLIST_FOREACH(sec, &bus->child, sibling) {
1981 pci_for_each_bus_depth_first(sec, begin, end, state);
1982 }
1983
1984 if (end) {
1985 end(bus, state);
1986 }
1987 }
1988
1989
1990 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1991 {
1992 bus = pci_find_bus_nr(bus, bus_num);
1993
1994 if (!bus)
1995 return NULL;
1996
1997 return bus->devices[devfn];
1998 }
1999
2000 static void pci_qdev_realize(DeviceState *qdev, Error **errp)
2001 {
2002 PCIDevice *pci_dev = (PCIDevice *)qdev;
2003 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
2004 Error *local_err = NULL;
2005 PCIBus *bus;
2006 bool is_default_rom;
2007
2008 /* initialize cap_present for pci_is_express() and pci_config_size() */
2009 if (pc->is_express) {
2010 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
2011 }
2012
2013 bus = PCI_BUS(qdev_get_parent_bus(qdev));
2014 pci_dev = do_pci_register_device(pci_dev, bus,
2015 object_get_typename(OBJECT(qdev)),
2016 pci_dev->devfn, errp);
2017 if (pci_dev == NULL)
2018 return;
2019
2020 if (pc->realize) {
2021 pc->realize(pci_dev, &local_err);
2022 if (local_err) {
2023 error_propagate(errp, local_err);
2024 do_pci_unregister_device(pci_dev);
2025 return;
2026 }
2027 }
2028
2029 /* rom loading */
2030 is_default_rom = false;
2031 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
2032 pci_dev->romfile = g_strdup(pc->romfile);
2033 is_default_rom = true;
2034 }
2035
2036 pci_add_option_rom(pci_dev, is_default_rom, &local_err);
2037 if (local_err) {
2038 error_propagate(errp, local_err);
2039 pci_qdev_unrealize(DEVICE(pci_dev), NULL);
2040 return;
2041 }
2042 }
2043
2044 static void pci_default_realize(PCIDevice *dev, Error **errp)
2045 {
2046 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2047
2048 if (pc->init) {
2049 if (pc->init(dev) < 0) {
2050 error_setg(errp, "Device initialization failed");
2051 return;
2052 }
2053 }
2054 }
2055
2056 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
2057 const char *name)
2058 {
2059 DeviceState *dev;
2060
2061 dev = qdev_create(&bus->qbus, name);
2062 qdev_prop_set_int32(dev, "addr", devfn);
2063 qdev_prop_set_bit(dev, "multifunction", multifunction);
2064 return PCI_DEVICE(dev);
2065 }
2066
2067 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
2068 bool multifunction,
2069 const char *name)
2070 {
2071 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
2072 qdev_init_nofail(&dev->qdev);
2073 return dev;
2074 }
2075
2076 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
2077 {
2078 return pci_create_multifunction(bus, devfn, false, name);
2079 }
2080
2081 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
2082 {
2083 return pci_create_simple_multifunction(bus, devfn, false, name);
2084 }
2085
2086 static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
2087 {
2088 int offset = PCI_CONFIG_HEADER_SIZE;
2089 int i;
2090 for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
2091 if (pdev->used[i])
2092 offset = i + 1;
2093 else if (i - offset + 1 == size)
2094 return offset;
2095 }
2096 return 0;
2097 }
2098
2099 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
2100 uint8_t *prev_p)
2101 {
2102 uint8_t next, prev;
2103
2104 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
2105 return 0;
2106
2107 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2108 prev = next + PCI_CAP_LIST_NEXT)
2109 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
2110 break;
2111
2112 if (prev_p)
2113 *prev_p = prev;
2114 return next;
2115 }
2116
2117 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
2118 {
2119 uint8_t next, prev, found = 0;
2120
2121 if (!(pdev->used[offset])) {
2122 return 0;
2123 }
2124
2125 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
2126
2127 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
2128 prev = next + PCI_CAP_LIST_NEXT) {
2129 if (next <= offset && next > found) {
2130 found = next;
2131 }
2132 }
2133 return found;
2134 }
2135
2136 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
2137 This is needed for an option rom which is used for more than one device. */
2138 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
2139 {
2140 uint16_t vendor_id;
2141 uint16_t device_id;
2142 uint16_t rom_vendor_id;
2143 uint16_t rom_device_id;
2144 uint16_t rom_magic;
2145 uint16_t pcir_offset;
2146 uint8_t checksum;
2147
2148 /* Words in rom data are little endian (like in PCI configuration),
2149 so they can be read / written with pci_get_word / pci_set_word. */
2150
2151 /* Only a valid rom will be patched. */
2152 rom_magic = pci_get_word(ptr);
2153 if (rom_magic != 0xaa55) {
2154 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
2155 return;
2156 }
2157 pcir_offset = pci_get_word(ptr + 0x18);
2158 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
2159 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
2160 return;
2161 }
2162
2163 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
2164 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
2165 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
2166 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
2167
2168 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
2169 vendor_id, device_id, rom_vendor_id, rom_device_id);
2170
2171 checksum = ptr[6];
2172
2173 if (vendor_id != rom_vendor_id) {
2174 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
2175 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
2176 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
2177 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2178 ptr[6] = checksum;
2179 pci_set_word(ptr + pcir_offset + 4, vendor_id);
2180 }
2181
2182 if (device_id != rom_device_id) {
2183 /* Patch device id and checksum (at offset 6 for etherboot roms). */
2184 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
2185 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
2186 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
2187 ptr[6] = checksum;
2188 pci_set_word(ptr + pcir_offset + 6, device_id);
2189 }
2190 }
2191
2192 /* Add an option rom for the device */
2193 static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom,
2194 Error **errp)
2195 {
2196 int size;
2197 char *path;
2198 void *ptr;
2199 char name[32];
2200 const VMStateDescription *vmsd;
2201
2202 if (!pdev->romfile)
2203 return;
2204 if (strlen(pdev->romfile) == 0)
2205 return;
2206
2207 if (!pdev->rom_bar) {
2208 /*
2209 * Load rom via fw_cfg instead of creating a rom bar,
2210 * for 0.11 compatibility.
2211 */
2212 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
2213
2214 /*
2215 * Hot-plugged devices can't use the option ROM
2216 * if the rom bar is disabled.
2217 */
2218 if (DEVICE(pdev)->hotplugged) {
2219 error_setg(errp, "Hot-plugged device without ROM bar"
2220 " can't have an option ROM");
2221 return;
2222 }
2223
2224 if (class == 0x0300) {
2225 rom_add_vga(pdev->romfile);
2226 } else {
2227 rom_add_option(pdev->romfile, -1);
2228 }
2229 return;
2230 }
2231
2232 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
2233 if (path == NULL) {
2234 path = g_strdup(pdev->romfile);
2235 }
2236
2237 size = get_image_size(path);
2238 if (size < 0) {
2239 error_setg(errp, "failed to find romfile \"%s\"", pdev->romfile);
2240 g_free(path);
2241 return;
2242 } else if (size == 0) {
2243 error_setg(errp, "romfile \"%s\" is empty", pdev->romfile);
2244 g_free(path);
2245 return;
2246 }
2247 size = pow2ceil(size);
2248
2249 vmsd = qdev_get_vmsd(DEVICE(pdev));
2250
2251 if (vmsd) {
2252 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
2253 } else {
2254 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
2255 }
2256 pdev->has_rom = true;
2257 memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal);
2258 vmstate_register_ram(&pdev->rom, &pdev->qdev);
2259 ptr = memory_region_get_ram_ptr(&pdev->rom);
2260 load_image(path, ptr);
2261 g_free(path);
2262
2263 if (is_default_rom) {
2264 /* Only the default rom images will be patched (if needed). */
2265 pci_patch_ids(pdev, ptr, size);
2266 }
2267
2268 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
2269 }
2270
2271 static void pci_del_option_rom(PCIDevice *pdev)
2272 {
2273 if (!pdev->has_rom)
2274 return;
2275
2276 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
2277 pdev->has_rom = false;
2278 }
2279
2280 /*
2281 * if offset = 0,
2282 * Find and reserve space and add capability to the linked list
2283 * in pci config space
2284 */
2285 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
2286 uint8_t offset, uint8_t size)
2287 {
2288 int ret;
2289 Error *local_err = NULL;
2290
2291 ret = pci_add_capability2(pdev, cap_id, offset, size, &local_err);
2292 if (local_err) {
2293 assert(ret < 0);
2294 error_report_err(local_err);
2295 } else {
2296 /* success implies a positive offset in config space */
2297 assert(ret > 0);
2298 }
2299 return ret;
2300 }
2301
2302 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
2303 uint8_t offset, uint8_t size,
2304 Error **errp)
2305 {
2306 uint8_t *config;
2307 int i, overlapping_cap;
2308
2309 if (!offset) {
2310 offset = pci_find_space(pdev, size);
2311 /* out of PCI config space is programming error */
2312 assert(offset);
2313 } else {
2314 /* Verify that capabilities don't overlap. Note: device assignment
2315 * depends on this check to verify that the device is not broken.
2316 * Should never trigger for emulated devices, but it's helpful
2317 * for debugging these. */
2318 for (i = offset; i < offset + size; i++) {
2319 overlapping_cap = pci_find_capability_at_offset(pdev, i);
2320 if (overlapping_cap) {
2321 error_setg(errp, "%s:%02x:%02x.%x "
2322 "Attempt to add PCI capability %x at offset "
2323 "%x overlaps existing capability %x at offset %x",
2324 pci_root_bus_path(pdev), pci_bus_num(pdev->bus),
2325 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2326 cap_id, offset, overlapping_cap, i);
2327 return -EINVAL;
2328 }
2329 }
2330 }
2331
2332 config = pdev->config + offset;
2333 config[PCI_CAP_LIST_ID] = cap_id;
2334 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
2335 pdev->config[PCI_CAPABILITY_LIST] = offset;
2336 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2337 memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4));
2338 /* Make capability read-only by default */
2339 memset(pdev->wmask + offset, 0, size);
2340 /* Check capability by default */
2341 memset(pdev->cmask + offset, 0xFF, size);
2342 return offset;
2343 }
2344
2345 /* Unlink capability from the pci config space. */
2346 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
2347 {
2348 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
2349 if (!offset)
2350 return;
2351 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
2352 /* Make capability writable again */
2353 memset(pdev->wmask + offset, 0xff, size);
2354 memset(pdev->w1cmask + offset, 0, size);
2355 /* Clear cmask as device-specific registers can't be checked */
2356 memset(pdev->cmask + offset, 0, size);
2357 memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4));
2358
2359 if (!pdev->config[PCI_CAPABILITY_LIST])
2360 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
2361 }
2362
2363 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
2364 {
2365 return pci_find_capability_list(pdev, cap_id, NULL);
2366 }
2367
2368 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2369 {
2370 PCIDevice *d = (PCIDevice *)dev;
2371 const pci_class_desc *desc;
2372 char ctxt[64];
2373 PCIIORegion *r;
2374 int i, class;
2375
2376 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2377 desc = pci_class_descriptions;
2378 while (desc->desc && class != desc->class)
2379 desc++;
2380 if (desc->desc) {
2381 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2382 } else {
2383 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2384 }
2385
2386 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2387 "pci id %04x:%04x (sub %04x:%04x)\n",
2388 indent, "", ctxt, pci_bus_num(d->bus),
2389 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2390 pci_get_word(d->config + PCI_VENDOR_ID),
2391 pci_get_word(d->config + PCI_DEVICE_ID),
2392 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2393 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2394 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2395 r = &d->io_regions[i];
2396 if (!r->size)
2397 continue;
2398 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2399 " [0x%"FMT_PCIBUS"]\n",
2400 indent, "",
2401 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2402 r->addr, r->addr + r->size - 1);
2403 }
2404 }
2405
2406 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2407 {
2408 PCIDevice *d = (PCIDevice *)dev;
2409 const char *name = NULL;
2410 const pci_class_desc *desc = pci_class_descriptions;
2411 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2412
2413 while (desc->desc &&
2414 (class & ~desc->fw_ign_bits) !=
2415 (desc->class & ~desc->fw_ign_bits)) {
2416 desc++;
2417 }
2418
2419 if (desc->desc) {
2420 name = desc->fw_name;
2421 }
2422
2423 if (name) {
2424 pstrcpy(buf, len, name);
2425 } else {
2426 snprintf(buf, len, "pci%04x,%04x",
2427 pci_get_word(d->config + PCI_VENDOR_ID),
2428 pci_get_word(d->config + PCI_DEVICE_ID));
2429 }
2430
2431 return buf;
2432 }
2433
2434 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2435 {
2436 PCIDevice *d = (PCIDevice *)dev;
2437 char path[50], name[33];
2438 int off;
2439
2440 off = snprintf(path, sizeof(path), "%s@%x",
2441 pci_dev_fw_name(dev, name, sizeof name),
2442 PCI_SLOT(d->devfn));
2443 if (PCI_FUNC(d->devfn))
2444 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2445 return g_strdup(path);
2446 }
2447
2448 static char *pcibus_get_dev_path(DeviceState *dev)
2449 {
2450 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2451 PCIDevice *t;
2452 int slot_depth;
2453 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2454 * 00 is added here to make this format compatible with
2455 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2456 * Slot.Function list specifies the slot and function numbers for all
2457 * devices on the path from root to the specific device. */
2458 const char *root_bus_path;
2459 int root_bus_len;
2460 char slot[] = ":SS.F";
2461 int slot_len = sizeof slot - 1 /* For '\0' */;
2462 int path_len;
2463 char *path, *p;
2464 int s;
2465
2466 root_bus_path = pci_root_bus_path(d);
2467 root_bus_len = strlen(root_bus_path);
2468
2469 /* Calculate # of slots on path between device and root. */;
2470 slot_depth = 0;
2471 for (t = d; t; t = t->bus->parent_dev) {
2472 ++slot_depth;
2473 }
2474
2475 path_len = root_bus_len + slot_len * slot_depth;
2476
2477 /* Allocate memory, fill in the terminating null byte. */
2478 path = g_malloc(path_len + 1 /* For '\0' */);
2479 path[path_len] = '\0';
2480
2481 memcpy(path, root_bus_path, root_bus_len);
2482
2483 /* Fill in slot numbers. We walk up from device to root, so need to print
2484 * them in the reverse order, last to first. */
2485 p = path + path_len;
2486 for (t = d; t; t = t->bus->parent_dev) {
2487 p -= slot_len;
2488 s = snprintf(slot, sizeof slot, ":%02x.%x",
2489 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2490 assert(s == slot_len);
2491 memcpy(p, slot, slot_len);
2492 }
2493
2494 return path;
2495 }
2496
2497 static int pci_qdev_find_recursive(PCIBus *bus,
2498 const char *id, PCIDevice **pdev)
2499 {
2500 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2501 if (!qdev) {
2502 return -ENODEV;
2503 }
2504
2505 /* roughly check if given qdev is pci device */
2506 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
2507 *pdev = PCI_DEVICE(qdev);
2508 return 0;
2509 }
2510 return -EINVAL;
2511 }
2512
2513 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2514 {
2515 PCIHostState *host_bridge;
2516 int rc = -ENODEV;
2517
2518 QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
2519 int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev);
2520 if (!tmp) {
2521 rc = 0;
2522 break;
2523 }
2524 if (tmp != -ENODEV) {
2525 rc = tmp;
2526 }
2527 }
2528
2529 return rc;
2530 }
2531
2532 MemoryRegion *pci_address_space(PCIDevice *dev)
2533 {
2534 return dev->bus->address_space_mem;
2535 }
2536
2537 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2538 {
2539 return dev->bus->address_space_io;
2540 }
2541
2542 static void pci_device_class_init(ObjectClass *klass, void *data)
2543 {
2544 DeviceClass *k = DEVICE_CLASS(klass);
2545 PCIDeviceClass *pc = PCI_DEVICE_CLASS(klass);
2546
2547 k->realize = pci_qdev_realize;
2548 k->unrealize = pci_qdev_unrealize;
2549 k->bus_type = TYPE_PCI_BUS;
2550 k->props = pci_props;
2551 pc->realize = pci_default_realize;
2552 }
2553
2554 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev)
2555 {
2556 PCIBus *bus = PCI_BUS(dev->bus);
2557 PCIBus *iommu_bus = bus;
2558
2559 while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) {
2560 iommu_bus = PCI_BUS(iommu_bus->parent_dev->bus);
2561 }
2562 if (iommu_bus && iommu_bus->iommu_fn) {
2563 return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn);
2564 }
2565 return &address_space_memory;
2566 }
2567
2568 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque)
2569 {
2570 bus->iommu_fn = fn;
2571 bus->iommu_opaque = opaque;
2572 }
2573
2574 static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
2575 {
2576 Range *range = opaque;
2577 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
2578 uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
2579 int i;
2580
2581 if (!(cmd & PCI_COMMAND_MEMORY)) {
2582 return;
2583 }
2584
2585 if (pc->is_bridge) {
2586 pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2587 pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
2588
2589 base = MAX(base, 0x1ULL << 32);
2590
2591 if (limit >= base) {
2592 Range pref_range;
2593 range_set_bounds(&pref_range, base, limit);
2594 range_extend(range, &pref_range);
2595 }
2596 }
2597 for (i = 0; i < PCI_NUM_REGIONS; ++i) {
2598 PCIIORegion *r = &dev->io_regions[i];
2599 pcibus_t lob, upb;
2600 Range region_range;
2601
2602 if (!r->size ||
2603 (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
2604 !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
2605 continue;
2606 }
2607
2608 lob = pci_bar_address(dev, i, r->type, r->size);
2609 upb = lob + r->size - 1;
2610 if (lob == PCI_BAR_UNMAPPED) {
2611 continue;
2612 }
2613
2614 lob = MAX(lob, 0x1ULL << 32);
2615
2616 if (upb >= lob) {
2617 range_set_bounds(&region_range, lob, upb);
2618 range_extend(range, &region_range);
2619 }
2620 }
2621 }
2622
2623 void pci_bus_get_w64_range(PCIBus *bus, Range *range)
2624 {
2625 range_make_empty(range);
2626 pci_for_each_device_under_bus(bus, pci_dev_get_w64, range);
2627 }
2628
2629 static bool pcie_has_upstream_port(PCIDevice *dev)
2630 {
2631 PCIDevice *parent_dev = pci_bridge_get_device(dev->bus);
2632
2633 /* Device associated with an upstream port.
2634 * As there are several types of these, it's easier to check the
2635 * parent device: upstream ports are always connected to
2636 * root or downstream ports.
2637 */
2638 return parent_dev &&
2639 pci_is_express(parent_dev) &&
2640 parent_dev->exp.exp_cap &&
2641 (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT ||
2642 pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM);
2643 }
2644
2645 PCIDevice *pci_get_function_0(PCIDevice *pci_dev)
2646 {
2647 if(pcie_has_upstream_port(pci_dev)) {
2648 /* With an upstream PCIe port, we only support 1 device at slot 0 */
2649 return pci_dev->bus->devices[0];
2650 } else {
2651 /* Other bus types might support multiple devices at slots 0-31 */
2652 return pci_dev->bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)];
2653 }
2654 }
2655
2656 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector)
2657 {
2658 MSIMessage msg;
2659 if (msix_enabled(dev)) {
2660 msg = msix_get_message(dev, vector);
2661 } else if (msi_enabled(dev)) {
2662 msg = msi_get_message(dev, vector);
2663 } else {
2664 /* Should never happen */
2665 error_report("%s: unknown interrupt type", __func__);
2666 abort();
2667 }
2668 return msg;
2669 }
2670
2671 static const TypeInfo pci_device_type_info = {
2672 .name = TYPE_PCI_DEVICE,
2673 .parent = TYPE_DEVICE,
2674 .instance_size = sizeof(PCIDevice),
2675 .abstract = true,
2676 .class_size = sizeof(PCIDeviceClass),
2677 .class_init = pci_device_class_init,
2678 };
2679
2680 static void pci_register_types(void)
2681 {
2682 type_register_static(&pci_bus_info);
2683 type_register_static(&pcie_bus_info);
2684 type_register_static(&pci_device_type_info);
2685 }
2686
2687 type_init(pci_register_types)
AR7 emulation for QEMU