4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
24 #include "qemu/cutils.h"
26 #include "exec/exec-all.h"
27 #include "exec/target_page.h"
29 #include "hw/qdev-core.h"
30 #include "hw/qdev-properties.h"
31 #if !defined(CONFIG_USER_ONLY)
32 #include "hw/boards.h"
33 #include "hw/xen/xen.h"
35 #include "sysemu/kvm.h"
36 #include "sysemu/sysemu.h"
37 #include "qemu/timer.h"
38 #include "qemu/config-file.h"
39 #include "qemu/error-report.h"
40 #if defined(CONFIG_USER_ONLY)
42 #else /* !CONFIG_USER_ONLY */
44 #include "exec/memory.h"
45 #include "exec/ioport.h"
46 #include "sysemu/dma.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/hw_accel.h"
49 #include "exec/address-spaces.h"
50 #include "sysemu/xen-mapcache.h"
51 #include "trace-root.h"
53 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
55 #include <linux/falloc.h>
59 #include "qemu/rcu_queue.h"
60 #include "qemu/main-loop.h"
61 #include "translate-all.h"
62 #include "sysemu/replay.h"
64 #include "exec/memory-internal.h"
65 #include "exec/ram_addr.h"
68 #include "migration/vmstate.h"
70 #include "qemu/range.h"
72 #include "qemu/mmap-alloc.h"
75 #include "monitor/monitor.h"
77 //#define DEBUG_SUBPAGE
79 #if !defined(CONFIG_USER_ONLY)
80 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
81 * are protected by the ramlist lock.
83 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
85 static MemoryRegion
*system_memory
;
86 static MemoryRegion
*system_io
;
88 AddressSpace address_space_io
;
89 AddressSpace address_space_memory
;
91 MemoryRegion io_mem_rom
, io_mem_notdirty
;
92 static MemoryRegion io_mem_unassigned
;
94 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
95 #define RAM_PREALLOC (1 << 0)
97 /* RAM is mmap-ed with MAP_SHARED */
98 #define RAM_SHARED (1 << 1)
100 /* Only a portion of RAM (used_length) is actually used, and migrated.
101 * This used_length size can change across reboots.
103 #define RAM_RESIZEABLE (1 << 2)
107 #ifdef TARGET_PAGE_BITS_VARY
108 int target_page_bits
;
109 bool target_page_bits_decided
;
112 struct CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
113 /* current CPU in the current thread. It is only valid inside
115 __thread CPUState
*current_cpu
;
116 /* 0 = Do not count executed instructions.
117 1 = Precise instruction counting.
118 2 = Adaptive rate instruction counting. */
121 uintptr_t qemu_host_page_size
;
122 intptr_t qemu_host_page_mask
;
124 bool set_preferred_target_page_bits(int bits
)
126 /* The target page size is the lowest common denominator for all
127 * the CPUs in the system, so we can only make it smaller, never
128 * larger. And we can't make it smaller once we've committed to
131 #ifdef TARGET_PAGE_BITS_VARY
132 assert(bits
>= TARGET_PAGE_BITS_MIN
);
133 if (target_page_bits
== 0 || target_page_bits
> bits
) {
134 if (target_page_bits_decided
) {
137 target_page_bits
= bits
;
143 #if !defined(CONFIG_USER_ONLY)
145 static void finalize_target_page_bits(void)
147 #ifdef TARGET_PAGE_BITS_VARY
148 if (target_page_bits
== 0) {
149 target_page_bits
= TARGET_PAGE_BITS_MIN
;
151 target_page_bits_decided
= true;
155 typedef struct PhysPageEntry PhysPageEntry
;
157 struct PhysPageEntry
{
158 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
160 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
164 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
166 /* Size of the L2 (and L3, etc) page tables. */
167 #define ADDR_SPACE_BITS 64
170 #define P_L2_SIZE (1 << P_L2_BITS)
172 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
174 typedef PhysPageEntry Node
[P_L2_SIZE
];
176 typedef struct PhysPageMap
{
179 unsigned sections_nb
;
180 unsigned sections_nb_alloc
;
182 unsigned nodes_nb_alloc
;
184 MemoryRegionSection
*sections
;
187 struct AddressSpaceDispatch
{
188 MemoryRegionSection
*mru_section
;
189 /* This is a multi-level map on the physical address space.
190 * The bottom level has pointers to MemoryRegionSections.
192 PhysPageEntry phys_map
;
196 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
197 typedef struct subpage_t
{
201 uint16_t sub_section
[];
204 #define PHYS_SECTION_UNASSIGNED 0
205 #define PHYS_SECTION_NOTDIRTY 1
206 #define PHYS_SECTION_ROM 2
207 #define PHYS_SECTION_WATCH 3
209 static void io_mem_init(void);
210 static void memory_map_init(void);
211 static void tcg_commit(MemoryListener
*listener
);
213 static MemoryRegion io_mem_watch
;
216 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
217 * @cpu: the CPU whose AddressSpace this is
218 * @as: the AddressSpace itself
219 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
220 * @tcg_as_listener: listener for tracking changes to the AddressSpace
222 struct CPUAddressSpace
{
225 struct AddressSpaceDispatch
*memory_dispatch
;
226 MemoryListener tcg_as_listener
;
229 struct DirtyBitmapSnapshot
{
232 unsigned long dirty
[];
237 #if !defined(CONFIG_USER_ONLY)
239 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
241 static unsigned alloc_hint
= 16;
242 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
243 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
244 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
245 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
246 alloc_hint
= map
->nodes_nb_alloc
;
250 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
257 ret
= map
->nodes_nb
++;
259 assert(ret
!= PHYS_MAP_NODE_NIL
);
260 assert(ret
!= map
->nodes_nb_alloc
);
262 e
.skip
= leaf
? 0 : 1;
263 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
264 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
265 memcpy(&p
[i
], &e
, sizeof(e
));
270 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
271 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
275 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
277 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
278 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
280 p
= map
->nodes
[lp
->ptr
];
281 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
283 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
284 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
290 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
296 static void phys_page_set(AddressSpaceDispatch
*d
,
297 hwaddr index
, hwaddr nb
,
300 /* Wildly overreserve - it doesn't matter much. */
301 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
303 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
306 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
307 * and update our entry so we can skip it and go directly to the destination.
309 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
311 unsigned valid_ptr
= P_L2_SIZE
;
316 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
321 for (i
= 0; i
< P_L2_SIZE
; i
++) {
322 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
329 phys_page_compact(&p
[i
], nodes
);
333 /* We can only compress if there's only one child. */
338 assert(valid_ptr
< P_L2_SIZE
);
340 /* Don't compress if it won't fit in the # of bits we have. */
341 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
345 lp
->ptr
= p
[valid_ptr
].ptr
;
346 if (!p
[valid_ptr
].skip
) {
347 /* If our only child is a leaf, make this a leaf. */
348 /* By design, we should have made this node a leaf to begin with so we
349 * should never reach here.
350 * But since it's so simple to handle this, let's do it just in case we
355 lp
->skip
+= p
[valid_ptr
].skip
;
359 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
361 if (d
->phys_map
.skip
) {
362 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
366 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
369 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
370 * the section must cover the entire address space.
372 return int128_gethi(section
->size
) ||
373 range_covers_byte(section
->offset_within_address_space
,
374 int128_getlo(section
->size
), addr
);
377 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
379 PhysPageEntry lp
= d
->phys_map
, *p
;
380 Node
*nodes
= d
->map
.nodes
;
381 MemoryRegionSection
*sections
= d
->map
.sections
;
382 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
385 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
386 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
387 return §ions
[PHYS_SECTION_UNASSIGNED
];
390 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
393 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
394 return §ions
[lp
.ptr
];
396 return §ions
[PHYS_SECTION_UNASSIGNED
];
400 bool memory_region_is_unassigned(MemoryRegion
*mr
)
402 return mr
!= &io_mem_rom
&& mr
!= &io_mem_notdirty
&& !mr
->rom_device
403 && mr
!= &io_mem_watch
;
406 /* Called from RCU critical section */
407 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
409 bool resolve_subpage
)
411 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
415 if (section
&& section
!= &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] &&
416 section_covers_addr(section
, addr
)) {
419 section
= phys_page_find(d
, addr
);
422 if (resolve_subpage
&& section
->mr
->subpage
) {
423 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
424 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
427 atomic_set(&d
->mru_section
, section
);
432 /* Called from RCU critical section */
433 static MemoryRegionSection
*
434 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
435 hwaddr
*plen
, bool resolve_subpage
)
437 MemoryRegionSection
*section
;
441 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
442 /* Compute offset within MemoryRegionSection */
443 addr
-= section
->offset_within_address_space
;
445 /* Compute offset within MemoryRegion */
446 *xlat
= addr
+ section
->offset_within_region
;
450 /* MMIO registers can be expected to perform full-width accesses based only
451 * on their address, without considering adjacent registers that could
452 * decode to completely different MemoryRegions. When such registers
453 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
454 * regions overlap wildly. For this reason we cannot clamp the accesses
457 * If the length is small (as is the case for address_space_ldl/stl),
458 * everything works fine. If the incoming length is large, however,
459 * the caller really has to do the clamping through memory_access_size.
461 if (memory_region_is_ram(mr
)) {
462 diff
= int128_sub(section
->size
, int128_make64(addr
));
463 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
468 /* Called from RCU critical section */
469 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
475 AddressSpace
**target_as
)
478 MemoryRegionSection
*section
;
479 IOMMUMemoryRegion
*iommu_mr
;
480 IOMMUMemoryRegionClass
*imrc
;
483 section
= address_space_translate_internal(
484 flatview_to_dispatch(fv
), addr
, &addr
,
487 iommu_mr
= memory_region_get_iommu(section
->mr
);
491 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
493 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
494 IOMMU_WO
: IOMMU_RO
);
495 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
496 | (addr
& iotlb
.addr_mask
));
497 *plen
= MIN(*plen
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
498 if (!(iotlb
.perm
& (1 << is_write
))) {
502 fv
= address_space_to_flatview(iotlb
.target_as
);
503 *target_as
= iotlb
.target_as
;
511 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
514 /* Called from RCU critical section */
515 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
518 MemoryRegionSection section
;
521 /* Try to get maximum page mask during translation. */
524 /* This can never be MMIO. */
525 section
= flatview_do_translate(address_space_to_flatview(as
), addr
,
526 &xlat
, &plen
, is_write
, false, &as
);
528 /* Illegal translation */
529 if (section
.mr
== &io_mem_unassigned
) {
533 /* Convert memory region offset into address space offset */
534 xlat
+= section
.offset_within_address_space
-
535 section
.offset_within_region
;
537 if (plen
== (hwaddr
)-1) {
539 * We use default page size here. Logically it only happens
540 * for identity mappings.
542 plen
= TARGET_PAGE_SIZE
;
545 /* Convert to address mask */
548 return (IOMMUTLBEntry
) {
550 .iova
= addr
& ~plen
,
551 .translated_addr
= xlat
& ~plen
,
553 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
558 return (IOMMUTLBEntry
) {0};
561 /* Called from RCU critical section */
562 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
563 hwaddr
*plen
, bool is_write
)
566 MemoryRegionSection section
;
567 AddressSpace
*as
= NULL
;
569 /* This can be MMIO, so setup MMIO bit. */
570 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, is_write
, true, &as
);
573 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
574 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
575 *plen
= MIN(page
, *plen
);
581 /* Called from RCU critical section */
582 MemoryRegionSection
*
583 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
584 hwaddr
*xlat
, hwaddr
*plen
)
586 MemoryRegionSection
*section
;
587 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
589 section
= address_space_translate_internal(d
, addr
, xlat
, plen
, false);
591 assert(!memory_region_is_iommu(section
->mr
));
596 #if !defined(CONFIG_USER_ONLY)
598 static int cpu_common_post_load(void *opaque
, int version_id
)
600 CPUState
*cpu
= opaque
;
602 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
603 version_id is increased. */
604 cpu
->interrupt_request
&= ~0x01;
610 static int cpu_common_pre_load(void *opaque
)
612 CPUState
*cpu
= opaque
;
614 cpu
->exception_index
= -1;
619 static bool cpu_common_exception_index_needed(void *opaque
)
621 CPUState
*cpu
= opaque
;
623 return tcg_enabled() && cpu
->exception_index
!= -1;
626 static const VMStateDescription vmstate_cpu_common_exception_index
= {
627 .name
= "cpu_common/exception_index",
629 .minimum_version_id
= 1,
630 .needed
= cpu_common_exception_index_needed
,
631 .fields
= (VMStateField
[]) {
632 VMSTATE_INT32(exception_index
, CPUState
),
633 VMSTATE_END_OF_LIST()
637 static bool cpu_common_crash_occurred_needed(void *opaque
)
639 CPUState
*cpu
= opaque
;
641 return cpu
->crash_occurred
;
644 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
645 .name
= "cpu_common/crash_occurred",
647 .minimum_version_id
= 1,
648 .needed
= cpu_common_crash_occurred_needed
,
649 .fields
= (VMStateField
[]) {
650 VMSTATE_BOOL(crash_occurred
, CPUState
),
651 VMSTATE_END_OF_LIST()
655 const VMStateDescription vmstate_cpu_common
= {
656 .name
= "cpu_common",
658 .minimum_version_id
= 1,
659 .pre_load
= cpu_common_pre_load
,
660 .post_load
= cpu_common_post_load
,
661 .fields
= (VMStateField
[]) {
662 VMSTATE_UINT32(halted
, CPUState
),
663 VMSTATE_UINT32(interrupt_request
, CPUState
),
664 VMSTATE_END_OF_LIST()
666 .subsections
= (const VMStateDescription
*[]) {
667 &vmstate_cpu_common_exception_index
,
668 &vmstate_cpu_common_crash_occurred
,
675 CPUState
*qemu_get_cpu(int index
)
680 if (cpu
->cpu_index
== index
) {
688 #if !defined(CONFIG_USER_ONLY)
689 void cpu_address_space_init(CPUState
*cpu
, AddressSpace
*as
, int asidx
)
691 CPUAddressSpace
*newas
;
693 /* Target code should have set num_ases before calling us */
694 assert(asidx
< cpu
->num_ases
);
697 /* address space 0 gets the convenience alias */
701 /* KVM cannot currently support multiple address spaces. */
702 assert(asidx
== 0 || !kvm_enabled());
704 if (!cpu
->cpu_ases
) {
705 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
708 newas
= &cpu
->cpu_ases
[asidx
];
712 newas
->tcg_as_listener
.commit
= tcg_commit
;
713 memory_listener_register(&newas
->tcg_as_listener
, as
);
717 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
719 /* Return the AddressSpace corresponding to the specified index */
720 return cpu
->cpu_ases
[asidx
].as
;
724 void cpu_exec_unrealizefn(CPUState
*cpu
)
726 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
728 cpu_list_remove(cpu
);
730 if (cc
->vmsd
!= NULL
) {
731 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
733 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
734 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
738 Property cpu_common_props
[] = {
739 #ifndef CONFIG_USER_ONLY
740 /* Create a memory property for softmmu CPU object,
741 * so users can wire up its memory. (This can't go in qom/cpu.c
742 * because that file is compiled only once for both user-mode
743 * and system builds.) The default if no link is set up is to use
744 * the system address space.
746 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
749 DEFINE_PROP_END_OF_LIST(),
752 void cpu_exec_initfn(CPUState
*cpu
)
754 #ifdef TARGET_WORDS_BIGENDIAN
755 cpu
->bigendian
= true;
757 cpu
->bigendian
= false;
762 #ifndef CONFIG_USER_ONLY
763 cpu
->thread_id
= qemu_get_thread_id();
764 cpu
->memory
= system_memory
;
765 object_ref(OBJECT(cpu
->memory
));
769 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
771 CPUClass
*cc ATTRIBUTE_UNUSED
= CPU_GET_CLASS(cpu
);
775 #ifndef CONFIG_USER_ONLY
776 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
777 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
779 if (cc
->vmsd
!= NULL
) {
780 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
785 #if defined(CONFIG_USER_ONLY)
786 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
790 tb_invalidate_phys_page_range(pc
, pc
+ 1, 0);
795 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
798 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
799 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
801 /* Locks grabbed by tb_invalidate_phys_addr */
802 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
803 phys
| (pc
& ~TARGET_PAGE_MASK
));
808 #if defined(CONFIG_USER_ONLY)
809 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
814 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
820 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
824 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
825 int flags
, CPUWatchpoint
**watchpoint
)
830 /* Add a watchpoint. */
831 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
832 int flags
, CPUWatchpoint
**watchpoint
)
836 /* forbid ranges which are empty or run off the end of the address space */
837 if (len
== 0 || (addr
+ len
- 1) < addr
) {
838 error_report("tried to set invalid watchpoint at %"
839 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
842 wp
= g_malloc(sizeof(*wp
));
848 /* keep all GDB-injected watchpoints in front */
849 if (flags
& BP_GDB
) {
850 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
852 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
855 tlb_flush_page(cpu
, addr
);
862 /* Remove a specific watchpoint. */
863 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
868 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
869 if (addr
== wp
->vaddr
&& len
== wp
->len
870 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
871 cpu_watchpoint_remove_by_ref(cpu
, wp
);
878 /* Remove a specific watchpoint by reference. */
879 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
881 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
883 tlb_flush_page(cpu
, watchpoint
->vaddr
);
888 /* Remove all matching watchpoints. */
889 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
891 CPUWatchpoint
*wp
, *next
;
893 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
894 if (wp
->flags
& mask
) {
895 cpu_watchpoint_remove_by_ref(cpu
, wp
);
900 /* Return true if this watchpoint address matches the specified
901 * access (ie the address range covered by the watchpoint overlaps
902 * partially or completely with the address range covered by the
905 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
909 /* We know the lengths are non-zero, but a little caution is
910 * required to avoid errors in the case where the range ends
911 * exactly at the top of the address space and so addr + len
912 * wraps round to zero.
914 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
915 vaddr addrend
= addr
+ len
- 1;
917 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
922 /* Add a breakpoint. */
923 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
924 CPUBreakpoint
**breakpoint
)
928 bp
= g_malloc(sizeof(*bp
));
933 /* keep all GDB-injected breakpoints in front */
934 if (flags
& BP_GDB
) {
935 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
937 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
940 breakpoint_invalidate(cpu
, pc
);
948 /* Remove a specific breakpoint. */
949 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
953 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
954 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
955 cpu_breakpoint_remove_by_ref(cpu
, bp
);
962 /* Remove a specific breakpoint by reference. */
963 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
965 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
967 breakpoint_invalidate(cpu
, breakpoint
->pc
);
972 /* Remove all matching breakpoints. */
973 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
975 CPUBreakpoint
*bp
, *next
;
977 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
978 if (bp
->flags
& mask
) {
979 cpu_breakpoint_remove_by_ref(cpu
, bp
);
984 /* enable or disable single step mode. EXCP_DEBUG is returned by the
985 CPU loop after each instruction */
986 void cpu_single_step(CPUState
*cpu
, int enabled
)
988 if (cpu
->singlestep_enabled
!= enabled
) {
989 cpu
->singlestep_enabled
= enabled
;
991 kvm_update_guest_debug(cpu
, 0);
993 /* must flush all the translated code to avoid inconsistencies */
994 /* XXX: only flush what is necessary */
1000 void QEMU_NORETURN
cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1007 fprintf(stderr
, "qemu: fatal: ");
1008 vfprintf(stderr
, fmt
, ap
);
1009 fprintf(stderr
, "\n");
1010 cpu_dump_state(cpu
, stderr
, fprintf
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1011 if (qemu_log_separate()) {
1013 qemu_log("qemu: fatal: ");
1014 qemu_log_vprintf(fmt
, ap2
);
1016 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1024 #if defined(CONFIG_USER_ONLY)
1026 struct sigaction act
;
1027 sigfillset(&act
.sa_mask
);
1028 act
.sa_handler
= SIG_DFL
;
1029 sigaction(SIGABRT
, &act
, NULL
);
1035 #if !defined(CONFIG_USER_ONLY)
1036 /* Called from RCU critical section */
1037 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1041 block
= atomic_rcu_read(&ram_list
.mru_block
);
1042 if (block
&& addr
- block
->offset
< block
->max_length
) {
1045 RAMBLOCK_FOREACH(block
) {
1046 if (addr
- block
->offset
< block
->max_length
) {
1051 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1055 /* It is safe to write mru_block outside the iothread lock. This
1060 * xxx removed from list
1064 * call_rcu(reclaim_ramblock, xxx);
1067 * atomic_rcu_set is not needed here. The block was already published
1068 * when it was placed into the list. Here we're just making an extra
1069 * copy of the pointer.
1071 ram_list
.mru_block
= block
;
1075 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1082 end
= TARGET_PAGE_ALIGN(start
+ length
);
1083 start
&= TARGET_PAGE_MASK
;
1086 block
= qemu_get_ram_block(start
);
1087 assert(block
== qemu_get_ram_block(end
- 1));
1088 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1090 tlb_reset_dirty(cpu
, start1
, length
);
1095 /* Note: start and end must be within the same ram block. */
1096 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1100 DirtyMemoryBlocks
*blocks
;
1101 unsigned long end
, page
;
1108 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1109 page
= start
>> TARGET_PAGE_BITS
;
1113 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1115 while (page
< end
) {
1116 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1117 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1118 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1120 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1127 if (dirty
&& tcg_enabled()) {
1128 tlb_reset_dirty_range_all(start
, length
);
1134 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1135 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1137 DirtyMemoryBlocks
*blocks
;
1138 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1139 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1140 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1141 DirtyBitmapSnapshot
*snap
;
1142 unsigned long page
, end
, dest
;
1144 snap
= g_malloc0(sizeof(*snap
) +
1145 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1146 snap
->start
= first
;
1149 page
= first
>> TARGET_PAGE_BITS
;
1150 end
= last
>> TARGET_PAGE_BITS
;
1155 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1157 while (page
< end
) {
1158 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1159 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1160 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1162 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1163 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1164 offset
>>= BITS_PER_LEVEL
;
1166 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1167 blocks
->blocks
[idx
] + offset
,
1170 dest
+= num
>> BITS_PER_LEVEL
;
1175 if (tcg_enabled()) {
1176 tlb_reset_dirty_range_all(start
, length
);
1182 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1186 unsigned long page
, end
;
1188 assert(start
>= snap
->start
);
1189 assert(start
+ length
<= snap
->end
);
1191 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1192 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1194 while (page
< end
) {
1195 if (test_bit(page
, snap
->dirty
)) {
1203 /* Called from RCU critical section */
1204 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1205 MemoryRegionSection
*section
,
1207 hwaddr paddr
, hwaddr xlat
,
1209 target_ulong
*address
)
1214 if (memory_region_is_ram(section
->mr
)) {
1216 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1217 if (!section
->readonly
) {
1218 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1220 iotlb
|= PHYS_SECTION_ROM
;
1223 AddressSpaceDispatch
*d
;
1225 d
= flatview_to_dispatch(section
->fv
);
1226 iotlb
= section
- d
->map
.sections
;
1230 /* Make accesses to pages with watchpoints go via the
1231 watchpoint trap routines. */
1232 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1233 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1234 /* Avoid trapping reads of pages with a write breakpoint. */
1235 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1236 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1237 *address
|= TLB_MMIO
;
1245 #endif /* defined(CONFIG_USER_ONLY) */
1247 #if !defined(CONFIG_USER_ONLY)
1249 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1251 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1253 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
) =
1254 qemu_anon_ram_alloc
;
1257 * Set a custom physical guest memory alloator.
1258 * Accelerators with unusual needs may need this. Hopefully, we can
1259 * get rid of it eventually.
1261 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
))
1263 phys_mem_alloc
= alloc
;
1266 static uint16_t phys_section_add(PhysPageMap
*map
,
1267 MemoryRegionSection
*section
)
1269 /* The physical section number is ORed with a page-aligned
1270 * pointer to produce the iotlb entries. Thus it should
1271 * never overflow into the page-aligned value.
1273 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1275 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1276 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1277 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1278 map
->sections_nb_alloc
);
1280 map
->sections
[map
->sections_nb
] = *section
;
1281 memory_region_ref(section
->mr
);
1282 return map
->sections_nb
++;
1285 static void phys_section_destroy(MemoryRegion
*mr
)
1287 bool have_sub_page
= mr
->subpage
;
1289 memory_region_unref(mr
);
1291 if (have_sub_page
) {
1292 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1293 object_unref(OBJECT(&subpage
->iomem
));
1298 static void phys_sections_free(PhysPageMap
*map
)
1300 while (map
->sections_nb
> 0) {
1301 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1302 phys_section_destroy(section
->mr
);
1304 g_free(map
->sections
);
1308 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1310 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1312 hwaddr base
= section
->offset_within_address_space
1314 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1315 MemoryRegionSection subsection
= {
1316 .offset_within_address_space
= base
,
1317 .size
= int128_make64(TARGET_PAGE_SIZE
),
1321 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1323 if (!(existing
->mr
->subpage
)) {
1324 subpage
= subpage_init(fv
, base
);
1326 subsection
.mr
= &subpage
->iomem
;
1327 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1328 phys_section_add(&d
->map
, &subsection
));
1330 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1332 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1333 end
= start
+ int128_get64(section
->size
) - 1;
1334 subpage_register(subpage
, start
, end
,
1335 phys_section_add(&d
->map
, section
));
1339 static void register_multipage(FlatView
*fv
,
1340 MemoryRegionSection
*section
)
1342 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1343 hwaddr start_addr
= section
->offset_within_address_space
;
1344 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1345 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1349 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1352 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1354 MemoryRegionSection now
= *section
, remain
= *section
;
1355 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1357 if (now
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1358 uint64_t left
= TARGET_PAGE_ALIGN(now
.offset_within_address_space
)
1359 - now
.offset_within_address_space
;
1361 now
.size
= int128_min(int128_make64(left
), now
.size
);
1362 register_subpage(fv
, &now
);
1364 now
.size
= int128_zero();
1366 while (int128_ne(remain
.size
, now
.size
)) {
1367 remain
.size
= int128_sub(remain
.size
, now
.size
);
1368 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1369 remain
.offset_within_region
+= int128_get64(now
.size
);
1371 if (int128_lt(remain
.size
, page_size
)) {
1372 register_subpage(fv
, &now
);
1373 } else if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1374 now
.size
= page_size
;
1375 register_subpage(fv
, &now
);
1377 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1378 register_multipage(fv
, &now
);
1383 void qemu_flush_coalesced_mmio_buffer(void)
1386 kvm_flush_coalesced_mmio_buffer();
1389 void qemu_mutex_lock_ramlist(void)
1391 qemu_mutex_lock(&ram_list
.mutex
);
1394 void qemu_mutex_unlock_ramlist(void)
1396 qemu_mutex_unlock(&ram_list
.mutex
);
1399 void ram_block_dump(Monitor
*mon
)
1405 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1406 "Block Name", "PSize", "Offset", "Used", "Total");
1407 RAMBLOCK_FOREACH(block
) {
1408 psize
= size_to_str(block
->page_size
);
1409 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1410 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1411 (uint64_t)block
->offset
,
1412 (uint64_t)block
->used_length
,
1413 (uint64_t)block
->max_length
);
1421 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1422 * may or may not name the same files / on the same filesystem now as
1423 * when we actually open and map them. Iterate over the file
1424 * descriptors instead, and use qemu_fd_getpagesize().
1426 static int find_max_supported_pagesize(Object
*obj
, void *opaque
)
1429 long *hpsize_min
= opaque
;
1431 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1432 mem_path
= object_property_get_str(obj
, "mem-path", NULL
);
1434 long hpsize
= qemu_mempath_getpagesize(mem_path
);
1435 if (hpsize
< *hpsize_min
) {
1436 *hpsize_min
= hpsize
;
1439 *hpsize_min
= getpagesize();
1446 long qemu_getrampagesize(void)
1448 long hpsize
= LONG_MAX
;
1449 long mainrampagesize
;
1450 Object
*memdev_root
;
1453 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1455 mainrampagesize
= getpagesize();
1458 /* it's possible we have memory-backend objects with
1459 * hugepage-backed RAM. these may get mapped into system
1460 * address space via -numa parameters or memory hotplug
1461 * hooks. we want to take these into account, but we
1462 * also want to make sure these supported hugepage
1463 * sizes are applicable across the entire range of memory
1464 * we may boot from, so we take the min across all
1465 * backends, and assume normal pages in cases where a
1466 * backend isn't backed by hugepages.
1468 memdev_root
= object_resolve_path("/objects", NULL
);
1470 object_child_foreach(memdev_root
, find_max_supported_pagesize
, &hpsize
);
1472 if (hpsize
== LONG_MAX
) {
1473 /* No additional memory regions found ==> Report main RAM page size */
1474 return mainrampagesize
;
1477 /* If NUMA is disabled or the NUMA nodes are not backed with a
1478 * memory-backend, then there is at least one node using "normal" RAM,
1479 * so if its page size is smaller we have got to report that size instead.
1481 if (hpsize
> mainrampagesize
&&
1482 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1485 error_report("Huge page support disabled (n/a for main memory).");
1488 return mainrampagesize
;
1494 long qemu_getrampagesize(void)
1496 return getpagesize();
1501 static int64_t get_file_size(int fd
)
1503 int64_t size
= lseek(fd
, 0, SEEK_END
);
1510 static int file_ram_open(const char *path
,
1511 const char *region_name
,
1516 char *sanitized_name
;
1522 fd
= open(path
, O_RDWR
);
1524 /* @path names an existing file, use it */
1527 if (errno
== ENOENT
) {
1528 /* @path names a file that doesn't exist, create it */
1529 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1534 } else if (errno
== EISDIR
) {
1535 /* @path names a directory, create a file there */
1536 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1537 sanitized_name
= g_strdup(region_name
);
1538 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1544 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1546 g_free(sanitized_name
);
1548 fd
= mkstemp(filename
);
1556 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1557 error_setg_errno(errp
, errno
,
1558 "can't open backing store %s for guest RAM",
1563 * Try again on EINTR and EEXIST. The latter happens when
1564 * something else creates the file between our two open().
1571 static void *file_ram_alloc(RAMBlock
*block
,
1579 block
->page_size
= qemu_fd_getpagesize(fd
);
1580 block
->mr
->align
= block
->page_size
;
1581 #if defined(__s390x__)
1582 if (kvm_enabled()) {
1583 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1587 if (memory
< block
->page_size
) {
1588 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1589 "or larger than page size 0x%zx",
1590 memory
, block
->page_size
);
1594 memory
= ROUND_UP(memory
, block
->page_size
);
1597 * ftruncate is not supported by hugetlbfs in older
1598 * hosts, so don't bother bailing out on errors.
1599 * If anything goes wrong with it under other filesystems,
1602 * Do not truncate the non-empty backend file to avoid corrupting
1603 * the existing data in the file. Disabling shrinking is not
1604 * enough. For example, the current vNVDIMM implementation stores
1605 * the guest NVDIMM labels at the end of the backend file. If the
1606 * backend file is later extended, QEMU will not be able to find
1607 * those labels. Therefore, extending the non-empty backend file
1608 * is disabled as well.
1610 if (truncate
&& ftruncate(fd
, memory
)) {
1611 perror("ftruncate");
1614 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1615 block
->flags
& RAM_SHARED
);
1616 if (area
== MAP_FAILED
) {
1617 error_setg_errno(errp
, errno
,
1618 "unable to map backing store for guest RAM");
1623 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1624 if (errp
&& *errp
) {
1625 qemu_ram_munmap(area
, memory
);
1635 /* Called with the ramlist lock held. */
1636 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1638 RAMBlock
*block
, *next_block
;
1639 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1641 assert(size
!= 0); /* it would hand out same offset multiple times */
1643 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1647 RAMBLOCK_FOREACH(block
) {
1648 ram_addr_t end
, next
= RAM_ADDR_MAX
;
1650 end
= block
->offset
+ block
->max_length
;
1652 RAMBLOCK_FOREACH(next_block
) {
1653 if (next_block
->offset
>= end
) {
1654 next
= MIN(next
, next_block
->offset
);
1657 if (next
- end
>= size
&& next
- end
< mingap
) {
1659 mingap
= next
- end
;
1663 if (offset
== RAM_ADDR_MAX
) {
1664 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1672 unsigned long last_ram_page(void)
1675 ram_addr_t last
= 0;
1678 RAMBLOCK_FOREACH(block
) {
1679 last
= MAX(last
, block
->offset
+ block
->max_length
);
1682 return last
>> TARGET_PAGE_BITS
;
1685 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
1689 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1690 if (!machine_dump_guest_core(current_machine
)) {
1691 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
1693 perror("qemu_madvise");
1694 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
1695 "but dump_guest_core=off specified\n");
1700 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
1705 bool qemu_ram_is_shared(RAMBlock
*rb
)
1707 return rb
->flags
& RAM_SHARED
;
1710 /* Called with iothread lock held. */
1711 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
1716 assert(!new_block
->idstr
[0]);
1719 char *id
= qdev_get_dev_path(dev
);
1721 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
1725 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
1728 RAMBLOCK_FOREACH(block
) {
1729 if (block
!= new_block
&&
1730 !strcmp(block
->idstr
, new_block
->idstr
)) {
1731 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
1739 /* Called with iothread lock held. */
1740 void qemu_ram_unset_idstr(RAMBlock
*block
)
1742 /* FIXME: arch_init.c assumes that this is not called throughout
1743 * migration. Ignore the problem since hot-unplug during migration
1744 * does not work anyway.
1747 memset(block
->idstr
, 0, sizeof(block
->idstr
));
1751 size_t qemu_ram_pagesize(RAMBlock
*rb
)
1753 return rb
->page_size
;
1756 /* Returns the largest size of page in use */
1757 size_t qemu_ram_pagesize_largest(void)
1762 RAMBLOCK_FOREACH(block
) {
1763 largest
= MAX(largest
, qemu_ram_pagesize(block
));
1769 static int memory_try_enable_merging(void *addr
, size_t len
)
1771 if (!machine_mem_merge(current_machine
)) {
1772 /* disabled by the user */
1776 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
1779 /* Only legal before guest might have detected the memory size: e.g. on
1780 * incoming migration, or right after reset.
1782 * As memory core doesn't know how is memory accessed, it is up to
1783 * resize callback to update device state and/or add assertions to detect
1784 * misuse, if necessary.
1786 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
1790 newsize
= HOST_PAGE_ALIGN(newsize
);
1792 if (block
->used_length
== newsize
) {
1796 if (!(block
->flags
& RAM_RESIZEABLE
)) {
1797 error_setg_errno(errp
, EINVAL
,
1798 "Length mismatch: %s: 0x" RAM_ADDR_FMT
1799 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
1800 newsize
, block
->used_length
);
1804 if (block
->max_length
< newsize
) {
1805 error_setg_errno(errp
, EINVAL
,
1806 "Length too large: %s: 0x" RAM_ADDR_FMT
1807 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
1808 newsize
, block
->max_length
);
1812 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
1813 block
->used_length
= newsize
;
1814 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
1816 memory_region_set_size(block
->mr
, newsize
);
1817 if (block
->resized
) {
1818 block
->resized(block
->idstr
, newsize
, block
->host
);
1823 /* Called with ram_list.mutex held */
1824 static void dirty_memory_extend(ram_addr_t old_ram_size
,
1825 ram_addr_t new_ram_size
)
1827 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
1828 DIRTY_MEMORY_BLOCK_SIZE
);
1829 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
1830 DIRTY_MEMORY_BLOCK_SIZE
);
1833 /* Only need to extend if block count increased */
1834 if (new_num_blocks
<= old_num_blocks
) {
1838 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
1839 DirtyMemoryBlocks
*old_blocks
;
1840 DirtyMemoryBlocks
*new_blocks
;
1843 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
1844 new_blocks
= g_malloc(sizeof(*new_blocks
) +
1845 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
1847 if (old_num_blocks
) {
1848 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
1849 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
1852 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
1853 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
1856 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
1859 g_free_rcu(old_blocks
, rcu
);
1864 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
)
1867 RAMBlock
*last_block
= NULL
;
1868 ram_addr_t old_ram_size
, new_ram_size
;
1871 old_ram_size
= last_ram_page();
1873 qemu_mutex_lock_ramlist();
1874 new_block
->offset
= find_ram_offset(new_block
->max_length
);
1876 if (!new_block
->host
) {
1877 if (xen_enabled()) {
1878 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
1879 new_block
->mr
, &err
);
1881 error_propagate(errp
, err
);
1882 qemu_mutex_unlock_ramlist();
1886 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
1887 &new_block
->mr
->align
);
1888 if (!new_block
->host
) {
1889 error_setg_errno(errp
, errno
,
1890 "cannot set up guest memory '%s'",
1891 memory_region_name(new_block
->mr
));
1892 qemu_mutex_unlock_ramlist();
1895 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
1899 new_ram_size
= MAX(old_ram_size
,
1900 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
1901 if (new_ram_size
> old_ram_size
) {
1902 dirty_memory_extend(old_ram_size
, new_ram_size
);
1904 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
1905 * QLIST (which has an RCU-friendly variant) does not have insertion at
1906 * tail, so save the last element in last_block.
1908 RAMBLOCK_FOREACH(block
) {
1910 if (block
->max_length
< new_block
->max_length
) {
1915 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
1916 } else if (last_block
) {
1917 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
1918 } else { /* list is empty */
1919 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
1921 ram_list
.mru_block
= NULL
;
1923 /* Write list before version */
1926 qemu_mutex_unlock_ramlist();
1928 cpu_physical_memory_set_dirty_range(new_block
->offset
,
1929 new_block
->used_length
,
1932 if (new_block
->host
) {
1933 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
1934 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
1935 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
1936 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
1937 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
1942 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
1946 RAMBlock
*new_block
;
1947 Error
*local_err
= NULL
;
1950 if (xen_enabled()) {
1951 error_setg(errp
, "-mem-path not supported with Xen");
1955 if (kvm_enabled() && !kvm_has_sync_mmu()) {
1957 "host lacks kvm mmu notifiers, -mem-path unsupported");
1961 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
1963 * file_ram_alloc() needs to allocate just like
1964 * phys_mem_alloc, but we haven't bothered to provide
1968 "-mem-path not supported with this accelerator");
1972 size
= HOST_PAGE_ALIGN(size
);
1973 file_size
= get_file_size(fd
);
1974 if (file_size
> 0 && file_size
< size
) {
1975 error_setg(errp
, "backing store %s size 0x%" PRIx64
1976 " does not match 'size' option 0x" RAM_ADDR_FMT
,
1977 mem_path
, file_size
, size
);
1981 new_block
= g_malloc0(sizeof(*new_block
));
1983 new_block
->used_length
= size
;
1984 new_block
->max_length
= size
;
1985 new_block
->flags
= share
? RAM_SHARED
: 0;
1986 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
1987 if (!new_block
->host
) {
1992 ram_block_add(new_block
, &local_err
);
1995 error_propagate(errp
, local_err
);
2003 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2004 bool share
, const char *mem_path
,
2011 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2016 block
= qemu_ram_alloc_from_fd(size
, mr
, share
, fd
, errp
);
2030 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2031 void (*resized
)(const char*,
2034 void *host
, bool resizeable
,
2035 MemoryRegion
*mr
, Error
**errp
)
2037 RAMBlock
*new_block
;
2038 Error
*local_err
= NULL
;
2040 size
= HOST_PAGE_ALIGN(size
);
2041 max_size
= HOST_PAGE_ALIGN(max_size
);
2042 new_block
= g_malloc0(sizeof(*new_block
));
2044 new_block
->resized
= resized
;
2045 new_block
->used_length
= size
;
2046 new_block
->max_length
= max_size
;
2047 assert(max_size
>= size
);
2049 new_block
->page_size
= getpagesize();
2050 new_block
->host
= host
;
2052 new_block
->flags
|= RAM_PREALLOC
;
2055 new_block
->flags
|= RAM_RESIZEABLE
;
2057 ram_block_add(new_block
, &local_err
);
2060 error_propagate(errp
, local_err
);
2066 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2067 MemoryRegion
*mr
, Error
**errp
)
2069 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false, mr
, errp
);
2072 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, MemoryRegion
*mr
, Error
**errp
)
2074 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false, mr
, errp
);
2077 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2078 void (*resized
)(const char*,
2081 MemoryRegion
*mr
, Error
**errp
)
2083 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true, mr
, errp
);
2086 static void reclaim_ramblock(RAMBlock
*block
)
2088 if (block
->flags
& RAM_PREALLOC
) {
2090 } else if (xen_enabled()) {
2091 xen_invalidate_map_cache_entry(block
->host
);
2093 } else if (block
->fd
>= 0) {
2094 qemu_ram_munmap(block
->host
, block
->max_length
);
2098 qemu_anon_ram_free(block
->host
, block
->max_length
);
2103 void qemu_ram_free(RAMBlock
*block
)
2110 ram_block_notify_remove(block
->host
, block
->max_length
);
2113 qemu_mutex_lock_ramlist();
2114 QLIST_REMOVE_RCU(block
, next
);
2115 ram_list
.mru_block
= NULL
;
2116 /* Write list before version */
2119 call_rcu(block
, reclaim_ramblock
, rcu
);
2120 qemu_mutex_unlock_ramlist();
2124 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2131 RAMBLOCK_FOREACH(block
) {
2132 offset
= addr
- block
->offset
;
2133 if (offset
< block
->max_length
) {
2134 vaddr
= ramblock_ptr(block
, offset
);
2135 if (block
->flags
& RAM_PREALLOC
) {
2137 } else if (xen_enabled()) {
2141 if (block
->fd
>= 0) {
2142 flags
|= (block
->flags
& RAM_SHARED
?
2143 MAP_SHARED
: MAP_PRIVATE
);
2144 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2145 flags
, block
->fd
, offset
);
2148 * Remap needs to match alloc. Accelerators that
2149 * set phys_mem_alloc never remap. If they did,
2150 * we'd need a remap hook here.
2152 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2154 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2155 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2158 if (area
!= vaddr
) {
2159 fprintf(stderr
, "Could not remap addr: "
2160 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"\n",
2164 memory_try_enable_merging(vaddr
, length
);
2165 qemu_ram_setup_dump(vaddr
, length
);
2170 #endif /* !_WIN32 */
2172 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2173 * This should not be used for general purpose DMA. Use address_space_map
2174 * or address_space_rw instead. For local memory (e.g. video ram) that the
2175 * device owns, use memory_region_get_ram_ptr.
2177 * Called within RCU critical section.
2179 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2181 RAMBlock
*block
= ram_block
;
2183 if (block
== NULL
) {
2184 block
= qemu_get_ram_block(addr
);
2185 addr
-= block
->offset
;
2188 if (xen_enabled() && block
->host
== NULL
) {
2189 /* We need to check if the requested address is in the RAM
2190 * because we don't want to map the entire memory in QEMU.
2191 * In that case just map until the end of the page.
2193 if (block
->offset
== 0) {
2194 return xen_map_cache(addr
, 0, 0, false);
2197 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2199 return ramblock_ptr(block
, addr
);
2202 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2203 * but takes a size argument.
2205 * Called within RCU critical section.
2207 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2208 hwaddr
*size
, bool lock
)
2210 RAMBlock
*block
= ram_block
;
2215 if (block
== NULL
) {
2216 block
= qemu_get_ram_block(addr
);
2217 addr
-= block
->offset
;
2219 *size
= MIN(*size
, block
->max_length
- addr
);
2221 if (xen_enabled() && block
->host
== NULL
) {
2222 /* We need to check if the requested address is in the RAM
2223 * because we don't want to map the entire memory in QEMU.
2224 * In that case just map the requested area.
2226 if (block
->offset
== 0) {
2227 return xen_map_cache(addr
, *size
, lock
, lock
);
2230 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2233 return ramblock_ptr(block
, addr
);
2237 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2240 * ptr: Host pointer to look up
2241 * round_offset: If true round the result offset down to a page boundary
2242 * *ram_addr: set to result ram_addr
2243 * *offset: set to result offset within the RAMBlock
2245 * Returns: RAMBlock (or NULL if not found)
2247 * By the time this function returns, the returned pointer is not protected
2248 * by RCU anymore. If the caller is not within an RCU critical section and
2249 * does not hold the iothread lock, it must have other means of protecting the
2250 * pointer, such as a reference to the region that includes the incoming
2253 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2257 uint8_t *host
= ptr
;
2259 if (xen_enabled()) {
2260 ram_addr_t ram_addr
;
2262 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2263 block
= qemu_get_ram_block(ram_addr
);
2265 *offset
= ram_addr
- block
->offset
;
2272 block
= atomic_rcu_read(&ram_list
.mru_block
);
2273 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2277 RAMBLOCK_FOREACH(block
) {
2278 /* This case append when the block is not mapped. */
2279 if (block
->host
== NULL
) {
2282 if (host
- block
->host
< block
->max_length
) {
2291 *offset
= (host
- block
->host
);
2293 *offset
&= TARGET_PAGE_MASK
;
2300 * Finds the named RAMBlock
2302 * name: The name of RAMBlock to find
2304 * Returns: RAMBlock (or NULL if not found)
2306 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2310 RAMBLOCK_FOREACH(block
) {
2311 if (!strcmp(name
, block
->idstr
)) {
2319 /* Some of the softmmu routines need to translate from a host pointer
2320 (typically a TLB entry) back to a ram offset. */
2321 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2326 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2328 return RAM_ADDR_INVALID
;
2331 return block
->offset
+ offset
;
2334 /* Called within RCU critical section. */
2335 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2336 uint64_t val
, unsigned size
)
2338 bool locked
= false;
2340 assert(tcg_enabled());
2341 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2344 tb_invalidate_phys_page_fast(ram_addr
, size
);
2348 stb_p(qemu_map_ram_ptr(NULL
, ram_addr
), val
);
2351 stw_p(qemu_map_ram_ptr(NULL
, ram_addr
), val
);
2354 stl_p(qemu_map_ram_ptr(NULL
, ram_addr
), val
);
2364 /* Set both VGA and migration bits for simplicity and to remove
2365 * the notdirty callback faster.
2367 cpu_physical_memory_set_dirty_range(ram_addr
, size
,
2368 DIRTY_CLIENTS_NOCODE
);
2369 /* we remove the notdirty callback only if the code has been
2371 if (!cpu_physical_memory_is_clean(ram_addr
)) {
2372 tlb_set_dirty(current_cpu
, current_cpu
->mem_io_vaddr
);
2376 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2377 unsigned size
, bool is_write
)
2382 static const MemoryRegionOps notdirty_mem_ops
= {
2383 .write
= notdirty_mem_write
,
2384 .valid
.accepts
= notdirty_mem_accepts
,
2385 .endianness
= DEVICE_NATIVE_ENDIAN
,
2388 /* Generate a debug exception if a watchpoint has been hit. */
2389 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2391 CPUState
*cpu
= current_cpu
;
2392 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2393 CPUArchState
*env
= cpu
->env_ptr
;
2394 target_ulong pc
, cs_base
;
2399 assert(tcg_enabled());
2400 if (cpu
->watchpoint_hit
) {
2401 /* We re-entered the check after replacing the TB. Now raise
2402 * the debug interrupt so that is will trigger after the
2403 * current instruction. */
2404 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2407 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2408 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2409 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2410 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2411 && (wp
->flags
& flags
)) {
2412 if (flags
== BP_MEM_READ
) {
2413 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2415 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2417 wp
->hitaddr
= vaddr
;
2418 wp
->hitattrs
= attrs
;
2419 if (!cpu
->watchpoint_hit
) {
2420 if (wp
->flags
& BP_CPU
&&
2421 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2422 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2425 cpu
->watchpoint_hit
= wp
;
2427 /* Both tb_lock and iothread_mutex will be reset when
2428 * cpu_loop_exit or cpu_loop_exit_noexc longjmp
2429 * back into the cpu_exec main loop.
2432 tb_check_watchpoint(cpu
);
2433 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2434 cpu
->exception_index
= EXCP_DEBUG
;
2437 cpu_get_tb_cpu_state(env
, &pc
, &cs_base
, &cpu_flags
);
2438 tb_gen_code(cpu
, pc
, cs_base
, cpu_flags
, 1);
2439 cpu_loop_exit_noexc(cpu
);
2443 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2448 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2449 so these check for a hit then pass through to the normal out-of-line
2451 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2452 unsigned size
, MemTxAttrs attrs
)
2456 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2457 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2459 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2462 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2465 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2468 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2476 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2477 uint64_t val
, unsigned size
,
2481 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2482 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2484 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2487 address_space_stb(as
, addr
, val
, attrs
, &res
);
2490 address_space_stw(as
, addr
, val
, attrs
, &res
);
2493 address_space_stl(as
, addr
, val
, attrs
, &res
);
2500 static const MemoryRegionOps watch_mem_ops
= {
2501 .read_with_attrs
= watch_mem_read
,
2502 .write_with_attrs
= watch_mem_write
,
2503 .endianness
= DEVICE_NATIVE_ENDIAN
,
2506 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2507 const uint8_t *buf
, int len
);
2508 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
2511 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2512 unsigned len
, MemTxAttrs attrs
)
2514 subpage_t
*subpage
= opaque
;
2518 #if defined(DEBUG_SUBPAGE)
2519 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2520 subpage
, len
, addr
);
2522 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2528 *data
= ldub_p(buf
);
2531 *data
= lduw_p(buf
);
2544 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2545 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2547 subpage_t
*subpage
= opaque
;
2550 #if defined(DEBUG_SUBPAGE)
2551 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2552 " value %"PRIx64
"\n",
2553 __func__
, subpage
, len
, addr
, value
);
2571 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2574 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2575 unsigned len
, bool is_write
)
2577 subpage_t
*subpage
= opaque
;
2578 #if defined(DEBUG_SUBPAGE)
2579 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2580 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2583 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2587 static const MemoryRegionOps subpage_ops
= {
2588 .read_with_attrs
= subpage_read
,
2589 .write_with_attrs
= subpage_write
,
2590 .impl
.min_access_size
= 1,
2591 .impl
.max_access_size
= 8,
2592 .valid
.min_access_size
= 1,
2593 .valid
.max_access_size
= 8,
2594 .valid
.accepts
= subpage_accepts
,
2595 .endianness
= DEVICE_NATIVE_ENDIAN
,
2598 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2603 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2605 idx
= SUBPAGE_IDX(start
);
2606 eidx
= SUBPAGE_IDX(end
);
2607 #if defined(DEBUG_SUBPAGE)
2608 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2609 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2611 for (; idx
<= eidx
; idx
++) {
2612 mmio
->sub_section
[idx
] = section
;
2618 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
2622 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
2625 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
2626 NULL
, TARGET_PAGE_SIZE
);
2627 mmio
->iomem
.subpage
= true;
2628 #if defined(DEBUG_SUBPAGE)
2629 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
2630 mmio
, base
, TARGET_PAGE_SIZE
);
2632 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
2637 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
2640 MemoryRegionSection section
= {
2643 .offset_within_address_space
= 0,
2644 .offset_within_region
= 0,
2645 .size
= int128_2_64(),
2648 return phys_section_add(map
, §ion
);
2651 MemoryRegion
*iotlb_to_region(CPUState
*cpu
, hwaddr index
, MemTxAttrs attrs
)
2653 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
2654 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
2655 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
2656 MemoryRegionSection
*sections
= d
->map
.sections
;
2658 return sections
[index
& ~TARGET_PAGE_MASK
].mr
;
2661 static void io_mem_init(void)
2663 memory_region_init_io(&io_mem_rom
, NULL
, &unassigned_mem_ops
, NULL
, NULL
, UINT64_MAX
);
2664 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
2667 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
2668 * which can be called without the iothread mutex.
2670 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
2672 memory_region_clear_global_locking(&io_mem_notdirty
);
2674 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
2678 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
2680 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
2683 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
2684 assert(n
== PHYS_SECTION_UNASSIGNED
);
2685 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
2686 assert(n
== PHYS_SECTION_NOTDIRTY
);
2687 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
2688 assert(n
== PHYS_SECTION_ROM
);
2689 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
2690 assert(n
== PHYS_SECTION_WATCH
);
2692 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
2697 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
2699 phys_sections_free(&d
->map
);
2703 static void tcg_commit(MemoryListener
*listener
)
2705 CPUAddressSpace
*cpuas
;
2706 AddressSpaceDispatch
*d
;
2708 /* since each CPU stores ram addresses in its TLB cache, we must
2709 reset the modified entries */
2710 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
2711 cpu_reloading_memory_map();
2712 /* The CPU and TLB are protected by the iothread lock.
2713 * We reload the dispatch pointer now because cpu_reloading_memory_map()
2714 * may have split the RCU critical section.
2716 d
= address_space_to_dispatch(cpuas
->as
);
2717 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
2718 tlb_flush(cpuas
->cpu
);
2721 static void memory_map_init(void)
2723 system_memory
= g_malloc(sizeof(*system_memory
));
2725 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
2726 address_space_init(&address_space_memory
, system_memory
, "memory");
2728 system_io
= g_malloc(sizeof(*system_io
));
2729 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
2731 address_space_init(&address_space_io
, system_io
, "I/O");
2734 MemoryRegion
*get_system_memory(void)
2736 return system_memory
;
2739 MemoryRegion
*get_system_io(void)
2744 #endif /* !defined(CONFIG_USER_ONLY) */
2746 /* physical memory access (slow version, mainly for debug) */
2747 #if defined(CONFIG_USER_ONLY)
2748 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
2749 uint8_t *buf
, int len
, int is_write
)
2756 page
= addr
& TARGET_PAGE_MASK
;
2757 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
2760 flags
= page_get_flags(page
);
2761 if (!(flags
& PAGE_VALID
))
2764 if (!(flags
& PAGE_WRITE
))
2766 /* XXX: this code should not depend on lock_user */
2767 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
2770 unlock_user(p
, addr
, l
);
2772 if (!(flags
& PAGE_READ
))
2774 /* XXX: this code should not depend on lock_user */
2775 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
2778 unlock_user(p
, addr
, 0);
2789 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
2792 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
2793 addr
+= memory_region_get_ram_addr(mr
);
2795 /* No early return if dirty_log_mask is or becomes 0, because
2796 * cpu_physical_memory_set_dirty_range will still call
2797 * xen_modified_memory.
2799 if (dirty_log_mask
) {
2801 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
2803 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
2804 assert(tcg_enabled());
2806 tb_invalidate_phys_range(addr
, addr
+ length
);
2808 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
2810 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
2813 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
2815 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
2817 /* Regions are assumed to support 1-4 byte accesses unless
2818 otherwise specified. */
2819 if (access_size_max
== 0) {
2820 access_size_max
= 4;
2823 /* Bound the maximum access by the alignment of the address. */
2824 if (!mr
->ops
->impl
.unaligned
) {
2825 unsigned align_size_max
= addr
& -addr
;
2826 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
2827 access_size_max
= align_size_max
;
2831 /* Don't attempt accesses larger than the maximum. */
2832 if (l
> access_size_max
) {
2833 l
= access_size_max
;
2840 static bool prepare_mmio_access(MemoryRegion
*mr
)
2842 bool unlocked
= !qemu_mutex_iothread_locked();
2843 bool release_lock
= false;
2845 if (unlocked
&& mr
->global_locking
) {
2846 qemu_mutex_lock_iothread();
2848 release_lock
= true;
2850 if (mr
->flush_coalesced_mmio
) {
2852 qemu_mutex_lock_iothread();
2854 qemu_flush_coalesced_mmio_buffer();
2856 qemu_mutex_unlock_iothread();
2860 return release_lock
;
2863 /* Called within RCU critical section. */
2864 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
2867 int len
, hwaddr addr1
,
2868 hwaddr l
, MemoryRegion
*mr
)
2872 MemTxResult result
= MEMTX_OK
;
2873 bool release_lock
= false;
2876 if (!memory_access_is_direct(mr
, true)) {
2877 release_lock
|= prepare_mmio_access(mr
);
2878 l
= memory_access_size(mr
, l
, addr1
);
2879 /* XXX: could force current_cpu to NULL to avoid
2883 /* 64 bit write access */
2885 result
|= memory_region_dispatch_write(mr
, addr1
, val
, 8,
2889 /* 32 bit write access */
2890 val
= (uint32_t)ldl_p(buf
);
2891 result
|= memory_region_dispatch_write(mr
, addr1
, val
, 4,
2895 /* 16 bit write access */
2897 result
|= memory_region_dispatch_write(mr
, addr1
, val
, 2,
2901 /* 8 bit write access */
2903 result
|= memory_region_dispatch_write(mr
, addr1
, val
, 1,
2911 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
2912 memcpy(ptr
, buf
, l
);
2913 invalidate_and_set_dirty(mr
, addr1
, l
);
2917 qemu_mutex_unlock_iothread();
2918 release_lock
= false;
2930 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true);
2936 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2937 const uint8_t *buf
, int len
)
2942 MemTxResult result
= MEMTX_OK
;
2947 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true);
2948 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
2956 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
2958 const uint8_t *buf
, int len
)
2960 return flatview_write(address_space_to_flatview(as
), addr
, attrs
, buf
, len
);
2963 /* Called within RCU critical section. */
2964 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
2965 MemTxAttrs attrs
, uint8_t *buf
,
2966 int len
, hwaddr addr1
, hwaddr l
,
2971 MemTxResult result
= MEMTX_OK
;
2972 bool release_lock
= false;
2975 if (!memory_access_is_direct(mr
, false)) {
2977 release_lock
|= prepare_mmio_access(mr
);
2978 l
= memory_access_size(mr
, l
, addr1
);
2981 /* 64 bit read access */
2982 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, 8,
2987 /* 32 bit read access */
2988 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, 4,
2993 /* 16 bit read access */
2994 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, 2,
2999 /* 8 bit read access */
3000 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, 1,
3009 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3010 memcpy(buf
, ptr
, l
);
3014 qemu_mutex_unlock_iothread();
3015 release_lock
= false;
3027 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false);
3033 MemTxResult
flatview_read_full(FlatView
*fv
, hwaddr addr
,
3034 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3039 MemTxResult result
= MEMTX_OK
;
3044 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false);
3045 result
= flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3053 static MemTxResult
flatview_rw(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3054 uint8_t *buf
, int len
, bool is_write
)
3057 return flatview_write(fv
, addr
, attrs
, (uint8_t *)buf
, len
);
3059 return flatview_read(fv
, addr
, attrs
, (uint8_t *)buf
, len
);
3063 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
,
3064 MemTxAttrs attrs
, uint8_t *buf
,
3065 int len
, bool is_write
)
3067 return flatview_rw(address_space_to_flatview(as
),
3068 addr
, attrs
, buf
, len
, is_write
);
3071 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3072 int len
, int is_write
)
3074 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3075 buf
, len
, is_write
);
3078 enum write_rom_type
{
3083 static inline void cpu_physical_memory_write_rom_internal(AddressSpace
*as
,
3084 hwaddr addr
, const uint8_t *buf
, int len
, enum write_rom_type type
)
3094 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true);
3096 if (!(memory_region_is_ram(mr
) ||
3097 memory_region_is_romd(mr
))) {
3098 l
= memory_access_size(mr
, l
, addr1
);
3101 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3104 memcpy(ptr
, buf
, l
);
3105 invalidate_and_set_dirty(mr
, addr1
, l
);
3108 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3119 /* used for ROM loading : can write in RAM and ROM */
3120 void cpu_physical_memory_write_rom(AddressSpace
*as
, hwaddr addr
,
3121 const uint8_t *buf
, int len
)
3123 cpu_physical_memory_write_rom_internal(as
, addr
, buf
, len
, WRITE_DATA
);
3126 void cpu_flush_icache_range(hwaddr start
, int len
)
3129 * This function should do the same thing as an icache flush that was
3130 * triggered from within the guest. For TCG we are always cache coherent,
3131 * so there is no need to flush anything. For KVM / Xen we need to flush
3132 * the host's instruction cache at least.
3134 if (tcg_enabled()) {
3138 cpu_physical_memory_write_rom_internal(&address_space_memory
,
3139 start
, NULL
, len
, FLUSH_CACHE
);
3150 static BounceBuffer bounce
;
3152 typedef struct MapClient
{
3154 QLIST_ENTRY(MapClient
) link
;
3157 QemuMutex map_client_list_lock
;
3158 static QLIST_HEAD(map_client_list
, MapClient
) map_client_list
3159 = QLIST_HEAD_INITIALIZER(map_client_list
);
3161 static void cpu_unregister_map_client_do(MapClient
*client
)
3163 QLIST_REMOVE(client
, link
);
3167 static void cpu_notify_map_clients_locked(void)
3171 while (!QLIST_EMPTY(&map_client_list
)) {
3172 client
= QLIST_FIRST(&map_client_list
);
3173 qemu_bh_schedule(client
->bh
);
3174 cpu_unregister_map_client_do(client
);
3178 void cpu_register_map_client(QEMUBH
*bh
)
3180 MapClient
*client
= g_malloc(sizeof(*client
));
3182 qemu_mutex_lock(&map_client_list_lock
);
3184 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3185 if (!atomic_read(&bounce
.in_use
)) {
3186 cpu_notify_map_clients_locked();
3188 qemu_mutex_unlock(&map_client_list_lock
);
3191 void cpu_exec_init_all(void)
3193 qemu_mutex_init(&ram_list
.mutex
);
3194 /* The data structures we set up here depend on knowing the page size,
3195 * so no more changes can be made after this point.
3196 * In an ideal world, nothing we did before we had finished the
3197 * machine setup would care about the target page size, and we could
3198 * do this much later, rather than requiring board models to state
3199 * up front what their requirements are.
3201 finalize_target_page_bits();
3204 qemu_mutex_init(&map_client_list_lock
);
3207 void cpu_unregister_map_client(QEMUBH
*bh
)
3211 qemu_mutex_lock(&map_client_list_lock
);
3212 QLIST_FOREACH(client
, &map_client_list
, link
) {
3213 if (client
->bh
== bh
) {
3214 cpu_unregister_map_client_do(client
);
3218 qemu_mutex_unlock(&map_client_list_lock
);
3221 static void cpu_notify_map_clients(void)
3223 qemu_mutex_lock(&map_client_list_lock
);
3224 cpu_notify_map_clients_locked();
3225 qemu_mutex_unlock(&map_client_list_lock
);
3228 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
3237 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
);
3238 if (!memory_access_is_direct(mr
, is_write
)) {
3239 l
= memory_access_size(mr
, l
, addr
);
3240 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
)) {
3253 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3254 int len
, bool is_write
)
3256 return flatview_access_valid(address_space_to_flatview(as
),
3257 addr
, len
, is_write
);
3261 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3263 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3268 MemoryRegion
*this_mr
;
3274 if (target_len
== 0) {
3279 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3281 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3287 /* Map a physical memory region into a host virtual address.
3288 * May map a subset of the requested range, given by and returned in *plen.
3289 * May return NULL if resources needed to perform the mapping are exhausted.
3290 * Use only for reads OR writes - not for read-modify-write operations.
3291 * Use cpu_register_map_client() to know when retrying the map operation is
3292 * likely to succeed.
3294 void *address_space_map(AddressSpace
*as
,
3303 FlatView
*fv
= address_space_to_flatview(as
);
3311 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
);
3313 if (!memory_access_is_direct(mr
, is_write
)) {
3314 if (atomic_xchg(&bounce
.in_use
, true)) {
3318 /* Avoid unbounded allocations */
3319 l
= MIN(l
, TARGET_PAGE_SIZE
);
3320 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3324 memory_region_ref(mr
);
3327 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3333 return bounce
.buffer
;
3337 memory_region_ref(mr
);
3338 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3340 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3346 /* Unmaps a memory region previously mapped by address_space_map().
3347 * Will also mark the memory as dirty if is_write == 1. access_len gives
3348 * the amount of memory that was actually read or written by the caller.
3350 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3351 int is_write
, hwaddr access_len
)
3353 if (buffer
!= bounce
.buffer
) {
3357 mr
= memory_region_from_host(buffer
, &addr1
);
3360 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3362 if (xen_enabled()) {
3363 xen_invalidate_map_cache_entry(buffer
);
3365 memory_region_unref(mr
);
3369 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3370 bounce
.buffer
, access_len
);
3372 qemu_vfree(bounce
.buffer
);
3373 bounce
.buffer
= NULL
;
3374 memory_region_unref(bounce
.mr
);
3375 atomic_mb_set(&bounce
.in_use
, false);
3376 cpu_notify_map_clients();
3379 void *cpu_physical_memory_map(hwaddr addr
,
3383 return address_space_map(&address_space_memory
, addr
, plen
, is_write
);
3386 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3387 int is_write
, hwaddr access_len
)
3389 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3392 #define ARG1_DECL AddressSpace *as
3395 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3396 #define IS_DIRECT(mr, is_write) memory_access_is_direct(mr, is_write)
3397 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3398 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3399 #define RCU_READ_LOCK(...) rcu_read_lock()
3400 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3401 #include "memory_ldst.inc.c"
3403 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3415 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3421 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3426 #define ARG1_DECL MemoryRegionCache *cache
3428 #define SUFFIX _cached
3429 #define TRANSLATE(addr, ...) \
3430 address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
3431 #define IS_DIRECT(mr, is_write) true
3432 #define MAP_RAM(mr, ofs) qemu_map_ram_ptr((mr)->ram_block, ofs)
3433 #define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
3434 #define RCU_READ_LOCK() rcu_read_lock()
3435 #define RCU_READ_UNLOCK() rcu_read_unlock()
3436 #include "memory_ldst.inc.c"
3438 /* virtual memory access for debug (includes writing to ROM) */
3439 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3440 uint8_t *buf
, int len
, int is_write
)
3446 cpu_synchronize_state(cpu
);
3451 page
= addr
& TARGET_PAGE_MASK
;
3452 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3453 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3454 /* if no physical page mapped, return an error */
3455 if (phys_addr
== -1)
3457 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3460 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3462 cpu_physical_memory_write_rom(cpu
->cpu_ases
[asidx
].as
,
3465 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3466 MEMTXATTRS_UNSPECIFIED
,
3477 * Allows code that needs to deal with migration bitmaps etc to still be built
3478 * target independent.
3480 size_t qemu_target_page_size(void)
3482 return TARGET_PAGE_SIZE
;
3485 int qemu_target_page_bits(void)
3487 return TARGET_PAGE_BITS
;
3490 int qemu_target_page_bits_min(void)
3492 return TARGET_PAGE_BITS_MIN
;
3497 * A helper function for the _utterly broken_ virtio device model to find out if
3498 * it's running on a big endian machine. Don't do this at home kids!
3500 bool target_words_bigendian(void);
3501 bool target_words_bigendian(void)
3503 #if defined(TARGET_WORDS_BIGENDIAN)
3510 #ifndef CONFIG_USER_ONLY
3511 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
3518 mr
= address_space_translate(&address_space_memory
,
3519 phys_addr
, &phys_addr
, &l
, false);
3521 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
3526 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
3532 RAMBLOCK_FOREACH(block
) {
3533 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3534 block
->used_length
, opaque
);
3544 * Unmap pages of memory from start to start+length such that
3545 * they a) read as 0, b) Trigger whatever fault mechanism
3546 * the OS provides for postcopy.
3547 * The pages must be unmapped by the end of the function.
3548 * Returns: 0 on success, none-0 on failure
3551 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
3555 uint8_t *host_startaddr
= rb
->host
+ start
;
3557 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
3558 error_report("ram_block_discard_range: Unaligned start address: %p",
3563 if ((start
+ length
) <= rb
->used_length
) {
3564 uint8_t *host_endaddr
= host_startaddr
+ length
;
3565 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
3566 error_report("ram_block_discard_range: Unaligned end address: %p",
3571 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
3573 if (rb
->page_size
== qemu_host_page_size
) {
3574 #if defined(CONFIG_MADVISE)
3575 /* Note: We need the madvise MADV_DONTNEED behaviour of definitely
3578 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
3581 /* Huge page case - unfortunately it can't do DONTNEED, but
3582 * it can do the equivalent by FALLOC_FL_PUNCH_HOLE in the
3585 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
3586 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
3592 error_report("ram_block_discard_range: Failed to discard range "
3593 "%s:%" PRIx64
" +%zx (%d)",
3594 rb
->idstr
, start
, length
, ret
);
3597 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
3598 "/%zx/" RAM_ADDR_FMT
")",
3599 rb
->idstr
, start
, length
, rb
->used_length
);
3608 void page_size_init(void)
3610 /* NOTE: we can always suppose that qemu_host_page_size >=
3612 if (qemu_host_page_size
== 0) {
3613 qemu_host_page_size
= qemu_real_host_page_size
;
3615 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
3616 qemu_host_page_size
= TARGET_PAGE_SIZE
;
3618 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
3621 #if !defined(CONFIG_USER_ONLY)
3623 static void mtree_print_phys_entries(fprintf_function mon
, void *f
,
3624 int start
, int end
, int skip
, int ptr
)
3626 if (start
== end
- 1) {
3627 mon(f
, "\t%3d ", start
);
3629 mon(f
, "\t%3d..%-3d ", start
, end
- 1);
3631 mon(f
, " skip=%d ", skip
);
3632 if (ptr
== PHYS_MAP_NODE_NIL
) {
3635 mon(f
, " ptr=#%d", ptr
);
3637 mon(f
, " ptr=[%d]", ptr
);
3642 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
3643 int128_sub((size), int128_one())) : 0)
3645 void mtree_print_dispatch(fprintf_function mon
, void *f
,
3646 AddressSpaceDispatch
*d
, MemoryRegion
*root
)
3650 mon(f
, " Dispatch\n");
3651 mon(f
, " Physical sections\n");
3653 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
3654 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
3655 const char *names
[] = { " [unassigned]", " [not dirty]",
3656 " [ROM]", " [watch]" };
3658 mon(f
, " #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
" %s%s%s%s%s",
3660 s
->offset_within_address_space
,
3661 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
3662 s
->mr
->name
? s
->mr
->name
: "(noname)",
3663 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
3664 s
->mr
== root
? " [ROOT]" : "",
3665 s
== d
->mru_section
? " [MRU]" : "",
3666 s
->mr
->is_iommu
? " [iommu]" : "");
3669 mon(f
, " alias=%s", s
->mr
->alias
->name
?
3670 s
->mr
->alias
->name
: "noname");
3675 mon(f
, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
3676 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
3677 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
3680 Node
*n
= d
->map
.nodes
+ i
;
3682 mon(f
, " [%d]\n", i
);
3684 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
3685 PhysPageEntry
*pe
= *n
+ j
;
3687 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
3691 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);
3697 if (jprev
!= ARRAY_SIZE(*n
)) {
3698 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);