2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "hw/sysbus.h"
34 #include "hw/arm/arm.h"
35 #include "hw/arm/primecell.h"
36 #include "hw/arm/virt.h"
37 #include "hw/devices.h"
39 #include "sysemu/block-backend.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/numa.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/kvm.h"
44 #include "hw/boards.h"
45 #include "hw/compat.h"
46 #include "hw/loader.h"
47 #include "exec/address-spaces.h"
48 #include "qemu/bitops.h"
49 #include "qemu/error-report.h"
50 #include "hw/pci-host/gpex.h"
51 #include "hw/arm/virt-acpi-build.h"
52 #include "hw/arm/sysbus-fdt.h"
53 #include "hw/platform-bus.h"
54 #include "hw/arm/fdt.h"
55 #include "hw/intc/arm_gic.h"
56 #include "hw/intc/arm_gicv3_common.h"
58 #include "hw/smbios/smbios.h"
59 #include "qapi/visitor.h"
60 #include "standard-headers/linux/input.h"
62 /* Number of external interrupt lines to configure the GIC with */
65 #define PLATFORM_BUS_NUM_IRQS 64
67 static ARMPlatformBusSystemParams platform_bus_params
;
71 bool disallow_affinity_adjustment
;
74 bool claim_edge_triggered_timers
;
79 VirtGuestInfo acpi_guest_info
;
80 Notifier machine_done
;
84 struct arm_boot_info bootinfo
;
85 const MemMapEntry
*memmap
;
90 uint32_t clock_phandle
;
96 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
97 #define VIRT_MACHINE(obj) \
98 OBJECT_CHECK(VirtMachineState, (obj), TYPE_VIRT_MACHINE)
99 #define VIRT_MACHINE_GET_CLASS(obj) \
100 OBJECT_GET_CLASS(VirtMachineClass, obj, TYPE_VIRT_MACHINE)
101 #define VIRT_MACHINE_CLASS(klass) \
102 OBJECT_CLASS_CHECK(VirtMachineClass, klass, TYPE_VIRT_MACHINE)
105 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
106 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
109 MachineClass *mc = MACHINE_CLASS(oc); \
110 virt_machine_##major##_##minor##_options(mc); \
111 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
113 mc->alias = "virt"; \
116 static const TypeInfo machvirt_##major##_##minor##_info = { \
117 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
118 .parent = TYPE_VIRT_MACHINE, \
119 .instance_init = virt_##major##_##minor##_instance_init, \
120 .class_init = virt_##major##_##minor##_class_init, \
122 static void machvirt_machine_##major##_##minor##_init(void) \
124 type_register_static(&machvirt_##major##_##minor##_info); \
126 type_init(machvirt_machine_##major##_##minor##_init);
128 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
129 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
130 #define DEFINE_VIRT_MACHINE(major, minor) \
131 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
134 /* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
135 * RAM can go up to the 256GB mark, leaving 256GB of the physical
136 * address space unallocated and free for future use between 256G and 512G.
137 * If we need to provide more RAM to VMs in the future then we need to:
138 * * allocate a second bank of RAM starting at 2TB and working up
139 * * fix the DT and ACPI table generation code in QEMU to correctly
140 * report two split lumps of RAM to the guest
141 * * fix KVM in the host kernel to allow guests with >40 bit address spaces
142 * (We don't want to fill all the way up to 512GB with RAM because
143 * we might want it for non-RAM purposes later. Conversely it seems
144 * reasonable to assume that anybody configuring a VM with a quarter
145 * of a terabyte of RAM will be doing it on a host with more than a
146 * terabyte of physical address space.)
148 #define RAMLIMIT_GB 255
149 #define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
151 /* Addresses and sizes of our components.
152 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
153 * 128MB..256MB is used for miscellaneous device I/O.
154 * 256MB..1GB is reserved for possible future PCI support (ie where the
155 * PCI memory window will go if we add a PCI host controller).
156 * 1GB and up is RAM (which may happily spill over into the
157 * high memory region beyond 4GB).
158 * This represents a compromise between how much RAM can be given to
159 * a 32 bit VM and leaving space for expansion and in particular for PCI.
160 * Note that devices should generally be placed at multiples of 0x10000,
161 * to accommodate guests using 64K pages.
163 static const MemMapEntry a15memmap
[] = {
164 /* Space up to 0x8000000 is reserved for a boot ROM */
165 [VIRT_FLASH
] = { 0, 0x08000000 },
166 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
167 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
168 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
169 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
170 [VIRT_GIC_V2M
] = { 0x08020000, 0x00001000 },
171 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
172 [VIRT_GIC_ITS
] = { 0x08080000, 0x00020000 },
173 /* This redistributor space allows up to 2*64kB*123 CPUs */
174 [VIRT_GIC_REDIST
] = { 0x080A0000, 0x00F60000 },
175 [VIRT_UART
] = { 0x09000000, 0x00001000 },
176 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
177 [VIRT_FW_CFG
] = { 0x09020000, 0x00000018 },
178 [VIRT_GPIO
] = { 0x09030000, 0x00001000 },
179 [VIRT_SECURE_UART
] = { 0x09040000, 0x00001000 },
180 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
181 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
182 [VIRT_PLATFORM_BUS
] = { 0x0c000000, 0x02000000 },
183 [VIRT_SECURE_MEM
] = { 0x0e000000, 0x01000000 },
184 [VIRT_PCIE_MMIO
] = { 0x10000000, 0x2eff0000 },
185 [VIRT_PCIE_PIO
] = { 0x3eff0000, 0x00010000 },
186 [VIRT_PCIE_ECAM
] = { 0x3f000000, 0x01000000 },
187 [VIRT_MEM
] = { 0x40000000, RAMLIMIT_BYTES
},
188 /* Second PCIe window, 512GB wide at the 512GB boundary */
189 [VIRT_PCIE_MMIO_HIGH
] = { 0x8000000000ULL
, 0x8000000000ULL
},
192 static const int a15irqmap
[] = {
195 [VIRT_PCIE
] = 3, /* ... to 6 */
197 [VIRT_SECURE_UART
] = 8,
198 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
199 [VIRT_GIC_V2M
] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
200 [VIRT_PLATFORM_BUS
] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
203 static const char *valid_cpus
[] = {
211 static bool cpuname_valid(const char *cpu
)
215 for (i
= 0; i
< ARRAY_SIZE(valid_cpus
); i
++) {
216 if (strcmp(cpu
, valid_cpus
[i
]) == 0) {
223 static void create_fdt(VirtMachineState
*vms
)
225 void *fdt
= create_device_tree(&vms
->fdt_size
);
228 error_report("create_device_tree() failed");
235 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
236 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
237 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
240 * /chosen and /memory nodes must exist for load_dtb
241 * to fill in necessary properties later
243 qemu_fdt_add_subnode(fdt
, "/chosen");
244 qemu_fdt_add_subnode(fdt
, "/memory");
245 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
247 /* Clock node, for the benefit of the UART. The kernel device tree
248 * binding documentation claims the PL011 node clock properties are
249 * optional but in practice if you omit them the kernel refuses to
250 * probe for the device.
252 vms
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
253 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
254 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
255 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
256 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
257 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
259 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vms
->clock_phandle
);
263 static void fdt_add_psci_node(const VirtMachineState
*vms
)
265 uint32_t cpu_suspend_fn
;
269 void *fdt
= vms
->fdt
;
270 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
272 if (!vms
->using_psci
) {
276 qemu_fdt_add_subnode(fdt
, "/psci");
277 if (armcpu
->psci_version
== 2) {
278 const char comp
[] = "arm,psci-0.2\0arm,psci";
279 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
281 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
282 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
283 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
284 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
285 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
287 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
288 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
289 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
292 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
294 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
295 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
296 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
297 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
300 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
301 * to the instruction that should be used to invoke PSCI functions.
302 * However, the device tree binding uses 'method' instead, so that is
303 * what we should use here.
305 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
307 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
308 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
309 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
310 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
313 static void fdt_add_timer_nodes(const VirtMachineState
*vms
)
315 /* On real hardware these interrupts are level-triggered.
316 * On KVM they were edge-triggered before host kernel version 4.4,
317 * and level-triggered afterwards.
318 * On emulated QEMU they are level-triggered.
320 * Getting the DTB info about them wrong is awkward for some
322 * pre-4.8 ignore the DT and leave the interrupt configured
323 * with whatever the GIC reset value (or the bootloader) left it at
324 * 4.8 before rc6 honour the incorrect data by programming it back
325 * into the GIC, causing problems
326 * 4.8rc6 and later ignore the DT and always write "level triggered"
329 * For backwards-compatibility, virt-2.8 and earlier will continue
330 * to say these are edge-triggered, but later machines will report
331 * the correct information.
334 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
335 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
337 if (vmc
->claim_edge_triggered_timers
) {
338 irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
341 if (vms
->gic_version
== 2) {
342 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
343 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
344 (1 << vms
->smp_cpus
) - 1);
347 qemu_fdt_add_subnode(vms
->fdt
, "/timer");
349 armcpu
= ARM_CPU(qemu_get_cpu(0));
350 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
351 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
352 qemu_fdt_setprop(vms
->fdt
, "/timer", "compatible",
353 compat
, sizeof(compat
));
355 qemu_fdt_setprop_string(vms
->fdt
, "/timer", "compatible",
358 qemu_fdt_setprop(vms
->fdt
, "/timer", "always-on", NULL
, 0);
359 qemu_fdt_setprop_cells(vms
->fdt
, "/timer", "interrupts",
360 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_S_EL1_IRQ
, irqflags
,
361 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL1_IRQ
, irqflags
,
362 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_VIRT_IRQ
, irqflags
,
363 GIC_FDT_IRQ_TYPE_PPI
, ARCH_TIMER_NS_EL2_IRQ
, irqflags
);
366 static void fdt_add_cpu_nodes(const VirtMachineState
*vms
)
373 * From Documentation/devicetree/bindings/arm/cpus.txt
374 * On ARM v8 64-bit systems value should be set to 2,
375 * that corresponds to the MPIDR_EL1 register size.
376 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
377 * in the system, #address-cells can be set to 1, since
378 * MPIDR_EL1[63:32] bits are not used for CPUs
381 * Here we actually don't know whether our system is 32- or 64-bit one.
382 * The simplest way to go is to examine affinity IDs of all our CPUs. If
383 * at least one of them has Aff3 populated, we set #address-cells to 2.
385 for (cpu
= 0; cpu
< vms
->smp_cpus
; cpu
++) {
386 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
388 if (armcpu
->mp_affinity
& ARM_AFF3_MASK
) {
394 qemu_fdt_add_subnode(vms
->fdt
, "/cpus");
395 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#address-cells", addr_cells
);
396 qemu_fdt_setprop_cell(vms
->fdt
, "/cpus", "#size-cells", 0x0);
398 for (cpu
= vms
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
399 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
400 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
402 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
403 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "cpu");
404 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible",
405 armcpu
->dtb_compatible
);
407 if (vms
->using_psci
&& vms
->smp_cpus
> 1) {
408 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
409 "enable-method", "psci");
412 if (addr_cells
== 2) {
413 qemu_fdt_setprop_u64(vms
->fdt
, nodename
, "reg",
414 armcpu
->mp_affinity
);
416 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "reg",
417 armcpu
->mp_affinity
);
420 i
= numa_get_node_for_cpu(cpu
);
421 if (i
< nb_numa_nodes
) {
422 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "numa-node-id", i
);
429 static void fdt_add_its_gic_node(VirtMachineState
*vms
)
431 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
432 qemu_fdt_add_subnode(vms
->fdt
, "/intc/its");
433 qemu_fdt_setprop_string(vms
->fdt
, "/intc/its", "compatible",
435 qemu_fdt_setprop(vms
->fdt
, "/intc/its", "msi-controller", NULL
, 0);
436 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/its", "reg",
437 2, vms
->memmap
[VIRT_GIC_ITS
].base
,
438 2, vms
->memmap
[VIRT_GIC_ITS
].size
);
439 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/its", "phandle", vms
->msi_phandle
);
442 static void fdt_add_v2m_gic_node(VirtMachineState
*vms
)
444 vms
->msi_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
445 qemu_fdt_add_subnode(vms
->fdt
, "/intc/v2m");
446 qemu_fdt_setprop_string(vms
->fdt
, "/intc/v2m", "compatible",
447 "arm,gic-v2m-frame");
448 qemu_fdt_setprop(vms
->fdt
, "/intc/v2m", "msi-controller", NULL
, 0);
449 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc/v2m", "reg",
450 2, vms
->memmap
[VIRT_GIC_V2M
].base
,
451 2, vms
->memmap
[VIRT_GIC_V2M
].size
);
452 qemu_fdt_setprop_cell(vms
->fdt
, "/intc/v2m", "phandle", vms
->msi_phandle
);
455 static void fdt_add_gic_node(VirtMachineState
*vms
)
457 vms
->gic_phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
458 qemu_fdt_setprop_cell(vms
->fdt
, "/", "interrupt-parent", vms
->gic_phandle
);
460 qemu_fdt_add_subnode(vms
->fdt
, "/intc");
461 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#interrupt-cells", 3);
462 qemu_fdt_setprop(vms
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
463 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#address-cells", 0x2);
464 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "#size-cells", 0x2);
465 qemu_fdt_setprop(vms
->fdt
, "/intc", "ranges", NULL
, 0);
466 if (vms
->gic_version
== 3) {
467 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
469 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
470 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
471 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
472 2, vms
->memmap
[VIRT_GIC_REDIST
].base
,
473 2, vms
->memmap
[VIRT_GIC_REDIST
].size
);
475 /* 'cortex-a15-gic' means 'GIC v2' */
476 qemu_fdt_setprop_string(vms
->fdt
, "/intc", "compatible",
477 "arm,cortex-a15-gic");
478 qemu_fdt_setprop_sized_cells(vms
->fdt
, "/intc", "reg",
479 2, vms
->memmap
[VIRT_GIC_DIST
].base
,
480 2, vms
->memmap
[VIRT_GIC_DIST
].size
,
481 2, vms
->memmap
[VIRT_GIC_CPU
].base
,
482 2, vms
->memmap
[VIRT_GIC_CPU
].size
);
485 qemu_fdt_setprop_cell(vms
->fdt
, "/intc", "phandle", vms
->gic_phandle
);
488 static void fdt_add_pmu_nodes(const VirtMachineState
*vms
)
492 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
495 armcpu
= ARM_CPU(cpu
);
496 if (!arm_feature(&armcpu
->env
, ARM_FEATURE_PMU
) ||
497 !kvm_arm_pmu_create(cpu
, PPI(VIRTUAL_PMU_IRQ
))) {
502 if (vms
->gic_version
== 2) {
503 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
504 GIC_FDT_IRQ_PPI_CPU_WIDTH
,
505 (1 << vms
->smp_cpus
) - 1);
508 armcpu
= ARM_CPU(qemu_get_cpu(0));
509 qemu_fdt_add_subnode(vms
->fdt
, "/pmu");
510 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
511 const char compat
[] = "arm,armv8-pmuv3";
512 qemu_fdt_setprop(vms
->fdt
, "/pmu", "compatible",
513 compat
, sizeof(compat
));
514 qemu_fdt_setprop_cells(vms
->fdt
, "/pmu", "interrupts",
515 GIC_FDT_IRQ_TYPE_PPI
, VIRTUAL_PMU_IRQ
, irqflags
);
519 static void create_its(VirtMachineState
*vms
, DeviceState
*gicdev
)
521 const char *itsclass
= its_class_name();
525 /* Do nothing if not supported */
529 dev
= qdev_create(NULL
, itsclass
);
531 object_property_set_link(OBJECT(dev
), OBJECT(gicdev
), "parent-gicv3",
533 qdev_init_nofail(dev
);
534 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_ITS
].base
);
536 fdt_add_its_gic_node(vms
);
539 static void create_v2m(VirtMachineState
*vms
, qemu_irq
*pic
)
542 int irq
= vms
->irqmap
[VIRT_GIC_V2M
];
545 dev
= qdev_create(NULL
, "arm-gicv2m");
546 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, vms
->memmap
[VIRT_GIC_V2M
].base
);
547 qdev_prop_set_uint32(dev
, "base-spi", irq
);
548 qdev_prop_set_uint32(dev
, "num-spi", NUM_GICV2M_SPIS
);
549 qdev_init_nofail(dev
);
551 for (i
= 0; i
< NUM_GICV2M_SPIS
; i
++) {
552 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
555 fdt_add_v2m_gic_node(vms
);
558 static void create_gic(VirtMachineState
*vms
, qemu_irq
*pic
)
560 /* We create a standalone GIC */
561 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(vms
);
563 SysBusDevice
*gicbusdev
;
565 int type
= vms
->gic_version
, i
;
567 gictype
= (type
== 3) ? gicv3_class_name() : gic_class_name();
569 gicdev
= qdev_create(NULL
, gictype
);
570 qdev_prop_set_uint32(gicdev
, "revision", type
);
571 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
572 /* Note that the num-irq property counts both internal and external
573 * interrupts; there are always 32 of the former (mandated by GIC spec).
575 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
576 if (!kvm_irqchip_in_kernel()) {
577 qdev_prop_set_bit(gicdev
, "has-security-extensions", vms
->secure
);
579 qdev_init_nofail(gicdev
);
580 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
581 sysbus_mmio_map(gicbusdev
, 0, vms
->memmap
[VIRT_GIC_DIST
].base
);
583 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_REDIST
].base
);
585 sysbus_mmio_map(gicbusdev
, 1, vms
->memmap
[VIRT_GIC_CPU
].base
);
588 /* Wire the outputs from each CPU's generic timer to the
589 * appropriate GIC PPI inputs, and the GIC's IRQ output to
590 * the CPU's IRQ input.
592 for (i
= 0; i
< smp_cpus
; i
++) {
593 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
594 int ppibase
= NUM_IRQS
+ i
* GIC_INTERNAL
+ GIC_NR_SGIS
;
596 /* Mapping from the output timer irq lines from the CPU to the
597 * GIC PPI inputs we use for the virt board.
599 const int timer_irq
[] = {
600 [GTIMER_PHYS
] = ARCH_TIMER_NS_EL1_IRQ
,
601 [GTIMER_VIRT
] = ARCH_TIMER_VIRT_IRQ
,
602 [GTIMER_HYP
] = ARCH_TIMER_NS_EL2_IRQ
,
603 [GTIMER_SEC
] = ARCH_TIMER_S_EL1_IRQ
,
606 for (irq
= 0; irq
< ARRAY_SIZE(timer_irq
); irq
++) {
607 qdev_connect_gpio_out(cpudev
, irq
,
608 qdev_get_gpio_in(gicdev
,
609 ppibase
+ timer_irq
[irq
]));
612 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
613 sysbus_connect_irq(gicbusdev
, i
+ smp_cpus
,
614 qdev_get_gpio_in(cpudev
, ARM_CPU_FIQ
));
617 for (i
= 0; i
< NUM_IRQS
; i
++) {
618 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
621 fdt_add_gic_node(vms
);
623 if (type
== 3 && !vmc
->no_its
) {
624 create_its(vms
, gicdev
);
625 } else if (type
== 2) {
626 create_v2m(vms
, pic
);
630 static void create_uart(const VirtMachineState
*vms
, qemu_irq
*pic
, int uart
,
631 MemoryRegion
*mem
, CharDriverState
*chr
)
634 hwaddr base
= vms
->memmap
[uart
].base
;
635 hwaddr size
= vms
->memmap
[uart
].size
;
636 int irq
= vms
->irqmap
[uart
];
637 const char compat
[] = "arm,pl011\0arm,primecell";
638 const char clocknames
[] = "uartclk\0apb_pclk";
639 DeviceState
*dev
= qdev_create(NULL
, "pl011");
640 SysBusDevice
*s
= SYS_BUS_DEVICE(dev
);
642 qdev_prop_set_chr(dev
, "chardev", chr
);
643 qdev_init_nofail(dev
);
644 memory_region_add_subregion(mem
, base
,
645 sysbus_mmio_get_region(s
, 0));
646 sysbus_connect_irq(s
, 0, pic
[irq
]);
648 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
649 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
650 /* Note that we can't use setprop_string because of the embedded NUL */
651 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible",
652 compat
, sizeof(compat
));
653 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
655 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
656 GIC_FDT_IRQ_TYPE_SPI
, irq
,
657 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
658 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "clocks",
659 vms
->clock_phandle
, vms
->clock_phandle
);
660 qemu_fdt_setprop(vms
->fdt
, nodename
, "clock-names",
661 clocknames
, sizeof(clocknames
));
663 if (uart
== VIRT_UART
) {
664 qemu_fdt_setprop_string(vms
->fdt
, "/chosen", "stdout-path", nodename
);
666 /* Mark as not usable by the normal world */
667 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
668 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
674 static void create_rtc(const VirtMachineState
*vms
, qemu_irq
*pic
)
677 hwaddr base
= vms
->memmap
[VIRT_RTC
].base
;
678 hwaddr size
= vms
->memmap
[VIRT_RTC
].size
;
679 int irq
= vms
->irqmap
[VIRT_RTC
];
680 const char compat
[] = "arm,pl031\0arm,primecell";
682 sysbus_create_simple("pl031", base
, pic
[irq
]);
684 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
685 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
686 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
687 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
689 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
690 GIC_FDT_IRQ_TYPE_SPI
, irq
,
691 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
692 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
693 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
697 static DeviceState
*gpio_key_dev
;
698 static void virt_powerdown_req(Notifier
*n
, void *opaque
)
700 /* use gpio Pin 3 for power button event */
701 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev
, 0), 1);
704 static Notifier virt_system_powerdown_notifier
= {
705 .notify
= virt_powerdown_req
708 static void create_gpio(const VirtMachineState
*vms
, qemu_irq
*pic
)
711 DeviceState
*pl061_dev
;
712 hwaddr base
= vms
->memmap
[VIRT_GPIO
].base
;
713 hwaddr size
= vms
->memmap
[VIRT_GPIO
].size
;
714 int irq
= vms
->irqmap
[VIRT_GPIO
];
715 const char compat
[] = "arm,pl061\0arm,primecell";
717 pl061_dev
= sysbus_create_simple("pl061", base
, pic
[irq
]);
719 uint32_t phandle
= qemu_fdt_alloc_phandle(vms
->fdt
);
720 nodename
= g_strdup_printf("/pl061@%" PRIx64
, base
);
721 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
722 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
724 qemu_fdt_setprop(vms
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
725 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#gpio-cells", 2);
726 qemu_fdt_setprop(vms
->fdt
, nodename
, "gpio-controller", NULL
, 0);
727 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
728 GIC_FDT_IRQ_TYPE_SPI
, irq
,
729 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
730 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "clocks", vms
->clock_phandle
);
731 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "clock-names", "apb_pclk");
732 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "phandle", phandle
);
734 gpio_key_dev
= sysbus_create_simple("gpio-key", -1,
735 qdev_get_gpio_in(pl061_dev
, 3));
736 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys");
737 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys", "compatible", "gpio-keys");
738 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#size-cells", 0);
739 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys", "#address-cells", 1);
741 qemu_fdt_add_subnode(vms
->fdt
, "/gpio-keys/poweroff");
742 qemu_fdt_setprop_string(vms
->fdt
, "/gpio-keys/poweroff",
743 "label", "GPIO Key Poweroff");
744 qemu_fdt_setprop_cell(vms
->fdt
, "/gpio-keys/poweroff", "linux,code",
746 qemu_fdt_setprop_cells(vms
->fdt
, "/gpio-keys/poweroff",
747 "gpios", phandle
, 3, 0);
749 /* connect powerdown request */
750 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier
);
755 static void create_virtio_devices(const VirtMachineState
*vms
, qemu_irq
*pic
)
758 hwaddr size
= vms
->memmap
[VIRT_MMIO
].size
;
760 /* We create the transports in forwards order. Since qbus_realize()
761 * prepends (not appends) new child buses, the incrementing loop below will
762 * create a list of virtio-mmio buses with decreasing base addresses.
764 * When a -device option is processed from the command line,
765 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
766 * order. The upshot is that -device options in increasing command line
767 * order are mapped to virtio-mmio buses with decreasing base addresses.
769 * When this code was originally written, that arrangement ensured that the
770 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
771 * the first -device on the command line. (The end-to-end order is a
772 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
773 * guest kernel's name-to-address assignment strategy.)
775 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
776 * the message, if not necessarily the code, of commit 70161ff336.
777 * Therefore the loop now establishes the inverse of the original intent.
779 * Unfortunately, we can't counteract the kernel change by reversing the
780 * loop; it would break existing command lines.
782 * In any case, the kernel makes no guarantee about the stability of
783 * enumeration order of virtio devices (as demonstrated by it changing
784 * between kernel versions). For reliable and stable identification
785 * of disks users must use UUIDs or similar mechanisms.
787 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
788 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
789 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
791 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
794 /* We add dtb nodes in reverse order so that they appear in the finished
795 * device tree lowest address first.
797 * Note that this mapping is independent of the loop above. The previous
798 * loop influences virtio device to virtio transport assignment, whereas
799 * this loop controls how virtio transports are laid out in the dtb.
801 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
803 int irq
= vms
->irqmap
[VIRT_MMIO
] + i
;
804 hwaddr base
= vms
->memmap
[VIRT_MMIO
].base
+ i
* size
;
806 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
807 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
808 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
809 "compatible", "virtio,mmio");
810 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
812 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupts",
813 GIC_FDT_IRQ_TYPE_SPI
, irq
,
814 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
819 static void create_one_flash(const char *name
, hwaddr flashbase
,
820 hwaddr flashsize
, const char *file
,
821 MemoryRegion
*sysmem
)
823 /* Create and map a single flash device. We use the same
824 * parameters as the flash devices on the Versatile Express board.
826 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
827 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
828 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
829 const uint64_t sectorlength
= 256 * 1024;
832 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
836 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
837 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
838 qdev_prop_set_uint8(dev
, "width", 4);
839 qdev_prop_set_uint8(dev
, "device-width", 2);
840 qdev_prop_set_bit(dev
, "big-endian", false);
841 qdev_prop_set_uint16(dev
, "id0", 0x89);
842 qdev_prop_set_uint16(dev
, "id1", 0x18);
843 qdev_prop_set_uint16(dev
, "id2", 0x00);
844 qdev_prop_set_uint16(dev
, "id3", 0x00);
845 qdev_prop_set_string(dev
, "name", name
);
846 qdev_init_nofail(dev
);
848 memory_region_add_subregion(sysmem
, flashbase
,
849 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0));
855 if (drive_get(IF_PFLASH
, 0, 0)) {
856 error_report("The contents of the first flash device may be "
857 "specified with -bios or with -drive if=pflash... "
858 "but you cannot use both options at once");
861 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, file
);
863 error_report("Could not find ROM image '%s'", file
);
866 image_size
= load_image_mr(fn
, sysbus_mmio_get_region(sbd
, 0));
868 if (image_size
< 0) {
869 error_report("Could not load ROM image '%s'", file
);
875 static void create_flash(const VirtMachineState
*vms
,
876 MemoryRegion
*sysmem
,
877 MemoryRegion
*secure_sysmem
)
879 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
880 * Any file passed via -bios goes in the first of these.
881 * sysmem is the system memory space. secure_sysmem is the secure view
882 * of the system, and the first flash device should be made visible only
883 * there. The second flash device is visible to both secure and nonsecure.
884 * If sysmem == secure_sysmem this means there is no separate Secure
885 * address space and both flash devices are generally visible.
887 hwaddr flashsize
= vms
->memmap
[VIRT_FLASH
].size
/ 2;
888 hwaddr flashbase
= vms
->memmap
[VIRT_FLASH
].base
;
891 create_one_flash("virt.flash0", flashbase
, flashsize
,
892 bios_name
, secure_sysmem
);
893 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
,
896 if (sysmem
== secure_sysmem
) {
897 /* Report both flash devices as a single node in the DT */
898 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
899 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
900 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
901 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
902 2, flashbase
, 2, flashsize
,
903 2, flashbase
+ flashsize
, 2, flashsize
);
904 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
907 /* Report the devices as separate nodes so we can mark one as
908 * only visible to the secure world.
910 nodename
= g_strdup_printf("/secflash@%" PRIx64
, flashbase
);
911 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
912 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
913 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
914 2, flashbase
, 2, flashsize
);
915 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
916 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
917 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
920 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
921 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
922 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "compatible", "cfi-flash");
923 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
924 2, flashbase
+ flashsize
, 2, flashsize
);
925 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "bank-width", 4);
930 static void create_fw_cfg(const VirtMachineState
*vms
, AddressSpace
*as
)
932 hwaddr base
= vms
->memmap
[VIRT_FW_CFG
].base
;
933 hwaddr size
= vms
->memmap
[VIRT_FW_CFG
].size
;
937 fw_cfg
= fw_cfg_init_mem_wide(base
+ 8, base
, 8, base
+ 16, as
);
938 fw_cfg_add_i16(fw_cfg
, FW_CFG_NB_CPUS
, (uint16_t)smp_cpus
);
940 nodename
= g_strdup_printf("/fw-cfg@%" PRIx64
, base
);
941 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
942 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
943 "compatible", "qemu,fw-cfg-mmio");
944 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
949 static void create_pcie_irq_map(const VirtMachineState
*vms
,
950 uint32_t gic_phandle
,
951 int first_irq
, const char *nodename
)
954 uint32_t full_irq_map
[4 * 4 * 10] = { 0 };
955 uint32_t *irq_map
= full_irq_map
;
957 for (devfn
= 0; devfn
<= 0x18; devfn
+= 0x8) {
958 for (pin
= 0; pin
< 4; pin
++) {
959 int irq_type
= GIC_FDT_IRQ_TYPE_SPI
;
960 int irq_nr
= first_irq
+ ((pin
+ PCI_SLOT(devfn
)) % PCI_NUM_PINS
);
961 int irq_level
= GIC_FDT_IRQ_FLAGS_LEVEL_HI
;
965 devfn
<< 8, 0, 0, /* devfn */
966 pin
+ 1, /* PCI pin */
967 gic_phandle
, 0, 0, irq_type
, irq_nr
, irq_level
}; /* GIC irq */
969 /* Convert map to big endian */
970 for (i
= 0; i
< 10; i
++) {
971 irq_map
[i
] = cpu_to_be32(map
[i
]);
977 qemu_fdt_setprop(vms
->fdt
, nodename
, "interrupt-map",
978 full_irq_map
, sizeof(full_irq_map
));
980 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "interrupt-map-mask",
981 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
985 static void create_pcie(const VirtMachineState
*vms
, qemu_irq
*pic
)
987 hwaddr base_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].base
;
988 hwaddr size_mmio
= vms
->memmap
[VIRT_PCIE_MMIO
].size
;
989 hwaddr base_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].base
;
990 hwaddr size_mmio_high
= vms
->memmap
[VIRT_PCIE_MMIO_HIGH
].size
;
991 hwaddr base_pio
= vms
->memmap
[VIRT_PCIE_PIO
].base
;
992 hwaddr size_pio
= vms
->memmap
[VIRT_PCIE_PIO
].size
;
993 hwaddr base_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].base
;
994 hwaddr size_ecam
= vms
->memmap
[VIRT_PCIE_ECAM
].size
;
995 hwaddr base
= base_mmio
;
996 int nr_pcie_buses
= size_ecam
/ PCIE_MMCFG_SIZE_MIN
;
997 int irq
= vms
->irqmap
[VIRT_PCIE
];
998 MemoryRegion
*mmio_alias
;
999 MemoryRegion
*mmio_reg
;
1000 MemoryRegion
*ecam_alias
;
1001 MemoryRegion
*ecam_reg
;
1007 dev
= qdev_create(NULL
, TYPE_GPEX_HOST
);
1008 qdev_init_nofail(dev
);
1010 /* Map only the first size_ecam bytes of ECAM space */
1011 ecam_alias
= g_new0(MemoryRegion
, 1);
1012 ecam_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 0);
1013 memory_region_init_alias(ecam_alias
, OBJECT(dev
), "pcie-ecam",
1014 ecam_reg
, 0, size_ecam
);
1015 memory_region_add_subregion(get_system_memory(), base_ecam
, ecam_alias
);
1017 /* Map the MMIO window into system address space so as to expose
1018 * the section of PCI MMIO space which starts at the same base address
1019 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1022 mmio_alias
= g_new0(MemoryRegion
, 1);
1023 mmio_reg
= sysbus_mmio_get_region(SYS_BUS_DEVICE(dev
), 1);
1024 memory_region_init_alias(mmio_alias
, OBJECT(dev
), "pcie-mmio",
1025 mmio_reg
, base_mmio
, size_mmio
);
1026 memory_region_add_subregion(get_system_memory(), base_mmio
, mmio_alias
);
1029 /* Map high MMIO space */
1030 MemoryRegion
*high_mmio_alias
= g_new0(MemoryRegion
, 1);
1032 memory_region_init_alias(high_mmio_alias
, OBJECT(dev
), "pcie-mmio-high",
1033 mmio_reg
, base_mmio_high
, size_mmio_high
);
1034 memory_region_add_subregion(get_system_memory(), base_mmio_high
,
1038 /* Map IO port space */
1039 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 2, base_pio
);
1041 for (i
= 0; i
< GPEX_NUM_IRQS
; i
++) {
1042 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
, pic
[irq
+ i
]);
1045 pci
= PCI_HOST_BRIDGE(dev
);
1047 for (i
= 0; i
< nb_nics
; i
++) {
1048 NICInfo
*nd
= &nd_table
[i
];
1051 nd
->model
= g_strdup("virtio");
1054 pci_nic_init_nofail(nd
, pci
->bus
, nd
->model
, NULL
);
1058 nodename
= g_strdup_printf("/pcie@%" PRIx64
, base
);
1059 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1060 qemu_fdt_setprop_string(vms
->fdt
, nodename
,
1061 "compatible", "pci-host-ecam-generic");
1062 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "pci");
1063 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#address-cells", 3);
1064 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#size-cells", 2);
1065 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "bus-range", 0,
1067 qemu_fdt_setprop(vms
->fdt
, nodename
, "dma-coherent", NULL
, 0);
1069 if (vms
->msi_phandle
) {
1070 qemu_fdt_setprop_cells(vms
->fdt
, nodename
, "msi-parent",
1074 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg",
1075 2, base_ecam
, 2, size_ecam
);
1078 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1079 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1080 2, base_pio
, 2, size_pio
,
1081 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1082 2, base_mmio
, 2, size_mmio
,
1083 1, FDT_PCI_RANGE_MMIO_64BIT
,
1085 2, base_mmio_high
, 2, size_mmio_high
);
1087 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "ranges",
1088 1, FDT_PCI_RANGE_IOPORT
, 2, 0,
1089 2, base_pio
, 2, size_pio
,
1090 1, FDT_PCI_RANGE_MMIO
, 2, base_mmio
,
1091 2, base_mmio
, 2, size_mmio
);
1094 qemu_fdt_setprop_cell(vms
->fdt
, nodename
, "#interrupt-cells", 1);
1095 create_pcie_irq_map(vms
, vms
->gic_phandle
, irq
, nodename
);
1100 static void create_platform_bus(VirtMachineState
*vms
, qemu_irq
*pic
)
1105 ARMPlatformBusFDTParams
*fdt_params
= g_new(ARMPlatformBusFDTParams
, 1);
1106 MemoryRegion
*sysmem
= get_system_memory();
1108 platform_bus_params
.platform_bus_base
= vms
->memmap
[VIRT_PLATFORM_BUS
].base
;
1109 platform_bus_params
.platform_bus_size
= vms
->memmap
[VIRT_PLATFORM_BUS
].size
;
1110 platform_bus_params
.platform_bus_first_irq
= vms
->irqmap
[VIRT_PLATFORM_BUS
];
1111 platform_bus_params
.platform_bus_num_irqs
= PLATFORM_BUS_NUM_IRQS
;
1113 fdt_params
->system_params
= &platform_bus_params
;
1114 fdt_params
->binfo
= &vms
->bootinfo
;
1115 fdt_params
->intc
= "/intc";
1117 * register a machine init done notifier that creates the device tree
1118 * nodes of the platform bus and its children dynamic sysbus devices
1120 arm_register_platform_bus_fdt_creator(fdt_params
);
1122 dev
= qdev_create(NULL
, TYPE_PLATFORM_BUS_DEVICE
);
1123 dev
->id
= TYPE_PLATFORM_BUS_DEVICE
;
1124 qdev_prop_set_uint32(dev
, "num_irqs",
1125 platform_bus_params
.platform_bus_num_irqs
);
1126 qdev_prop_set_uint32(dev
, "mmio_size",
1127 platform_bus_params
.platform_bus_size
);
1128 qdev_init_nofail(dev
);
1129 s
= SYS_BUS_DEVICE(dev
);
1131 for (i
= 0; i
< platform_bus_params
.platform_bus_num_irqs
; i
++) {
1132 int irqn
= platform_bus_params
.platform_bus_first_irq
+ i
;
1133 sysbus_connect_irq(s
, i
, pic
[irqn
]);
1136 memory_region_add_subregion(sysmem
,
1137 platform_bus_params
.platform_bus_base
,
1138 sysbus_mmio_get_region(s
, 0));
1141 static void create_secure_ram(VirtMachineState
*vms
,
1142 MemoryRegion
*secure_sysmem
)
1144 MemoryRegion
*secram
= g_new(MemoryRegion
, 1);
1146 hwaddr base
= vms
->memmap
[VIRT_SECURE_MEM
].base
;
1147 hwaddr size
= vms
->memmap
[VIRT_SECURE_MEM
].size
;
1149 memory_region_init_ram(secram
, NULL
, "virt.secure-ram", size
, &error_fatal
);
1150 vmstate_register_ram_global(secram
);
1151 memory_region_add_subregion(secure_sysmem
, base
, secram
);
1153 nodename
= g_strdup_printf("/secram@%" PRIx64
, base
);
1154 qemu_fdt_add_subnode(vms
->fdt
, nodename
);
1155 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "device_type", "memory");
1156 qemu_fdt_setprop_sized_cells(vms
->fdt
, nodename
, "reg", 2, base
, 2, size
);
1157 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "status", "disabled");
1158 qemu_fdt_setprop_string(vms
->fdt
, nodename
, "secure-status", "okay");
1163 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
1165 const VirtMachineState
*board
= container_of(binfo
, VirtMachineState
,
1168 *fdt_size
= board
->fdt_size
;
1172 static void virt_build_smbios(VirtGuestInfo
*guest_info
)
1174 FWCfgState
*fw_cfg
= guest_info
->fw_cfg
;
1175 uint8_t *smbios_tables
, *smbios_anchor
;
1176 size_t smbios_tables_len
, smbios_anchor_len
;
1177 const char *product
= "QEMU Virtual Machine";
1183 if (kvm_enabled()) {
1184 product
= "KVM Virtual Machine";
1187 smbios_set_defaults("QEMU", product
,
1188 "1.0", false, true, SMBIOS_ENTRY_POINT_30
);
1190 smbios_get_tables(NULL
, 0, &smbios_tables
, &smbios_tables_len
,
1191 &smbios_anchor
, &smbios_anchor_len
);
1193 if (smbios_anchor
) {
1194 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-tables",
1195 smbios_tables
, smbios_tables_len
);
1196 fw_cfg_add_file(fw_cfg
, "etc/smbios/smbios-anchor",
1197 smbios_anchor
, smbios_anchor_len
);
1202 void virt_machine_done(Notifier
*notifier
, void *data
)
1204 VirtMachineState
*vms
= container_of(notifier
, VirtMachineState
,
1207 virt_acpi_setup(&vms
->acpi_guest_info
);
1208 virt_build_smbios(&vms
->acpi_guest_info
);
1211 static void machvirt_init(MachineState
*machine
)
1213 VirtMachineState
*vms
= VIRT_MACHINE(machine
);
1214 VirtMachineClass
*vmc
= VIRT_MACHINE_GET_CLASS(machine
);
1215 qemu_irq pic
[NUM_IRQS
];
1216 MemoryRegion
*sysmem
= get_system_memory();
1217 MemoryRegion
*secure_sysmem
= NULL
;
1218 int n
, virt_max_cpus
;
1219 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1220 const char *cpu_model
= machine
->cpu_model
;
1221 VirtGuestInfo
*guest_info
= &vms
->acpi_guest_info
;
1224 const char *typename
;
1227 bool firmware_loaded
= bios_name
|| drive_get(IF_PFLASH
, 0, 0);
1231 cpu_model
= "cortex-a15";
1234 /* We can probe only here because during property set
1235 * KVM is not available yet
1237 if (!vms
->gic_version
) {
1238 if (!kvm_enabled()) {
1239 error_report("gic-version=host requires KVM");
1243 vms
->gic_version
= kvm_arm_vgic_probe();
1244 if (!vms
->gic_version
) {
1245 error_report("Unable to determine GIC version supported by host");
1250 /* Separate the actual CPU model name from any appended features */
1251 cpustr
= g_strsplit(cpu_model
, ",", 2);
1253 if (!cpuname_valid(cpustr
[0])) {
1254 error_report("mach-virt: CPU %s not supported", cpustr
[0]);
1258 /* If we have an EL3 boot ROM then the assumption is that it will
1259 * implement PSCI itself, so disable QEMU's internal implementation
1260 * so it doesn't get in the way. Instead of starting secondary
1261 * CPUs in PSCI powerdown state we will start them all running and
1262 * let the boot ROM sort them out.
1263 * The usual case is that we do use QEMU's PSCI implementation.
1265 vms
->using_psci
= !(vms
->secure
&& firmware_loaded
);
1267 /* The maximum number of CPUs depends on the GIC version, or on how
1268 * many redistributors we can fit into the memory map.
1270 if (vms
->gic_version
== 3) {
1271 virt_max_cpus
= vms
->memmap
[VIRT_GIC_REDIST
].size
/ 0x20000;
1272 clustersz
= GICV3_TARGETLIST_BITS
;
1274 virt_max_cpus
= GIC_NCPU
;
1275 clustersz
= GIC_TARGETLIST_BITS
;
1278 if (max_cpus
> virt_max_cpus
) {
1279 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1280 "supported by machine 'mach-virt' (%d)",
1281 max_cpus
, virt_max_cpus
);
1285 vms
->smp_cpus
= smp_cpus
;
1287 if (machine
->ram_size
> vms
->memmap
[VIRT_MEM
].size
) {
1288 error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB
);
1293 if (kvm_enabled()) {
1294 error_report("mach-virt: KVM does not support Security extensions");
1298 /* The Secure view of the world is the same as the NonSecure,
1299 * but with a few extra devices. Create it as a container region
1300 * containing the system memory at low priority; any secure-only
1301 * devices go in at higher priority and take precedence.
1303 secure_sysmem
= g_new(MemoryRegion
, 1);
1304 memory_region_init(secure_sysmem
, OBJECT(machine
), "secure-memory",
1306 memory_region_add_subregion_overlap(secure_sysmem
, 0, sysmem
, -1);
1311 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpustr
[0]);
1313 error_report("Unable to find CPU definition");
1316 typename
= object_class_get_name(oc
);
1318 /* convert -smp CPU options specified by the user into global props */
1320 cc
->parse_features(typename
, cpustr
[1], &err
);
1323 error_report_err(err
);
1327 for (n
= 0; n
< smp_cpus
; n
++) {
1328 Object
*cpuobj
= object_new(typename
);
1329 if (!vmc
->disallow_affinity_adjustment
) {
1330 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1331 * GIC's target-list limitations. 32-bit KVM hosts currently
1332 * always create clusters of 4 CPUs, but that is expected to
1333 * change when they gain support for gicv3. When KVM is enabled
1334 * it will override the changes we make here, therefore our
1335 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1336 * and to improve SGI efficiency.
1338 uint8_t aff1
= n
/ clustersz
;
1339 uint8_t aff0
= n
% clustersz
;
1340 object_property_set_int(cpuobj
, (aff1
<< ARM_AFF1_SHIFT
) | aff0
,
1341 "mp-affinity", NULL
);
1345 object_property_set_bool(cpuobj
, false, "has_el3", NULL
);
1348 if (vms
->using_psci
) {
1349 object_property_set_int(cpuobj
, QEMU_PSCI_CONDUIT_HVC
,
1350 "psci-conduit", NULL
);
1352 /* Secondary CPUs start in PSCI powered-down state */
1354 object_property_set_bool(cpuobj
, true,
1355 "start-powered-off", NULL
);
1359 if (vmc
->no_pmu
&& object_property_find(cpuobj
, "pmu", NULL
)) {
1360 object_property_set_bool(cpuobj
, false, "pmu", NULL
);
1363 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
1364 object_property_set_int(cpuobj
, vms
->memmap
[VIRT_CPUPERIPHS
].base
,
1365 "reset-cbar", &error_abort
);
1368 object_property_set_link(cpuobj
, OBJECT(sysmem
), "memory",
1371 object_property_set_link(cpuobj
, OBJECT(secure_sysmem
),
1372 "secure-memory", &error_abort
);
1375 object_property_set_bool(cpuobj
, true, "realized", NULL
);
1377 fdt_add_timer_nodes(vms
);
1378 fdt_add_cpu_nodes(vms
);
1379 fdt_add_psci_node(vms
);
1381 memory_region_allocate_system_memory(ram
, NULL
, "mach-virt.ram",
1383 memory_region_add_subregion(sysmem
, vms
->memmap
[VIRT_MEM
].base
, ram
);
1385 create_flash(vms
, sysmem
, secure_sysmem
? secure_sysmem
: sysmem
);
1387 create_gic(vms
, pic
);
1389 fdt_add_pmu_nodes(vms
);
1391 create_uart(vms
, pic
, VIRT_UART
, sysmem
, serial_hds
[0]);
1394 create_secure_ram(vms
, secure_sysmem
);
1395 create_uart(vms
, pic
, VIRT_SECURE_UART
, secure_sysmem
, serial_hds
[1]);
1398 create_rtc(vms
, pic
);
1400 create_pcie(vms
, pic
);
1402 create_gpio(vms
, pic
);
1404 /* Create mmio transports, so the user can create virtio backends
1405 * (which will be automatically plugged in to the transports). If
1406 * no backend is created the transport will just sit harmlessly idle.
1408 create_virtio_devices(vms
, pic
);
1410 create_fw_cfg(vms
, &address_space_memory
);
1411 rom_set_fw(fw_cfg_find());
1413 guest_info
->smp_cpus
= smp_cpus
;
1414 guest_info
->fw_cfg
= fw_cfg_find();
1415 guest_info
->memmap
= vms
->memmap
;
1416 guest_info
->irqmap
= vms
->irqmap
;
1417 guest_info
->use_highmem
= vms
->highmem
;
1418 guest_info
->gic_version
= vms
->gic_version
;
1419 guest_info
->no_its
= vmc
->no_its
;
1420 vms
->machine_done
.notify
= virt_machine_done
;
1421 qemu_add_machine_init_done_notifier(&vms
->machine_done
);
1423 vms
->bootinfo
.ram_size
= machine
->ram_size
;
1424 vms
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
1425 vms
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
1426 vms
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
1427 vms
->bootinfo
.nb_cpus
= smp_cpus
;
1428 vms
->bootinfo
.board_id
= -1;
1429 vms
->bootinfo
.loader_start
= vms
->memmap
[VIRT_MEM
].base
;
1430 vms
->bootinfo
.get_dtb
= machvirt_dtb
;
1431 vms
->bootinfo
.firmware_loaded
= firmware_loaded
;
1432 arm_load_kernel(ARM_CPU(first_cpu
), &vms
->bootinfo
);
1435 * arm_load_kernel machine init done notifier registration must
1436 * happen before the platform_bus_create call. In this latter,
1437 * another notifier is registered which adds platform bus nodes.
1438 * Notifiers are executed in registration reverse order.
1440 create_platform_bus(vms
, pic
);
1443 static bool virt_get_secure(Object
*obj
, Error
**errp
)
1445 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1450 static void virt_set_secure(Object
*obj
, bool value
, Error
**errp
)
1452 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1454 vms
->secure
= value
;
1457 static bool virt_get_highmem(Object
*obj
, Error
**errp
)
1459 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1461 return vms
->highmem
;
1464 static void virt_set_highmem(Object
*obj
, bool value
, Error
**errp
)
1466 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1468 vms
->highmem
= value
;
1471 static char *virt_get_gic_version(Object
*obj
, Error
**errp
)
1473 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1474 const char *val
= vms
->gic_version
== 3 ? "3" : "2";
1476 return g_strdup(val
);
1479 static void virt_set_gic_version(Object
*obj
, const char *value
, Error
**errp
)
1481 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1483 if (!strcmp(value
, "3")) {
1484 vms
->gic_version
= 3;
1485 } else if (!strcmp(value
, "2")) {
1486 vms
->gic_version
= 2;
1487 } else if (!strcmp(value
, "host")) {
1488 vms
->gic_version
= 0; /* Will probe later */
1490 error_setg(errp
, "Invalid gic-version value");
1491 error_append_hint(errp
, "Valid values are 3, 2, host.\n");
1495 static void virt_machine_class_init(ObjectClass
*oc
, void *data
)
1497 MachineClass
*mc
= MACHINE_CLASS(oc
);
1499 mc
->init
= machvirt_init
;
1500 /* Start max_cpus at the maximum QEMU supports. We'll further restrict
1501 * it later in machvirt_init, where we have more information about the
1502 * configuration of the particular instance.
1505 mc
->has_dynamic_sysbus
= true;
1506 mc
->block_default_type
= IF_VIRTIO
;
1508 mc
->pci_allow_0_address
= true;
1509 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1510 mc
->minimum_page_bits
= 12;
1513 static const TypeInfo virt_machine_info
= {
1514 .name
= TYPE_VIRT_MACHINE
,
1515 .parent
= TYPE_MACHINE
,
1517 .instance_size
= sizeof(VirtMachineState
),
1518 .class_size
= sizeof(VirtMachineClass
),
1519 .class_init
= virt_machine_class_init
,
1522 static void machvirt_machine_init(void)
1524 type_register_static(&virt_machine_info
);
1526 type_init(machvirt_machine_init
);
1528 static void virt_2_9_instance_init(Object
*obj
)
1530 VirtMachineState
*vms
= VIRT_MACHINE(obj
);
1532 /* EL3 is disabled by default on virt: this makes us consistent
1533 * between KVM and TCG for this board, and it also allows us to
1534 * boot UEFI blobs which assume no TrustZone support.
1536 vms
->secure
= false;
1537 object_property_add_bool(obj
, "secure", virt_get_secure
,
1538 virt_set_secure
, NULL
);
1539 object_property_set_description(obj
, "secure",
1540 "Set on/off to enable/disable the ARM "
1541 "Security Extensions (TrustZone)",
1544 /* High memory is enabled by default */
1545 vms
->highmem
= true;
1546 object_property_add_bool(obj
, "highmem", virt_get_highmem
,
1547 virt_set_highmem
, NULL
);
1548 object_property_set_description(obj
, "highmem",
1549 "Set on/off to enable/disable using "
1550 "physical address space above 32 bits",
1552 /* Default GIC type is v2 */
1553 vms
->gic_version
= 2;
1554 object_property_add_str(obj
, "gic-version", virt_get_gic_version
,
1555 virt_set_gic_version
, NULL
);
1556 object_property_set_description(obj
, "gic-version",
1558 "Valid values are 2, 3 and host", NULL
);
1560 vms
->memmap
= a15memmap
;
1561 vms
->irqmap
= a15irqmap
;
1564 static void virt_machine_2_9_options(MachineClass
*mc
)
1567 DEFINE_VIRT_MACHINE_AS_LATEST(2, 9)
1569 #define VIRT_COMPAT_2_8 \
1572 static void virt_2_8_instance_init(Object
*obj
)
1574 virt_2_9_instance_init(obj
);
1577 static void virt_machine_2_8_options(MachineClass
*mc
)
1579 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1581 virt_machine_2_9_options(mc
);
1582 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_8
);
1583 /* For 2.8 and earlier we falsely claimed in the DT that
1584 * our timers were edge-triggered, not level-triggered.
1586 vmc
->claim_edge_triggered_timers
= true;
1588 DEFINE_VIRT_MACHINE(2, 8)
1590 #define VIRT_COMPAT_2_7 \
1593 static void virt_2_7_instance_init(Object
*obj
)
1595 virt_2_8_instance_init(obj
);
1598 static void virt_machine_2_7_options(MachineClass
*mc
)
1600 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1602 virt_machine_2_8_options(mc
);
1603 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_7
);
1604 /* ITS was introduced with 2.8 */
1606 /* Stick with 1K pages for migration compatibility */
1607 mc
->minimum_page_bits
= 0;
1609 DEFINE_VIRT_MACHINE(2, 7)
1611 #define VIRT_COMPAT_2_6 \
1614 static void virt_2_6_instance_init(Object
*obj
)
1616 virt_2_7_instance_init(obj
);
1619 static void virt_machine_2_6_options(MachineClass
*mc
)
1621 VirtMachineClass
*vmc
= VIRT_MACHINE_CLASS(OBJECT_CLASS(mc
));
1623 virt_machine_2_7_options(mc
);
1624 SET_MACHINE_COMPAT(mc
, VIRT_COMPAT_2_6
);
1625 vmc
->disallow_affinity_adjustment
= true;
1626 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
1629 DEFINE_VIRT_MACHINE(2, 6)