hw/display/vga-pci.c

   1 /*
   2  * QEMU PCI VGA Emulator.
   3  *
   4  * see docs/specs/standard-vga.txt for virtual hardware specs.
   5  *
   6  * Copyright (c) 2003 Fabrice Bellard
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "ui/console.h"
  29 #include "hw/pci/pci.h"
  30 #include "vga_int.h"
  31 #include "ui/pixel_ops.h"
  32 #include "qemu/timer.h"
  33 #include "hw/loader.h"
  34
  35 #define PCI_VGA_IOPORT_OFFSET 0x400
  36 #define PCI_VGA_IOPORT_SIZE   (0x3e0 - 0x3c0)
  37 #define PCI_VGA_BOCHS_OFFSET  0x500
  38 #define PCI_VGA_BOCHS_SIZE    (0x0b * 2)
  39 #define PCI_VGA_QEXT_OFFSET   0x600
  40 #define PCI_VGA_QEXT_SIZE     (2 * 4)
  41 #define PCI_VGA_MMIO_SIZE     0x1000
  42
  43 #define PCI_VGA_QEXT_REG_SIZE         (0 * 4)
  44 #define PCI_VGA_QEXT_REG_BYTEORDER    (1 * 4)
  45 #define  PCI_VGA_QEXT_LITTLE_ENDIAN   0x1e1e1e1e
  46 #define  PCI_VGA_QEXT_BIG_ENDIAN      0xbebebebe
  47
  48 enum vga_pci_flags {
  49     PCI_VGA_FLAG_ENABLE_MMIO = 1,
  50     PCI_VGA_FLAG_ENABLE_QEXT = 2,
  51 };
  52
  53 typedef struct PCIVGAState {
  54     PCIDevice dev;
  55     VGACommonState vga;
  56     uint32_t flags;
  57     MemoryRegion mmio;
  58     MemoryRegion mrs[3];
  59 } PCIVGAState;
  60
  61 #define TYPE_PCI_VGA "pci-vga"
  62 #define PCI_VGA(obj) OBJECT_CHECK(PCIVGAState, (obj), TYPE_PCI_VGA)
  63
  64 static const VMStateDescription vmstate_vga_pci = {
  65     .name = "vga",
  66     .version_id = 2,
  67     .minimum_version_id = 2,
  68     .fields = (VMStateField[]) {
  69         VMSTATE_PCI_DEVICE(dev, PCIVGAState),
  70         VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
  71         VMSTATE_END_OF_LIST()
  72     }
  73 };
  74
  75 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
  76                                     unsigned size)
  77 {
  78     VGACommonState *s = ptr;
  79     uint64_t ret = 0;
  80
  81     switch (size) {
  82     case 1:
  83         ret = vga_ioport_read(s, addr + 0x3c0);
  84         break;
  85     case 2:
  86         ret  = vga_ioport_read(s, addr + 0x3c0);
  87         ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
  88         break;
  89     }
  90     return ret;
  91 }
  92
  93 static void pci_vga_ioport_write(void *ptr, hwaddr addr,
  94                                  uint64_t val, unsigned size)
  95 {
  96     VGACommonState *s = ptr;
  97
  98     switch (size) {
  99     case 1:
 100         vga_ioport_write(s, addr + 0x3c0, val);
 101         break;
 102     case 2:
 103         /*
 104          * Update bytes in little endian order.  Allows to update
 105          * indexed registers with a single word write because the
 106          * index byte is updated first.
 107          */
 108         vga_ioport_write(s, addr + 0x3c0, val & 0xff);
 109         vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
 110         break;
 111     }
 112 }
 113
 114 static const MemoryRegionOps pci_vga_ioport_ops = {
 115     .read = pci_vga_ioport_read,
 116     .write = pci_vga_ioport_write,
 117     .valid.min_access_size = 1,
 118     .valid.max_access_size = 4,
 119     .impl.min_access_size = 1,
 120     .impl.max_access_size = 2,
 121     .endianness = DEVICE_LITTLE_ENDIAN,
 122 };
 123
 124 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
 125                                    unsigned size)
 126 {
 127     VGACommonState *s = ptr;
 128     int index = addr >> 1;
 129
 130     vbe_ioport_write_index(s, 0, index);
 131     return vbe_ioport_read_data(s, 0);
 132 }
 133
 134 static void pci_vga_bochs_write(void *ptr, hwaddr addr,
 135                                 uint64_t val, unsigned size)
 136 {
 137     VGACommonState *s = ptr;
 138     int index = addr >> 1;
 139
 140     vbe_ioport_write_index(s, 0, index);
 141     vbe_ioport_write_data(s, 0, val);
 142 }
 143
 144 static const MemoryRegionOps pci_vga_bochs_ops = {
 145     .read = pci_vga_bochs_read,
 146     .write = pci_vga_bochs_write,
 147     .valid.min_access_size = 1,
 148     .valid.max_access_size = 4,
 149     .impl.min_access_size = 2,
 150     .impl.max_access_size = 2,
 151     .endianness = DEVICE_LITTLE_ENDIAN,
 152 };
 153
 154 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
 155 {
 156     VGACommonState *s = ptr;
 157
 158     switch (addr) {
 159     case PCI_VGA_QEXT_REG_SIZE:
 160         return PCI_VGA_QEXT_SIZE;
 161     case PCI_VGA_QEXT_REG_BYTEORDER:
 162         return s->big_endian_fb ?
 163             PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
 164     default:
 165         return 0;
 166     }
 167 }
 168
 169 static void pci_vga_qext_write(void *ptr, hwaddr addr,
 170                                uint64_t val, unsigned size)
 171 {
 172     VGACommonState *s = ptr;
 173
 174     switch (addr) {
 175     case PCI_VGA_QEXT_REG_BYTEORDER:
 176         if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
 177             s->big_endian_fb = true;
 178         }
 179         if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
 180             s->big_endian_fb = false;
 181         }
 182         break;
 183     }
 184 }
 185
 186 static bool vga_get_big_endian_fb(Object *obj, Error **errp)
 187 {
 188     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 189
 190     return d->vga.big_endian_fb;
 191 }
 192
 193 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
 194 {
 195     PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
 196
 197     d->vga.big_endian_fb = value;
 198 }
 199
 200 static const MemoryRegionOps pci_vga_qext_ops = {
 201     .read = pci_vga_qext_read,
 202     .write = pci_vga_qext_write,
 203     .valid.min_access_size = 4,
 204     .valid.max_access_size = 4,
 205     .endianness = DEVICE_LITTLE_ENDIAN,
 206 };
 207
 208 void pci_std_vga_mmio_region_init(VGACommonState *s,
 209                                   MemoryRegion *parent,
 210                                   MemoryRegion *subs,
 211                                   bool qext)
 212 {
 213     memory_region_init_io(&subs[0], NULL, &pci_vga_ioport_ops, s,
 214                           "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
 215     memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
 216                                 &subs[0]);
 217
 218     memory_region_init_io(&subs[1], NULL, &pci_vga_bochs_ops, s,
 219                           "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
 220     memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
 221                                 &subs[1]);
 222
 223     if (qext) {
 224         memory_region_init_io(&subs[2], NULL, &pci_vga_qext_ops, s,
 225                               "qemu extended regs", PCI_VGA_QEXT_SIZE);
 226         memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
 227                                     &subs[2]);
 228     }
 229 }
 230
 231 static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
 232 {
 233     PCIVGAState *d = PCI_VGA(dev);
 234     VGACommonState *s = &d->vga;
 235     bool qext = false;
 236
 237     /* vga + console init */
 238     vga_common_init(s, OBJECT(dev), true);
 239     vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
 240              true);
 241
 242     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 243
 244     /* XXX: VGA_RAM_SIZE must be a power of two */
 245     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 246
 247     /* mmio bar for vga register access */
 248     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
 249         memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
 250
 251         if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 252             qext = true;
 253             pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 254         }
 255         pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);
 256
 257         pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 258     }
 259
 260     if (!dev->rom_bar) {
 261         /* compatibility with pc-0.13 and older */
 262         vga_init_vbe(s, OBJECT(dev), pci_address_space(dev));
 263     }
 264 }
 265
 266 static void pci_std_vga_init(Object *obj)
 267 {
 268     /* Expose framebuffer byteorder via QOM */
 269     object_property_add_bool(obj, "big-endian-framebuffer",
 270                              vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
 271 }
 272
 273 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
 274 {
 275     PCIVGAState *d = PCI_VGA(dev);
 276     VGACommonState *s = &d->vga;
 277     bool qext = false;
 278
 279     /* vga + console init */
 280     vga_common_init(s, OBJECT(dev), false);
 281     s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
 282
 283     /* mmio bar */
 284     memory_region_init(&d->mmio, OBJECT(dev), "vga.mmio", 4096);
 285
 286     if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
 287         qext = true;
 288         pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
 289     }
 290     pci_std_vga_mmio_region_init(s, &d->mmio, d->mrs, qext);
 291
 292     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
 293     pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
 294 }
 295
 296 static void pci_secondary_vga_init(Object *obj)
 297 {
 298     /* Expose framebuffer byteorder via QOM */
 299     object_property_add_bool(obj, "big-endian-framebuffer",
 300                              vga_get_big_endian_fb, vga_set_big_endian_fb, NULL);
 301 }
 302
 303 static void pci_secondary_vga_reset(DeviceState *dev)
 304 {
 305     PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
 306     vga_common_reset(&d->vga);
 307 }
 308
 309 static Property vga_pci_properties[] = {
 310     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 311     DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
 312     DEFINE_PROP_BIT("qemu-extended-regs",
 313                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 314     DEFINE_PROP_END_OF_LIST(),
 315 };
 316
 317 static Property secondary_pci_properties[] = {
 318     DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
 319     DEFINE_PROP_BIT("qemu-extended-regs",
 320                     PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
 321     DEFINE_PROP_END_OF_LIST(),
 322 };
 323
 324 static void vga_pci_class_init(ObjectClass *klass, void *data)
 325 {
 326     DeviceClass *dc = DEVICE_CLASS(klass);
 327     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 328
 329     k->vendor_id = PCI_VENDOR_ID_QEMU;
 330     k->device_id = PCI_DEVICE_ID_QEMU_VGA;
 331     dc->vmsd = &vmstate_vga_pci;
 332     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 333 }
 334
 335 static const TypeInfo vga_pci_type_info = {
 336     .name = TYPE_PCI_VGA,
 337     .parent = TYPE_PCI_DEVICE,
 338     .instance_size = sizeof(PCIVGAState),
 339     .abstract = true,
 340     .class_init = vga_pci_class_init,
 341     .interfaces = (InterfaceInfo[]) {
 342         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 343         { },
 344     },
 345 };
 346
 347 static void vga_class_init(ObjectClass *klass, void *data)
 348 {
 349     DeviceClass *dc = DEVICE_CLASS(klass);
 350     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 351
 352     k->realize = pci_std_vga_realize;
 353     k->romfile = "vgabios-stdvga.bin";
 354     k->class_id = PCI_CLASS_DISPLAY_VGA;
 355     dc->props = vga_pci_properties;
 356     dc->hotpluggable = false;
 357 }
 358
 359 static void secondary_class_init(ObjectClass *klass, void *data)
 360 {
 361     DeviceClass *dc = DEVICE_CLASS(klass);
 362     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 363
 364     k->realize = pci_secondary_vga_realize;
 365     k->class_id = PCI_CLASS_DISPLAY_OTHER;
 366     dc->props = secondary_pci_properties;
 367     dc->reset = pci_secondary_vga_reset;
 368 }
 369
 370 static const TypeInfo vga_info = {
 371     .name          = "VGA",
 372     .parent        = TYPE_PCI_VGA,
 373     .instance_init = pci_std_vga_init,
 374     .class_init    = vga_class_init,
 375 };
 376
 377 static const TypeInfo secondary_info = {
 378     .name          = "secondary-vga",
 379     .parent        = TYPE_PCI_VGA,
 380     .instance_init = pci_secondary_vga_init,
 381     .class_init    = secondary_class_init,
 382 };
 383
 384 static void vga_register_types(void)
 385 {
 386     type_register_static(&vga_pci_type_info);
 387     type_register_static(&vga_info);
 388     type_register_static(&secondary_info);
 389 }
 390
 391 type_init(vga_register_types)