devices/pci_device.c

   1 #include "qemu/pci_device.h"
   2 #include "qemu/pci_bus.h"
   3 #include "hw/pci_regs.h"
   4
   5 void pci_device_initialize(PciDevice *obj, const char *id)
   6 {
   7     type_initialize(obj, TYPE_PCI_DEVICE, id);
   8 }
   9
  10 void pci_device_finalize(PciDevice *obj)
  11 {
  12     type_finalize(obj);
  13 }
  14
  15 void pci_device_visit(PciDevice *device, Visitor *v, const char *name, Error **errp)
  16 {
  17     device_visit(DEVICE(device), v, name, errp);
  18 }
  19
  20 static void pci_device_initfn(TypeInstance *inst)
  21 {
  22     PciDevice *obj = PCI_DEVICE(inst);
  23
  24     plug_add_property_socket(PLUG(obj), "bus", (Plug **)&obj->bus, TYPE_PCI_BUS);
  25 }
  26
  27 uint32_t pci_device_config_read_std(PciDevice *device, uint8_t offset, int size)
  28 {
  29     if (size == 1) {
  30         return device->config[offset];
  31     } else if (size == 2) {
  32         return (device->config[offset] << 0) | (device->config[offset + 1] << 8);
  33     } else if (size == 4) {
  34         return (device->config[offset] << 0) | (device->config[offset + 1] << 8) |
  35             (device->config[offset + 2] << 16) | (device->config[offset + 3] << 24);
  36     } else {
  37         return ~0;
  38     }
  39 }
  40
  41 void pci_device_config_write_std(PciDevice *device, uint8_t offset, int size, uint32_t value)
  42 {
  43     if (size == 1) {
  44         device->config[offset] = value & 0xFF;
  45     } else if (size == 2) {
  46         device->config[offset] = value & 0xFF;
  47         device->config[offset + 1] = (value >> 8) & 0xFF;
  48     } else if (size == 4) {
  49         device->config[offset] = value & 0xFF;
  50         device->config[offset + 1] = (value >> 8) & 0xFF;
  51         device->config[offset + 2] = (value >> 16) & 0xFF;
  52         device->config[offset + 3] = (value >> 24) & 0xFF;
  53     }
  54 }
  55
  56 static void pci_device_class_initfn(TypeClass *class)
  57 {
  58     PciDeviceClass *pci_class = PCI_DEVICE_CLASS(class);
  59
  60     pci_class->config_read = pci_device_config_read_std;
  61     pci_class->config_write = pci_device_config_write_std;
  62 }
  63
  64 uint32_t pci_device_config_read(PciDevice *device, uint8_t offset, int size)
  65 {
  66     return PCI_DEVICE_GET_CLASS(device)->config_read(device, offset, size);
  67 }
  68
  69 void pci_device_config_write(PciDevice *device, uint8_t offset, int size, uint32_t value)
  70 {
  71     PCI_DEVICE_GET_CLASS(device)->config_write(device, offset, size, value);
  72 }
  73
  74 uint64_t pci_device_read(PciDevice *device, uint64_t offset, int size, bool ioio)
  75 {
  76     return PCI_DEVICE_GET_CLASS(device)->read(device, offset, size, ioio);
  77 }
  78
  79 void pci_device_write(PciDevice *device, uint64_t offset, int size, uint64_t value, bool ioio)
  80 {
  81     PCI_DEVICE_GET_CLASS(device)->write(device, offset, size, value, ioio);
  82 }
  83
  84 uint64_t pci_device_region_read(PciDevice *device, int region, uint64_t offset, int size)
  85 {
  86     return PCI_DEVICE_GET_CLASS(device)->region_read(device, region, offset, size);
  87 }
  88
  89 void pci_device_region_write(PciDevice *device, int region, uint64_t offset, int size, uint64_t value)
  90 {
  91     PCI_DEVICE_GET_CLASS(device)->region_write(device, region, offset, size, value);
  92 }
  93
  94 bool pci_device_is_target(PciDevice *device, uint64_t addr, int size, bool ioio)
  95 {
  96     /* FIXME */
  97     return false;
  98 }
  99
 100 void pci_device_set_vendor_id(PciDevice *device, uint16_t value)
 101 {
 102     pci_device_config_write(device, PCI_VENDOR_ID, 2, value);
 103 }
 104
 105 uint16_t pci_device_get_vendor_id(PciDevice *device)
 106 {
 107     return pci_device_config_read(device, PCI_VENDOR_ID, 2);
 108 }
 109
 110 void pci_device_set_device_id(PciDevice *device, uint16_t value)
 111 {
 112     pci_device_config_write(device, PCI_DEVICE_ID, 2, value);
 113 }
 114
 115 uint16_t pci_device_get_device_id(PciDevice *device)
 116 {
 117     return pci_device_config_read(device, PCI_DEVICE_ID, 2);
 118 }
 119
 120 void pci_device_set_command(PciDevice *device, uint16_t value)
 121 {
 122     pci_device_config_write(device, PCI_COMMAND, 2, value);
 123 }
 124
 125 uint16_t pci_device_get_command(PciDevice *device)
 126 {
 127     return pci_device_config_read(device, PCI_COMMAND, 2);
 128 }
 129
 130 void pci_device_set_status(PciDevice *device, uint16_t value)
 131 {
 132     pci_device_config_write(device, PCI_STATUS, 2, value);
 133 }
 134
 135 uint16_t pci_device_get_status(PciDevice *device)
 136 {
 137     return pci_device_config_read(device, PCI_STATUS, 2);
 138 }
 139
 140 void pci_device_set_class_revision(PciDevice *device, uint8_t value)
 141 {
 142     pci_device_config_write(device, PCI_CLASS_REVISION, 1, value);
 143 }
 144
 145 uint8_t pci_device_get_class_revision(PciDevice *device)
 146 {
 147     return pci_device_config_read(device, PCI_CLASS_REVISION, 1);
 148 }
 149
 150 void pci_device_set_class_prog(PciDevice *device, uint8_t value)
 151 {
 152     pci_device_config_write(device, PCI_CLASS_PROG, 1, value);
 153 }
 154
 155 uint8_t pci_device_get_class_prog(PciDevice *device)
 156 {
 157     return pci_device_config_read(device, PCI_CLASS_PROG, 1);
 158 }
 159
 160 void pci_device_set_class_device(PciDevice *device, uint16_t value)
 161 {
 162     pci_device_config_write(device, PCI_CLASS_DEVICE, 2, value);
 163 }
 164
 165 uint16_t pci_device_get_class_device(PciDevice *device)
 166 {
 167     return pci_device_config_read(device, PCI_CLASS_DEVICE, 2);
 168 }
 169
 170 void pci_device_set_cache_line_size(PciDevice *device, uint8_t value)
 171 {
 172     pci_device_config_write(device, PCI_CACHE_LINE_SIZE, 1, value);
 173 }
 174
 175 uint8_t pci_device_get_cache_line_size(PciDevice *device)
 176 {
 177     return pci_device_config_read(device, PCI_CACHE_LINE_SIZE, 1);
 178 }
 179
 180 void pci_device_set_latency_timer(PciDevice *device, uint8_t value)
 181 {
 182     pci_device_config_write(device, PCI_LATENCY_TIMER, 1, value);
 183 }
 184
 185 uint8_t pci_device_get_latency_timer(PciDevice *device)
 186 {
 187     return pci_device_config_read(device, PCI_LATENCY_TIMER, 1);
 188 }
 189
 190 void pci_device_set_header_type(PciDevice *device, uint8_t value)
 191 {
 192     pci_device_config_write(device, PCI_HEADER_TYPE, 1, value);
 193 }
 194
 195 uint8_t pci_device_get_header_type(PciDevice *device)
 196 {
 197     return pci_device_config_read(device, PCI_HEADER_TYPE, 1);
 198 }
 199
 200 void pci_device_set_bist(PciDevice *device, uint8_t value)
 201 {
 202     pci_device_config_write(device, PCI_BIST, 1, value);
 203 }
 204
 205 uint8_t pci_device_get_bist(PciDevice *device)
 206 {
 207     return pci_device_config_read(device, PCI_BIST, 1);
 208 }
 209
 210 static TypeInfo pci_device_info = {
 211     .name = TYPE_PCI_DEVICE,
 212     .parent = TYPE_DEVICE,
 213     .instance_size = sizeof(PciDevice),
 214     .class_size = sizeof(PciDeviceClass),
 215     .instance_init = pci_device_initfn,
 216     .class_init = pci_device_class_initfn,
 217 };
 218
 219 static void register_devices(void)
 220 {
 221     type_register_static(&pci_device_info);
 222 }
 223
 224 device_init(register_devices);