hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "sysemu.h"
  29
  30 //#define DEBUG_PCI
  31 #ifdef DEBUG_PCI
  32 # define PCI_DPRINTF(format, ...)       printf(format, ## __VA_ARGS__)
  33 #else
  34 # define PCI_DPRINTF(format, ...)       do { } while (0)
  35 #endif
  36
  37 struct PCIBus {
  38     BusState qbus;
  39     int devfn_min;
  40     pci_set_irq_fn set_irq;
  41     pci_map_irq_fn map_irq;
  42     pci_hotplug_fn hotplug;
  43     uint32_t config_reg; /* XXX: suppress */
  44     void *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47
  48     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
  49     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
  50
  51     /* The bus IRQ state is the logical OR of the connected devices.
  52        Keep a count of the number of devices with raised IRQs.  */
  53     int nirq;
  54     int *irq_count;
  55 };
  56
  57 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
  58
  59 static struct BusInfo pci_bus_info = {
  60     .name       = "PCI",
  61     .size       = sizeof(PCIBus),
  62     .print_dev  = pcibus_dev_print,
  63     .props      = (Property[]) {
  64         DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
  65         DEFINE_PROP_END_OF_LIST()
  66     }
  67 };
  68
  69 static void pci_update_mappings(PCIDevice *d);
  70 static void pci_set_irq(void *opaque, int irq_num, int level);
  71
  72 target_phys_addr_t pci_mem_base;
  73 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  74 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  75
  76 struct PCIHostBus {
  77     int domain;
  78     struct PCIBus *bus;
  79     QLIST_ENTRY(PCIHostBus) next;
  80 };
  81 static QLIST_HEAD(, PCIHostBus) host_buses;
  82
  83 static const VMStateDescription vmstate_pcibus = {
  84     .name = "PCIBUS",
  85     .version_id = 1,
  86     .minimum_version_id = 1,
  87     .minimum_version_id_old = 1,
  88     .fields      = (VMStateField []) {
  89         VMSTATE_INT32_EQUAL(nirq, PCIBus),
  90         VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
  91         VMSTATE_END_OF_LIST()
  92     }
  93 };
  94
  95 static int pci_bar(PCIDevice *d, int reg)
  96 {
  97     uint8_t type;
  98
  99     if (reg != PCI_ROM_SLOT)
 100         return PCI_BASE_ADDRESS_0 + reg * 4;
 101
 102     type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 103     return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
 104 }
 105
 106 static inline int pci_irq_state(PCIDevice *d, int irq_num)
 107 {
 108         return (d->irq_state >> irq_num) & 0x1;
 109 }
 110
 111 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
 112 {
 113         d->irq_state &= ~(0x1 << irq_num);
 114         d->irq_state |= level << irq_num;
 115 }
 116
 117 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
 118 {
 119     PCIBus *bus;
 120     for (;;) {
 121         bus = pci_dev->bus;
 122         irq_num = bus->map_irq(pci_dev, irq_num);
 123         if (bus->set_irq)
 124             break;
 125         pci_dev = bus->parent_dev;
 126     }
 127     bus->irq_count[irq_num] += change;
 128     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 129 }
 130
 131 /* Update interrupt status bit in config space on interrupt
 132  * state change. */
 133 static void pci_update_irq_status(PCIDevice *dev)
 134 {
 135     if (dev->irq_state) {
 136         dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
 137     } else {
 138         dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 139     }
 140 }
 141
 142 static void pci_device_reset(PCIDevice *dev)
 143 {
 144     int r;
 145
 146     dev->irq_state = 0;
 147     pci_update_irq_status(dev);
 148     dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 149                                   PCI_COMMAND_MASTER);
 150     dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
 151     dev->config[PCI_INTERRUPT_LINE] = 0x0;
 152     for (r = 0; r < PCI_NUM_REGIONS; ++r) {
 153         if (!dev->io_regions[r].size) {
 154             continue;
 155         }
 156         pci_set_long(dev->config + pci_bar(dev, r), dev->io_regions[r].type);
 157     }
 158     pci_update_mappings(dev);
 159 }
 160
 161 static void pci_bus_reset(void *opaque)
 162 {
 163     PCIBus *bus = opaque;
 164     int i;
 165
 166     for (i = 0; i < bus->nirq; i++) {
 167         bus->irq_count[i] = 0;
 168     }
 169     for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
 170         if (bus->devices[i]) {
 171             pci_device_reset(bus->devices[i]);
 172         }
 173     }
 174 }
 175
 176 static void pci_host_bus_register(int domain, PCIBus *bus)
 177 {
 178     struct PCIHostBus *host;
 179     host = qemu_mallocz(sizeof(*host));
 180     host->domain = domain;
 181     host->bus = bus;
 182     QLIST_INSERT_HEAD(&host_buses, host, next);
 183 }
 184
 185 PCIBus *pci_find_root_bus(int domain)
 186 {
 187     struct PCIHostBus *host;
 188
 189     QLIST_FOREACH(host, &host_buses, next) {
 190         if (host->domain == domain) {
 191             return host->bus;
 192         }
 193     }
 194
 195     return NULL;
 196 }
 197
 198 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 199                          const char *name, int devfn_min)
 200 {
 201     qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
 202     bus->devfn_min = devfn_min;
 203
 204     /* host bridge */
 205     QLIST_INIT(&bus->child);
 206     pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
 207
 208     vmstate_register(-1, &vmstate_pcibus, bus);
 209     qemu_register_reset(pci_bus_reset, bus);
 210 }
 211
 212 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
 213 {
 214     PCIBus *bus;
 215
 216     bus = qemu_mallocz(sizeof(*bus));
 217     bus->qbus.qdev_allocated = 1;
 218     pci_bus_new_inplace(bus, parent, name, devfn_min);
 219     return bus;
 220 }
 221
 222 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 223                   void *irq_opaque, int nirq)
 224 {
 225     bus->set_irq = set_irq;
 226     bus->map_irq = map_irq;
 227     bus->irq_opaque = irq_opaque;
 228     bus->nirq = nirq;
 229     bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
 230 }
 231
 232 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug)
 233 {
 234     bus->qbus.allow_hotplug = 1;
 235     bus->hotplug = hotplug;
 236 }
 237
 238 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 239                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 240                          void *irq_opaque, int devfn_min, int nirq)
 241 {
 242     PCIBus *bus;
 243
 244     bus = pci_bus_new(parent, name, devfn_min);
 245     pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
 246     return bus;
 247 }
 248
 249 static void pci_register_secondary_bus(PCIBus *parent,
 250                                        PCIBus *bus,
 251                                        PCIDevice *dev,
 252                                        pci_map_irq_fn map_irq,
 253                                        const char *name)
 254 {
 255     qbus_create_inplace(&bus->qbus, &pci_bus_info, &dev->qdev, name);
 256     bus->map_irq = map_irq;
 257     bus->parent_dev = dev;
 258
 259     QLIST_INIT(&bus->child);
 260     QLIST_INSERT_HEAD(&parent->child, bus, sibling);
 261 }
 262
 263 static void pci_unregister_secondary_bus(PCIBus *bus)
 264 {
 265     assert(QLIST_EMPTY(&bus->child));
 266     QLIST_REMOVE(bus, sibling);
 267 }
 268
 269 int pci_bus_num(PCIBus *s)
 270 {
 271     if (!s->parent_dev)
 272         return 0;       /* pci host bridge */
 273     return s->parent_dev->config[PCI_SECONDARY_BUS];
 274 }
 275
 276 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
 277 {
 278     PCIDevice *s = container_of(pv, PCIDevice, config);
 279     uint8_t *config;
 280     int i;
 281
 282     assert(size == pci_config_size(s));
 283     config = qemu_malloc(size);
 284
 285     qemu_get_buffer(f, config, size);
 286     for (i = 0; i < size; ++i) {
 287         if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
 288             qemu_free(config);
 289             return -EINVAL;
 290         }
 291     }
 292     memcpy(s->config, config, size);
 293
 294     pci_update_mappings(s);
 295
 296     qemu_free(config);
 297     return 0;
 298 }
 299
 300 /* just put buffer */
 301 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
 302 {
 303     const uint8_t **v = pv;
 304     assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
 305     qemu_put_buffer(f, *v, size);
 306 }
 307
 308 static VMStateInfo vmstate_info_pci_config = {
 309     .name = "pci config",
 310     .get  = get_pci_config_device,
 311     .put  = put_pci_config_device,
 312 };
 313
 314 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 315 {
 316     PCIDevice *s = container_of(pv, PCIDevice, config);
 317     uint32_t irq_state[PCI_NUM_PINS];
 318     int i;
 319     for (i = 0; i < PCI_NUM_PINS; ++i) {
 320         irq_state[i] = qemu_get_be32(f);
 321         if (irq_state[i] != 0x1 && irq_state[i] != 0) {
 322             fprintf(stderr, "irq state %d: must be 0 or 1.\n",
 323                     irq_state[i]);
 324             return -EINVAL;
 325         }
 326     }
 327
 328     for (i = 0; i < PCI_NUM_PINS; ++i) {
 329         pci_set_irq_state(s, i, irq_state[i]);
 330     }
 331
 332     return 0;
 333 }
 334
 335 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
 336 {
 337     int i;
 338     PCIDevice *s = container_of(pv, PCIDevice, config);
 339
 340     for (i = 0; i < PCI_NUM_PINS; ++i) {
 341         qemu_put_be32(f, pci_irq_state(s, i));
 342     }
 343 }
 344
 345 static VMStateInfo vmstate_info_pci_irq_state = {
 346     .name = "pci irq state",
 347     .get  = get_pci_irq_state,
 348     .put  = put_pci_irq_state,
 349 };
 350
 351 const VMStateDescription vmstate_pci_device = {
 352     .name = "PCIDevice",
 353     .version_id = 2,
 354     .minimum_version_id = 1,
 355     .minimum_version_id_old = 1,
 356     .fields      = (VMStateField []) {
 357         VMSTATE_INT32_LE(version_id, PCIDevice),
 358         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 359                                    vmstate_info_pci_config,
 360                                    PCI_CONFIG_SPACE_SIZE),
 361         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 362                                    vmstate_info_pci_irq_state,
 363                                    PCI_NUM_PINS * sizeof(int32_t)),
 364         VMSTATE_END_OF_LIST()
 365     }
 366 };
 367
 368 const VMStateDescription vmstate_pcie_device = {
 369     .name = "PCIDevice",
 370     .version_id = 2,
 371     .minimum_version_id = 1,
 372     .minimum_version_id_old = 1,
 373     .fields      = (VMStateField []) {
 374         VMSTATE_INT32_LE(version_id, PCIDevice),
 375         VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
 376                                    vmstate_info_pci_config,
 377                                    PCIE_CONFIG_SPACE_SIZE),
 378         VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
 379                                    vmstate_info_pci_irq_state,
 380                                    PCI_NUM_PINS * sizeof(int32_t)),
 381         VMSTATE_END_OF_LIST()
 382     }
 383 };
 384
 385 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
 386 {
 387     return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
 388 }
 389
 390 void pci_device_save(PCIDevice *s, QEMUFile *f)
 391 {
 392     /* Clear interrupt status bit: it is implicit
 393      * in irq_state which we are saving.
 394      * This makes us compatible with old devices
 395      * which never set or clear this bit. */
 396     s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
 397     vmstate_save_state(f, pci_get_vmstate(s), s);
 398     /* Restore the interrupt status bit. */
 399     pci_update_irq_status(s);
 400 }
 401
 402 int pci_device_load(PCIDevice *s, QEMUFile *f)
 403 {
 404     int ret;
 405     ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
 406     /* Restore the interrupt status bit. */
 407     pci_update_irq_status(s);
 408     return ret;
 409 }
 410
 411 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 412 {
 413     uint16_t *id;
 414
 415     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 416     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 417     id[1] = cpu_to_le16(pci_default_sub_device_id);
 418     return 0;
 419 }
 420
 421 /*
 422  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 423  */
 424 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 425 {
 426     const char *p;
 427     char *e;
 428     unsigned long val;
 429     unsigned long dom = 0, bus = 0;
 430     unsigned slot = 0;
 431
 432     p = addr;
 433     val = strtoul(p, &e, 16);
 434     if (e == p)
 435         return -1;
 436     if (*e == ':') {
 437         bus = val;
 438         p = e + 1;
 439         val = strtoul(p, &e, 16);
 440         if (e == p)
 441             return -1;
 442         if (*e == ':') {
 443             dom = bus;
 444             bus = val;
 445             p = e + 1;
 446             val = strtoul(p, &e, 16);
 447             if (e == p)
 448                 return -1;
 449         }
 450     }
 451
 452     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 453         return -1;
 454
 455     slot = val;
 456
 457     if (*e)
 458         return -1;
 459
 460     /* Note: QEMU doesn't implement domains other than 0 */
 461     if (!pci_find_bus(pci_find_root_bus(dom), bus))
 462         return -1;
 463
 464     *domp = dom;
 465     *busp = bus;
 466     *slotp = slot;
 467     return 0;
 468 }
 469
 470 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 471                      unsigned *slotp)
 472 {
 473     /* strip legacy tag */
 474     if (!strncmp(addr, "pci_addr=", 9)) {
 475         addr += 9;
 476     }
 477     if (pci_parse_devaddr(addr, domp, busp, slotp)) {
 478         monitor_printf(mon, "Invalid pci address\n");
 479         return -1;
 480     }
 481     return 0;
 482 }
 483
 484 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
 485 {
 486     int dom, bus;
 487     unsigned slot;
 488
 489     if (!devaddr) {
 490         *devfnp = -1;
 491         return pci_find_bus(pci_find_root_bus(0), 0);
 492     }
 493
 494     if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
 495         return NULL;
 496     }
 497
 498     *devfnp = slot << 3;
 499     return pci_find_bus(pci_find_root_bus(0), bus);
 500 }
 501
 502 static void pci_init_cmask(PCIDevice *dev)
 503 {
 504     pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
 505     pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
 506     dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
 507     dev->cmask[PCI_REVISION_ID] = 0xff;
 508     dev->cmask[PCI_CLASS_PROG] = 0xff;
 509     pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
 510     dev->cmask[PCI_HEADER_TYPE] = 0xff;
 511     dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
 512 }
 513
 514 static void pci_init_wmask(PCIDevice *dev)
 515 {
 516     int config_size = pci_config_size(dev);
 517
 518     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
 519     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
 520     pci_set_word(dev->wmask + PCI_COMMAND,
 521                  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 522
 523     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
 524            config_size - PCI_CONFIG_HEADER_SIZE);
 525 }
 526
 527 static void pci_init_wmask_bridge(PCIDevice *d)
 528 {
 529     /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
 530        PCI_SEC_LETENCY_TIMER */
 531     memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
 532
 533     /* base and limit */
 534     d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
 535     d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
 536     pci_set_word(d->wmask + PCI_MEMORY_BASE,
 537                  PCI_MEMORY_RANGE_MASK & 0xffff);
 538     pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
 539                  PCI_MEMORY_RANGE_MASK & 0xffff);
 540     pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
 541                  PCI_PREF_RANGE_MASK & 0xffff);
 542     pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
 543                  PCI_PREF_RANGE_MASK & 0xffff);
 544
 545     /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
 546     memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
 547
 548     pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
 549 }
 550
 551 static void pci_config_alloc(PCIDevice *pci_dev)
 552 {
 553     int config_size = pci_config_size(pci_dev);
 554
 555     pci_dev->config = qemu_mallocz(config_size);
 556     pci_dev->cmask = qemu_mallocz(config_size);
 557     pci_dev->wmask = qemu_mallocz(config_size);
 558     pci_dev->used = qemu_mallocz(config_size);
 559 }
 560
 561 static void pci_config_free(PCIDevice *pci_dev)
 562 {
 563     qemu_free(pci_dev->config);
 564     qemu_free(pci_dev->cmask);
 565     qemu_free(pci_dev->wmask);
 566     qemu_free(pci_dev->used);
 567 }
 568
 569 /* -1 for devfn means auto assign */
 570 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
 571                                          const char *name, int devfn,
 572                                          PCIConfigReadFunc *config_read,
 573                                          PCIConfigWriteFunc *config_write,
 574                                          uint8_t header_type)
 575 {
 576     if (devfn < 0) {
 577         for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
 578             devfn += 8) {
 579             if (!bus->devices[devfn])
 580                 goto found;
 581         }
 582         qemu_error("PCI: no devfn available for %s, all in use\n", name);
 583         return NULL;
 584     found: ;
 585     } else if (bus->devices[devfn]) {
 586         qemu_error("PCI: devfn %d not available for %s, in use by %s\n", devfn,
 587                  name, bus->devices[devfn]->name);
 588         return NULL;
 589     }
 590     pci_dev->bus = bus;
 591     pci_dev->devfn = devfn;
 592     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 593     pci_dev->irq_state = 0;
 594     pci_config_alloc(pci_dev);
 595
 596     header_type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
 597     if (header_type == PCI_HEADER_TYPE_NORMAL) {
 598         pci_set_default_subsystem_id(pci_dev);
 599     }
 600     pci_init_cmask(pci_dev);
 601     pci_init_wmask(pci_dev);
 602     if (header_type == PCI_HEADER_TYPE_BRIDGE) {
 603         pci_init_wmask_bridge(pci_dev);
 604     }
 605
 606     if (!config_read)
 607         config_read = pci_default_read_config;
 608     if (!config_write)
 609         config_write = pci_default_write_config;
 610     pci_dev->config_read = config_read;
 611     pci_dev->config_write = config_write;
 612     bus->devices[devfn] = pci_dev;
 613     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
 614     pci_dev->version_id = 2; /* Current pci device vmstate version */
 615     return pci_dev;
 616 }
 617
 618 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 619                                int instance_size, int devfn,
 620                                PCIConfigReadFunc *config_read,
 621                                PCIConfigWriteFunc *config_write)
 622 {
 623     PCIDevice *pci_dev;
 624
 625     pci_dev = qemu_mallocz(instance_size);
 626     pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
 627                                      config_read, config_write,
 628                                      PCI_HEADER_TYPE_NORMAL);
 629     if (pci_dev == NULL) {
 630         hw_error("PCI: can't register device\n");
 631     }
 632     return pci_dev;
 633 }
 634 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 635 {
 636     return addr + pci_mem_base;
 637 }
 638
 639 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 640 {
 641     PCIIORegion *r;
 642     int i;
 643
 644     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 645         r = &pci_dev->io_regions[i];
 646         if (!r->size || r->addr == PCI_BAR_UNMAPPED)
 647             continue;
 648         if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
 649             isa_unassign_ioport(r->addr, r->filtered_size);
 650         } else {
 651             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 652                                                      r->filtered_size,
 653                                                      IO_MEM_UNASSIGNED);
 654         }
 655     }
 656 }
 657
 658 static int pci_unregister_device(DeviceState *dev)
 659 {
 660     PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
 661     PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
 662     int ret = 0;
 663
 664     if (info->exit)
 665         ret = info->exit(pci_dev);
 666     if (ret)
 667         return ret;
 668
 669     pci_unregister_io_regions(pci_dev);
 670
 671     qemu_free_irqs(pci_dev->irq);
 672     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 673     pci_config_free(pci_dev);
 674     return 0;
 675 }
 676
 677 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 678                             pcibus_t size, int type,
 679                             PCIMapIORegionFunc *map_func)
 680 {
 681     PCIIORegion *r;
 682     uint32_t addr;
 683     pcibus_t wmask;
 684
 685     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 686         return;
 687
 688     if (size & (size-1)) {
 689         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 690                     "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
 691         exit(1);
 692     }
 693
 694     r = &pci_dev->io_regions[region_num];
 695     r->addr = PCI_BAR_UNMAPPED;
 696     r->size = size;
 697     r->filtered_size = size;
 698     r->type = type;
 699     r->map_func = map_func;
 700
 701     wmask = ~(size - 1);
 702     addr = pci_bar(pci_dev, region_num);
 703     if (region_num == PCI_ROM_SLOT) {
 704         /* ROM enable bit is writeable */
 705         wmask |= PCI_ROM_ADDRESS_ENABLE;
 706     }
 707     pci_set_long(pci_dev->config + addr, type);
 708     if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
 709         r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 710         pci_set_quad(pci_dev->wmask + addr, wmask);
 711         pci_set_quad(pci_dev->cmask + addr, ~0ULL);
 712     } else {
 713         pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
 714         pci_set_long(pci_dev->cmask + addr, 0xffffffff);
 715     }
 716 }
 717
 718 static uint32_t pci_config_get_io_base(PCIDevice *d,
 719                                        uint32_t base, uint32_t base_upper16)
 720 {
 721     uint32_t val;
 722
 723     val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
 724     if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
 725         val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
 726     }
 727     return val;
 728 }
 729
 730 static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
 731 {
 732     return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
 733         << 16;
 734 }
 735
 736 static pcibus_t pci_config_get_pref_base(PCIDevice *d,
 737                                          uint32_t base, uint32_t upper)
 738 {
 739     pcibus_t tmp;
 740     pcibus_t val;
 741
 742     tmp = (pcibus_t)pci_get_word(d->config + base);
 743     val = (tmp & PCI_PREF_RANGE_MASK) << 16;
 744     if (tmp & PCI_PREF_RANGE_TYPE_64) {
 745         val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
 746     }
 747     return val;
 748 }
 749
 750 static pcibus_t pci_bridge_get_base(PCIDevice *bridge, uint8_t type)
 751 {
 752     pcibus_t base;
 753     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 754         base = pci_config_get_io_base(bridge,
 755                                       PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 756     } else {
 757         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 758             base = pci_config_get_pref_base(
 759                 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 760         } else {
 761             base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 762         }
 763     }
 764
 765     return base;
 766 }
 767
 768 static pcibus_t pci_bridge_get_limit(PCIDevice *bridge, uint8_t type)
 769 {
 770     pcibus_t limit;
 771     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 772         limit = pci_config_get_io_base(bridge,
 773                                       PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 774         limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 775     } else {
 776         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 777             limit = pci_config_get_pref_base(
 778                 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 779         } else {
 780             limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 781         }
 782         limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 783     }
 784     return limit;
 785 }
 786
 787 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
 788                               uint8_t type)
 789 {
 790     pcibus_t base = *addr;
 791     pcibus_t limit = *addr + *size - 1;
 792     PCIDevice *br;
 793
 794     for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
 795         uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 796
 797         if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 798             if (!(cmd & PCI_COMMAND_IO)) {
 799                 goto no_map;
 800             }
 801         } else {
 802             if (!(cmd & PCI_COMMAND_MEMORY)) {
 803                 goto no_map;
 804             }
 805         }
 806
 807         base = MAX(base, pci_bridge_get_base(br, type));
 808         limit = MIN(limit, pci_bridge_get_limit(br, type));
 809     }
 810
 811     if (base > limit) {
 812         goto no_map;
 813     }
 814     *addr = base;
 815     *size = limit - base + 1;
 816     return;
 817 no_map:
 818     *addr = PCI_BAR_UNMAPPED;
 819     *size = 0;
 820 }
 821
 822 static pcibus_t pci_bar_address(PCIDevice *d,
 823                                 int reg, uint8_t type, pcibus_t size)
 824 {
 825     pcibus_t new_addr, last_addr;
 826     int bar = pci_bar(d, reg);
 827     uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
 828
 829     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 830         if (!(cmd & PCI_COMMAND_IO)) {
 831             return PCI_BAR_UNMAPPED;
 832         }
 833         new_addr = pci_get_long(d->config + bar) & ~(size - 1);
 834         last_addr = new_addr + size - 1;
 835         /* NOTE: we have only 64K ioports on PC */
 836         if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
 837             return PCI_BAR_UNMAPPED;
 838         }
 839         return new_addr;
 840     }
 841
 842     if (!(cmd & PCI_COMMAND_MEMORY)) {
 843         return PCI_BAR_UNMAPPED;
 844     }
 845     if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 846         new_addr = pci_get_quad(d->config + bar);
 847     } else {
 848         new_addr = pci_get_long(d->config + bar);
 849     }
 850     /* the ROM slot has a specific enable bit */
 851     if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
 852         return PCI_BAR_UNMAPPED;
 853     }
 854     new_addr &= ~(size - 1);
 855     last_addr = new_addr + size - 1;
 856     /* NOTE: we do not support wrapping */
 857     /* XXX: as we cannot support really dynamic
 858        mappings, we handle specific values as invalid
 859        mappings. */
 860     if (last_addr <= new_addr || new_addr == 0 ||
 861         last_addr == PCI_BAR_UNMAPPED) {
 862         return PCI_BAR_UNMAPPED;
 863     }
 864
 865     /* Now pcibus_t is 64bit.
 866      * Check if 32 bit BAR wraps around explicitly.
 867      * Without this, PC ide doesn't work well.
 868      * TODO: remove this work around.
 869      */
 870     if  (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
 871         return PCI_BAR_UNMAPPED;
 872     }
 873
 874     /*
 875      * OS is allowed to set BAR beyond its addressable
 876      * bits. For example, 32 bit OS can set 64bit bar
 877      * to >4G. Check it. TODO: we might need to support
 878      * it in the future for e.g. PAE.
 879      */
 880     if (last_addr >= TARGET_PHYS_ADDR_MAX) {
 881         return PCI_BAR_UNMAPPED;
 882     }
 883
 884     return new_addr;
 885 }
 886
 887 static void pci_update_mappings(PCIDevice *d)
 888 {
 889     PCIIORegion *r;
 890     int i;
 891     pcibus_t new_addr, filtered_size;
 892
 893     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 894         r = &d->io_regions[i];
 895
 896         /* this region isn't registered */
 897         if (!r->size)
 898             continue;
 899
 900         new_addr = pci_bar_address(d, i, r->type, r->size);
 901
 902         /* bridge filtering */
 903         filtered_size = r->size;
 904         if (new_addr != PCI_BAR_UNMAPPED) {
 905             pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
 906         }
 907
 908         /* This bar isn't changed */
 909         if (new_addr == r->addr && filtered_size == r->filtered_size)
 910             continue;
 911
 912         /* now do the real mapping */
 913         if (r->addr != PCI_BAR_UNMAPPED) {
 914             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
 915                 int class;
 916                 /* NOTE: specific hack for IDE in PC case:
 917                    only one byte must be mapped. */
 918                 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
 919                 if (class == 0x0101 && r->size == 4) {
 920                     isa_unassign_ioport(r->addr + 2, 1);
 921                 } else {
 922                     isa_unassign_ioport(r->addr, r->filtered_size);
 923                 }
 924             } else {
 925                 cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 926                                              r->filtered_size,
 927                                              IO_MEM_UNASSIGNED);
 928                 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
 929             }
 930         }
 931         r->addr = new_addr;
 932         r->filtered_size = filtered_size;
 933         if (r->addr != PCI_BAR_UNMAPPED) {
 934             /*
 935              * TODO: currently almost all the map funcions assumes
 936              * filtered_size == size and addr & ~(size - 1) == addr.
 937              * However with bridge filtering, they aren't always true.
 938              * Teach them such cases, such that filtered_size < size and
 939              * addr & (size - 1) != 0.
 940              */
 941             r->map_func(d, i, r->addr, r->filtered_size, r->type);
 942         }
 943     }
 944 }
 945
 946 uint32_t pci_default_read_config(PCIDevice *d,
 947                                  uint32_t address, int len)
 948 {
 949     uint32_t val = 0;
 950     assert(len == 1 || len == 2 || len == 4);
 951     len = MIN(len, pci_config_size(d) - address);
 952     memcpy(&val, d->config + address, len);
 953     return le32_to_cpu(val);
 954 }
 955
 956 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 957 {
 958     int i;
 959     uint32_t config_size = pci_config_size(d);
 960
 961     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
 962         uint8_t wmask = d->wmask[addr + i];
 963         d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
 964     }
 965     if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
 966         ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
 967         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
 968         range_covers_byte(addr, l, PCI_COMMAND))
 969         pci_update_mappings(d);
 970 }
 971
 972 /***********************************************************/
 973 /* generic PCI irq support */
 974
 975 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 976 static void pci_set_irq(void *opaque, int irq_num, int level)
 977 {
 978     PCIDevice *pci_dev = opaque;
 979     int change;
 980
 981     change = level - pci_irq_state(pci_dev, irq_num);
 982     if (!change)
 983         return;
 984
 985     pci_set_irq_state(pci_dev, irq_num, level);
 986     pci_update_irq_status(pci_dev);
 987     pci_change_irq_level(pci_dev, irq_num, change);
 988 }
 989
 990 /***********************************************************/
 991 /* monitor info on PCI */
 992
 993 typedef struct {
 994     uint16_t class;
 995     const char *desc;
 996 } pci_class_desc;
 997
 998 static const pci_class_desc pci_class_descriptions[] =
 999 {
1000     { 0x0100, "SCSI controller"},
1001     { 0x0101, "IDE controller"},
1002     { 0x0102, "Floppy controller"},
1003     { 0x0103, "IPI controller"},
1004     { 0x0104, "RAID controller"},
1005     { 0x0106, "SATA controller"},
1006     { 0x0107, "SAS controller"},
1007     { 0x0180, "Storage controller"},
1008     { 0x0200, "Ethernet controller"},
1009     { 0x0201, "Token Ring controller"},
1010     { 0x0202, "FDDI controller"},
1011     { 0x0203, "ATM controller"},
1012     { 0x0280, "Network controller"},
1013     { 0x0300, "VGA controller"},
1014     { 0x0301, "XGA controller"},
1015     { 0x0302, "3D controller"},
1016     { 0x0380, "Display controller"},
1017     { 0x0400, "Video controller"},
1018     { 0x0401, "Audio controller"},
1019     { 0x0402, "Phone"},
1020     { 0x0480, "Multimedia controller"},
1021     { 0x0500, "RAM controller"},
1022     { 0x0501, "Flash controller"},
1023     { 0x0580, "Memory controller"},
1024     { 0x0600, "Host bridge"},
1025     { 0x0601, "ISA bridge"},
1026     { 0x0602, "EISA bridge"},
1027     { 0x0603, "MC bridge"},
1028     { 0x0604, "PCI bridge"},
1029     { 0x0605, "PCMCIA bridge"},
1030     { 0x0606, "NUBUS bridge"},
1031     { 0x0607, "CARDBUS bridge"},
1032     { 0x0608, "RACEWAY bridge"},
1033     { 0x0680, "Bridge"},
1034     { 0x0c03, "USB controller"},
1035     { 0, NULL}
1036 };
1037
1038 static void pci_info_device(PCIBus *bus, PCIDevice *d)
1039 {
1040     Monitor *mon = cur_mon;
1041     int i, class;
1042     PCIIORegion *r;
1043     const pci_class_desc *desc;
1044
1045     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
1046                    pci_bus_num(d->bus),
1047                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1048     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1049     monitor_printf(mon, "    ");
1050     desc = pci_class_descriptions;
1051     while (desc->desc && class != desc->class)
1052         desc++;
1053     if (desc->desc) {
1054         monitor_printf(mon, "%s", desc->desc);
1055     } else {
1056         monitor_printf(mon, "Class %04x", class);
1057     }
1058     monitor_printf(mon, ": PCI device %04x:%04x\n",
1059            pci_get_word(d->config + PCI_VENDOR_ID),
1060            pci_get_word(d->config + PCI_DEVICE_ID));
1061
1062     if (d->config[PCI_INTERRUPT_PIN] != 0) {
1063         monitor_printf(mon, "      IRQ %d.\n",
1064                        d->config[PCI_INTERRUPT_LINE]);
1065     }
1066     if (class == 0x0604) {
1067         uint64_t base;
1068         uint64_t limit;
1069
1070         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
1071         monitor_printf(mon, "      secondary bus %d.\n",
1072                        d->config[PCI_SECONDARY_BUS]);
1073         monitor_printf(mon, "      subordinate bus %d.\n",
1074                        d->config[PCI_SUBORDINATE_BUS]);
1075
1076         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_IO);
1077         limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_IO);
1078         monitor_printf(mon, "      IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1079                        base, limit);
1080
1081         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
1082         limit= pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY);
1083         monitor_printf(mon,
1084                        "      memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1085                        base, limit);
1086
1087         base = pci_bridge_get_base(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1088                                    PCI_BASE_ADDRESS_MEM_PREFETCH);
1089         limit = pci_bridge_get_limit(d, PCI_BASE_ADDRESS_SPACE_MEMORY |
1090                                      PCI_BASE_ADDRESS_MEM_PREFETCH);
1091         monitor_printf(mon, "      prefetchable memory range "
1092                        "[0x%08"PRIx64", 0x%08"PRIx64"]\n", base, limit);
1093     }
1094     for(i = 0;i < PCI_NUM_REGIONS; i++) {
1095         r = &d->io_regions[i];
1096         if (r->size != 0) {
1097             monitor_printf(mon, "      BAR%d: ", i);
1098             if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1099                 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1100                                " [0x%04"FMT_PCIBUS"].\n",
1101                                r->addr, r->addr + r->size - 1);
1102             } else {
1103                 const char *type = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64 ?
1104                     "64 bit" : "32 bit";
1105                 const char *prefetch =
1106                     r->type & PCI_BASE_ADDRESS_MEM_PREFETCH ?
1107                     " prefetchable" : "";
1108
1109                 monitor_printf(mon, "%s%s memory at 0x%08"FMT_PCIBUS
1110                                " [0x%08"FMT_PCIBUS"].\n",
1111                                type, prefetch,
1112                                r->addr, r->addr + r->size - 1);
1113             }
1114         }
1115     }
1116     monitor_printf(mon, "      id \"%s\"\n", d->qdev.id ? d->qdev.id : "");
1117     if (class == 0x0604 && d->config[0x19] != 0) {
1118         pci_for_each_device(bus, d->config[0x19], pci_info_device);
1119     }
1120 }
1121
1122 static void pci_for_each_device_under_bus(PCIBus *bus,
1123                                           void (*fn)(PCIBus *b, PCIDevice *d))
1124 {
1125     PCIDevice *d;
1126     int devfn;
1127
1128     for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1129         d = bus->devices[devfn];
1130         if (d)
1131             fn(bus, d);
1132     }
1133 }
1134
1135 void pci_for_each_device(PCIBus *bus, int bus_num,
1136                          void (*fn)(PCIBus *b, PCIDevice *d))
1137 {
1138     bus = pci_find_bus(bus, bus_num);
1139
1140     if (bus) {
1141         pci_for_each_device_under_bus(bus, fn);
1142     }
1143 }
1144
1145 void pci_info(Monitor *mon)
1146 {
1147     struct PCIHostBus *host;
1148     QLIST_FOREACH(host, &host_buses, next) {
1149         pci_for_each_device(host->bus, 0, pci_info_device);
1150     }
1151 }
1152
1153 static const char * const pci_nic_models[] = {
1154     "ne2k_pci",
1155     "i82551",
1156     "i82557b",
1157     "i82559er",
1158     "rtl8139",
1159     "e1000",
1160     "pcnet",
1161     "virtio",
1162     NULL
1163 };
1164
1165 static const char * const pci_nic_names[] = {
1166     "ne2k_pci",
1167     "i82551",
1168     "i82557b",
1169     "i82559er",
1170     "rtl8139",
1171     "e1000",
1172     "pcnet",
1173     "virtio-net-pci",
1174     NULL
1175 };
1176
1177 /* Initialize a PCI NIC.  */
1178 /* FIXME callers should check for failure, but don't */
1179 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1180                         const char *default_devaddr)
1181 {
1182     const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1183     PCIBus *bus;
1184     int devfn;
1185     PCIDevice *pci_dev;
1186     DeviceState *dev;
1187     int i;
1188
1189     i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1190     if (i < 0)
1191         return NULL;
1192
1193     bus = pci_get_bus_devfn(&devfn, devaddr);
1194     if (!bus) {
1195         qemu_error("Invalid PCI device address %s for device %s\n",
1196                    devaddr, pci_nic_names[i]);
1197         return NULL;
1198     }
1199
1200     pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1201     dev = &pci_dev->qdev;
1202     if (nd->name)
1203         dev->id = qemu_strdup(nd->name);
1204     qdev_set_nic_properties(dev, nd);
1205     if (qdev_init(dev) < 0)
1206         return NULL;
1207     return pci_dev;
1208 }
1209
1210 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1211                                const char *default_devaddr)
1212 {
1213     PCIDevice *res;
1214
1215     if (qemu_show_nic_models(nd->model, pci_nic_models))
1216         exit(0);
1217
1218     res = pci_nic_init(nd, default_model, default_devaddr);
1219     if (!res)
1220         exit(1);
1221     return res;
1222 }
1223
1224 typedef struct {
1225     PCIDevice dev;
1226     PCIBus bus;
1227     uint32_t vid;
1228     uint32_t did;
1229 } PCIBridge;
1230
1231
1232 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1233 {
1234     pci_update_mappings(d);
1235 }
1236
1237 static void pci_bridge_update_mappings(PCIBus *b)
1238 {
1239     PCIBus *child;
1240
1241     pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1242
1243     QLIST_FOREACH(child, &b->child, sibling) {
1244         pci_bridge_update_mappings(child);
1245     }
1246 }
1247
1248 static void pci_bridge_write_config(PCIDevice *d,
1249                              uint32_t address, uint32_t val, int len)
1250 {
1251     pci_default_write_config(d, address, val, len);
1252
1253     if (/* io base/limit */
1254         ranges_overlap(address, len, PCI_IO_BASE, 2) ||
1255
1256         /* memory base/limit, prefetchable base/limit and
1257            io base/limit upper 16 */
1258         ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
1259         pci_bridge_update_mappings(d->bus);
1260     }
1261 }
1262
1263 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1264 {
1265     PCIBus *sec;
1266
1267     if (!bus)
1268         return NULL;
1269
1270     if (pci_bus_num(bus) == bus_num) {
1271         return bus;
1272     }
1273
1274     /* try child bus */
1275     QLIST_FOREACH(sec, &bus->child, sibling) {
1276
1277         if (!bus->parent_dev /* pci host bridge */
1278             || (pci_bus_num(sec) <= bus_num &&
1279                 bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
1280             return pci_find_bus(sec, bus_num);
1281         }
1282     }
1283
1284     return NULL;
1285 }
1286
1287 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1288 {
1289     bus = pci_find_bus(bus, bus_num);
1290
1291     if (!bus)
1292         return NULL;
1293
1294     return bus->devices[PCI_DEVFN(slot, function)];
1295 }
1296
1297 static int pci_bridge_initfn(PCIDevice *dev)
1298 {
1299     PCIBridge *s = DO_UPCAST(PCIBridge, dev, dev);
1300
1301     pci_config_set_vendor_id(s->dev.config, s->vid);
1302     pci_config_set_device_id(s->dev.config, s->did);
1303
1304     pci_set_word(dev->config + PCI_STATUS,
1305                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1306     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
1307     dev->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE;
1308     pci_set_word(dev->config + PCI_SEC_STATUS,
1309                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
1310     return 0;
1311 }
1312
1313 static int pci_bridge_exitfn(PCIDevice *pci_dev)
1314 {
1315     PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
1316     PCIBus *bus = &s->bus;
1317     pci_unregister_secondary_bus(bus);
1318     return 0;
1319 }
1320
1321 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
1322                         pci_map_irq_fn map_irq, const char *name)
1323 {
1324     PCIDevice *dev;
1325     PCIBridge *s;
1326
1327     dev = pci_create(bus, devfn, "pci-bridge");
1328     qdev_prop_set_uint32(&dev->qdev, "vendorid", vid);
1329     qdev_prop_set_uint32(&dev->qdev, "deviceid", did);
1330     qdev_init_nofail(&dev->qdev);
1331
1332     s = DO_UPCAST(PCIBridge, dev, dev);
1333     pci_register_secondary_bus(bus, &s->bus, &s->dev, map_irq, name);
1334     return &s->bus;
1335 }
1336
1337 PCIDevice *pci_bridge_get_device(PCIBus *bus)
1338 {
1339     return bus->parent_dev;
1340 }
1341
1342 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1343 {
1344     PCIDevice *pci_dev = (PCIDevice *)qdev;
1345     PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1346     PCIBus *bus;
1347     int devfn, rc;
1348
1349     /* initialize cap_present for pci_is_express() and pci_config_size() */
1350     if (info->is_express) {
1351         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1352     }
1353
1354     bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1355     devfn = pci_dev->devfn;
1356     pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1357                                      info->config_read, info->config_write,
1358                                      info->header_type);
1359     if (pci_dev == NULL)
1360         return -1;
1361     rc = info->init(pci_dev);
1362     if (rc != 0)
1363         return rc;
1364     if (qdev->hotplugged)
1365         bus->hotplug(pci_dev, 1);
1366     return 0;
1367 }
1368
1369 static int pci_unplug_device(DeviceState *qdev)
1370 {
1371     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1372
1373     dev->bus->hotplug(dev, 0);
1374     return 0;
1375 }
1376
1377 void pci_qdev_register(PCIDeviceInfo *info)
1378 {
1379     info->qdev.init = pci_qdev_init;
1380     info->qdev.unplug = pci_unplug_device;
1381     info->qdev.exit = pci_unregister_device;
1382     info->qdev.bus_info = &pci_bus_info;
1383     qdev_register(&info->qdev);
1384 }
1385
1386 void pci_qdev_register_many(PCIDeviceInfo *info)
1387 {
1388     while (info->qdev.name) {
1389         pci_qdev_register(info);
1390         info++;
1391     }
1392 }
1393
1394 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1395 {
1396     DeviceState *dev;
1397
1398     dev = qdev_create(&bus->qbus, name);
1399     qdev_prop_set_uint32(dev, "addr", devfn);
1400     return DO_UPCAST(PCIDevice, qdev, dev);
1401 }
1402
1403 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1404 {
1405     PCIDevice *dev = pci_create(bus, devfn, name);
1406     qdev_init_nofail(&dev->qdev);
1407     return dev;
1408 }
1409
1410 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1411 {
1412     int config_size = pci_config_size(pdev);
1413     int offset = PCI_CONFIG_HEADER_SIZE;
1414     int i;
1415     for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1416         if (pdev->used[i])
1417             offset = i + 1;
1418         else if (i - offset + 1 == size)
1419             return offset;
1420     return 0;
1421 }
1422
1423 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1424                                         uint8_t *prev_p)
1425 {
1426     uint8_t next, prev;
1427
1428     if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1429         return 0;
1430
1431     for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1432          prev = next + PCI_CAP_LIST_NEXT)
1433         if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1434             break;
1435
1436     if (prev_p)
1437         *prev_p = prev;
1438     return next;
1439 }
1440
1441 /* Reserve space and add capability to the linked list in pci config space */
1442 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1443 {
1444     uint8_t offset = pci_find_space(pdev, size);
1445     uint8_t *config = pdev->config + offset;
1446     if (!offset)
1447         return -ENOSPC;
1448     config[PCI_CAP_LIST_ID] = cap_id;
1449     config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1450     pdev->config[PCI_CAPABILITY_LIST] = offset;
1451     pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1452     memset(pdev->used + offset, 0xFF, size);
1453     /* Make capability read-only by default */
1454     memset(pdev->wmask + offset, 0, size);
1455     /* Check capability by default */
1456     memset(pdev->cmask + offset, 0xFF, size);
1457     return offset;
1458 }
1459
1460 /* Unlink capability from the pci config space. */
1461 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1462 {
1463     uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1464     if (!offset)
1465         return;
1466     pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1467     /* Make capability writeable again */
1468     memset(pdev->wmask + offset, 0xff, size);
1469     /* Clear cmask as device-specific registers can't be checked */
1470     memset(pdev->cmask + offset, 0, size);
1471     memset(pdev->used + offset, 0, size);
1472
1473     if (!pdev->config[PCI_CAPABILITY_LIST])
1474         pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1475 }
1476
1477 /* Reserve space for capability at a known offset (to call after load). */
1478 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1479 {
1480     memset(pdev->used + offset, 0xff, size);
1481 }
1482
1483 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1484 {
1485     return pci_find_capability_list(pdev, cap_id, NULL);
1486 }
1487
1488 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1489 {
1490     PCIDevice *d = (PCIDevice *)dev;
1491     const pci_class_desc *desc;
1492     char ctxt[64];
1493     PCIIORegion *r;
1494     int i, class;
1495
1496     class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1497     desc = pci_class_descriptions;
1498     while (desc->desc && class != desc->class)
1499         desc++;
1500     if (desc->desc) {
1501         snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1502     } else {
1503         snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1504     }
1505
1506     monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1507                    "pci id %04x:%04x (sub %04x:%04x)\n",
1508                    indent, "", ctxt,
1509                    d->config[PCI_SECONDARY_BUS],
1510                    PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1511                    pci_get_word(d->config + PCI_VENDOR_ID),
1512                    pci_get_word(d->config + PCI_DEVICE_ID),
1513                    pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1514                    pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1515     for (i = 0; i < PCI_NUM_REGIONS; i++) {
1516         r = &d->io_regions[i];
1517         if (!r->size)
1518             continue;
1519         monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1520                        " [0x%"FMT_PCIBUS"]\n",
1521                        indent, "",
1522                        i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1523                        r->addr, r->addr + r->size - 1);
1524     }
1525 }
1526
1527 static PCIDeviceInfo bridge_info = {
1528     .qdev.name    = "pci-bridge",
1529     .qdev.size    = sizeof(PCIBridge),
1530     .init         = pci_bridge_initfn,
1531     .exit         = pci_bridge_exitfn,
1532     .config_write = pci_bridge_write_config,
1533     .qdev.props   = (Property[]) {
1534         DEFINE_PROP_HEX32("vendorid", PCIBridge, vid, 0),
1535         DEFINE_PROP_HEX32("deviceid", PCIBridge, did, 0),
1536         DEFINE_PROP_END_OF_LIST(),
1537     }
1538 };
1539
1540 static void pci_register_devices(void)
1541 {
1542     pci_qdev_register(&bridge_info);
1543 }
1544
1545 device_init(pci_register_devices)