?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
virtio-9p: Add P9_TCREATE support
[qemu/aliguori-queue.git] / target-sparc / op_helper.c
blobb27778bb2a4feef964362840ded1d0919fc2b0f9
1 #include "exec.h"
2 #include "host-utils.h"
3 #include "helper.h"
4 #if !defined(CONFIG_USER_ONLY)
5 #include "softmmu_exec.h"
6 #endif /* !defined(CONFIG_USER_ONLY) */
7
8 //#define DEBUG_MMU
9 //#define DEBUG_MXCC
10 //#define DEBUG_UNALIGNED
11 //#define DEBUG_UNASSIGNED
12 //#define DEBUG_ASI
13 //#define DEBUG_PCALL
14 //#define DEBUG_PSTATE
15
16 #ifdef DEBUG_MMU
17 #define DPRINTF_MMU(fmt, ...) \
18 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
19 #else
20 #define DPRINTF_MMU(fmt, ...) do {} while (0)
21 #endif
22
23 #ifdef DEBUG_MXCC
24 #define DPRINTF_MXCC(fmt, ...) \
25 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
26 #else
27 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
28 #endif
29
30 #ifdef DEBUG_ASI
31 #define DPRINTF_ASI(fmt, ...) \
32 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
33 #endif
34
35 #ifdef DEBUG_PSTATE
36 #define DPRINTF_PSTATE(fmt, ...) \
37 do { printf("PSTATE: " fmt , ## __VA_ARGS__); } while (0)
38 #else
39 #define DPRINTF_PSTATE(fmt, ...) do {} while (0)
40 #endif
41
42 #ifdef TARGET_SPARC64
43 #ifndef TARGET_ABI32
44 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
45 #else
46 #define AM_CHECK(env1) (1)
47 #endif
48 #endif
49
50 #if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
51 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
52 int is_asi, int size);
53 #endif
54
55 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
56 // Calculates TSB pointer value for fault page size 8k or 64k
57 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
58 uint64_t tag_access_register,
59 int page_size)
60 {
61 uint64_t tsb_base = tsb_register & ~0x1fffULL;
62 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
63 int tsb_size = tsb_register & 0xf;
64
65 // discard lower 13 bits which hold tag access context
66 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
67
68 // now reorder bits
69 uint64_t tsb_base_mask = ~0x1fffULL;
70 uint64_t va = tag_access_va;
71
72 // move va bits to correct position
73 if (page_size == 8*1024) {
74 va >>= 9;
75 } else if (page_size == 64*1024) {
76 va >>= 12;
77 }
78
79 if (tsb_size) {
80 tsb_base_mask <<= tsb_size;
81 }
82
83 // calculate tsb_base mask and adjust va if split is in use
84 if (tsb_split) {
85 if (page_size == 8*1024) {
86 va &= ~(1ULL << (13 + tsb_size));
87 } else if (page_size == 64*1024) {
88 va |= (1ULL << (13 + tsb_size));
89 }
90 tsb_base_mask <<= 1;
91 }
92
93 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
94 }
95
96 // Calculates tag target register value by reordering bits
97 // in tag access register
98 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
99 {
100 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
101 }
102
103 static void replace_tlb_entry(SparcTLBEntry *tlb,
104 uint64_t tlb_tag, uint64_t tlb_tte,
105 CPUState *env1)
106 {
107 target_ulong mask, size, va, offset;
108
109 // flush page range if translation is valid
110 if (TTE_IS_VALID(tlb->tte)) {
111
112 mask = 0xffffffffffffe000ULL;
113 mask <<= 3 * ((tlb->tte >> 61) & 3);
114 size = ~mask + 1;
115
116 va = tlb->tag & mask;
117
118 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
119 tlb_flush_page(env1, va + offset);
120 }
121 }
122
123 tlb->tag = tlb_tag;
124 tlb->tte = tlb_tte;
125 }
126
127 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
128 const char* strmmu, CPUState *env1)
129 {
130 unsigned int i;
131 target_ulong mask;
132
133 for (i = 0; i < 64; i++) {
134 if (TTE_IS_VALID(tlb[i].tte)) {
135
136 mask = 0xffffffffffffe000ULL;
137 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
138
139 if ((demap_addr & mask) == (tlb[i].tag & mask)) {
140 replace_tlb_entry(&tlb[i], 0, 0, env1);
141 #ifdef DEBUG_MMU
142 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
143 dump_mmu(env1);
144 #endif
145 }
146 //return;
147 }
148 }
149
150 }
151
152 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
153 uint64_t tlb_tag, uint64_t tlb_tte,
154 const char* strmmu, CPUState *env1)
155 {
156 unsigned int i, replace_used;
157
158 // Try replacing invalid entry
159 for (i = 0; i < 64; i++) {
160 if (!TTE_IS_VALID(tlb[i].tte)) {
161 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
162 #ifdef DEBUG_MMU
163 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
164 dump_mmu(env1);
165 #endif
166 return;
167 }
168 }
169
170 // All entries are valid, try replacing unlocked entry
171
172 for (replace_used = 0; replace_used < 2; ++replace_used) {
173
174 // Used entries are not replaced on first pass
175
176 for (i = 0; i < 64; i++) {
177 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
178
179 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
180 #ifdef DEBUG_MMU
181 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
182 strmmu, (replace_used?"used":"unused"), i);
183 dump_mmu(env1);
184 #endif
185 return;
186 }
187 }
188
189 // Now reset used bit and search for unused entries again
190
191 for (i = 0; i < 64; i++) {
192 TTE_SET_UNUSED(tlb[i].tte);
193 }
194 }
195
196 #ifdef DEBUG_MMU
197 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
198 #endif
199 // error state?
200 }
201
202 #endif
203
204 static inline target_ulong address_mask(CPUState *env1, target_ulong addr)
205 {
206 #ifdef TARGET_SPARC64
207 if (AM_CHECK(env1))
208 addr &= 0xffffffffULL;
209 #endif
210 return addr;
211 }
212
213 static void raise_exception(int tt)
214 {
215 env->exception_index = tt;
216 cpu_loop_exit();
217 }
218
219 void HELPER(raise_exception)(int tt)
220 {
221 raise_exception(tt);
222 }
223
224 static inline void set_cwp(int new_cwp)
225 {
226 cpu_set_cwp(env, new_cwp);
227 }
228
229 void helper_check_align(target_ulong addr, uint32_t align)
230 {
231 if (addr & align) {
232 #ifdef DEBUG_UNALIGNED
233 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
234 "\n", addr, env->pc);
235 #endif
236 raise_exception(TT_UNALIGNED);
237 }
238 }
239
240 #define F_HELPER(name, p) void helper_f##name##p(void)
241
242 #define F_BINOP(name) \
243 float32 helper_f ## name ## s (float32 src1, float32 src2) \
244 { \
245 return float32_ ## name (src1, src2, &env->fp_status); \
246 } \
247 F_HELPER(name, d) \
248 { \
249 DT0 = float64_ ## name (DT0, DT1, &env->fp_status); \
250 } \
251 F_HELPER(name, q) \
252 { \
253 QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
254 }
255
256 F_BINOP(add);
257 F_BINOP(sub);
258 F_BINOP(mul);
259 F_BINOP(div);
260 #undef F_BINOP
261
262 void helper_fsmuld(float32 src1, float32 src2)
263 {
264 DT0 = float64_mul(float32_to_float64(src1, &env->fp_status),
265 float32_to_float64(src2, &env->fp_status),
266 &env->fp_status);
267 }
268
269 void helper_fdmulq(void)
270 {
271 QT0 = float128_mul(float64_to_float128(DT0, &env->fp_status),
272 float64_to_float128(DT1, &env->fp_status),
273 &env->fp_status);
274 }
275
276 float32 helper_fnegs(float32 src)
277 {
278 return float32_chs(src);
279 }
280
281 #ifdef TARGET_SPARC64
282 F_HELPER(neg, d)
283 {
284 DT0 = float64_chs(DT1);
285 }
286
287 F_HELPER(neg, q)
288 {
289 QT0 = float128_chs(QT1);
290 }
291 #endif
292
293 /* Integer to float conversion. */
294 float32 helper_fitos(int32_t src)
295 {
296 return int32_to_float32(src, &env->fp_status);
297 }
298
299 void helper_fitod(int32_t src)
300 {
301 DT0 = int32_to_float64(src, &env->fp_status);
302 }
303
304 void helper_fitoq(int32_t src)
305 {
306 QT0 = int32_to_float128(src, &env->fp_status);
307 }
308
309 #ifdef TARGET_SPARC64
310 float32 helper_fxtos(void)
311 {
312 return int64_to_float32(*((int64_t *)&DT1), &env->fp_status);
313 }
314
315 F_HELPER(xto, d)
316 {
317 DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);
318 }
319
320 F_HELPER(xto, q)
321 {
322 QT0 = int64_to_float128(*((int64_t *)&DT1), &env->fp_status);
323 }
324 #endif
325 #undef F_HELPER
326
327 /* floating point conversion */
328 float32 helper_fdtos(void)
329 {
330 return float64_to_float32(DT1, &env->fp_status);
331 }
332
333 void helper_fstod(float32 src)
334 {
335 DT0 = float32_to_float64(src, &env->fp_status);
336 }
337
338 float32 helper_fqtos(void)
339 {
340 return float128_to_float32(QT1, &env->fp_status);
341 }
342
343 void helper_fstoq(float32 src)
344 {
345 QT0 = float32_to_float128(src, &env->fp_status);
346 }
347
348 void helper_fqtod(void)
349 {
350 DT0 = float128_to_float64(QT1, &env->fp_status);
351 }
352
353 void helper_fdtoq(void)
354 {
355 QT0 = float64_to_float128(DT1, &env->fp_status);
356 }
357
358 /* Float to integer conversion. */
359 int32_t helper_fstoi(float32 src)
360 {
361 return float32_to_int32_round_to_zero(src, &env->fp_status);
362 }
363
364 int32_t helper_fdtoi(void)
365 {
366 return float64_to_int32_round_to_zero(DT1, &env->fp_status);
367 }
368
369 int32_t helper_fqtoi(void)
370 {
371 return float128_to_int32_round_to_zero(QT1, &env->fp_status);
372 }
373
374 #ifdef TARGET_SPARC64
375 void helper_fstox(float32 src)
376 {
377 *((int64_t *)&DT0) = float32_to_int64_round_to_zero(src, &env->fp_status);
378 }
379
380 void helper_fdtox(void)
381 {
382 *((int64_t *)&DT0) = float64_to_int64_round_to_zero(DT1, &env->fp_status);
383 }
384
385 void helper_fqtox(void)
386 {
387 *((int64_t *)&DT0) = float128_to_int64_round_to_zero(QT1, &env->fp_status);
388 }
389
390 void helper_faligndata(void)
391 {
392 uint64_t tmp;
393
394 tmp = (*((uint64_t *)&DT0)) << ((env->gsr & 7) * 8);
395 /* on many architectures a shift of 64 does nothing */
396 if ((env->gsr & 7) != 0) {
397 tmp |= (*((uint64_t *)&DT1)) >> (64 - (env->gsr & 7) * 8);
398 }
399 *((uint64_t *)&DT0) = tmp;
400 }
401
402 #ifdef HOST_WORDS_BIGENDIAN
403 #define VIS_B64(n) b[7 - (n)]
404 #define VIS_W64(n) w[3 - (n)]
405 #define VIS_SW64(n) sw[3 - (n)]
406 #define VIS_L64(n) l[1 - (n)]
407 #define VIS_B32(n) b[3 - (n)]
408 #define VIS_W32(n) w[1 - (n)]
409 #else
410 #define VIS_B64(n) b[n]
411 #define VIS_W64(n) w[n]
412 #define VIS_SW64(n) sw[n]
413 #define VIS_L64(n) l[n]
414 #define VIS_B32(n) b[n]
415 #define VIS_W32(n) w[n]
416 #endif
417
418 typedef union {
419 uint8_t b[8];
420 uint16_t w[4];
421 int16_t sw[4];
422 uint32_t l[2];
423 float64 d;
424 } vis64;
425
426 typedef union {
427 uint8_t b[4];
428 uint16_t w[2];
429 uint32_t l;
430 float32 f;
431 } vis32;
432
433 void helper_fpmerge(void)
434 {
435 vis64 s, d;
436
437 s.d = DT0;
438 d.d = DT1;
439
440 // Reverse calculation order to handle overlap
441 d.VIS_B64(7) = s.VIS_B64(3);
442 d.VIS_B64(6) = d.VIS_B64(3);
443 d.VIS_B64(5) = s.VIS_B64(2);
444 d.VIS_B64(4) = d.VIS_B64(2);
445 d.VIS_B64(3) = s.VIS_B64(1);
446 d.VIS_B64(2) = d.VIS_B64(1);
447 d.VIS_B64(1) = s.VIS_B64(0);
448 //d.VIS_B64(0) = d.VIS_B64(0);
449
450 DT0 = d.d;
451 }
452
453 void helper_fmul8x16(void)
454 {
455 vis64 s, d;
456 uint32_t tmp;
457
458 s.d = DT0;
459 d.d = DT1;
460
461 #define PMUL(r) \
462 tmp = (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \
463 if ((tmp & 0xff) > 0x7f) \
464 tmp += 0x100; \
465 d.VIS_W64(r) = tmp >> 8;
466
467 PMUL(0);
468 PMUL(1);
469 PMUL(2);
470 PMUL(3);
471 #undef PMUL
472
473 DT0 = d.d;
474 }
475
476 void helper_fmul8x16al(void)
477 {
478 vis64 s, d;
479 uint32_t tmp;
480
481 s.d = DT0;
482 d.d = DT1;
483
484 #define PMUL(r) \
485 tmp = (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \
486 if ((tmp & 0xff) > 0x7f) \
487 tmp += 0x100; \
488 d.VIS_W64(r) = tmp >> 8;
489
490 PMUL(0);
491 PMUL(1);
492 PMUL(2);
493 PMUL(3);
494 #undef PMUL
495
496 DT0 = d.d;
497 }
498
499 void helper_fmul8x16au(void)
500 {
501 vis64 s, d;
502 uint32_t tmp;
503
504 s.d = DT0;
505 d.d = DT1;
506
507 #define PMUL(r) \
508 tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
509 if ((tmp & 0xff) > 0x7f) \
510 tmp += 0x100; \
511 d.VIS_W64(r) = tmp >> 8;
512
513 PMUL(0);
514 PMUL(1);
515 PMUL(2);
516 PMUL(3);
517 #undef PMUL
518
519 DT0 = d.d;
520 }
521
522 void helper_fmul8sux16(void)
523 {
524 vis64 s, d;
525 uint32_t tmp;
526
527 s.d = DT0;
528 d.d = DT1;
529
530 #define PMUL(r) \
531 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
532 if ((tmp & 0xff) > 0x7f) \
533 tmp += 0x100; \
534 d.VIS_W64(r) = tmp >> 8;
535
536 PMUL(0);
537 PMUL(1);
538 PMUL(2);
539 PMUL(3);
540 #undef PMUL
541
542 DT0 = d.d;
543 }
544
545 void helper_fmul8ulx16(void)
546 {
547 vis64 s, d;
548 uint32_t tmp;
549
550 s.d = DT0;
551 d.d = DT1;
552
553 #define PMUL(r) \
554 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
555 if ((tmp & 0xff) > 0x7f) \
556 tmp += 0x100; \
557 d.VIS_W64(r) = tmp >> 8;
558
559 PMUL(0);
560 PMUL(1);
561 PMUL(2);
562 PMUL(3);
563 #undef PMUL
564
565 DT0 = d.d;
566 }
567
568 void helper_fmuld8sux16(void)
569 {
570 vis64 s, d;
571 uint32_t tmp;
572
573 s.d = DT0;
574 d.d = DT1;
575
576 #define PMUL(r) \
577 tmp = (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \
578 if ((tmp & 0xff) > 0x7f) \
579 tmp += 0x100; \
580 d.VIS_L64(r) = tmp;
581
582 // Reverse calculation order to handle overlap
583 PMUL(1);
584 PMUL(0);
585 #undef PMUL
586
587 DT0 = d.d;
588 }
589
590 void helper_fmuld8ulx16(void)
591 {
592 vis64 s, d;
593 uint32_t tmp;
594
595 s.d = DT0;
596 d.d = DT1;
597
598 #define PMUL(r) \
599 tmp = (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \
600 if ((tmp & 0xff) > 0x7f) \
601 tmp += 0x100; \
602 d.VIS_L64(r) = tmp;
603
604 // Reverse calculation order to handle overlap
605 PMUL(1);
606 PMUL(0);
607 #undef PMUL
608
609 DT0 = d.d;
610 }
611
612 void helper_fexpand(void)
613 {
614 vis32 s;
615 vis64 d;
616
617 s.l = (uint32_t)(*(uint64_t *)&DT0 & 0xffffffff);
618 d.d = DT1;
619 d.VIS_W64(0) = s.VIS_B32(0) << 4;
620 d.VIS_W64(1) = s.VIS_B32(1) << 4;
621 d.VIS_W64(2) = s.VIS_B32(2) << 4;
622 d.VIS_W64(3) = s.VIS_B32(3) << 4;
623
624 DT0 = d.d;
625 }
626
627 #define VIS_HELPER(name, F) \
628 void name##16(void) \
629 { \
630 vis64 s, d; \
631 \
632 s.d = DT0; \
633 d.d = DT1; \
634 \
635 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \
636 d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \
637 d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \
638 d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \
639 \
640 DT0 = d.d; \
641 } \
642 \
643 uint32_t name##16s(uint32_t src1, uint32_t src2) \
644 { \
645 vis32 s, d; \
646 \
647 s.l = src1; \
648 d.l = src2; \
649 \
650 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
651 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
652 \
653 return d.l; \
654 } \
655 \
656 void name##32(void) \
657 { \
658 vis64 s, d; \
659 \
660 s.d = DT0; \
661 d.d = DT1; \
662 \
663 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \
664 d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \
665 \
666 DT0 = d.d; \
667 } \
668 \
669 uint32_t name##32s(uint32_t src1, uint32_t src2) \
670 { \
671 vis32 s, d; \
672 \
673 s.l = src1; \
674 d.l = src2; \
675 \
676 d.l = F(d.l, s.l); \
677 \
678 return d.l; \
679 }
680
681 #define FADD(a, b) ((a) + (b))
682 #define FSUB(a, b) ((a) - (b))
683 VIS_HELPER(helper_fpadd, FADD)
684 VIS_HELPER(helper_fpsub, FSUB)
685
686 #define VIS_CMPHELPER(name, F) \
687 void name##16(void) \
688 { \
689 vis64 s, d; \
690 \
691 s.d = DT0; \
692 d.d = DT1; \
693 \
694 d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0))? 1: 0; \
695 d.VIS_W64(0) |= F(d.VIS_W64(1), s.VIS_W64(1))? 2: 0; \
696 d.VIS_W64(0) |= F(d.VIS_W64(2), s.VIS_W64(2))? 4: 0; \
697 d.VIS_W64(0) |= F(d.VIS_W64(3), s.VIS_W64(3))? 8: 0; \
698 \
699 DT0 = d.d; \
700 } \
701 \
702 void name##32(void) \
703 { \
704 vis64 s, d; \
705 \
706 s.d = DT0; \
707 d.d = DT1; \
708 \
709 d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0))? 1: 0; \
710 d.VIS_L64(0) |= F(d.VIS_L64(1), s.VIS_L64(1))? 2: 0; \
711 \
712 DT0 = d.d; \
713 }
714
715 #define FCMPGT(a, b) ((a) > (b))
716 #define FCMPEQ(a, b) ((a) == (b))
717 #define FCMPLE(a, b) ((a) <= (b))
718 #define FCMPNE(a, b) ((a) != (b))
719
720 VIS_CMPHELPER(helper_fcmpgt, FCMPGT)
721 VIS_CMPHELPER(helper_fcmpeq, FCMPEQ)
722 VIS_CMPHELPER(helper_fcmple, FCMPLE)
723 VIS_CMPHELPER(helper_fcmpne, FCMPNE)
724 #endif
725
726 void helper_check_ieee_exceptions(void)
727 {
728 target_ulong status;
729
730 status = get_float_exception_flags(&env->fp_status);
731 if (status) {
732 /* Copy IEEE 754 flags into FSR */
733 if (status & float_flag_invalid)
734 env->fsr |= FSR_NVC;
735 if (status & float_flag_overflow)
736 env->fsr |= FSR_OFC;
737 if (status & float_flag_underflow)
738 env->fsr |= FSR_UFC;
739 if (status & float_flag_divbyzero)
740 env->fsr |= FSR_DZC;
741 if (status & float_flag_inexact)
742 env->fsr |= FSR_NXC;
743
744 if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
745 /* Unmasked exception, generate a trap */
746 env->fsr |= FSR_FTT_IEEE_EXCP;
747 raise_exception(TT_FP_EXCP);
748 } else {
749 /* Accumulate exceptions */
750 env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
751 }
752 }
753 }
754
755 void helper_clear_float_exceptions(void)
756 {
757 set_float_exception_flags(0, &env->fp_status);
758 }
759
760 float32 helper_fabss(float32 src)
761 {
762 return float32_abs(src);
763 }
764
765 #ifdef TARGET_SPARC64
766 void helper_fabsd(void)
767 {
768 DT0 = float64_abs(DT1);
769 }
770
771 void helper_fabsq(void)
772 {
773 QT0 = float128_abs(QT1);
774 }
775 #endif
776
777 float32 helper_fsqrts(float32 src)
778 {
779 return float32_sqrt(src, &env->fp_status);
780 }
781
782 void helper_fsqrtd(void)
783 {
784 DT0 = float64_sqrt(DT1, &env->fp_status);
785 }
786
787 void helper_fsqrtq(void)
788 {
789 QT0 = float128_sqrt(QT1, &env->fp_status);
790 }
791
792 #define GEN_FCMP(name, size, reg1, reg2, FS, TRAP) \
793 void glue(helper_, name) (void) \
794 { \
795 target_ulong new_fsr; \
796 \
797 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
798 switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) { \
799 case float_relation_unordered: \
800 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
801 if ((env->fsr & FSR_NVM) || TRAP) { \
802 env->fsr |= new_fsr; \
803 env->fsr |= FSR_NVC; \
804 env->fsr |= FSR_FTT_IEEE_EXCP; \
805 raise_exception(TT_FP_EXCP); \
806 } else { \
807 env->fsr |= FSR_NVA; \
808 } \
809 break; \
810 case float_relation_less: \
811 new_fsr = FSR_FCC0 << FS; \
812 break; \
813 case float_relation_greater: \
814 new_fsr = FSR_FCC1 << FS; \
815 break; \
816 default: \
817 new_fsr = 0; \
818 break; \
819 } \
820 env->fsr |= new_fsr; \
821 }
822 #define GEN_FCMPS(name, size, FS, TRAP) \
823 void glue(helper_, name)(float32 src1, float32 src2) \
824 { \
825 target_ulong new_fsr; \
826 \
827 env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
828 switch (glue(size, _compare) (src1, src2, &env->fp_status)) { \
829 case float_relation_unordered: \
830 new_fsr = (FSR_FCC1 | FSR_FCC0) << FS; \
831 if ((env->fsr & FSR_NVM) || TRAP) { \
832 env->fsr |= new_fsr; \
833 env->fsr |= FSR_NVC; \
834 env->fsr |= FSR_FTT_IEEE_EXCP; \
835 raise_exception(TT_FP_EXCP); \
836 } else { \
837 env->fsr |= FSR_NVA; \
838 } \
839 break; \
840 case float_relation_less: \
841 new_fsr = FSR_FCC0 << FS; \
842 break; \
843 case float_relation_greater: \
844 new_fsr = FSR_FCC1 << FS; \
845 break; \
846 default: \
847 new_fsr = 0; \
848 break; \
849 } \
850 env->fsr |= new_fsr; \
851 }
852
853 GEN_FCMPS(fcmps, float32, 0, 0);
854 GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);
855
856 GEN_FCMPS(fcmpes, float32, 0, 1);
857 GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);
858
859 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
860 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
861
862 static uint32_t compute_all_flags(void)
863 {
864 return env->psr & PSR_ICC;
865 }
866
867 static uint32_t compute_C_flags(void)
868 {
869 return env->psr & PSR_CARRY;
870 }
871
872 static inline uint32_t get_NZ_icc(target_ulong dst)
873 {
874 uint32_t ret = 0;
875
876 if (!(dst & 0xffffffffULL))
877 ret |= PSR_ZERO;
878 if ((int32_t) (dst & 0xffffffffULL) < 0)
879 ret |= PSR_NEG;
880 return ret;
881 }
882
883 #ifdef TARGET_SPARC64
884 static uint32_t compute_all_flags_xcc(void)
885 {
886 return env->xcc & PSR_ICC;
887 }
888
889 static uint32_t compute_C_flags_xcc(void)
890 {
891 return env->xcc & PSR_CARRY;
892 }
893
894 static inline uint32_t get_NZ_xcc(target_ulong dst)
895 {
896 uint32_t ret = 0;
897
898 if (!dst)
899 ret |= PSR_ZERO;
900 if ((int64_t)dst < 0)
901 ret |= PSR_NEG;
902 return ret;
903 }
904 #endif
905
906 static inline uint32_t get_V_div_icc(target_ulong src2)
907 {
908 uint32_t ret = 0;
909
910 if (src2 != 0)
911 ret |= PSR_OVF;
912 return ret;
913 }
914
915 static uint32_t compute_all_div(void)
916 {
917 uint32_t ret;
918
919 ret = get_NZ_icc(CC_DST);
920 ret |= get_V_div_icc(CC_SRC2);
921 return ret;
922 }
923
924 static uint32_t compute_C_div(void)
925 {
926 return 0;
927 }
928
929 /* carry = (src1[31] & src2[31]) | ( ~dst[31] & (src1[31] | src2[31])) */
930 static inline uint32_t get_C_add_icc(target_ulong dst, target_ulong src1,
931 target_ulong src2)
932 {
933 uint32_t ret = 0;
934
935 if (((src1 & (1ULL << 31)) & (src2 & (1ULL << 31)))
936 | ((~(dst & (1ULL << 31)))
937 & ((src1 & (1ULL << 31)) | (src2 & (1ULL << 31)))))
938 ret |= PSR_CARRY;
939 return ret;
940 }
941
942 static inline uint32_t get_V_add_icc(target_ulong dst, target_ulong src1,
943 target_ulong src2)
944 {
945 uint32_t ret = 0;
946
947 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 31))
948 ret |= PSR_OVF;
949 return ret;
950 }
951
952 #ifdef TARGET_SPARC64
953 static inline uint32_t get_C_add_xcc(target_ulong dst, target_ulong src1)
954 {
955 uint32_t ret = 0;
956
957 if (dst < src1)
958 ret |= PSR_CARRY;
959 return ret;
960 }
961
962 static inline uint32_t get_V_add_xcc(target_ulong dst, target_ulong src1,
963 target_ulong src2)
964 {
965 uint32_t ret = 0;
966
967 if (((src1 ^ src2 ^ -1) & (src1 ^ dst)) & (1ULL << 63))
968 ret |= PSR_OVF;
969 return ret;
970 }
971
972 static uint32_t compute_all_add_xcc(void)
973 {
974 uint32_t ret;
975
976 ret = get_NZ_xcc(CC_DST);
977 ret |= get_C_add_xcc(CC_DST, CC_SRC);
978 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
979 return ret;
980 }
981
982 static uint32_t compute_C_add_xcc(void)
983 {
984 return get_C_add_xcc(CC_DST, CC_SRC);
985 }
986 #endif
987
988 static uint32_t compute_all_add(void)
989 {
990 uint32_t ret;
991
992 ret = get_NZ_icc(CC_DST);
993 ret |= get_C_add_icc(CC_DST, CC_SRC, CC_SRC2);
994 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
995 return ret;
996 }
997
998 static uint32_t compute_C_add(void)
999 {
1000 return get_C_add_icc(CC_DST, CC_SRC, CC_SRC2);
1001 }
1002
1003 #ifdef TARGET_SPARC64
1004 static uint32_t compute_all_addx_xcc(void)
1005 {
1006 uint32_t ret;
1007
1008 ret = get_NZ_xcc(CC_DST);
1009 ret |= get_C_add_xcc(CC_DST - CC_SRC2, CC_SRC);
1010 ret |= get_C_add_xcc(CC_DST, CC_SRC);
1011 ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
1012 return ret;
1013 }
1014
1015 static uint32_t compute_C_addx_xcc(void)
1016 {
1017 uint32_t ret;
1018
1019 ret = get_C_add_xcc(CC_DST - CC_SRC2, CC_SRC);
1020 ret |= get_C_add_xcc(CC_DST, CC_SRC);
1021 return ret;
1022 }
1023 #endif
1024
1025 static inline uint32_t get_V_tag_icc(target_ulong src1, target_ulong src2)
1026 {
1027 uint32_t ret = 0;
1028
1029 if ((src1 | src2) & 0x3)
1030 ret |= PSR_OVF;
1031 return ret;
1032 }
1033
1034 static uint32_t compute_all_tadd(void)
1035 {
1036 uint32_t ret;
1037
1038 ret = get_NZ_icc(CC_DST);
1039 ret |= get_C_add_icc(CC_DST, CC_SRC, CC_SRC2);
1040 ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
1041 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
1042 return ret;
1043 }
1044
1045 static uint32_t compute_C_tadd(void)
1046 {
1047 return get_C_add_icc(CC_DST, CC_SRC, CC_SRC2);
1048 }
1049
1050 static uint32_t compute_all_taddtv(void)
1051 {
1052 uint32_t ret;
1053
1054 ret = get_NZ_icc(CC_DST);
1055 ret |= get_C_add_icc(CC_DST, CC_SRC, CC_SRC2);
1056 return ret;
1057 }
1058
1059 static uint32_t compute_C_taddtv(void)
1060 {
1061 return get_C_add_icc(CC_DST, CC_SRC, CC_SRC2);
1062 }
1063
1064 /* carry = (~src1[31] & src2[31]) | ( dst[31] & (~src1[31] | src2[31])) */
1065 static inline uint32_t get_C_sub_icc(target_ulong dst, target_ulong src1,
1066 target_ulong src2)
1067 {
1068 uint32_t ret = 0;
1069
1070 if (((~(src1 & (1ULL << 31))) & (src2 & (1ULL << 31)))
1071 | ((dst & (1ULL << 31)) & (( ~(src1 & (1ULL << 31)))
1072 | (src2 & (1ULL << 31)))))
1073 ret |= PSR_CARRY;
1074 return ret;
1075 }
1076
1077 static inline uint32_t get_V_sub_icc(target_ulong dst, target_ulong src1,
1078 target_ulong src2)
1079 {
1080 uint32_t ret = 0;
1081
1082 if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 31))
1083 ret |= PSR_OVF;
1084 return ret;
1085 }
1086
1087
1088 #ifdef TARGET_SPARC64
1089 static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2)
1090 {
1091 uint32_t ret = 0;
1092
1093 if (src1 < src2)
1094 ret |= PSR_CARRY;
1095 return ret;
1096 }
1097
1098 static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
1099 target_ulong src2)
1100 {
1101 uint32_t ret = 0;
1102
1103 if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63))
1104 ret |= PSR_OVF;
1105 return ret;
1106 }
1107
1108 static uint32_t compute_all_sub_xcc(void)
1109 {
1110 uint32_t ret;
1111
1112 ret = get_NZ_xcc(CC_DST);
1113 ret |= get_C_sub_xcc(CC_SRC, CC_SRC2);
1114 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1115 return ret;
1116 }
1117
1118 static uint32_t compute_C_sub_xcc(void)
1119 {
1120 return get_C_sub_xcc(CC_SRC, CC_SRC2);
1121 }
1122 #endif
1123
1124 static uint32_t compute_all_sub(void)
1125 {
1126 uint32_t ret;
1127
1128 ret = get_NZ_icc(CC_DST);
1129 ret |= get_C_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1130 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1131 return ret;
1132 }
1133
1134 static uint32_t compute_C_sub(void)
1135 {
1136 return get_C_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1137 }
1138
1139 #ifdef TARGET_SPARC64
1140 static uint32_t compute_all_subx_xcc(void)
1141 {
1142 uint32_t ret;
1143
1144 ret = get_NZ_xcc(CC_DST);
1145 ret |= get_C_sub_xcc(CC_DST - CC_SRC2, CC_SRC);
1146 ret |= get_C_sub_xcc(CC_DST, CC_SRC2);
1147 ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
1148 return ret;
1149 }
1150
1151 static uint32_t compute_C_subx_xcc(void)
1152 {
1153 uint32_t ret;
1154
1155 ret = get_C_sub_xcc(CC_DST - CC_SRC2, CC_SRC);
1156 ret |= get_C_sub_xcc(CC_DST, CC_SRC2);
1157 return ret;
1158 }
1159 #endif
1160
1161 static uint32_t compute_all_tsub(void)
1162 {
1163 uint32_t ret;
1164
1165 ret = get_NZ_icc(CC_DST);
1166 ret |= get_C_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1167 ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1168 ret |= get_V_tag_icc(CC_SRC, CC_SRC2);
1169 return ret;
1170 }
1171
1172 static uint32_t compute_C_tsub(void)
1173 {
1174 return get_C_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1175 }
1176
1177 static uint32_t compute_all_tsubtv(void)
1178 {
1179 uint32_t ret;
1180
1181 ret = get_NZ_icc(CC_DST);
1182 ret |= get_C_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1183 return ret;
1184 }
1185
1186 static uint32_t compute_C_tsubtv(void)
1187 {
1188 return get_C_sub_icc(CC_DST, CC_SRC, CC_SRC2);
1189 }
1190
1191 static uint32_t compute_all_logic(void)
1192 {
1193 return get_NZ_icc(CC_DST);
1194 }
1195
1196 static uint32_t compute_C_logic(void)
1197 {
1198 return 0;
1199 }
1200
1201 #ifdef TARGET_SPARC64
1202 static uint32_t compute_all_logic_xcc(void)
1203 {
1204 return get_NZ_xcc(CC_DST);
1205 }
1206 #endif
1207
1208 typedef struct CCTable {
1209 uint32_t (*compute_all)(void); /* return all the flags */
1210 uint32_t (*compute_c)(void); /* return the C flag */
1211 } CCTable;
1212
1213 static const CCTable icc_table[CC_OP_NB] = {
1214 /* CC_OP_DYNAMIC should never happen */
1215 [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
1216 [CC_OP_DIV] = { compute_all_div, compute_C_div },
1217 [CC_OP_ADD] = { compute_all_add, compute_C_add },
1218 [CC_OP_ADDX] = { compute_all_add, compute_C_add },
1219 [CC_OP_TADD] = { compute_all_tadd, compute_C_tadd },
1220 [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_taddtv },
1221 [CC_OP_SUB] = { compute_all_sub, compute_C_sub },
1222 [CC_OP_SUBX] = { compute_all_sub, compute_C_sub },
1223 [CC_OP_TSUB] = { compute_all_tsub, compute_C_tsub },
1224 [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_tsubtv },
1225 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
1226 };
1227
1228 #ifdef TARGET_SPARC64
1229 static const CCTable xcc_table[CC_OP_NB] = {
1230 /* CC_OP_DYNAMIC should never happen */
1231 [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
1232 [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic },
1233 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
1234 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
1235 [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc },
1236 [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc },
1237 [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1238 [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc },
1239 [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
1240 [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc },
1241 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
1242 };
1243 #endif
1244
1245 void helper_compute_psr(void)
1246 {
1247 uint32_t new_psr;
1248
1249 new_psr = icc_table[CC_OP].compute_all();
1250 env->psr = new_psr;
1251 #ifdef TARGET_SPARC64
1252 new_psr = xcc_table[CC_OP].compute_all();
1253 env->xcc = new_psr;
1254 #endif
1255 CC_OP = CC_OP_FLAGS;
1256 }
1257
1258 uint32_t helper_compute_C_icc(void)
1259 {
1260 uint32_t ret;
1261
1262 ret = icc_table[CC_OP].compute_c() >> PSR_CARRY_SHIFT;
1263 return ret;
1264 }
1265
1266 #ifdef TARGET_SPARC64
1267 GEN_FCMPS(fcmps_fcc1, float32, 22, 0);
1268 GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);
1269 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
1270
1271 GEN_FCMPS(fcmps_fcc2, float32, 24, 0);
1272 GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);
1273 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
1274
1275 GEN_FCMPS(fcmps_fcc3, float32, 26, 0);
1276 GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);
1277 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
1278
1279 GEN_FCMPS(fcmpes_fcc1, float32, 22, 1);
1280 GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);
1281 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
1282
1283 GEN_FCMPS(fcmpes_fcc2, float32, 24, 1);
1284 GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);
1285 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
1286
1287 GEN_FCMPS(fcmpes_fcc3, float32, 26, 1);
1288 GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
1289 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
1290 #endif
1291 #undef GEN_FCMPS
1292
1293 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
1294 defined(DEBUG_MXCC)
1295 static void dump_mxcc(CPUState *env)
1296 {
1297 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1298 "\n",
1299 env->mxccdata[0], env->mxccdata[1],
1300 env->mxccdata[2], env->mxccdata[3]);
1301 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1302 "\n"
1303 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
1304 "\n",
1305 env->mxccregs[0], env->mxccregs[1],
1306 env->mxccregs[2], env->mxccregs[3],
1307 env->mxccregs[4], env->mxccregs[5],
1308 env->mxccregs[6], env->mxccregs[7]);
1309 }
1310 #endif
1311
1312 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
1313 && defined(DEBUG_ASI)
1314 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
1315 uint64_t r1)
1316 {
1317 switch (size)
1318 {
1319 case 1:
1320 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
1321 addr, asi, r1 & 0xff);
1322 break;
1323 case 2:
1324 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
1325 addr, asi, r1 & 0xffff);
1326 break;
1327 case 4:
1328 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
1329 addr, asi, r1 & 0xffffffff);
1330 break;
1331 case 8:
1332 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
1333 addr, asi, r1);
1334 break;
1335 }
1336 }
1337 #endif
1338
1339 #ifndef TARGET_SPARC64
1340 #ifndef CONFIG_USER_ONLY
1341 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1342 {
1343 uint64_t ret = 0;
1344 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
1345 uint32_t last_addr = addr;
1346 #endif
1347
1348 helper_check_align(addr, size - 1);
1349 switch (asi) {
1350 case 2: /* SuperSparc MXCC registers */
1351 switch (addr) {
1352 case 0x01c00a00: /* MXCC control register */
1353 if (size == 8)
1354 ret = env->mxccregs[3];
1355 else
1356 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1357 size);
1358 break;
1359 case 0x01c00a04: /* MXCC control register */
1360 if (size == 4)
1361 ret = env->mxccregs[3];
1362 else
1363 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1364 size);
1365 break;
1366 case 0x01c00c00: /* Module reset register */
1367 if (size == 8) {
1368 ret = env->mxccregs[5];
1369 // should we do something here?
1370 } else
1371 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1372 size);
1373 break;
1374 case 0x01c00f00: /* MBus port address register */
1375 if (size == 8)
1376 ret = env->mxccregs[7];
1377 else
1378 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1379 size);
1380 break;
1381 default:
1382 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1383 size);
1384 break;
1385 }
1386 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
1387 "addr = %08x -> ret = %" PRIx64 ","
1388 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
1389 #ifdef DEBUG_MXCC
1390 dump_mxcc(env);
1391 #endif
1392 break;
1393 case 3: /* MMU probe */
1394 {
1395 int mmulev;
1396
1397 mmulev = (addr >> 8) & 15;
1398 if (mmulev > 4)
1399 ret = 0;
1400 else
1401 ret = mmu_probe(env, addr, mmulev);
1402 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
1403 addr, mmulev, ret);
1404 }
1405 break;
1406 case 4: /* read MMU regs */
1407 {
1408 int reg = (addr >> 8) & 0x1f;
1409
1410 ret = env->mmuregs[reg];
1411 if (reg == 3) /* Fault status cleared on read */
1412 env->mmuregs[3] = 0;
1413 else if (reg == 0x13) /* Fault status read */
1414 ret = env->mmuregs[3];
1415 else if (reg == 0x14) /* Fault address read */
1416 ret = env->mmuregs[4];
1417 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
1418 }
1419 break;
1420 case 5: // Turbosparc ITLB Diagnostic
1421 case 6: // Turbosparc DTLB Diagnostic
1422 case 7: // Turbosparc IOTLB Diagnostic
1423 break;
1424 case 9: /* Supervisor code access */
1425 switch(size) {
1426 case 1:
1427 ret = ldub_code(addr);
1428 break;
1429 case 2:
1430 ret = lduw_code(addr);
1431 break;
1432 default:
1433 case 4:
1434 ret = ldl_code(addr);
1435 break;
1436 case 8:
1437 ret = ldq_code(addr);
1438 break;
1439 }
1440 break;
1441 case 0xa: /* User data access */
1442 switch(size) {
1443 case 1:
1444 ret = ldub_user(addr);
1445 break;
1446 case 2:
1447 ret = lduw_user(addr);
1448 break;
1449 default:
1450 case 4:
1451 ret = ldl_user(addr);
1452 break;
1453 case 8:
1454 ret = ldq_user(addr);
1455 break;
1456 }
1457 break;
1458 case 0xb: /* Supervisor data access */
1459 switch(size) {
1460 case 1:
1461 ret = ldub_kernel(addr);
1462 break;
1463 case 2:
1464 ret = lduw_kernel(addr);
1465 break;
1466 default:
1467 case 4:
1468 ret = ldl_kernel(addr);
1469 break;
1470 case 8:
1471 ret = ldq_kernel(addr);
1472 break;
1473 }
1474 break;
1475 case 0xc: /* I-cache tag */
1476 case 0xd: /* I-cache data */
1477 case 0xe: /* D-cache tag */
1478 case 0xf: /* D-cache data */
1479 break;
1480 case 0x20: /* MMU passthrough */
1481 switch(size) {
1482 case 1:
1483 ret = ldub_phys(addr);
1484 break;
1485 case 2:
1486 ret = lduw_phys(addr);
1487 break;
1488 default:
1489 case 4:
1490 ret = ldl_phys(addr);
1491 break;
1492 case 8:
1493 ret = ldq_phys(addr);
1494 break;
1495 }
1496 break;
1497 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1498 switch(size) {
1499 case 1:
1500 ret = ldub_phys((target_phys_addr_t)addr
1501 | ((target_phys_addr_t)(asi & 0xf) << 32));
1502 break;
1503 case 2:
1504 ret = lduw_phys((target_phys_addr_t)addr
1505 | ((target_phys_addr_t)(asi & 0xf) << 32));
1506 break;
1507 default:
1508 case 4:
1509 ret = ldl_phys((target_phys_addr_t)addr
1510 | ((target_phys_addr_t)(asi & 0xf) << 32));
1511 break;
1512 case 8:
1513 ret = ldq_phys((target_phys_addr_t)addr
1514 | ((target_phys_addr_t)(asi & 0xf) << 32));
1515 break;
1516 }
1517 break;
1518 case 0x30: // Turbosparc secondary cache diagnostic
1519 case 0x31: // Turbosparc RAM snoop
1520 case 0x32: // Turbosparc page table descriptor diagnostic
1521 case 0x39: /* data cache diagnostic register */
1522 ret = 0;
1523 break;
1524 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
1525 {
1526 int reg = (addr >> 8) & 3;
1527
1528 switch(reg) {
1529 case 0: /* Breakpoint Value (Addr) */
1530 ret = env->mmubpregs[reg];
1531 break;
1532 case 1: /* Breakpoint Mask */
1533 ret = env->mmubpregs[reg];
1534 break;
1535 case 2: /* Breakpoint Control */
1536 ret = env->mmubpregs[reg];
1537 break;
1538 case 3: /* Breakpoint Status */
1539 ret = env->mmubpregs[reg];
1540 env->mmubpregs[reg] = 0ULL;
1541 break;
1542 }
1543 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
1544 ret);
1545 }
1546 break;
1547 case 8: /* User code access, XXX */
1548 default:
1549 do_unassigned_access(addr, 0, 0, asi, size);
1550 ret = 0;
1551 break;
1552 }
1553 if (sign) {
1554 switch(size) {
1555 case 1:
1556 ret = (int8_t) ret;
1557 break;
1558 case 2:
1559 ret = (int16_t) ret;
1560 break;
1561 case 4:
1562 ret = (int32_t) ret;
1563 break;
1564 default:
1565 break;
1566 }
1567 }
1568 #ifdef DEBUG_ASI
1569 dump_asi("read ", last_addr, asi, size, ret);
1570 #endif
1571 return ret;
1572 }
1573
1574 void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
1575 {
1576 helper_check_align(addr, size - 1);
1577 switch(asi) {
1578 case 2: /* SuperSparc MXCC registers */
1579 switch (addr) {
1580 case 0x01c00000: /* MXCC stream data register 0 */
1581 if (size == 8)
1582 env->mxccdata[0] = val;
1583 else
1584 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1585 size);
1586 break;
1587 case 0x01c00008: /* MXCC stream data register 1 */
1588 if (size == 8)
1589 env->mxccdata[1] = val;
1590 else
1591 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1592 size);
1593 break;
1594 case 0x01c00010: /* MXCC stream data register 2 */
1595 if (size == 8)
1596 env->mxccdata[2] = val;
1597 else
1598 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1599 size);
1600 break;
1601 case 0x01c00018: /* MXCC stream data register 3 */
1602 if (size == 8)
1603 env->mxccdata[3] = val;
1604 else
1605 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1606 size);
1607 break;
1608 case 0x01c00100: /* MXCC stream source */
1609 if (size == 8)
1610 env->mxccregs[0] = val;
1611 else
1612 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1613 size);
1614 env->mxccdata[0] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1615 0);
1616 env->mxccdata[1] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1617 8);
1618 env->mxccdata[2] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1619 16);
1620 env->mxccdata[3] = ldq_phys((env->mxccregs[0] & 0xffffffffULL) +
1621 24);
1622 break;
1623 case 0x01c00200: /* MXCC stream destination */
1624 if (size == 8)
1625 env->mxccregs[1] = val;
1626 else
1627 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1628 size);
1629 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 0,
1630 env->mxccdata[0]);
1631 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 8,
1632 env->mxccdata[1]);
1633 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 16,
1634 env->mxccdata[2]);
1635 stq_phys((env->mxccregs[1] & 0xffffffffULL) + 24,
1636 env->mxccdata[3]);
1637 break;
1638 case 0x01c00a00: /* MXCC control register */
1639 if (size == 8)
1640 env->mxccregs[3] = val;
1641 else
1642 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1643 size);
1644 break;
1645 case 0x01c00a04: /* MXCC control register */
1646 if (size == 4)
1647 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
1648 | val;
1649 else
1650 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1651 size);
1652 break;
1653 case 0x01c00e00: /* MXCC error register */
1654 // writing a 1 bit clears the error
1655 if (size == 8)
1656 env->mxccregs[6] &= ~val;
1657 else
1658 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1659 size);
1660 break;
1661 case 0x01c00f00: /* MBus port address register */
1662 if (size == 8)
1663 env->mxccregs[7] = val;
1664 else
1665 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", addr,
1666 size);
1667 break;
1668 default:
1669 DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", addr,
1670 size);
1671 break;
1672 }
1673 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
1674 asi, size, addr, val);
1675 #ifdef DEBUG_MXCC
1676 dump_mxcc(env);
1677 #endif
1678 break;
1679 case 3: /* MMU flush */
1680 {
1681 int mmulev;
1682
1683 mmulev = (addr >> 8) & 15;
1684 DPRINTF_MMU("mmu flush level %d\n", mmulev);
1685 switch (mmulev) {
1686 case 0: // flush page
1687 tlb_flush_page(env, addr & 0xfffff000);
1688 break;
1689 case 1: // flush segment (256k)
1690 case 2: // flush region (16M)
1691 case 3: // flush context (4G)
1692 case 4: // flush entire
1693 tlb_flush(env, 1);
1694 break;
1695 default:
1696 break;
1697 }
1698 #ifdef DEBUG_MMU
1699 dump_mmu(env);
1700 #endif
1701 }
1702 break;
1703 case 4: /* write MMU regs */
1704 {
1705 int reg = (addr >> 8) & 0x1f;
1706 uint32_t oldreg;
1707
1708 oldreg = env->mmuregs[reg];
1709 switch(reg) {
1710 case 0: // Control Register
1711 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
1712 (val & 0x00ffffff);
1713 // Mappings generated during no-fault mode or MMU
1714 // disabled mode are invalid in normal mode
1715 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
1716 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm)))
1717 tlb_flush(env, 1);
1718 break;
1719 case 1: // Context Table Pointer Register
1720 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
1721 break;
1722 case 2: // Context Register
1723 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
1724 if (oldreg != env->mmuregs[reg]) {
1725 /* we flush when the MMU context changes because
1726 QEMU has no MMU context support */
1727 tlb_flush(env, 1);
1728 }
1729 break;
1730 case 3: // Synchronous Fault Status Register with Clear
1731 case 4: // Synchronous Fault Address Register
1732 break;
1733 case 0x10: // TLB Replacement Control Register
1734 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
1735 break;
1736 case 0x13: // Synchronous Fault Status Register with Read and Clear
1737 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
1738 break;
1739 case 0x14: // Synchronous Fault Address Register
1740 env->mmuregs[4] = val;
1741 break;
1742 default:
1743 env->mmuregs[reg] = val;
1744 break;
1745 }
1746 if (oldreg != env->mmuregs[reg]) {
1747 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
1748 reg, oldreg, env->mmuregs[reg]);
1749 }
1750 #ifdef DEBUG_MMU
1751 dump_mmu(env);
1752 #endif
1753 }
1754 break;
1755 case 5: // Turbosparc ITLB Diagnostic
1756 case 6: // Turbosparc DTLB Diagnostic
1757 case 7: // Turbosparc IOTLB Diagnostic
1758 break;
1759 case 0xa: /* User data access */
1760 switch(size) {
1761 case 1:
1762 stb_user(addr, val);
1763 break;
1764 case 2:
1765 stw_user(addr, val);
1766 break;
1767 default:
1768 case 4:
1769 stl_user(addr, val);
1770 break;
1771 case 8:
1772 stq_user(addr, val);
1773 break;
1774 }
1775 break;
1776 case 0xb: /* Supervisor data access */
1777 switch(size) {
1778 case 1:
1779 stb_kernel(addr, val);
1780 break;
1781 case 2:
1782 stw_kernel(addr, val);
1783 break;
1784 default:
1785 case 4:
1786 stl_kernel(addr, val);
1787 break;
1788 case 8:
1789 stq_kernel(addr, val);
1790 break;
1791 }
1792 break;
1793 case 0xc: /* I-cache tag */
1794 case 0xd: /* I-cache data */
1795 case 0xe: /* D-cache tag */
1796 case 0xf: /* D-cache data */
1797 case 0x10: /* I/D-cache flush page */
1798 case 0x11: /* I/D-cache flush segment */
1799 case 0x12: /* I/D-cache flush region */
1800 case 0x13: /* I/D-cache flush context */
1801 case 0x14: /* I/D-cache flush user */
1802 break;
1803 case 0x17: /* Block copy, sta access */
1804 {
1805 // val = src
1806 // addr = dst
1807 // copy 32 bytes
1808 unsigned int i;
1809 uint32_t src = val & ~3, dst = addr & ~3, temp;
1810
1811 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
1812 temp = ldl_kernel(src);
1813 stl_kernel(dst, temp);
1814 }
1815 }
1816 break;
1817 case 0x1f: /* Block fill, stda access */
1818 {
1819 // addr = dst
1820 // fill 32 bytes with val
1821 unsigned int i;
1822 uint32_t dst = addr & 7;
1823
1824 for (i = 0; i < 32; i += 8, dst += 8)
1825 stq_kernel(dst, val);
1826 }
1827 break;
1828 case 0x20: /* MMU passthrough */
1829 {
1830 switch(size) {
1831 case 1:
1832 stb_phys(addr, val);
1833 break;
1834 case 2:
1835 stw_phys(addr, val);
1836 break;
1837 case 4:
1838 default:
1839 stl_phys(addr, val);
1840 break;
1841 case 8:
1842 stq_phys(addr, val);
1843 break;
1844 }
1845 }
1846 break;
1847 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1848 {
1849 switch(size) {
1850 case 1:
1851 stb_phys((target_phys_addr_t)addr
1852 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1853 break;
1854 case 2:
1855 stw_phys((target_phys_addr_t)addr
1856 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1857 break;
1858 case 4:
1859 default:
1860 stl_phys((target_phys_addr_t)addr
1861 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1862 break;
1863 case 8:
1864 stq_phys((target_phys_addr_t)addr
1865 | ((target_phys_addr_t)(asi & 0xf) << 32), val);
1866 break;
1867 }
1868 }
1869 break;
1870 case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic
1871 case 0x31: // store buffer data, Ross RT620 I-cache flush or
1872 // Turbosparc snoop RAM
1873 case 0x32: // store buffer control or Turbosparc page table
1874 // descriptor diagnostic
1875 case 0x36: /* I-cache flash clear */
1876 case 0x37: /* D-cache flash clear */
1877 case 0x4c: /* breakpoint action */
1878 break;
1879 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1880 {
1881 int reg = (addr >> 8) & 3;
1882
1883 switch(reg) {
1884 case 0: /* Breakpoint Value (Addr) */
1885 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1886 break;
1887 case 1: /* Breakpoint Mask */
1888 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1889 break;
1890 case 2: /* Breakpoint Control */
1891 env->mmubpregs[reg] = (val & 0x7fULL);
1892 break;
1893 case 3: /* Breakpoint Status */
1894 env->mmubpregs[reg] = (val & 0xfULL);
1895 break;
1896 }
1897 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1898 env->mmuregs[reg]);
1899 }
1900 break;
1901 case 8: /* User code access, XXX */
1902 case 9: /* Supervisor code access, XXX */
1903 default:
1904 do_unassigned_access(addr, 1, 0, asi, size);
1905 break;
1906 }
1907 #ifdef DEBUG_ASI
1908 dump_asi("write", addr, asi, size, val);
1909 #endif
1910 }
1911
1912 #endif /* CONFIG_USER_ONLY */
1913 #else /* TARGET_SPARC64 */
1914
1915 #ifdef CONFIG_USER_ONLY
1916 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
1917 {
1918 uint64_t ret = 0;
1919 #if defined(DEBUG_ASI)
1920 target_ulong last_addr = addr;
1921 #endif
1922
1923 if (asi < 0x80)
1924 raise_exception(TT_PRIV_ACT);
1925
1926 helper_check_align(addr, size - 1);
1927 addr = address_mask(env, addr);
1928
1929 switch (asi) {
1930 case 0x82: // Primary no-fault
1931 case 0x8a: // Primary no-fault LE
1932 if (page_check_range(addr, size, PAGE_READ) == -1) {
1933 #ifdef DEBUG_ASI
1934 dump_asi("read ", last_addr, asi, size, ret);
1935 #endif
1936 return 0;
1937 }
1938 // Fall through
1939 case 0x80: // Primary
1940 case 0x88: // Primary LE
1941 {
1942 switch(size) {
1943 case 1:
1944 ret = ldub_raw(addr);
1945 break;
1946 case 2:
1947 ret = lduw_raw(addr);
1948 break;
1949 case 4:
1950 ret = ldl_raw(addr);
1951 break;
1952 default:
1953 case 8:
1954 ret = ldq_raw(addr);
1955 break;
1956 }
1957 }
1958 break;
1959 case 0x83: // Secondary no-fault
1960 case 0x8b: // Secondary no-fault LE
1961 if (page_check_range(addr, size, PAGE_READ) == -1) {
1962 #ifdef DEBUG_ASI
1963 dump_asi("read ", last_addr, asi, size, ret);
1964 #endif
1965 return 0;
1966 }
1967 // Fall through
1968 case 0x81: // Secondary
1969 case 0x89: // Secondary LE
1970 // XXX
1971 break;
1972 default:
1973 break;
1974 }
1975
1976 /* Convert from little endian */
1977 switch (asi) {
1978 case 0x88: // Primary LE
1979 case 0x89: // Secondary LE
1980 case 0x8a: // Primary no-fault LE
1981 case 0x8b: // Secondary no-fault LE
1982 switch(size) {
1983 case 2:
1984 ret = bswap16(ret);
1985 break;
1986 case 4:
1987 ret = bswap32(ret);
1988 break;
1989 case 8:
1990 ret = bswap64(ret);
1991 break;
1992 default:
1993 break;
1994 }
1995 default:
1996 break;
1997 }
1998
1999 /* Convert to signed number */
2000 if (sign) {
2001 switch(size) {
2002 case 1:
2003 ret = (int8_t) ret;
2004 break;
2005 case 2:
2006 ret = (int16_t) ret;
2007 break;
2008 case 4:
2009 ret = (int32_t) ret;
2010 break;
2011 default:
2012 break;
2013 }
2014 }
2015 #ifdef DEBUG_ASI
2016 dump_asi("read ", last_addr, asi, size, ret);
2017 #endif
2018 return ret;
2019 }
2020
2021 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2022 {
2023 #ifdef DEBUG_ASI
2024 dump_asi("write", addr, asi, size, val);
2025 #endif
2026 if (asi < 0x80)
2027 raise_exception(TT_PRIV_ACT);
2028
2029 helper_check_align(addr, size - 1);
2030 addr = address_mask(env, addr);
2031
2032 /* Convert to little endian */
2033 switch (asi) {
2034 case 0x88: // Primary LE
2035 case 0x89: // Secondary LE
2036 switch(size) {
2037 case 2:
2038 val = bswap16(val);
2039 break;
2040 case 4:
2041 val = bswap32(val);
2042 break;
2043 case 8:
2044 val = bswap64(val);
2045 break;
2046 default:
2047 break;
2048 }
2049 default:
2050 break;
2051 }
2052
2053 switch(asi) {
2054 case 0x80: // Primary
2055 case 0x88: // Primary LE
2056 {
2057 switch(size) {
2058 case 1:
2059 stb_raw(addr, val);
2060 break;
2061 case 2:
2062 stw_raw(addr, val);
2063 break;
2064 case 4:
2065 stl_raw(addr, val);
2066 break;
2067 case 8:
2068 default:
2069 stq_raw(addr, val);
2070 break;
2071 }
2072 }
2073 break;
2074 case 0x81: // Secondary
2075 case 0x89: // Secondary LE
2076 // XXX
2077 return;
2078
2079 case 0x82: // Primary no-fault, RO
2080 case 0x83: // Secondary no-fault, RO
2081 case 0x8a: // Primary no-fault LE, RO
2082 case 0x8b: // Secondary no-fault LE, RO
2083 default:
2084 do_unassigned_access(addr, 1, 0, 1, size);
2085 return;
2086 }
2087 }
2088
2089 #else /* CONFIG_USER_ONLY */
2090
2091 uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
2092 {
2093 uint64_t ret = 0;
2094 #if defined(DEBUG_ASI)
2095 target_ulong last_addr = addr;
2096 #endif
2097
2098 asi &= 0xff;
2099
2100 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2101 || ((env->def->features & CPU_FEATURE_HYPV)
2102 && asi >= 0x30 && asi < 0x80
2103 && !(env->hpstate & HS_PRIV)))
2104 raise_exception(TT_PRIV_ACT);
2105
2106 helper_check_align(addr, size - 1);
2107 switch (asi) {
2108 case 0x82: // Primary no-fault
2109 case 0x8a: // Primary no-fault LE
2110 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
2111 #ifdef DEBUG_ASI
2112 dump_asi("read ", last_addr, asi, size, ret);
2113 #endif
2114 return 0;
2115 }
2116 // Fall through
2117 case 0x10: // As if user primary
2118 case 0x18: // As if user primary LE
2119 case 0x80: // Primary
2120 case 0x88: // Primary LE
2121 case 0xe2: // UA2007 Primary block init
2122 case 0xe3: // UA2007 Secondary block init
2123 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2124 if ((env->def->features & CPU_FEATURE_HYPV)
2125 && env->hpstate & HS_PRIV) {
2126 switch(size) {
2127 case 1:
2128 ret = ldub_hypv(addr);
2129 break;
2130 case 2:
2131 ret = lduw_hypv(addr);
2132 break;
2133 case 4:
2134 ret = ldl_hypv(addr);
2135 break;
2136 default:
2137 case 8:
2138 ret = ldq_hypv(addr);
2139 break;
2140 }
2141 } else {
2142 switch(size) {
2143 case 1:
2144 ret = ldub_kernel(addr);
2145 break;
2146 case 2:
2147 ret = lduw_kernel(addr);
2148 break;
2149 case 4:
2150 ret = ldl_kernel(addr);
2151 break;
2152 default:
2153 case 8:
2154 ret = ldq_kernel(addr);
2155 break;
2156 }
2157 }
2158 } else {
2159 switch(size) {
2160 case 1:
2161 ret = ldub_user(addr);
2162 break;
2163 case 2:
2164 ret = lduw_user(addr);
2165 break;
2166 case 4:
2167 ret = ldl_user(addr);
2168 break;
2169 default:
2170 case 8:
2171 ret = ldq_user(addr);
2172 break;
2173 }
2174 }
2175 break;
2176 case 0x14: // Bypass
2177 case 0x15: // Bypass, non-cacheable
2178 case 0x1c: // Bypass LE
2179 case 0x1d: // Bypass, non-cacheable LE
2180 {
2181 switch(size) {
2182 case 1:
2183 ret = ldub_phys(addr);
2184 break;
2185 case 2:
2186 ret = lduw_phys(addr);
2187 break;
2188 case 4:
2189 ret = ldl_phys(addr);
2190 break;
2191 default:
2192 case 8:
2193 ret = ldq_phys(addr);
2194 break;
2195 }
2196 break;
2197 }
2198 case 0x24: // Nucleus quad LDD 128 bit atomic
2199 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2200 // Only ldda allowed
2201 raise_exception(TT_ILL_INSN);
2202 return 0;
2203 case 0x83: // Secondary no-fault
2204 case 0x8b: // Secondary no-fault LE
2205 if (cpu_get_phys_page_debug(env, addr) == -1ULL) {
2206 #ifdef DEBUG_ASI
2207 dump_asi("read ", last_addr, asi, size, ret);
2208 #endif
2209 return 0;
2210 }
2211 // Fall through
2212 case 0x04: // Nucleus
2213 case 0x0c: // Nucleus Little Endian (LE)
2214 case 0x11: // As if user secondary
2215 case 0x19: // As if user secondary LE
2216 case 0x4a: // UPA config
2217 case 0x81: // Secondary
2218 case 0x89: // Secondary LE
2219 // XXX
2220 break;
2221 case 0x45: // LSU
2222 ret = env->lsu;
2223 break;
2224 case 0x50: // I-MMU regs
2225 {
2226 int reg = (addr >> 3) & 0xf;
2227
2228 if (reg == 0) {
2229 // I-TSB Tag Target register
2230 ret = ultrasparc_tag_target(env->immu.tag_access);
2231 } else {
2232 ret = env->immuregs[reg];
2233 }
2234
2235 break;
2236 }
2237 case 0x51: // I-MMU 8k TSB pointer
2238 {
2239 // env->immuregs[5] holds I-MMU TSB register value
2240 // env->immuregs[6] holds I-MMU Tag Access register value
2241 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
2242 8*1024);
2243 break;
2244 }
2245 case 0x52: // I-MMU 64k TSB pointer
2246 {
2247 // env->immuregs[5] holds I-MMU TSB register value
2248 // env->immuregs[6] holds I-MMU Tag Access register value
2249 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
2250 64*1024);
2251 break;
2252 }
2253 case 0x55: // I-MMU data access
2254 {
2255 int reg = (addr >> 3) & 0x3f;
2256
2257 ret = env->itlb[reg].tte;
2258 break;
2259 }
2260 case 0x56: // I-MMU tag read
2261 {
2262 int reg = (addr >> 3) & 0x3f;
2263
2264 ret = env->itlb[reg].tag;
2265 break;
2266 }
2267 case 0x58: // D-MMU regs
2268 {
2269 int reg = (addr >> 3) & 0xf;
2270
2271 if (reg == 0) {
2272 // D-TSB Tag Target register
2273 ret = ultrasparc_tag_target(env->dmmu.tag_access);
2274 } else {
2275 ret = env->dmmuregs[reg];
2276 }
2277 break;
2278 }
2279 case 0x59: // D-MMU 8k TSB pointer
2280 {
2281 // env->dmmuregs[5] holds D-MMU TSB register value
2282 // env->dmmuregs[6] holds D-MMU Tag Access register value
2283 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
2284 8*1024);
2285 break;
2286 }
2287 case 0x5a: // D-MMU 64k TSB pointer
2288 {
2289 // env->dmmuregs[5] holds D-MMU TSB register value
2290 // env->dmmuregs[6] holds D-MMU Tag Access register value
2291 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
2292 64*1024);
2293 break;
2294 }
2295 case 0x5d: // D-MMU data access
2296 {
2297 int reg = (addr >> 3) & 0x3f;
2298
2299 ret = env->dtlb[reg].tte;
2300 break;
2301 }
2302 case 0x5e: // D-MMU tag read
2303 {
2304 int reg = (addr >> 3) & 0x3f;
2305
2306 ret = env->dtlb[reg].tag;
2307 break;
2308 }
2309 case 0x46: // D-cache data
2310 case 0x47: // D-cache tag access
2311 case 0x4b: // E-cache error enable
2312 case 0x4c: // E-cache asynchronous fault status
2313 case 0x4d: // E-cache asynchronous fault address
2314 case 0x4e: // E-cache tag data
2315 case 0x66: // I-cache instruction access
2316 case 0x67: // I-cache tag access
2317 case 0x6e: // I-cache predecode
2318 case 0x6f: // I-cache LRU etc.
2319 case 0x76: // E-cache tag
2320 case 0x7e: // E-cache tag
2321 break;
2322 case 0x5b: // D-MMU data pointer
2323 case 0x48: // Interrupt dispatch, RO
2324 case 0x49: // Interrupt data receive
2325 case 0x7f: // Incoming interrupt vector, RO
2326 // XXX
2327 break;
2328 case 0x54: // I-MMU data in, WO
2329 case 0x57: // I-MMU demap, WO
2330 case 0x5c: // D-MMU data in, WO
2331 case 0x5f: // D-MMU demap, WO
2332 case 0x77: // Interrupt vector, WO
2333 default:
2334 do_unassigned_access(addr, 0, 0, 1, size);
2335 ret = 0;
2336 break;
2337 }
2338
2339 /* Convert from little endian */
2340 switch (asi) {
2341 case 0x0c: // Nucleus Little Endian (LE)
2342 case 0x18: // As if user primary LE
2343 case 0x19: // As if user secondary LE
2344 case 0x1c: // Bypass LE
2345 case 0x1d: // Bypass, non-cacheable LE
2346 case 0x88: // Primary LE
2347 case 0x89: // Secondary LE
2348 case 0x8a: // Primary no-fault LE
2349 case 0x8b: // Secondary no-fault LE
2350 switch(size) {
2351 case 2:
2352 ret = bswap16(ret);
2353 break;
2354 case 4:
2355 ret = bswap32(ret);
2356 break;
2357 case 8:
2358 ret = bswap64(ret);
2359 break;
2360 default:
2361 break;
2362 }
2363 default:
2364 break;
2365 }
2366
2367 /* Convert to signed number */
2368 if (sign) {
2369 switch(size) {
2370 case 1:
2371 ret = (int8_t) ret;
2372 break;
2373 case 2:
2374 ret = (int16_t) ret;
2375 break;
2376 case 4:
2377 ret = (int32_t) ret;
2378 break;
2379 default:
2380 break;
2381 }
2382 }
2383 #ifdef DEBUG_ASI
2384 dump_asi("read ", last_addr, asi, size, ret);
2385 #endif
2386 return ret;
2387 }
2388
2389 void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
2390 {
2391 #ifdef DEBUG_ASI
2392 dump_asi("write", addr, asi, size, val);
2393 #endif
2394
2395 asi &= 0xff;
2396
2397 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2398 || ((env->def->features & CPU_FEATURE_HYPV)
2399 && asi >= 0x30 && asi < 0x80
2400 && !(env->hpstate & HS_PRIV)))
2401 raise_exception(TT_PRIV_ACT);
2402
2403 helper_check_align(addr, size - 1);
2404 /* Convert to little endian */
2405 switch (asi) {
2406 case 0x0c: // Nucleus Little Endian (LE)
2407 case 0x18: // As if user primary LE
2408 case 0x19: // As if user secondary LE
2409 case 0x1c: // Bypass LE
2410 case 0x1d: // Bypass, non-cacheable LE
2411 case 0x88: // Primary LE
2412 case 0x89: // Secondary LE
2413 switch(size) {
2414 case 2:
2415 val = bswap16(val);
2416 break;
2417 case 4:
2418 val = bswap32(val);
2419 break;
2420 case 8:
2421 val = bswap64(val);
2422 break;
2423 default:
2424 break;
2425 }
2426 default:
2427 break;
2428 }
2429
2430 switch(asi) {
2431 case 0x10: // As if user primary
2432 case 0x18: // As if user primary LE
2433 case 0x80: // Primary
2434 case 0x88: // Primary LE
2435 case 0xe2: // UA2007 Primary block init
2436 case 0xe3: // UA2007 Secondary block init
2437 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
2438 if ((env->def->features & CPU_FEATURE_HYPV)
2439 && env->hpstate & HS_PRIV) {
2440 switch(size) {
2441 case 1:
2442 stb_hypv(addr, val);
2443 break;
2444 case 2:
2445 stw_hypv(addr, val);
2446 break;
2447 case 4:
2448 stl_hypv(addr, val);
2449 break;
2450 case 8:
2451 default:
2452 stq_hypv(addr, val);
2453 break;
2454 }
2455 } else {
2456 switch(size) {
2457 case 1:
2458 stb_kernel(addr, val);
2459 break;
2460 case 2:
2461 stw_kernel(addr, val);
2462 break;
2463 case 4:
2464 stl_kernel(addr, val);
2465 break;
2466 case 8:
2467 default:
2468 stq_kernel(addr, val);
2469 break;
2470 }
2471 }
2472 } else {
2473 switch(size) {
2474 case 1:
2475 stb_user(addr, val);
2476 break;
2477 case 2:
2478 stw_user(addr, val);
2479 break;
2480 case 4:
2481 stl_user(addr, val);
2482 break;
2483 case 8:
2484 default:
2485 stq_user(addr, val);
2486 break;
2487 }
2488 }
2489 break;
2490 case 0x14: // Bypass
2491 case 0x15: // Bypass, non-cacheable
2492 case 0x1c: // Bypass LE
2493 case 0x1d: // Bypass, non-cacheable LE
2494 {
2495 switch(size) {
2496 case 1:
2497 stb_phys(addr, val);
2498 break;
2499 case 2:
2500 stw_phys(addr, val);
2501 break;
2502 case 4:
2503 stl_phys(addr, val);
2504 break;
2505 case 8:
2506 default:
2507 stq_phys(addr, val);
2508 break;
2509 }
2510 }
2511 return;
2512 case 0x24: // Nucleus quad LDD 128 bit atomic
2513 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2514 // Only ldda allowed
2515 raise_exception(TT_ILL_INSN);
2516 return;
2517 case 0x04: // Nucleus
2518 case 0x0c: // Nucleus Little Endian (LE)
2519 case 0x11: // As if user secondary
2520 case 0x19: // As if user secondary LE
2521 case 0x4a: // UPA config
2522 case 0x81: // Secondary
2523 case 0x89: // Secondary LE
2524 // XXX
2525 return;
2526 case 0x45: // LSU
2527 {
2528 uint64_t oldreg;
2529
2530 oldreg = env->lsu;
2531 env->lsu = val & (DMMU_E | IMMU_E);
2532 // Mappings generated during D/I MMU disabled mode are
2533 // invalid in normal mode
2534 if (oldreg != env->lsu) {
2535 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
2536 oldreg, env->lsu);
2537 #ifdef DEBUG_MMU
2538 dump_mmu(env);
2539 #endif
2540 tlb_flush(env, 1);
2541 }
2542 return;
2543 }
2544 case 0x50: // I-MMU regs
2545 {
2546 int reg = (addr >> 3) & 0xf;
2547 uint64_t oldreg;
2548
2549 oldreg = env->immuregs[reg];
2550 switch(reg) {
2551 case 0: // RO
2552 return;
2553 case 1: // Not in I-MMU
2554 case 2:
2555 return;
2556 case 3: // SFSR
2557 if ((val & 1) == 0)
2558 val = 0; // Clear SFSR
2559 env->immu.sfsr = val;
2560 break;
2561 case 4: // RO
2562 return;
2563 case 5: // TSB access
2564 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
2565 PRIx64 "\n", env->immu.tsb, val);
2566 env->immu.tsb = val;
2567 break;
2568 case 6: // Tag access
2569 env->immu.tag_access = val;
2570 break;
2571 case 7:
2572 case 8:
2573 return;
2574 default:
2575 break;
2576 }
2577
2578 if (oldreg != env->immuregs[reg]) {
2579 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
2580 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
2581 }
2582 #ifdef DEBUG_MMU
2583 dump_mmu(env);
2584 #endif
2585 return;
2586 }
2587 case 0x54: // I-MMU data in
2588 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
2589 return;
2590 case 0x55: // I-MMU data access
2591 {
2592 // TODO: auto demap
2593
2594 unsigned int i = (addr >> 3) & 0x3f;
2595
2596 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
2597
2598 #ifdef DEBUG_MMU
2599 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
2600 dump_mmu(env);
2601 #endif
2602 return;
2603 }
2604 case 0x57: // I-MMU demap
2605 demap_tlb(env->itlb, val, "immu", env);
2606 return;
2607 case 0x58: // D-MMU regs
2608 {
2609 int reg = (addr >> 3) & 0xf;
2610 uint64_t oldreg;
2611
2612 oldreg = env->dmmuregs[reg];
2613 switch(reg) {
2614 case 0: // RO
2615 case 4:
2616 return;
2617 case 3: // SFSR
2618 if ((val & 1) == 0) {
2619 val = 0; // Clear SFSR, Fault address
2620 env->dmmu.sfar = 0;
2621 }
2622 env->dmmu.sfsr = val;
2623 break;
2624 case 1: // Primary context
2625 env->dmmu.mmu_primary_context = val;
2626 break;
2627 case 2: // Secondary context
2628 env->dmmu.mmu_secondary_context = val;
2629 break;
2630 case 5: // TSB access
2631 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
2632 PRIx64 "\n", env->dmmu.tsb, val);
2633 env->dmmu.tsb = val;
2634 break;
2635 case 6: // Tag access
2636 env->dmmu.tag_access = val;
2637 break;
2638 case 7: // Virtual Watchpoint
2639 case 8: // Physical Watchpoint
2640 default:
2641 env->dmmuregs[reg] = val;
2642 break;
2643 }
2644
2645 if (oldreg != env->dmmuregs[reg]) {
2646 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
2647 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
2648 }
2649 #ifdef DEBUG_MMU
2650 dump_mmu(env);
2651 #endif
2652 return;
2653 }
2654 case 0x5c: // D-MMU data in
2655 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
2656 return;
2657 case 0x5d: // D-MMU data access
2658 {
2659 unsigned int i = (addr >> 3) & 0x3f;
2660
2661 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
2662
2663 #ifdef DEBUG_MMU
2664 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
2665 dump_mmu(env);
2666 #endif
2667 return;
2668 }
2669 case 0x5f: // D-MMU demap
2670 demap_tlb(env->dtlb, val, "dmmu", env);
2671 return;
2672 case 0x49: // Interrupt data receive
2673 // XXX
2674 return;
2675 case 0x46: // D-cache data
2676 case 0x47: // D-cache tag access
2677 case 0x4b: // E-cache error enable
2678 case 0x4c: // E-cache asynchronous fault status
2679 case 0x4d: // E-cache asynchronous fault address
2680 case 0x4e: // E-cache tag data
2681 case 0x66: // I-cache instruction access
2682 case 0x67: // I-cache tag access
2683 case 0x6e: // I-cache predecode
2684 case 0x6f: // I-cache LRU etc.
2685 case 0x76: // E-cache tag
2686 case 0x7e: // E-cache tag
2687 return;
2688 case 0x51: // I-MMU 8k TSB pointer, RO
2689 case 0x52: // I-MMU 64k TSB pointer, RO
2690 case 0x56: // I-MMU tag read, RO
2691 case 0x59: // D-MMU 8k TSB pointer, RO
2692 case 0x5a: // D-MMU 64k TSB pointer, RO
2693 case 0x5b: // D-MMU data pointer, RO
2694 case 0x5e: // D-MMU tag read, RO
2695 case 0x48: // Interrupt dispatch, RO
2696 case 0x7f: // Incoming interrupt vector, RO
2697 case 0x82: // Primary no-fault, RO
2698 case 0x83: // Secondary no-fault, RO
2699 case 0x8a: // Primary no-fault LE, RO
2700 case 0x8b: // Secondary no-fault LE, RO
2701 default:
2702 do_unassigned_access(addr, 1, 0, 1, size);
2703 return;
2704 }
2705 }
2706 #endif /* CONFIG_USER_ONLY */
2707
2708 void helper_ldda_asi(target_ulong addr, int asi, int rd)
2709 {
2710 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2711 || ((env->def->features & CPU_FEATURE_HYPV)
2712 && asi >= 0x30 && asi < 0x80
2713 && !(env->hpstate & HS_PRIV)))
2714 raise_exception(TT_PRIV_ACT);
2715
2716 switch (asi) {
2717 case 0x24: // Nucleus quad LDD 128 bit atomic
2718 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
2719 helper_check_align(addr, 0xf);
2720 if (rd == 0) {
2721 env->gregs[1] = ldq_kernel(addr + 8);
2722 if (asi == 0x2c)
2723 bswap64s(&env->gregs[1]);
2724 } else if (rd < 8) {
2725 env->gregs[rd] = ldq_kernel(addr);
2726 env->gregs[rd + 1] = ldq_kernel(addr + 8);
2727 if (asi == 0x2c) {
2728 bswap64s(&env->gregs[rd]);
2729 bswap64s(&env->gregs[rd + 1]);
2730 }
2731 } else {
2732 env->regwptr[rd] = ldq_kernel(addr);
2733 env->regwptr[rd + 1] = ldq_kernel(addr + 8);
2734 if (asi == 0x2c) {
2735 bswap64s(&env->regwptr[rd]);
2736 bswap64s(&env->regwptr[rd + 1]);
2737 }
2738 }
2739 break;
2740 default:
2741 helper_check_align(addr, 0x3);
2742 if (rd == 0)
2743 env->gregs[1] = helper_ld_asi(addr + 4, asi, 4, 0);
2744 else if (rd < 8) {
2745 env->gregs[rd] = helper_ld_asi(addr, asi, 4, 0);
2746 env->gregs[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2747 } else {
2748 env->regwptr[rd] = helper_ld_asi(addr, asi, 4, 0);
2749 env->regwptr[rd + 1] = helper_ld_asi(addr + 4, asi, 4, 0);
2750 }
2751 break;
2752 }
2753 }
2754
2755 void helper_ldf_asi(target_ulong addr, int asi, int size, int rd)
2756 {
2757 unsigned int i;
2758 target_ulong val;
2759
2760 helper_check_align(addr, 3);
2761 switch (asi) {
2762 case 0xf0: // Block load primary
2763 case 0xf1: // Block load secondary
2764 case 0xf8: // Block load primary LE
2765 case 0xf9: // Block load secondary LE
2766 if (rd & 7) {
2767 raise_exception(TT_ILL_INSN);
2768 return;
2769 }
2770 helper_check_align(addr, 0x3f);
2771 for (i = 0; i < 16; i++) {
2772 *(uint32_t *)&env->fpr[rd++] = helper_ld_asi(addr, asi & 0x8f, 4,
2773 0);
2774 addr += 4;
2775 }
2776
2777 return;
2778 default:
2779 break;
2780 }
2781
2782 val = helper_ld_asi(addr, asi, size, 0);
2783 switch(size) {
2784 default:
2785 case 4:
2786 *((uint32_t *)&env->fpr[rd]) = val;
2787 break;
2788 case 8:
2789 *((int64_t *)&DT0) = val;
2790 break;
2791 case 16:
2792 // XXX
2793 break;
2794 }
2795 }
2796
2797 void helper_stf_asi(target_ulong addr, int asi, int size, int rd)
2798 {
2799 unsigned int i;
2800 target_ulong val = 0;
2801
2802 helper_check_align(addr, 3);
2803 switch (asi) {
2804 case 0xe0: // UA2007 Block commit store primary (cache flush)
2805 case 0xe1: // UA2007 Block commit store secondary (cache flush)
2806 case 0xf0: // Block store primary
2807 case 0xf1: // Block store secondary
2808 case 0xf8: // Block store primary LE
2809 case 0xf9: // Block store secondary LE
2810 if (rd & 7) {
2811 raise_exception(TT_ILL_INSN);
2812 return;
2813 }
2814 helper_check_align(addr, 0x3f);
2815 for (i = 0; i < 16; i++) {
2816 val = *(uint32_t *)&env->fpr[rd++];
2817 helper_st_asi(addr, val, asi & 0x8f, 4);
2818 addr += 4;
2819 }
2820
2821 return;
2822 default:
2823 break;
2824 }
2825
2826 switch(size) {
2827 default:
2828 case 4:
2829 val = *((uint32_t *)&env->fpr[rd]);
2830 break;
2831 case 8:
2832 val = *((int64_t *)&DT0);
2833 break;
2834 case 16:
2835 // XXX
2836 break;
2837 }
2838 helper_st_asi(addr, val, asi, size);
2839 }
2840
2841 target_ulong helper_cas_asi(target_ulong addr, target_ulong val1,
2842 target_ulong val2, uint32_t asi)
2843 {
2844 target_ulong ret;
2845
2846 val2 &= 0xffffffffUL;
2847 ret = helper_ld_asi(addr, asi, 4, 0);
2848 ret &= 0xffffffffUL;
2849 if (val2 == ret)
2850 helper_st_asi(addr, val1 & 0xffffffffUL, asi, 4);
2851 return ret;
2852 }
2853
2854 target_ulong helper_casx_asi(target_ulong addr, target_ulong val1,
2855 target_ulong val2, uint32_t asi)
2856 {
2857 target_ulong ret;
2858
2859 ret = helper_ld_asi(addr, asi, 8, 0);
2860 if (val2 == ret)
2861 helper_st_asi(addr, val1, asi, 8);
2862 return ret;
2863 }
2864 #endif /* TARGET_SPARC64 */
2865
2866 #ifndef TARGET_SPARC64
2867 void helper_rett(void)
2868 {
2869 unsigned int cwp;
2870
2871 if (env->psret == 1)
2872 raise_exception(TT_ILL_INSN);
2873
2874 env->psret = 1;
2875 cwp = cpu_cwp_inc(env, env->cwp + 1) ;
2876 if (env->wim & (1 << cwp)) {
2877 raise_exception(TT_WIN_UNF);
2878 }
2879 set_cwp(cwp);
2880 env->psrs = env->psrps;
2881 }
2882 #endif
2883
2884 target_ulong helper_udiv(target_ulong a, target_ulong b)
2885 {
2886 uint64_t x0;
2887 uint32_t x1;
2888
2889 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2890 x1 = b;
2891
2892 if (x1 == 0) {
2893 raise_exception(TT_DIV_ZERO);
2894 }
2895
2896 x0 = x0 / x1;
2897 if (x0 > 0xffffffff) {
2898 env->cc_src2 = 1;
2899 return 0xffffffff;
2900 } else {
2901 env->cc_src2 = 0;
2902 return x0;
2903 }
2904 }
2905
2906 target_ulong helper_sdiv(target_ulong a, target_ulong b)
2907 {
2908 int64_t x0;
2909 int32_t x1;
2910
2911 x0 = (a & 0xffffffff) | ((int64_t) (env->y) << 32);
2912 x1 = b;
2913
2914 if (x1 == 0) {
2915 raise_exception(TT_DIV_ZERO);
2916 }
2917
2918 x0 = x0 / x1;
2919 if ((int32_t) x0 != x0) {
2920 env->cc_src2 = 1;
2921 return x0 < 0? 0x80000000: 0x7fffffff;
2922 } else {
2923 env->cc_src2 = 0;
2924 return x0;
2925 }
2926 }
2927
2928 void helper_stdf(target_ulong addr, int mem_idx)
2929 {
2930 helper_check_align(addr, 7);
2931 #if !defined(CONFIG_USER_ONLY)
2932 switch (mem_idx) {
2933 case 0:
2934 stfq_user(addr, DT0);
2935 break;
2936 case 1:
2937 stfq_kernel(addr, DT0);
2938 break;
2939 #ifdef TARGET_SPARC64
2940 case 2:
2941 stfq_hypv(addr, DT0);
2942 break;
2943 #endif
2944 default:
2945 break;
2946 }
2947 #else
2948 stfq_raw(address_mask(env, addr), DT0);
2949 #endif
2950 }
2951
2952 void helper_lddf(target_ulong addr, int mem_idx)
2953 {
2954 helper_check_align(addr, 7);
2955 #if !defined(CONFIG_USER_ONLY)
2956 switch (mem_idx) {
2957 case 0:
2958 DT0 = ldfq_user(addr);
2959 break;
2960 case 1:
2961 DT0 = ldfq_kernel(addr);
2962 break;
2963 #ifdef TARGET_SPARC64
2964 case 2:
2965 DT0 = ldfq_hypv(addr);
2966 break;
2967 #endif
2968 default:
2969 break;
2970 }
2971 #else
2972 DT0 = ldfq_raw(address_mask(env, addr));
2973 #endif
2974 }
2975
2976 void helper_ldqf(target_ulong addr, int mem_idx)
2977 {
2978 // XXX add 128 bit load
2979 CPU_QuadU u;
2980
2981 helper_check_align(addr, 7);
2982 #if !defined(CONFIG_USER_ONLY)
2983 switch (mem_idx) {
2984 case 0:
2985 u.ll.upper = ldq_user(addr);
2986 u.ll.lower = ldq_user(addr + 8);
2987 QT0 = u.q;
2988 break;
2989 case 1:
2990 u.ll.upper = ldq_kernel(addr);
2991 u.ll.lower = ldq_kernel(addr + 8);
2992 QT0 = u.q;
2993 break;
2994 #ifdef TARGET_SPARC64
2995 case 2:
2996 u.ll.upper = ldq_hypv(addr);
2997 u.ll.lower = ldq_hypv(addr + 8);
2998 QT0 = u.q;
2999 break;
3000 #endif
3001 default:
3002 break;
3003 }
3004 #else
3005 u.ll.upper = ldq_raw(address_mask(env, addr));
3006 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
3007 QT0 = u.q;
3008 #endif
3009 }
3010
3011 void helper_stqf(target_ulong addr, int mem_idx)
3012 {
3013 // XXX add 128 bit store
3014 CPU_QuadU u;
3015
3016 helper_check_align(addr, 7);
3017 #if !defined(CONFIG_USER_ONLY)
3018 switch (mem_idx) {
3019 case 0:
3020 u.q = QT0;
3021 stq_user(addr, u.ll.upper);
3022 stq_user(addr + 8, u.ll.lower);
3023 break;
3024 case 1:
3025 u.q = QT0;
3026 stq_kernel(addr, u.ll.upper);
3027 stq_kernel(addr + 8, u.ll.lower);
3028 break;
3029 #ifdef TARGET_SPARC64
3030 case 2:
3031 u.q = QT0;
3032 stq_hypv(addr, u.ll.upper);
3033 stq_hypv(addr + 8, u.ll.lower);
3034 break;
3035 #endif
3036 default:
3037 break;
3038 }
3039 #else
3040 u.q = QT0;
3041 stq_raw(address_mask(env, addr), u.ll.upper);
3042 stq_raw(address_mask(env, addr + 8), u.ll.lower);
3043 #endif
3044 }
3045
3046 static inline void set_fsr(void)
3047 {
3048 int rnd_mode;
3049
3050 switch (env->fsr & FSR_RD_MASK) {
3051 case FSR_RD_NEAREST:
3052 rnd_mode = float_round_nearest_even;
3053 break;
3054 default:
3055 case FSR_RD_ZERO:
3056 rnd_mode = float_round_to_zero;
3057 break;
3058 case FSR_RD_POS:
3059 rnd_mode = float_round_up;
3060 break;
3061 case FSR_RD_NEG:
3062 rnd_mode = float_round_down;
3063 break;
3064 }
3065 set_float_rounding_mode(rnd_mode, &env->fp_status);
3066 }
3067
3068 void helper_ldfsr(uint32_t new_fsr)
3069 {
3070 env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
3071 set_fsr();
3072 }
3073
3074 #ifdef TARGET_SPARC64
3075 void helper_ldxfsr(uint64_t new_fsr)
3076 {
3077 env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
3078 set_fsr();
3079 }
3080 #endif
3081
3082 void helper_debug(void)
3083 {
3084 env->exception_index = EXCP_DEBUG;
3085 cpu_loop_exit();
3086 }
3087
3088 #ifndef TARGET_SPARC64
3089 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3090 handling ? */
3091 void helper_save(void)
3092 {
3093 uint32_t cwp;
3094
3095 cwp = cpu_cwp_dec(env, env->cwp - 1);
3096 if (env->wim & (1 << cwp)) {
3097 raise_exception(TT_WIN_OVF);
3098 }
3099 set_cwp(cwp);
3100 }
3101
3102 void helper_restore(void)
3103 {
3104 uint32_t cwp;
3105
3106 cwp = cpu_cwp_inc(env, env->cwp + 1);
3107 if (env->wim & (1 << cwp)) {
3108 raise_exception(TT_WIN_UNF);
3109 }
3110 set_cwp(cwp);
3111 }
3112
3113 void helper_wrpsr(target_ulong new_psr)
3114 {
3115 if ((new_psr & PSR_CWP) >= env->nwindows)
3116 raise_exception(TT_ILL_INSN);
3117 else
3118 PUT_PSR(env, new_psr);
3119 }
3120
3121 target_ulong helper_rdpsr(void)
3122 {
3123 return GET_PSR(env);
3124 }
3125
3126 #else
3127 /* XXX: use another pointer for %iN registers to avoid slow wrapping
3128 handling ? */
3129 void helper_save(void)
3130 {
3131 uint32_t cwp;
3132
3133 cwp = cpu_cwp_dec(env, env->cwp - 1);
3134 if (env->cansave == 0) {
3135 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3136 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3137 ((env->wstate & 0x7) << 2)));
3138 } else {
3139 if (env->cleanwin - env->canrestore == 0) {
3140 // XXX Clean windows without trap
3141 raise_exception(TT_CLRWIN);
3142 } else {
3143 env->cansave--;
3144 env->canrestore++;
3145 set_cwp(cwp);
3146 }
3147 }
3148 }
3149
3150 void helper_restore(void)
3151 {
3152 uint32_t cwp;
3153
3154 cwp = cpu_cwp_inc(env, env->cwp + 1);
3155 if (env->canrestore == 0) {
3156 raise_exception(TT_FILL | (env->otherwin != 0 ?
3157 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3158 ((env->wstate & 0x7) << 2)));
3159 } else {
3160 env->cansave++;
3161 env->canrestore--;
3162 set_cwp(cwp);
3163 }
3164 }
3165
3166 void helper_flushw(void)
3167 {
3168 if (env->cansave != env->nwindows - 2) {
3169 raise_exception(TT_SPILL | (env->otherwin != 0 ?
3170 (TT_WOTHER | ((env->wstate & 0x38) >> 1)):
3171 ((env->wstate & 0x7) << 2)));
3172 }
3173 }
3174
3175 void helper_saved(void)
3176 {
3177 env->cansave++;
3178 if (env->otherwin == 0)
3179 env->canrestore--;
3180 else
3181 env->otherwin--;
3182 }
3183
3184 void helper_restored(void)
3185 {
3186 env->canrestore++;
3187 if (env->cleanwin < env->nwindows - 1)
3188 env->cleanwin++;
3189 if (env->otherwin == 0)
3190 env->cansave--;
3191 else
3192 env->otherwin--;
3193 }
3194
3195 target_ulong helper_rdccr(void)
3196 {
3197 return GET_CCR(env);
3198 }
3199
3200 void helper_wrccr(target_ulong new_ccr)
3201 {
3202 PUT_CCR(env, new_ccr);
3203 }
3204
3205 // CWP handling is reversed in V9, but we still use the V8 register
3206 // order.
3207 target_ulong helper_rdcwp(void)
3208 {
3209 return GET_CWP64(env);
3210 }
3211
3212 void helper_wrcwp(target_ulong new_cwp)
3213 {
3214 PUT_CWP64(env, new_cwp);
3215 }
3216
3217 // This function uses non-native bit order
3218 #define GET_FIELD(X, FROM, TO) \
3219 ((X) >> (63 - (TO)) & ((1ULL << ((TO) - (FROM) + 1)) - 1))
3220
3221 // This function uses the order in the manuals, i.e. bit 0 is 2^0
3222 #define GET_FIELD_SP(X, FROM, TO) \
3223 GET_FIELD(X, 63 - (TO), 63 - (FROM))
3224
3225 target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
3226 {
3227 return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
3228 (GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
3229 (GET_FIELD_SP(pixel_addr, 17 + cubesize - 1, 17) << 17) |
3230 (GET_FIELD_SP(pixel_addr, 56, 59) << 13) |
3231 (GET_FIELD_SP(pixel_addr, 35, 38) << 9) |
3232 (GET_FIELD_SP(pixel_addr, 13, 16) << 5) |
3233 (((pixel_addr >> 55) & 1) << 4) |
3234 (GET_FIELD_SP(pixel_addr, 33, 34) << 2) |
3235 GET_FIELD_SP(pixel_addr, 11, 12);
3236 }
3237
3238 target_ulong helper_alignaddr(target_ulong addr, target_ulong offset)
3239 {
3240 uint64_t tmp;
3241
3242 tmp = addr + offset;
3243 env->gsr &= ~7ULL;
3244 env->gsr |= tmp & 7ULL;
3245 return tmp & ~7ULL;
3246 }
3247
3248 target_ulong helper_popc(target_ulong val)
3249 {
3250 return ctpop64(val);
3251 }
3252
3253 static inline uint64_t *get_gregset(uint32_t pstate)
3254 {
3255 switch (pstate) {
3256 default:
3257 DPRINTF_PSTATE("ERROR in get_gregset: active pstate bits=%x%s%s%s\n",
3258 pstate,
3259 (pstate & PS_IG) ? " IG" : "",
3260 (pstate & PS_MG) ? " MG" : "",
3261 (pstate & PS_AG) ? " AG" : "");
3262 /* pass through to normal set of global registers */
3263 case 0:
3264 return env->bgregs;
3265 case PS_AG:
3266 return env->agregs;
3267 case PS_MG:
3268 return env->mgregs;
3269 case PS_IG:
3270 return env->igregs;
3271 }
3272 }
3273
3274 static inline void change_pstate(uint32_t new_pstate)
3275 {
3276 uint32_t pstate_regs, new_pstate_regs;
3277 uint64_t *src, *dst;
3278
3279 if (env->def->features & CPU_FEATURE_GL) {
3280 // PS_AG is not implemented in this case
3281 new_pstate &= ~PS_AG;
3282 }
3283
3284 pstate_regs = env->pstate & 0xc01;
3285 new_pstate_regs = new_pstate & 0xc01;
3286
3287 if (new_pstate_regs != pstate_regs) {
3288 DPRINTF_PSTATE("change_pstate: switching regs old=%x new=%x\n",
3289 pstate_regs, new_pstate_regs);
3290 // Switch global register bank
3291 src = get_gregset(new_pstate_regs);
3292 dst = get_gregset(pstate_regs);
3293 memcpy32(dst, env->gregs);
3294 memcpy32(env->gregs, src);
3295 }
3296 else {
3297 DPRINTF_PSTATE("change_pstate: regs new=%x (unchanged)\n",
3298 new_pstate_regs);
3299 }
3300 env->pstate = new_pstate;
3301 }
3302
3303 void helper_wrpstate(target_ulong new_state)
3304 {
3305 change_pstate(new_state & 0xf3f);
3306
3307 #if !defined(CONFIG_USER_ONLY)
3308 if (cpu_interrupts_enabled(env)) {
3309 cpu_check_irqs(env);
3310 }
3311 #endif
3312 }
3313
3314 void helper_wrpil(target_ulong new_pil)
3315 {
3316 #if !defined(CONFIG_USER_ONLY)
3317 DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
3318 env->psrpil, (uint32_t)new_pil);
3319
3320 env->psrpil = new_pil;
3321
3322 if (cpu_interrupts_enabled(env)) {
3323 cpu_check_irqs(env);
3324 }
3325 #endif
3326 }
3327
3328 void helper_done(void)
3329 {
3330 trap_state* tsptr = cpu_tsptr(env);
3331
3332 env->pc = tsptr->tnpc;
3333 env->npc = tsptr->tnpc + 4;
3334 PUT_CCR(env, tsptr->tstate >> 32);
3335 env->asi = (tsptr->tstate >> 24) & 0xff;
3336 change_pstate((tsptr->tstate >> 8) & 0xf3f);
3337 PUT_CWP64(env, tsptr->tstate & 0xff);
3338 env->tl--;
3339
3340 DPRINTF_PSTATE("... helper_done tl=%d\n", env->tl);
3341
3342 #if !defined(CONFIG_USER_ONLY)
3343 if (cpu_interrupts_enabled(env)) {
3344 cpu_check_irqs(env);
3345 }
3346 #endif
3347 }
3348
3349 void helper_retry(void)
3350 {
3351 trap_state* tsptr = cpu_tsptr(env);
3352
3353 env->pc = tsptr->tpc;
3354 env->npc = tsptr->tnpc;
3355 PUT_CCR(env, tsptr->tstate >> 32);
3356 env->asi = (tsptr->tstate >> 24) & 0xff;
3357 change_pstate((tsptr->tstate >> 8) & 0xf3f);
3358 PUT_CWP64(env, tsptr->tstate & 0xff);
3359 env->tl--;
3360
3361 DPRINTF_PSTATE("... helper_retry tl=%d\n", env->tl);
3362
3363 #if !defined(CONFIG_USER_ONLY)
3364 if (cpu_interrupts_enabled(env)) {
3365 cpu_check_irqs(env);
3366 }
3367 #endif
3368 }
3369
3370 static void do_modify_softint(const char* operation, uint32_t value)
3371 {
3372 if (env->softint != value) {
3373 env->softint = value;
3374 DPRINTF_PSTATE(": %s new %08x\n", operation, env->softint);
3375 #if !defined(CONFIG_USER_ONLY)
3376 if (cpu_interrupts_enabled(env)) {
3377 cpu_check_irqs(env);
3378 }
3379 #endif
3380 }
3381 }
3382
3383 void helper_set_softint(uint64_t value)
3384 {
3385 do_modify_softint("helper_set_softint", env->softint | (uint32_t)value);
3386 }
3387
3388 void helper_clear_softint(uint64_t value)
3389 {
3390 do_modify_softint("helper_clear_softint", env->softint & (uint32_t)~value);
3391 }
3392
3393 void helper_write_softint(uint64_t value)
3394 {
3395 do_modify_softint("helper_write_softint", (uint32_t)value);
3396 }
3397 #endif
3398
3399 void helper_flush(target_ulong addr)
3400 {
3401 addr &= ~7;
3402 tb_invalidate_page_range(addr, addr + 8);
3403 }
3404
3405 #ifdef TARGET_SPARC64
3406 #ifdef DEBUG_PCALL
3407 static const char * const excp_names[0x80] = {
3408 [TT_TFAULT] = "Instruction Access Fault",
3409 [TT_TMISS] = "Instruction Access MMU Miss",
3410 [TT_CODE_ACCESS] = "Instruction Access Error",
3411 [TT_ILL_INSN] = "Illegal Instruction",
3412 [TT_PRIV_INSN] = "Privileged Instruction",
3413 [TT_NFPU_INSN] = "FPU Disabled",
3414 [TT_FP_EXCP] = "FPU Exception",
3415 [TT_TOVF] = "Tag Overflow",
3416 [TT_CLRWIN] = "Clean Windows",
3417 [TT_DIV_ZERO] = "Division By Zero",
3418 [TT_DFAULT] = "Data Access Fault",
3419 [TT_DMISS] = "Data Access MMU Miss",
3420 [TT_DATA_ACCESS] = "Data Access Error",
3421 [TT_DPROT] = "Data Protection Error",
3422 [TT_UNALIGNED] = "Unaligned Memory Access",
3423 [TT_PRIV_ACT] = "Privileged Action",
3424 [TT_EXTINT | 0x1] = "External Interrupt 1",
3425 [TT_EXTINT | 0x2] = "External Interrupt 2",
3426 [TT_EXTINT | 0x3] = "External Interrupt 3",
3427 [TT_EXTINT | 0x4] = "External Interrupt 4",
3428 [TT_EXTINT | 0x5] = "External Interrupt 5",
3429 [TT_EXTINT | 0x6] = "External Interrupt 6",
3430 [TT_EXTINT | 0x7] = "External Interrupt 7",
3431 [TT_EXTINT | 0x8] = "External Interrupt 8",
3432 [TT_EXTINT | 0x9] = "External Interrupt 9",
3433 [TT_EXTINT | 0xa] = "External Interrupt 10",
3434 [TT_EXTINT | 0xb] = "External Interrupt 11",
3435 [TT_EXTINT | 0xc] = "External Interrupt 12",
3436 [TT_EXTINT | 0xd] = "External Interrupt 13",
3437 [TT_EXTINT | 0xe] = "External Interrupt 14",
3438 [TT_EXTINT | 0xf] = "External Interrupt 15",
3439 };
3440 #endif
3441
3442 trap_state* cpu_tsptr(CPUState* env)
3443 {
3444 return &env->ts[env->tl & MAXTL_MASK];
3445 }
3446
3447 void do_interrupt(CPUState *env)
3448 {
3449 int intno = env->exception_index;
3450 trap_state* tsptr;
3451
3452 #ifdef DEBUG_PCALL
3453 if (qemu_loglevel_mask(CPU_LOG_INT)) {
3454 static int count;
3455 const char *name;
3456
3457 if (intno < 0 || intno >= 0x180)
3458 name = "Unknown";
3459 else if (intno >= 0x100)
3460 name = "Trap Instruction";
3461 else if (intno >= 0xc0)
3462 name = "Window Fill";
3463 else if (intno >= 0x80)
3464 name = "Window Spill";
3465 else {
3466 name = excp_names[intno];
3467 if (!name)
3468 name = "Unknown";
3469 }
3470
3471 qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
3472 " SP=%016" PRIx64 "\n",
3473 count, name, intno,
3474 env->pc,
3475 env->npc, env->regwptr[6]);
3476 log_cpu_state(env, 0);
3477 #if 0
3478 {
3479 int i;
3480 uint8_t *ptr;
3481
3482 qemu_log(" code=");
3483 ptr = (uint8_t *)env->pc;
3484 for(i = 0; i < 16; i++) {
3485 qemu_log(" %02x", ldub(ptr + i));
3486 }
3487 qemu_log("\n");
3488 }
3489 #endif
3490 count++;
3491 }
3492 #endif
3493 #if !defined(CONFIG_USER_ONLY)
3494 if (env->tl >= env->maxtl) {
3495 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
3496 " Error state", env->exception_index, env->tl, env->maxtl);
3497 return;
3498 }
3499 #endif
3500 if (env->tl < env->maxtl - 1) {
3501 env->tl++;
3502 } else {
3503 env->pstate |= PS_RED;
3504 if (env->tl < env->maxtl)
3505 env->tl++;
3506 }
3507 tsptr = cpu_tsptr(env);
3508
3509 tsptr->tstate = ((uint64_t)GET_CCR(env) << 32) |
3510 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
3511 GET_CWP64(env);
3512 tsptr->tpc = env->pc;
3513 tsptr->tnpc = env->npc;
3514 tsptr->tt = intno;
3515
3516 switch (intno) {
3517 case TT_IVEC:
3518 change_pstate(PS_PEF | PS_PRIV | PS_IG);
3519 break;
3520 case TT_TFAULT:
3521 case TT_DFAULT:
3522 case TT_TMISS ... TT_TMISS + 3:
3523 case TT_DMISS ... TT_DMISS + 3:
3524 case TT_DPROT ... TT_DPROT + 3:
3525 change_pstate(PS_PEF | PS_PRIV | PS_MG);
3526 break;
3527 default:
3528 change_pstate(PS_PEF | PS_PRIV | PS_AG);
3529 break;
3530 }
3531
3532 if (intno == TT_CLRWIN)
3533 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
3534 else if ((intno & 0x1c0) == TT_SPILL)
3535 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
3536 else if ((intno & 0x1c0) == TT_FILL)
3537 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
3538 env->tbr &= ~0x7fffULL;
3539 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
3540 env->pc = env->tbr;
3541 env->npc = env->pc + 4;
3542 env->exception_index = -1;
3543 }
3544 #else
3545 #ifdef DEBUG_PCALL
3546 static const char * const excp_names[0x80] = {
3547 [TT_TFAULT] = "Instruction Access Fault",
3548 [TT_ILL_INSN] = "Illegal Instruction",
3549 [TT_PRIV_INSN] = "Privileged Instruction",
3550 [TT_NFPU_INSN] = "FPU Disabled",
3551 [TT_WIN_OVF] = "Window Overflow",
3552 [TT_WIN_UNF] = "Window Underflow",
3553 [TT_UNALIGNED] = "Unaligned Memory Access",
3554 [TT_FP_EXCP] = "FPU Exception",
3555 [TT_DFAULT] = "Data Access Fault",
3556 [TT_TOVF] = "Tag Overflow",
3557 [TT_EXTINT | 0x1] = "External Interrupt 1",
3558 [TT_EXTINT | 0x2] = "External Interrupt 2",
3559 [TT_EXTINT | 0x3] = "External Interrupt 3",
3560 [TT_EXTINT | 0x4] = "External Interrupt 4",
3561 [TT_EXTINT | 0x5] = "External Interrupt 5",
3562 [TT_EXTINT | 0x6] = "External Interrupt 6",
3563 [TT_EXTINT | 0x7] = "External Interrupt 7",
3564 [TT_EXTINT | 0x8] = "External Interrupt 8",
3565 [TT_EXTINT | 0x9] = "External Interrupt 9",
3566 [TT_EXTINT | 0xa] = "External Interrupt 10",
3567 [TT_EXTINT | 0xb] = "External Interrupt 11",
3568 [TT_EXTINT | 0xc] = "External Interrupt 12",
3569 [TT_EXTINT | 0xd] = "External Interrupt 13",
3570 [TT_EXTINT | 0xe] = "External Interrupt 14",
3571 [TT_EXTINT | 0xf] = "External Interrupt 15",
3572 [TT_TOVF] = "Tag Overflow",
3573 [TT_CODE_ACCESS] = "Instruction Access Error",
3574 [TT_DATA_ACCESS] = "Data Access Error",
3575 [TT_DIV_ZERO] = "Division By Zero",
3576 [TT_NCP_INSN] = "Coprocessor Disabled",
3577 };
3578 #endif
3579
3580 void do_interrupt(CPUState *env)
3581 {
3582 int cwp, intno = env->exception_index;
3583
3584 #ifdef DEBUG_PCALL
3585 if (qemu_loglevel_mask(CPU_LOG_INT)) {
3586 static int count;
3587 const char *name;
3588
3589 if (intno < 0 || intno >= 0x100)
3590 name = "Unknown";
3591 else if (intno >= 0x80)
3592 name = "Trap Instruction";
3593 else {
3594 name = excp_names[intno];
3595 if (!name)
3596 name = "Unknown";
3597 }
3598
3599 qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
3600 count, name, intno,
3601 env->pc,
3602 env->npc, env->regwptr[6]);
3603 log_cpu_state(env, 0);
3604 #if 0
3605 {
3606 int i;
3607 uint8_t *ptr;
3608
3609 qemu_log(" code=");
3610 ptr = (uint8_t *)env->pc;
3611 for(i = 0; i < 16; i++) {
3612 qemu_log(" %02x", ldub(ptr + i));
3613 }
3614 qemu_log("\n");
3615 }
3616 #endif
3617 count++;
3618 }
3619 #endif
3620 #if !defined(CONFIG_USER_ONLY)
3621 if (env->psret == 0) {
3622 cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
3623 env->exception_index);
3624 return;
3625 }
3626 #endif
3627 env->psret = 0;
3628 cwp = cpu_cwp_dec(env, env->cwp - 1);
3629 cpu_set_cwp(env, cwp);
3630 env->regwptr[9] = env->pc;
3631 env->regwptr[10] = env->npc;
3632 env->psrps = env->psrs;
3633 env->psrs = 1;
3634 env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
3635 env->pc = env->tbr;
3636 env->npc = env->pc + 4;
3637 env->exception_index = -1;
3638 }
3639 #endif
3640
3641 #if !defined(CONFIG_USER_ONLY)
3642
3643 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
3644 void *retaddr);
3645
3646 #define MMUSUFFIX _mmu
3647 #define ALIGNED_ONLY
3648
3649 #define SHIFT 0
3650 #include "softmmu_template.h"
3651
3652 #define SHIFT 1
3653 #include "softmmu_template.h"
3654
3655 #define SHIFT 2
3656 #include "softmmu_template.h"
3657
3658 #define SHIFT 3
3659 #include "softmmu_template.h"
3660
3661 /* XXX: make it generic ? */
3662 static void cpu_restore_state2(void *retaddr)
3663 {
3664 TranslationBlock *tb;
3665 unsigned long pc;
3666
3667 if (retaddr) {
3668 /* now we have a real cpu fault */
3669 pc = (unsigned long)retaddr;
3670 tb = tb_find_pc(pc);
3671 if (tb) {
3672 /* the PC is inside the translated code. It means that we have
3673 a virtual CPU fault */
3674 cpu_restore_state(tb, env, pc, (void *)(long)env->cond);
3675 }
3676 }
3677 }
3678
3679 static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
3680 void *retaddr)
3681 {
3682 #ifdef DEBUG_UNALIGNED
3683 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
3684 "\n", addr, env->pc);
3685 #endif
3686 cpu_restore_state2(retaddr);
3687 raise_exception(TT_UNALIGNED);
3688 }
3689
3690 /* try to fill the TLB and return an exception if error. If retaddr is
3691 NULL, it means that the function was called in C code (i.e. not
3692 from generated code or from helper.c) */
3693 /* XXX: fix it to restore all registers */
3694 void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
3695 {
3696 int ret;
3697 CPUState *saved_env;
3698
3699 /* XXX: hack to restore env in all cases, even if not called from
3700 generated code */
3701 saved_env = env;
3702 env = cpu_single_env;
3703
3704 ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
3705 if (ret) {
3706 cpu_restore_state2(retaddr);
3707 cpu_loop_exit();
3708 }
3709 env = saved_env;
3710 }
3711
3712 #endif /* !CONFIG_USER_ONLY */
3713
3714 #ifndef TARGET_SPARC64
3715 #if !defined(CONFIG_USER_ONLY)
3716 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
3717 int is_asi, int size)
3718 {
3719 CPUState *saved_env;
3720 int fault_type;
3721
3722 /* XXX: hack to restore env in all cases, even if not called from
3723 generated code */
3724 saved_env = env;
3725 env = cpu_single_env;
3726 #ifdef DEBUG_UNASSIGNED
3727 if (is_asi)
3728 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3729 " asi 0x%02x from " TARGET_FMT_lx "\n",
3730 is_exec ? "exec" : is_write ? "write" : "read", size,
3731 size == 1 ? "" : "s", addr, is_asi, env->pc);
3732 else
3733 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
3734 " from " TARGET_FMT_lx "\n",
3735 is_exec ? "exec" : is_write ? "write" : "read", size,
3736 size == 1 ? "" : "s", addr, env->pc);
3737 #endif
3738 /* Don't overwrite translation and access faults */
3739 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
3740 if ((fault_type > 4) || (fault_type == 0)) {
3741 env->mmuregs[3] = 0; /* Fault status register */
3742 if (is_asi)
3743 env->mmuregs[3] |= 1 << 16;
3744 if (env->psrs)
3745 env->mmuregs[3] |= 1 << 5;
3746 if (is_exec)
3747 env->mmuregs[3] |= 1 << 6;
3748 if (is_write)
3749 env->mmuregs[3] |= 1 << 7;
3750 env->mmuregs[3] |= (5 << 2) | 2;
3751 /* SuperSPARC will never place instruction fault addresses in the FAR */
3752 if (!is_exec) {
3753 env->mmuregs[4] = addr; /* Fault address register */
3754 }
3755 }
3756 /* overflow (same type fault was not read before another fault) */
3757 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
3758 env->mmuregs[3] |= 1;
3759 }
3760
3761 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
3762 if (is_exec)
3763 raise_exception(TT_CODE_ACCESS);
3764 else
3765 raise_exception(TT_DATA_ACCESS);
3766 }
3767
3768 /* flush neverland mappings created during no-fault mode,
3769 so the sequential MMU faults report proper fault types */
3770 if (env->mmuregs[0] & MMU_NF) {
3771 tlb_flush(env, 1);
3772 }
3773
3774 env = saved_env;
3775 }
3776 #endif
3777 #else
3778 #if defined(CONFIG_USER_ONLY)
3779 static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
3780 int is_asi, int size)
3781 #else
3782 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
3783 int is_asi, int size)
3784 #endif
3785 {
3786 CPUState *saved_env;
3787
3788 /* XXX: hack to restore env in all cases, even if not called from
3789 generated code */
3790 saved_env = env;
3791 env = cpu_single_env;
3792
3793 #ifdef DEBUG_UNASSIGNED
3794 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
3795 "\n", addr, env->pc);
3796 #endif
3797
3798 if (is_exec)
3799 raise_exception(TT_CODE_ACCESS);
3800 else
3801 raise_exception(TT_DATA_ACCESS);
3802
3803 env = saved_env;
3804 }
3805 #endif
3806
3807
3808 #ifdef TARGET_SPARC64
3809 void helper_tick_set_count(void *opaque, uint64_t count)
3810 {
3811 #if !defined(CONFIG_USER_ONLY)
3812 cpu_tick_set_count(opaque, count);
3813 #endif
3814 }
3815
3816 uint64_t helper_tick_get_count(void *opaque)
3817 {
3818 #if !defined(CONFIG_USER_ONLY)
3819 return cpu_tick_get_count(opaque);
3820 #else
3821 return 0;
3822 #endif
3823 }
3824
3825 void helper_tick_set_limit(void *opaque, uint64_t limit)
3826 {
3827 #if !defined(CONFIG_USER_ONLY)
3828 cpu_tick_set_limit(opaque, limit);
3829 #endif
3830 }
3831 #endif
Anthony Liguori's QEMU queue