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Add a QObject JSON wrapper
[qemu/aliguori-queue.git] / hw / eepro100.c
blob8734907e42642a6323a88292c2633c924ce0dd2e
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (c) 2006-2007 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) no valid link
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 */
35
36 #if defined(TARGET_I386)
37 # warning "PXE boot still not working!"
38 #endif
39
40 #include <stddef.h> /* offsetof */
41 #include <stdbool.h>
42 #include "hw.h"
43 #include "loader.h" /* rom_add_option */
44 #include "pci.h"
45 #include "net.h"
46 #include "eeprom93xx.h"
47
48 /* Common declarations for all PCI devices. */
49
50 #define PCI_CONFIG_8(offset, value) \
51 (pci_conf[offset] = (value))
52 #define PCI_CONFIG_16(offset, value) \
53 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
54 #define PCI_CONFIG_32(offset, value) \
55 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
56
57 #define KiB 1024
58
59 /* Debug EEPRO100 card. */
60 //~ #define DEBUG_EEPRO100
61
62 #ifdef DEBUG_EEPRO100
63 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
64 #else
65 #define logout(fmt, ...) ((void)0)
66 #endif
67
68 /* Set flags to 0 to disable debug output. */
69 #define INT 1 /* interrupt related actions */
70 #define MDI 1 /* mdi related actions */
71 #define OTHER 1
72 #define RXTX 1
73 #define EEPROM 1 /* eeprom related actions */
74
75 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
76
77 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
78
79 #define MAX_ETH_FRAME_SIZE 1514
80
81 /* This driver supports several different devices which are declared here. */
82 #define i82550 0x82550
83 #define i82551 0x82551
84 #define i82557A 0x82557a
85 #define i82557B 0x82557b
86 #define i82557C 0x82557c
87 #define i82558A 0x82558a
88 #define i82558B 0x82558b
89 #define i82559A 0x82559a
90 #define i82559B 0x82559b
91 #define i82559C 0x82559c
92 #define i82559ER 0x82559e
93 #define i82562 0x82562
94
95 /* Use 64 word EEPROM. TODO: could be a runtime option. */
96 #define EEPROM_SIZE 64
97
98 #define PCI_MEM_SIZE (4 * KiB)
99 #define PCI_IO_SIZE 64
100 #define PCI_FLASH_SIZE (128 * KiB)
101
102 #define BIT(n) (1 << (n))
103 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
104
105 /* The SCB accepts the following controls for the Tx and Rx units: */
106 #define CU_NOP 0x0000 /* No operation. */
107 #define CU_START 0x0010 /* CU start. */
108 #define CU_RESUME 0x0020 /* CU resume. */
109 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
110 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
111 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
112 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
113 #define CU_SRESUME 0x00a0 /* CU static resume. */
114
115 #define RU_NOP 0x0000
116 #define RX_START 0x0001
117 #define RX_RESUME 0x0002
118 #define RX_ABORT 0x0004
119 #define RX_ADDR_LOAD 0x0006
120 #define RX_RESUMENR 0x0007
121 #define INT_MASK 0x0100
122 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
123
124 /* Offsets to the various registers.
125 All accesses need not be longword aligned. */
126 enum speedo_offsets {
127 SCBStatus = 0,
128 SCBAck = 1,
129 SCBCmd = 2, /* Rx/Command Unit command and status. */
130 SCBIntmask = 3,
131 SCBPointer = 4, /* General purpose pointer. */
132 SCBPort = 8, /* Misc. commands and operands. */
133 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
134 SCBCtrlMDI = 16, /* MDI interface control. */
135 SCBEarlyRx = 20, /* Early receive byte count. */
136 SCBFlow = 24,
137 };
138
139 /* A speedo3 transmit buffer descriptor with two buffers... */
140 typedef struct {
141 uint16_t status;
142 uint16_t command;
143 uint32_t link; /* void * */
144 uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
145 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
146 uint8_t tx_threshold; /* transmit threshold */
147 uint8_t tbd_count; /* TBD number */
148 //~ /* This constitutes two "TBD" entries: hdr and data */
149 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
150 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
151 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
152 //~ int32_t tx_buf_size1; /* Length of Tx data. */
153 } eepro100_tx_t;
154
155 /* Receive frame descriptor. */
156 typedef struct {
157 int16_t status;
158 uint16_t command;
159 uint32_t link; /* struct RxFD * */
160 uint32_t rx_buf_addr; /* void * */
161 uint16_t count;
162 uint16_t size;
163 char packet[MAX_ETH_FRAME_SIZE + 4];
164 } eepro100_rx_t;
165
166 typedef struct {
167 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
168 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
169 tx_multiple_collisions, tx_total_collisions;
170 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
171 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
172 rx_short_frame_errors;
173 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
174 uint16_t xmt_tco_frames, rcv_tco_frames;
175 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
176 uint32_t reserved[4];
177 } eepro100_stats_t;
178
179 typedef enum {
180 cu_idle = 0,
181 cu_suspended = 1,
182 cu_active = 2,
183 cu_lpq_active = 2,
184 cu_hqp_active = 3
185 } cu_state_t;
186
187 typedef enum {
188 ru_idle = 0,
189 ru_suspended = 1,
190 ru_no_resources = 2,
191 ru_ready = 4
192 } ru_state_t;
193
194 typedef struct {
195 PCIDevice dev;
196 uint8_t mult[8]; /* multicast mask array */
197 int mmio_index;
198 VLANClientState *vc;
199 NICConf conf;
200 uint8_t scb_stat; /* SCB stat/ack byte */
201 uint8_t int_stat; /* PCI interrupt status */
202 /* region must not be saved by nic_save. */
203 uint32_t region[3]; /* PCI region addresses */
204 uint16_t mdimem[32];
205 eeprom_t *eeprom;
206 uint32_t device; /* device variant */
207 uint32_t pointer;
208 /* (cu_base + cu_offset) address the next command block in the command block list. */
209 uint32_t cu_base; /* CU base address */
210 uint32_t cu_offset; /* CU address offset */
211 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
212 uint32_t ru_base; /* RU base address */
213 uint32_t ru_offset; /* RU address offset */
214 uint32_t statsaddr; /* pointer to eepro100_stats_t */
215
216 /* Statistical counters. Also used for wake-up packet (i82559). */
217 eepro100_stats_t statistics;
218
219 #if 0
220 uint16_t status;
221 #endif
222
223 /* Configuration bytes. */
224 uint8_t configuration[22];
225
226 /* Data in mem is always in the byte order of the controller (le). */
227 uint8_t mem[PCI_MEM_SIZE];
228 /* vmstate for each particular nic */
229 VMStateDescription *vmstate;
230
231 /* Quasi static device properties (no need to save them). */
232 uint16_t stats_size;
233 bool has_extended_tcb_support;
234 } EEPRO100State;
235
236 /* Default values for MDI (PHY) registers */
237 static const uint16_t eepro100_mdi_default[] = {
238 /* MDI Registers 0 - 6, 7 */
239 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
240 /* MDI Registers 8 - 15 */
241 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
242 /* MDI Registers 16 - 31 */
243 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
244 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
245 };
246
247 /* Readonly mask for MDI (PHY) registers */
248 static const uint16_t eepro100_mdi_mask[] = {
249 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
250 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
251 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
252 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
253 };
254
255 /* XXX: optimize */
256 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
257 {
258 val = cpu_to_le32(val);
259 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
260 }
261
262 #define POLYNOMIAL 0x04c11db6
263
264 /* From FreeBSD */
265 /* XXX: optimize */
266 static int compute_mcast_idx(const uint8_t * ep)
267 {
268 uint32_t crc;
269 int carry, i, j;
270 uint8_t b;
271
272 crc = 0xffffffff;
273 for (i = 0; i < 6; i++) {
274 b = *ep++;
275 for (j = 0; j < 8; j++) {
276 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
277 crc <<= 1;
278 b >>= 1;
279 if (carry) {
280 crc = ((crc ^ POLYNOMIAL) | carry);
281 }
282 }
283 }
284 return (crc >> 26);
285 }
286
287 #if defined(DEBUG_EEPRO100)
288 static const char *nic_dump(const uint8_t * buf, unsigned size)
289 {
290 static char dump[3 * 16 + 1];
291 char *p = &dump[0];
292 if (size > 16) {
293 size = 16;
294 }
295 while (size-- > 0) {
296 p += sprintf(p, " %02x", *buf++);
297 }
298 return dump;
299 }
300 #endif /* DEBUG_EEPRO100 */
301
302 enum scb_stat_ack {
303 stat_ack_not_ours = 0x00,
304 stat_ack_sw_gen = 0x04,
305 stat_ack_rnr = 0x10,
306 stat_ack_cu_idle = 0x20,
307 stat_ack_frame_rx = 0x40,
308 stat_ack_cu_cmd_done = 0x80,
309 stat_ack_not_present = 0xFF,
310 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
311 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
312 };
313
314 static void disable_interrupt(EEPRO100State * s)
315 {
316 if (s->int_stat) {
317 TRACE(INT, logout("interrupt disabled\n"));
318 qemu_irq_lower(s->dev.irq[0]);
319 s->int_stat = 0;
320 }
321 }
322
323 static void enable_interrupt(EEPRO100State * s)
324 {
325 if (!s->int_stat) {
326 TRACE(INT, logout("interrupt enabled\n"));
327 qemu_irq_raise(s->dev.irq[0]);
328 s->int_stat = 1;
329 }
330 }
331
332 static void eepro100_acknowledge(EEPRO100State * s)
333 {
334 s->scb_stat &= ~s->mem[SCBAck];
335 s->mem[SCBAck] = s->scb_stat;
336 if (s->scb_stat == 0) {
337 disable_interrupt(s);
338 }
339 }
340
341 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
342 {
343 uint8_t mask = ~s->mem[SCBIntmask];
344 s->mem[SCBAck] |= stat;
345 stat = s->scb_stat = s->mem[SCBAck];
346 stat &= (mask | 0x0f);
347 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
348 if (stat && (mask & 0x01)) {
349 /* SCB mask and SCB Bit M do not disable interrupt. */
350 enable_interrupt(s);
351 } else if (s->int_stat) {
352 disable_interrupt(s);
353 }
354 }
355
356 static void eepro100_cx_interrupt(EEPRO100State * s)
357 {
358 /* CU completed action command. */
359 /* Transmit not ok (82557 only, not in emulation). */
360 eepro100_interrupt(s, 0x80);
361 }
362
363 static void eepro100_cna_interrupt(EEPRO100State * s)
364 {
365 /* CU left the active state. */
366 eepro100_interrupt(s, 0x20);
367 }
368
369 static void eepro100_fr_interrupt(EEPRO100State * s)
370 {
371 /* RU received a complete frame. */
372 eepro100_interrupt(s, 0x40);
373 }
374
375 #if 0
376 static void eepro100_rnr_interrupt(EEPRO100State * s)
377 {
378 /* RU is not ready. */
379 eepro100_interrupt(s, 0x10);
380 }
381 #endif
382
383 static void eepro100_mdi_interrupt(EEPRO100State * s)
384 {
385 /* MDI completed read or write cycle. */
386 eepro100_interrupt(s, 0x08);
387 }
388
389 static void eepro100_swi_interrupt(EEPRO100State * s)
390 {
391 /* Software has requested an interrupt. */
392 eepro100_interrupt(s, 0x04);
393 }
394
395 #if 0
396 static void eepro100_fcp_interrupt(EEPRO100State * s)
397 {
398 /* Flow control pause interrupt (82558 and later). */
399 eepro100_interrupt(s, 0x01);
400 }
401 #endif
402
403 static void pci_reset(EEPRO100State * s)
404 {
405 uint32_t device = s->device;
406 uint8_t *pci_conf = s->dev.config;
407 bool power_management = 1;
408
409 TRACE(OTHER, logout("%p\n", s));
410
411 /* PCI Vendor ID */
412 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
413 /* PCI Device ID depends on device and is set below. */
414 /* PCI Command */
415 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
416 /* PCI Status */
417 PCI_CONFIG_16(PCI_STATUS, 0x2800);
418 /* PCI Revision ID */
419 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
420 /* PCI Class Code */
421 PCI_CONFIG_8(0x09, 0x00);
422 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
423 /* PCI Cache Line Size */
424 /* check cache line size!!! */
425 //~ PCI_CONFIG_8(0x0c, 0x00);
426 /* PCI Latency Timer */
427 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
428 /* PCI Header Type */
429 /* BIST (built-in self test) */
430 #if defined(TARGET_I386)
431 // !!! workaround for buggy bios
432 //~ #define PCI_BASE_ADDRESS_MEM_PREFETCH 0
433 #endif
434 #if 0
435 /* PCI Base Address Registers */
436 /* CSR Memory Mapped Base Address */
437 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
438 PCI_BASE_ADDRESS_SPACE_MEMORY |
439 PCI_BASE_ADDRESS_MEM_PREFETCH);
440 /* CSR I/O Mapped Base Address */
441 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_SPACE_IO);
442 #if 0
443 /* Flash Memory Mapped Base Address */
444 PCI_CONFIG_32(PCI_BASE_ADDRESS_2,
445 0xfffe0000 | PCI_BASE_ADDRESS_SPACE_MEMORY);
446 #endif
447 #endif
448 /* Expansion ROM Base Address (depends on boot disable!!!) */
449 PCI_CONFIG_32(0x30, 0x00000000);
450 /* Capability Pointer */
451 PCI_CONFIG_8(0x34, 0xdc);
452 /* Interrupt Line */
453 /* Interrupt Pin */
454 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
455 /* Minimum Grant */
456 PCI_CONFIG_8(0x3e, 0x08);
457 /* Maximum Latency */
458 PCI_CONFIG_8(0x3f, 0x18);
459
460 switch (device) {
461 case i82550:
462 // TODO: check device id.
463 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
464 /* Revision ID: 0x0c, 0x0d, 0x0e. */
465 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
466 // TODO: check size of statistical counters.
467 s->stats_size = 80;
468 // TODO: check extended tcb support.
469 s->has_extended_tcb_support = 1;
470 break;
471 case i82551:
472 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
473 /* Revision ID: 0x0f, 0x10. */
474 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
475 // TODO: check size of statistical counters.
476 s->stats_size = 80;
477 s->has_extended_tcb_support = 1;
478 break;
479 case i82557A:
480 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
481 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
482 PCI_CONFIG_8(0x34, 0x00);
483 power_management = 0;
484 break;
485 case i82557B:
486 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
487 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
488 PCI_CONFIG_8(0x34, 0x00);
489 power_management = 0;
490 break;
491 case i82557C:
492 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
493 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
494 PCI_CONFIG_8(0x34, 0x00);
495 power_management = 0;
496 break;
497 case i82558A:
498 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
499 PCI_CONFIG_16(PCI_STATUS, 0x0290);
500 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
501 s->stats_size = 76;
502 s->has_extended_tcb_support = 1;
503 break;
504 case i82558B:
505 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
506 PCI_CONFIG_16(PCI_STATUS, 0x0290);
507 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
508 s->stats_size = 76;
509 s->has_extended_tcb_support = 1;
510 break;
511 case i82559A:
512 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
513 PCI_CONFIG_16(PCI_STATUS, 0x0290);
514 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
515 s->stats_size = 80;
516 s->has_extended_tcb_support = 1;
517 break;
518 case i82559B:
519 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
520 PCI_CONFIG_16(PCI_STATUS, 0x0290);
521 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
522 s->stats_size = 80;
523 s->has_extended_tcb_support = 1;
524 break;
525 case i82559C:
526 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
527 PCI_CONFIG_16(PCI_STATUS, 0x0290);
528 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
529 // TODO: Windows wants revision id 0x0c.
530 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
531 #if EEPROM_SIZE > 0
532 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
533 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
534 #endif
535 s->stats_size = 80;
536 s->has_extended_tcb_support = 1;
537 break;
538 case i82559ER:
539 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
540 PCI_CONFIG_16(PCI_STATUS, 0x0290);
541 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
542 s->stats_size = 80;
543 s->has_extended_tcb_support = 1;
544 break;
545 case i82562:
546 // TODO: check device id.
547 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
548 /* TODO: wrong revision id. */
549 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
550 s->stats_size = 80;
551 s->has_extended_tcb_support = 1;
552 break;
553 default:
554 logout("Device %X is undefined!\n", device);
555 }
556
557 s->configuration[6] |= BIT(5);
558
559 if (s->stats_size == 80) {
560 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
561 if (s->configuration[6] & BIT(2)) {
562 /* TCO statistical counters. */
563 assert(s->configuration[6] & BIT(5));
564 } else {
565 if (s->configuration[6] & BIT(5)) {
566 /* No extended statistical counters, i82557 compatible. */
567 s->stats_size = 64;
568 } else {
569 /* i82558 compatible. */
570 s->stats_size = 76;
571 }
572 }
573 } else {
574 if (s->configuration[6] & BIT(5)) {
575 /* No extended statistical counters. */
576 s->stats_size = 64;
577 }
578 }
579 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
580
581 if (power_management) {
582 /* Power Management Capabilities */
583 PCI_CONFIG_8(0xdc, 0x01);
584 /* Next Item Pointer */
585 /* Capability ID */
586 PCI_CONFIG_16(0xde, 0x7e21);
587 /* TODO: Power Management Control / Status. */
588 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
589 }
590
591 #if EEPROM_SIZE > 0
592 if (device == i82557C || device == i82558B || device == i82559C) {
593 // TODO: get vendor id from EEPROM for i82557C or later.
594 // TODO: get device id from EEPROM for i82557C or later.
595 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
596 // TODO: header type is determined by EEPROM for i82559.
597 // TODO: get subsystem id from EEPROM for i82557C or later.
598 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
599 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
600 // TODO: capability pointer depends on EEPROM for i82558.
601 logout("Get device id and revision from EEPROM!!!\n");
602 }
603 #endif /* EEPROM_SIZE > 0 */
604 }
605
606 static void nic_selective_reset(EEPRO100State * s)
607 {
608 size_t i;
609 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
610 //~ eeprom93xx_reset(s->eeprom);
611 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
612 eeprom_contents[0xa] = 0x4000;
613 if (s->device == i82557B || s->device == i82557C)
614 eeprom_contents[5] = 0x0100;
615 uint16_t sum = 0;
616 for (i = 0; i < EEPROM_SIZE - 1; i++) {
617 sum += eeprom_contents[i];
618 }
619 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
620 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
621
622 memset(s->mem, 0, sizeof(s->mem));
623 uint32_t val = BIT(21);
624 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
625
626 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
627 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
628 }
629
630 static void nic_reset(void *opaque)
631 {
632 EEPRO100State *s = opaque;
633 TRACE(OTHER, logout("%p\n", s));
634 nic_selective_reset(s);
635 }
636
637 #if defined(DEBUG_EEPRO100)
638 static const char * const reg[PCI_IO_SIZE / 4] = {
639 "Command/Status",
640 "General Pointer",
641 "Port",
642 "EEPROM/Flash Control",
643 "MDI Control",
644 "Receive DMA Byte Count",
645 "Flow control",
646 "General Status/Control"
647 };
648
649 static char *regname(uint32_t addr)
650 {
651 static char buf[16];
652 if (addr < PCI_IO_SIZE) {
653 const char *r = reg[addr / 4];
654 if (r != 0) {
655 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
656 } else {
657 snprintf(buf, sizeof(buf), "0x%02x", addr);
658 }
659 } else {
660 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
661 }
662 return buf;
663 }
664 #endif /* DEBUG_EEPRO100 */
665
666 #if 0
667 static uint16_t eepro100_read_status(EEPRO100State * s)
668 {
669 uint16_t val = s->status;
670 TRACE(OTHER, logout("val=0x%04x\n", val));
671 return val;
672 }
673
674 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
675 {
676 TRACE(OTHER, logout("val=0x%04x\n", val));
677 s->status = val;
678 }
679 #endif
680
681 /*****************************************************************************
682 *
683 * Command emulation.
684 *
685 ****************************************************************************/
686
687 #if 0
688 static uint16_t eepro100_read_command(EEPRO100State * s)
689 {
690 uint16_t val = 0xffff;
691 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
692 return val;
693 }
694 #endif
695
696 /* Commands that can be put in a command list entry. */
697 enum commands {
698 CmdNOp = 0,
699 CmdIASetup = 1,
700 CmdConfigure = 2,
701 CmdMulticastList = 3,
702 CmdTx = 4,
703 CmdTDR = 5, /* load microcode */
704 CmdDump = 6,
705 CmdDiagnose = 7,
706
707 /* And some extra flags: */
708 CmdSuspend = 0x4000, /* Suspend after completion. */
709 CmdIntr = 0x2000, /* Interrupt after completion. */
710 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
711 };
712
713 static cu_state_t get_cu_state(EEPRO100State * s)
714 {
715 return ((s->mem[SCBStatus] >> 6) & 0x03);
716 }
717
718 static void set_cu_state(EEPRO100State * s, cu_state_t state)
719 {
720 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
721 }
722
723 static ru_state_t get_ru_state(EEPRO100State * s)
724 {
725 return ((s->mem[SCBStatus] >> 2) & 0x0f);
726 }
727
728 static void set_ru_state(EEPRO100State * s, ru_state_t state)
729 {
730 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
731 }
732
733 static void dump_statistics(EEPRO100State * s)
734 {
735 /* Dump statistical data. Most data is never changed by the emulation
736 * and always 0, so we first just copy the whole block and then those
737 * values which really matter.
738 * Number of data should check configuration!!!
739 */
740 cpu_physical_memory_write(s->statsaddr,
741 (uint8_t *) & s->statistics, s->stats_size);
742 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
743 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
744 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
745 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
746 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
747 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
748 //~ missing("CU dump statistical counters");
749 }
750
751 static void action_command(EEPRO100State *s)
752 {
753 for (;;) {
754 uint32_t cb_address = s->cu_base + s->cu_offset;
755 eepro100_tx_t tx;
756 cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
757 uint16_t status = le16_to_cpu(tx.status);
758 uint16_t command = le16_to_cpu(tx.command);
759 logout
760 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
761 val, status, command, tx.link);
762 bool bit_el = ((command & 0x8000) != 0);
763 bool bit_s = ((command & 0x4000) != 0);
764 bool bit_i = ((command & 0x2000) != 0);
765 bool bit_nc = ((command & 0x0010) != 0);
766 bool success = true;
767 //~ bool bit_sf = ((command & 0x0008) != 0);
768 uint16_t cmd = command & 0x0007;
769 s->cu_offset = le32_to_cpu(tx.link);
770 switch (cmd) {
771 case CmdNOp:
772 /* Do nothing. */
773 break;
774 case CmdIASetup:
775 cpu_physical_memory_read(cb_address + 8, &s->conf.macaddr.a[0], 6);
776 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)));
777 break;
778 case CmdConfigure:
779 cpu_physical_memory_read(cb_address + 8, &s->configuration[0],
780 sizeof(s->configuration));
781 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
782 break;
783 case CmdMulticastList:
784 //~ missing("multicast list");
785 break;
786 case CmdTx:
787 (void)0;
788 uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr);
789 uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
790 TRACE(RXTX, logout
791 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
792 tbd_array, tcb_bytes, tx.tbd_count));
793
794 if (bit_nc) {
795 missing("CmdTx: NC = 0");
796 success = false;
797 break;
798 }
799 //~ assert(!bit_sf);
800 if (tcb_bytes > 2600) {
801 logout("TCB byte count too large, using 2600\n");
802 tcb_bytes = 2600;
803 }
804 /* Next assertion fails for local configuration. */
805 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
806 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
807 logout
808 ("illegal values of TBD array address and TCB byte count!\n");
809 }
810 // sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes
811 uint8_t buf[2600];
812 uint16_t size = 0;
813 uint32_t tbd_address = cb_address + 0x10;
814 assert(tcb_bytes <= sizeof(buf));
815 while (size < tcb_bytes) {
816 uint32_t tx_buffer_address = ldl_phys(tbd_address);
817 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
818 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
819 tbd_address += 8;
820 TRACE(RXTX, logout
821 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
822 tx_buffer_address, tx_buffer_size));
823 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
824 cpu_physical_memory_read(tx_buffer_address, &buf[size],
825 tx_buffer_size);
826 size += tx_buffer_size;
827 }
828 if (tbd_array == 0xffffffff) {
829 /* Simplified mode. Was already handled by code above. */
830 } else {
831 /* Flexible mode. */
832 uint8_t tbd_count = 0;
833 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
834 /* Extended Flexible TCB. */
835 for (; tbd_count < 2; tbd_count++) {
836 uint32_t tx_buffer_address = ldl_phys(tbd_address);
837 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
838 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
839 tbd_address += 8;
840 TRACE(RXTX, logout
841 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
842 tx_buffer_address, tx_buffer_size));
843 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
844 cpu_physical_memory_read(tx_buffer_address, &buf[size],
845 tx_buffer_size);
846 size += tx_buffer_size;
847 if (tx_buffer_el & 1) {
848 break;
849 }
850 }
851 }
852 tbd_address = tbd_array;
853 for (; tbd_count < tx.tbd_count; tbd_count++) {
854 uint32_t tx_buffer_address = ldl_phys(tbd_address);
855 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
856 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
857 tbd_address += 8;
858 TRACE(RXTX, logout
859 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
860 tx_buffer_address, tx_buffer_size));
861 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
862 cpu_physical_memory_read(tx_buffer_address, &buf[size],
863 tx_buffer_size);
864 size += tx_buffer_size;
865 if (tx_buffer_el & 1) {
866 break;
867 }
868 }
869 }
870 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
871 qemu_send_packet(s->vc, buf, size);
872 s->statistics.tx_good_frames++;
873 /* Transmit with bad status would raise an CX/TNO interrupt.
874 * (82557 only). Emulation never has bad status. */
875 //~ eepro100_cx_interrupt(s);
876 break;
877 case CmdTDR:
878 TRACE(OTHER, logout("load microcode\n"));
879 /* Starting with offset 8, the command contains
880 * 64 dwords microcode which we just ignore here. */
881 break;
882 default:
883 missing("undefined command");
884 success = false;
885 break;
886 }
887 /* Write new status. */
888 stw_phys(cb_address, status | 0x8000 | (success ? 0x2000 : 0));
889 if (bit_i) {
890 /* CU completed action. */
891 eepro100_cx_interrupt(s);
892 }
893 if (bit_el) {
894 /* CU becomes idle. Terminate command loop. */
895 set_cu_state(s, cu_idle);
896 eepro100_cna_interrupt(s);
897 break;
898 } else if (bit_s) {
899 /* CU becomes suspended. Terminate command loop. */
900 set_cu_state(s, cu_suspended);
901 eepro100_cna_interrupt(s);
902 break;
903 } else {
904 /* More entries in list. */
905 TRACE(OTHER, logout("CU list with at least one more entry\n"));
906 }
907 }
908 TRACE(OTHER, logout("CU list empty\n"));
909 /* List is empty. Now CU is idle or suspended. */
910 }
911
912 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
913 {
914 switch (val) {
915 case CU_NOP:
916 /* No operation. */
917 break;
918 case CU_START:
919 if (get_cu_state(s) != cu_idle) {
920 /* Intel documentation says that CU must be idle for the CU
921 * start command. Intel driver for Linux also starts the CU
922 * from suspended state. */
923 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
924 //~ assert(!"wrong CU state");
925 }
926 set_cu_state(s, cu_active);
927 s->cu_offset = s->pointer;
928 action_command(s);
929 break;
930 case CU_RESUME:
931 if (get_cu_state(s) != cu_suspended) {
932 logout("bad CU resume from CU state %u\n", get_cu_state(s));
933 /* Workaround for bad Linux eepro100 driver which resumes
934 * from idle state. */
935 //~ missing("cu resume");
936 set_cu_state(s, cu_suspended);
937 }
938 if (get_cu_state(s) == cu_suspended) {
939 TRACE(OTHER, logout("CU resuming\n"));
940 set_cu_state(s, cu_active);
941 action_command(s);
942 }
943 break;
944 case CU_STATSADDR:
945 /* Load dump counters address. */
946 s->statsaddr = s->pointer;
947 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
948 break;
949 case CU_SHOWSTATS:
950 /* Dump statistical counters. */
951 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
952 dump_statistics(s);
953 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
954 break;
955 case CU_CMD_BASE:
956 /* Load CU base. */
957 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
958 s->cu_base = s->pointer;
959 break;
960 case CU_DUMPSTATS:
961 /* Dump and reset statistical counters. */
962 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
963 dump_statistics(s);
964 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
965 memset(&s->statistics, 0, sizeof(s->statistics));
966 break;
967 case CU_SRESUME:
968 /* CU static resume. */
969 missing("CU static resume");
970 break;
971 default:
972 missing("Undefined CU command");
973 }
974 }
975
976 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
977 {
978 switch (val) {
979 case RU_NOP:
980 /* No operation. */
981 break;
982 case RX_START:
983 /* RU start. */
984 if (get_ru_state(s) != ru_idle) {
985 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
986 //~ assert(!"wrong RU state");
987 }
988 set_ru_state(s, ru_ready);
989 s->ru_offset = s->pointer;
990 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
991 break;
992 case RX_RESUME:
993 /* Restart RU. */
994 if (get_ru_state(s) != ru_suspended) {
995 logout("RU state is %u, should be %u\n", get_ru_state(s),
996 ru_suspended);
997 //~ assert(!"wrong RU state");
998 }
999 set_ru_state(s, ru_ready);
1000 break;
1001 case RX_ADDR_LOAD:
1002 /* Load RU base. */
1003 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1004 s->ru_base = s->pointer;
1005 break;
1006 default:
1007 logout("val=0x%02x (undefined RU command)\n", val);
1008 missing("Undefined SU command");
1009 }
1010 }
1011
1012 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1013 {
1014 eepro100_ru_command(s, val & 0x0f);
1015 eepro100_cu_command(s, val & 0xf0);
1016 if ((val) == 0) {
1017 TRACE(OTHER, logout("val=0x%02x\n", val));
1018 }
1019 /* Clear command byte after command was accepted. */
1020 s->mem[SCBCmd] = 0;
1021 }
1022
1023 /*****************************************************************************
1024 *
1025 * EEPROM emulation.
1026 *
1027 ****************************************************************************/
1028
1029 #define EEPROM_CS 0x02
1030 #define EEPROM_SK 0x01
1031 #define EEPROM_DI 0x04
1032 #define EEPROM_DO 0x08
1033
1034 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1035 {
1036 uint16_t val;
1037 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1038 if (eeprom93xx_read(s->eeprom)) {
1039 val |= EEPROM_DO;
1040 } else {
1041 val &= ~EEPROM_DO;
1042 }
1043 TRACE(EEPROM, logout("val=0x%04x\n", val));
1044 return val;
1045 }
1046
1047 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1048 {
1049 TRACE(EEPROM, logout("val=0x%02x\n", val));
1050
1051 /* mask unwriteable bits */
1052 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1053
1054 int eecs = ((val & EEPROM_CS) != 0);
1055 int eesk = ((val & EEPROM_SK) != 0);
1056 int eedi = ((val & EEPROM_DI) != 0);
1057 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1058 }
1059
1060 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1061 {
1062 s->pointer = le32_to_cpu(val);
1063 TRACE(OTHER, logout("val=0x%08x\n", val));
1064 }
1065
1066 /*****************************************************************************
1067 *
1068 * MDI emulation.
1069 *
1070 ****************************************************************************/
1071
1072 #if defined(DEBUG_EEPRO100)
1073 static const char * const mdi_op_name[] = {
1074 "opcode 0",
1075 "write",
1076 "read",
1077 "opcode 3"
1078 };
1079
1080 static const char * const mdi_reg_name[] = {
1081 "Control",
1082 "Status",
1083 "PHY Identification (Word 1)",
1084 "PHY Identification (Word 2)",
1085 "Auto-Negotiation Advertisement",
1086 "Auto-Negotiation Link Partner Ability",
1087 "Auto-Negotiation Expansion"
1088 };
1089
1090 static const char *reg2name(uint8_t reg)
1091 {
1092 static char buffer[10];
1093 const char *p = buffer;
1094 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1095 p = mdi_reg_name[reg];
1096 } else {
1097 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1098 }
1099 return p;
1100 }
1101 #endif /* DEBUG_EEPRO100 */
1102
1103 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1104 {
1105 uint32_t val;
1106 memcpy(&val, &s->mem[0x10], sizeof(val));
1107
1108 #ifdef DEBUG_EEPRO100
1109 uint8_t raiseint = (val & BIT(29)) >> 29;
1110 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1111 uint8_t phy = (val & BITS(25, 21)) >> 21;
1112 uint8_t reg = (val & BITS(20, 16)) >> 16;
1113 uint16_t data = (val & BITS(15, 0));
1114 #endif
1115 /* Emulation takes no time to finish MDI transaction. */
1116 val |= BIT(28);
1117 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1118 val, raiseint, mdi_op_name[opcode], phy,
1119 reg2name(reg), data));
1120 return val;
1121 }
1122
1123 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1124 {
1125 uint8_t raiseint = (val & BIT(29)) >> 29;
1126 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1127 uint8_t phy = (val & BITS(25, 21)) >> 21;
1128 uint8_t reg = (val & BITS(20, 16)) >> 16;
1129 uint16_t data = (val & BITS(15, 0));
1130 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1131 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1132 if (phy != 1) {
1133 /* Unsupported PHY address. */
1134 //~ logout("phy must be 1 but is %u\n", phy);
1135 data = 0;
1136 } else if (opcode != 1 && opcode != 2) {
1137 /* Unsupported opcode. */
1138 logout("opcode must be 1 or 2 but is %u\n", opcode);
1139 data = 0;
1140 } else if (reg > 6) {
1141 /* Unsupported register. */
1142 logout("register must be 0...6 but is %u\n", reg);
1143 data = 0;
1144 } else {
1145 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1146 val, raiseint, mdi_op_name[opcode], phy,
1147 reg2name(reg), data));
1148 if (opcode == 1) {
1149 /* MDI write */
1150 switch (reg) {
1151 case 0: /* Control Register */
1152 if (data & 0x8000) {
1153 /* Reset status and control registers to default. */
1154 s->mdimem[0] = eepro100_mdi_default[0];
1155 s->mdimem[1] = eepro100_mdi_default[1];
1156 data = s->mdimem[reg];
1157 } else {
1158 /* Restart Auto Configuration = Normal Operation */
1159 data &= ~0x0200;
1160 }
1161 break;
1162 case 1: /* Status Register */
1163 missing("not writable");
1164 data = s->mdimem[reg];
1165 break;
1166 case 2: /* PHY Identification Register (Word 1) */
1167 case 3: /* PHY Identification Register (Word 2) */
1168 missing("not implemented");
1169 break;
1170 case 4: /* Auto-Negotiation Advertisement Register */
1171 case 5: /* Auto-Negotiation Link Partner Ability Register */
1172 break;
1173 case 6: /* Auto-Negotiation Expansion Register */
1174 default:
1175 missing("not implemented");
1176 }
1177 s->mdimem[reg] = data;
1178 } else if (opcode == 2) {
1179 /* MDI read */
1180 switch (reg) {
1181 case 0: /* Control Register */
1182 if (data & 0x8000) {
1183 /* Reset status and control registers to default. */
1184 s->mdimem[0] = eepro100_mdi_default[0];
1185 s->mdimem[1] = eepro100_mdi_default[1];
1186 }
1187 break;
1188 case 1: /* Status Register */
1189 s->mdimem[reg] |= 0x0020;
1190 break;
1191 case 2: /* PHY Identification Register (Word 1) */
1192 case 3: /* PHY Identification Register (Word 2) */
1193 case 4: /* Auto-Negotiation Advertisement Register */
1194 break;
1195 case 5: /* Auto-Negotiation Link Partner Ability Register */
1196 s->mdimem[reg] = 0x41fe;
1197 break;
1198 case 6: /* Auto-Negotiation Expansion Register */
1199 s->mdimem[reg] = 0x0001;
1200 break;
1201 }
1202 data = s->mdimem[reg];
1203 }
1204 /* Emulation takes no time to finish MDI transaction.
1205 * Set MDI bit in SCB status register. */
1206 s->mem[SCBAck] |= 0x08;
1207 val |= BIT(28);
1208 if (raiseint) {
1209 eepro100_mdi_interrupt(s);
1210 }
1211 }
1212 val = (val & 0xffff0000) + data;
1213 memcpy(&s->mem[0x10], &val, sizeof(val));
1214 }
1215
1216 /*****************************************************************************
1217 *
1218 * Port emulation.
1219 *
1220 ****************************************************************************/
1221
1222 #define PORT_SOFTWARE_RESET 0
1223 #define PORT_SELFTEST 1
1224 #define PORT_SELECTIVE_RESET 2
1225 #define PORT_DUMP 3
1226 #define PORT_SELECTION_MASK 3
1227
1228 typedef struct {
1229 uint32_t st_sign; /* Self Test Signature */
1230 uint32_t st_result; /* Self Test Results */
1231 } eepro100_selftest_t;
1232
1233 static uint32_t eepro100_read_port(EEPRO100State * s)
1234 {
1235 return 0;
1236 }
1237
1238 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1239 {
1240 val = le32_to_cpu(val);
1241 uint32_t address = (val & ~PORT_SELECTION_MASK);
1242 uint8_t selection = (val & PORT_SELECTION_MASK);
1243 switch (selection) {
1244 case PORT_SOFTWARE_RESET:
1245 nic_reset(s);
1246 break;
1247 case PORT_SELFTEST:
1248 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1249 eepro100_selftest_t data;
1250 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1251 data.st_sign = 0xffffffff;
1252 data.st_result = 0;
1253 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1254 break;
1255 case PORT_SELECTIVE_RESET:
1256 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1257 nic_selective_reset(s);
1258 break;
1259 default:
1260 logout("val=0x%08x\n", val);
1261 missing("unknown port selection");
1262 }
1263 }
1264
1265 /*****************************************************************************
1266 *
1267 * General hardware emulation.
1268 *
1269 ****************************************************************************/
1270
1271 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1272 {
1273 uint8_t val;
1274 if (addr <= sizeof(s->mem) - sizeof(val)) {
1275 memcpy(&val, &s->mem[addr], sizeof(val));
1276 }
1277
1278 switch (addr) {
1279 case SCBStatus:
1280 //~ val = eepro100_read_status(s);
1281 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1282 break;
1283 case SCBAck:
1284 //~ val = eepro100_read_status(s);
1285 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1286 break;
1287 case SCBCmd:
1288 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1289 //~ val = eepro100_read_command(s);
1290 break;
1291 case SCBIntmask:
1292 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1293 break;
1294 case SCBPort + 3:
1295 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1296 break;
1297 case SCBeeprom:
1298 val = eepro100_read_eeprom(s);
1299 break;
1300 case 0x1b: /* PMDR (power management driver register) */
1301 val = 0;
1302 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1303 break;
1304 case 0x1d: /* general status register */
1305 /* 100 Mbps full duplex, valid link */
1306 val = 0x07;
1307 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1308 break;
1309 default:
1310 logout("addr=%s val=0x%02x\n", regname(addr), val);
1311 missing("unknown byte read");
1312 }
1313 return val;
1314 }
1315
1316 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1317 {
1318 uint16_t val;
1319 if (addr <= sizeof(s->mem) - sizeof(val)) {
1320 memcpy(&val, &s->mem[addr], sizeof(val));
1321 }
1322
1323 switch (addr) {
1324 case SCBStatus:
1325 //~ val = eepro100_read_status(s);
1326 case SCBCmd:
1327 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1328 break;
1329 case SCBeeprom:
1330 val = eepro100_read_eeprom(s);
1331 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1332 break;
1333 default:
1334 logout("addr=%s val=0x%04x\n", regname(addr), val);
1335 missing("unknown word read");
1336 }
1337 return val;
1338 }
1339
1340 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1341 {
1342 uint32_t val;
1343 if (addr <= sizeof(s->mem) - sizeof(val)) {
1344 memcpy(&val, &s->mem[addr], sizeof(val));
1345 }
1346
1347 switch (addr) {
1348 case SCBStatus:
1349 //~ val = eepro100_read_status(s);
1350 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1351 break;
1352 case SCBPointer:
1353 //~ val = eepro100_read_pointer(s);
1354 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1355 break;
1356 case SCBPort:
1357 val = eepro100_read_port(s);
1358 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1359 break;
1360 case SCBCtrlMDI:
1361 val = eepro100_read_mdi(s);
1362 break;
1363 default:
1364 logout("addr=%s val=0x%08x\n", regname(addr), val);
1365 missing("unknown longword read");
1366 }
1367 return val;
1368 }
1369
1370 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1371 {
1372 if (addr <= sizeof(s->mem) - sizeof(val)) {
1373 memcpy(&s->mem[addr], &val, sizeof(val));
1374 }
1375
1376 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1377
1378 switch (addr) {
1379 case SCBStatus:
1380 //~ eepro100_write_status(s, val);
1381 break;
1382 case SCBAck:
1383 eepro100_acknowledge(s);
1384 break;
1385 case SCBCmd:
1386 eepro100_write_command(s, val);
1387 break;
1388 case SCBIntmask:
1389 if (val & BIT(1)) {
1390 eepro100_swi_interrupt(s);
1391 }
1392 eepro100_interrupt(s, 0);
1393 break;
1394 case SCBPort + 3:
1395 case SCBFlow: /* does not exist on 82557 */
1396 case SCBFlow + 1:
1397 case SCBFlow + 2:
1398 case SCBFlow + 3:
1399 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1400 break;
1401 case SCBeeprom:
1402 eepro100_write_eeprom(s->eeprom, val);
1403 break;
1404 default:
1405 logout("addr=%s val=0x%02x\n", regname(addr), val);
1406 missing("unknown byte write");
1407 }
1408 }
1409
1410 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1411 {
1412 if (addr <= sizeof(s->mem) - sizeof(val)) {
1413 memcpy(&s->mem[addr], &val, sizeof(val));
1414 }
1415
1416 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1417
1418 switch (addr) {
1419 case SCBStatus:
1420 //~ eepro100_write_status(s, val);
1421 eepro100_acknowledge(s);
1422 break;
1423 case SCBCmd:
1424 eepro100_write_command(s, val);
1425 eepro100_write1(s, SCBIntmask, val >> 8);
1426 break;
1427 case SCBeeprom:
1428 eepro100_write_eeprom(s->eeprom, val);
1429 break;
1430 default:
1431 logout("addr=%s val=0x%04x\n", regname(addr), val);
1432 missing("unknown word write");
1433 }
1434 }
1435
1436 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1437 {
1438 if (addr <= sizeof(s->mem) - sizeof(val)) {
1439 memcpy(&s->mem[addr], &val, sizeof(val));
1440 }
1441
1442 switch (addr) {
1443 case SCBPointer:
1444 eepro100_write_pointer(s, val);
1445 break;
1446 case SCBPort:
1447 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1448 eepro100_write_port(s, val);
1449 break;
1450 case SCBCtrlMDI:
1451 eepro100_write_mdi(s, val);
1452 break;
1453 default:
1454 logout("addr=%s val=0x%08x\n", regname(addr), val);
1455 missing("unknown longword write");
1456 }
1457 }
1458
1459 /*****************************************************************************
1460 *
1461 * Port mapped I/O.
1462 *
1463 ****************************************************************************/
1464
1465 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1466 {
1467 EEPRO100State *s = opaque;
1468 //~ logout("addr=%s\n", regname(addr));
1469 return eepro100_read1(s, addr - s->region[1]);
1470 }
1471
1472 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1473 {
1474 EEPRO100State *s = opaque;
1475 return eepro100_read2(s, addr - s->region[1]);
1476 }
1477
1478 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1479 {
1480 EEPRO100State *s = opaque;
1481 return eepro100_read4(s, addr - s->region[1]);
1482 }
1483
1484 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1485 {
1486 EEPRO100State *s = opaque;
1487 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1488 eepro100_write1(s, addr - s->region[1], val);
1489 }
1490
1491 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1492 {
1493 EEPRO100State *s = opaque;
1494 eepro100_write2(s, addr - s->region[1], val);
1495 }
1496
1497 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1498 {
1499 EEPRO100State *s = opaque;
1500 eepro100_write4(s, addr - s->region[1], val);
1501 }
1502
1503 /***********************************************************/
1504 /* PCI EEPRO100 definitions */
1505
1506 static void pci_map(PCIDevice * pci_dev, int region_num,
1507 pcibus_t addr, pcibus_t size, int type)
1508 {
1509 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1510
1511 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1512 "size=0x%08"FMT_PCIBUS", type=%d\n",
1513 region_num, addr, size, type));
1514
1515 assert(region_num == 1);
1516 register_ioport_write(addr, size, 1, ioport_write1, s);
1517 register_ioport_read(addr, size, 1, ioport_read1, s);
1518 register_ioport_write(addr, size, 2, ioport_write2, s);
1519 register_ioport_read(addr, size, 2, ioport_read2, s);
1520 register_ioport_write(addr, size, 4, ioport_write4, s);
1521 register_ioport_read(addr, size, 4, ioport_read4, s);
1522
1523 s->region[region_num] = addr;
1524 }
1525
1526 /*****************************************************************************
1527 *
1528 * Memory mapped I/O.
1529 *
1530 ****************************************************************************/
1531
1532 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1533 {
1534 EEPRO100State *s = opaque;
1535 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1536 eepro100_write1(s, addr, val);
1537 }
1538
1539 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1540 {
1541 EEPRO100State *s = opaque;
1542 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1543 eepro100_write2(s, addr, val);
1544 }
1545
1546 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1547 {
1548 EEPRO100State *s = opaque;
1549 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1550 eepro100_write4(s, addr, val);
1551 }
1552
1553 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1554 {
1555 EEPRO100State *s = opaque;
1556 //~ logout("addr=%s\n", regname(addr));
1557 return eepro100_read1(s, addr);
1558 }
1559
1560 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1561 {
1562 EEPRO100State *s = opaque;
1563 //~ logout("addr=%s\n", regname(addr));
1564 return eepro100_read2(s, addr);
1565 }
1566
1567 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1568 {
1569 EEPRO100State *s = opaque;
1570 //~ logout("addr=%s\n", regname(addr));
1571 return eepro100_read4(s, addr);
1572 }
1573
1574 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1575 pci_mmio_writeb,
1576 pci_mmio_writew,
1577 pci_mmio_writel
1578 };
1579
1580 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1581 pci_mmio_readb,
1582 pci_mmio_readw,
1583 pci_mmio_readl
1584 };
1585
1586 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1587 pcibus_t addr, pcibus_t size, int type)
1588 {
1589 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1590
1591 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1592 "size=0x%08"FMT_PCIBUS", type=%d\n",
1593 region_num, addr, size, type));
1594
1595 if (region_num == 0) {
1596 /* Map control / status registers. */
1597 cpu_register_physical_memory(addr, size, s->mmio_index);
1598 s->region[region_num] = addr;
1599 }
1600 }
1601
1602 static int nic_can_receive(VLANClientState *vc)
1603 {
1604 EEPRO100State *s = vc->opaque;
1605 TRACE(RXTX, logout("%p\n", s));
1606 return get_ru_state(s) == ru_ready;
1607 //~ return !eepro100_buffer_full(s);
1608 }
1609
1610 static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size)
1611 {
1612 /* TODO:
1613 * - Magic packets should set bit 30 in power management driver register.
1614 * - Interesting packets should set bit 29 in power management driver register.
1615 */
1616 EEPRO100State *s = vc->opaque;
1617 uint16_t rfd_status = 0xa000;
1618 static const uint8_t broadcast_macaddr[6] =
1619 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1620
1621 /* TODO: check multiple IA bit. */
1622 if (s->configuration[20] & BIT(6)) {
1623 missing("Multiple IA bit");
1624 return -1;
1625 }
1626
1627 if (s->configuration[8] & 0x80) {
1628 /* CSMA is disabled. */
1629 logout("%p received while CSMA is disabled\n", s);
1630 return -1;
1631 } else if (size < 64 && (s->configuration[7] & 1)) {
1632 /* Short frame and configuration byte 7/0 (discard short receive) set:
1633 * Short frame is discarded */
1634 logout("%p received short frame (%zu byte)\n", s, size);
1635 s->statistics.rx_short_frame_errors++;
1636 //~ return -1;
1637 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1638 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1639 * Long frames are discarded. */
1640 logout("%p received long frame (%zu byte), ignored\n", s, size);
1641 return -1;
1642 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
1643 /* Frame matches individual address. */
1644 /* TODO: check configuration byte 15/4 (ignore U/L). */
1645 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1646 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1647 /* Broadcast frame. */
1648 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1649 rfd_status |= 0x0002;
1650 } else if (buf[0] & 0x01) { // !!!
1651 /* Multicast frame. */
1652 TRACE(RXTX, logout("%p received multicast, len=%zu\n", s, size));
1653 /* TODO: check multicast all bit. */
1654 if (s->configuration[21] & BIT(3)) {
1655 missing("Multicast All bit");
1656 }
1657 int mcast_idx = compute_mcast_idx(buf);
1658 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
1659 return size;
1660 }
1661 rfd_status |= 0x0002;
1662 } else if (s->configuration[15] & 1) {
1663 /* Promiscuous: receive all. */
1664 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1665 rfd_status |= 0x0004;
1666 } else {
1667 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1668 nic_dump(buf, size)));
1669 return size;
1670 }
1671
1672 if (get_ru_state(s) != ru_ready) {
1673 /* No resources available. */
1674 logout("no resources, state=%u\n", get_ru_state(s));
1675 s->statistics.rx_resource_errors++;
1676 //~ assert(!"no resources");
1677 return -1;
1678 }
1679 //~ !!!
1680 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1681 eepro100_rx_t rx;
1682 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1683 offsetof(eepro100_rx_t, packet));
1684 uint16_t rfd_command = le16_to_cpu(rx.command);
1685 uint16_t rfd_size = le16_to_cpu(rx.size);
1686
1687 if (size > rfd_size) {
1688 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1689 "(%zu bytes); data truncated\n", rfd_size, size);
1690 size = rfd_size;
1691 }
1692 if (size < 64) {
1693 rfd_status |= 0x0080;
1694 }
1695 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1696 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1697 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1698 rfd_status);
1699 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1700 /* Early receive interrupt not supported. */
1701 //~ eepro100_er_interrupt(s);
1702 /* Receive CRC Transfer not supported. */
1703 if (s->configuration[18] & 4) {
1704 missing("Receive CRC Transfer");
1705 return -1;
1706 }
1707 /* TODO: check stripping enable bit. */
1708 //~ assert(!(s->configuration[17] & 1));
1709 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1710 offsetof(eepro100_rx_t, packet), buf, size);
1711 s->statistics.rx_good_frames++;
1712 eepro100_fr_interrupt(s);
1713 s->ru_offset = le32_to_cpu(rx.link);
1714 if (rfd_command & 0x8000) {
1715 /* EL bit is set, so this was the last frame. */
1716 logout("receive: Running out of frames\n");
1717 set_ru_state(s, ru_suspended);
1718 }
1719 if (rfd_command & 0x4000) {
1720 /* S bit is set. */
1721 set_ru_state(s, ru_suspended);
1722 }
1723 return size;
1724 }
1725
1726 static const VMStateDescription vmstate_eepro100 = {
1727 .version_id = 3,
1728 .minimum_version_id = 2,
1729 .minimum_version_id_old = 2,
1730 .fields = (VMStateField []) {
1731 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1732 VMSTATE_UNUSED(32),
1733 VMSTATE_BUFFER(mult, EEPRO100State),
1734 VMSTATE_BUFFER(mem, EEPRO100State),
1735 /* Save all members of struct between scb_stat and mem. */
1736 VMSTATE_UINT8(scb_stat, EEPRO100State),
1737 VMSTATE_UINT8(int_stat, EEPRO100State),
1738 VMSTATE_UNUSED(3*4),
1739 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1740 VMSTATE_UNUSED(19*4),
1741 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1742 /* The eeprom should be saved and restored by its own routines. */
1743 VMSTATE_UINT32(device, EEPRO100State),
1744 /* TODO check device. */
1745 VMSTATE_UINT32(pointer, EEPRO100State),
1746 VMSTATE_UINT32(cu_base, EEPRO100State),
1747 VMSTATE_UINT32(cu_offset, EEPRO100State),
1748 VMSTATE_UINT32(ru_base, EEPRO100State),
1749 VMSTATE_UINT32(ru_offset, EEPRO100State),
1750 VMSTATE_UINT32(statsaddr, EEPRO100State),
1751 /* Save eepro100_stats_t statistics. */
1752 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1753 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1754 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1755 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1756 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1757 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1758 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1759 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1760 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1761 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1762 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1763 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1764 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1765 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1766 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1767 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1768 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1769 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1770 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1771 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1772 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1773 #if 0
1774 VMSTATE_UINT16(status, EEPRO100State),
1775 #endif
1776 /* Configuration bytes. */
1777 VMSTATE_BUFFER(configuration, EEPRO100State),
1778 VMSTATE_END_OF_LIST()
1779 }
1780 };
1781
1782 static void nic_cleanup(VLANClientState *vc)
1783 {
1784 EEPRO100State *s = vc->opaque;
1785
1786 s->vc = NULL;
1787 }
1788
1789 static int pci_nic_uninit(PCIDevice *pci_dev)
1790 {
1791 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1792
1793 cpu_unregister_io_memory(s->mmio_index);
1794 vmstate_unregister(s->vmstate, s);
1795 eeprom93xx_free(s->eeprom);
1796 qemu_del_vlan_client(s->vc);
1797 return 0;
1798 }
1799
1800 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1801 {
1802 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1803
1804 TRACE(OTHER, logout("\n"));
1805
1806 s->device = device;
1807
1808 pci_reset(s);
1809
1810 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1811 * i82559 and later support 64 or 256 word EEPROM. */
1812 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1813
1814 /* Handler for memory-mapped I/O */
1815 s->mmio_index =
1816 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1817
1818 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1819 PCI_BASE_ADDRESS_SPACE_MEMORY |
1820 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1821 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1822 pci_map);
1823 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1824 pci_mmio_map);
1825
1826 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1827 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
1828 assert(s->region[1] == 0);
1829
1830 nic_reset(s);
1831
1832 s->vc = qemu_new_vlan_client(NET_CLIENT_TYPE_NIC,
1833 s->conf.vlan, s->conf.peer,
1834 pci_dev->qdev.info->name, pci_dev->qdev.id,
1835 nic_can_receive, nic_receive, NULL, NULL,
1836 nic_cleanup, s);
1837
1838 qemu_format_nic_info_str(s->vc, s->conf.macaddr.a);
1839 TRACE(OTHER, logout("%s\n", s->vc->info_str));
1840
1841 qemu_register_reset(nic_reset, s);
1842
1843 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1844 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1845 s->vmstate->name = s->vc->model;
1846 vmstate_register(-1, s->vmstate, s);
1847
1848 if (!pci_dev->qdev.hotplugged) {
1849 static int loaded = 0;
1850 if (!loaded) {
1851 char fname[32];
1852 snprintf(fname, sizeof(fname), "pxe-%s.bin", s->vc->model);
1853 rom_add_option(fname);
1854 loaded = 1;
1855 }
1856 }
1857 return 0;
1858 }
1859
1860 static int pci_i82550_init(PCIDevice *pci_dev)
1861 {
1862 return nic_init(pci_dev, i82550);
1863 }
1864
1865 static int pci_i82551_init(PCIDevice *pci_dev)
1866 {
1867 return nic_init(pci_dev, i82551);
1868 }
1869
1870 static int pci_i82557a_init(PCIDevice *pci_dev)
1871 {
1872 return nic_init(pci_dev, i82557A);
1873 }
1874
1875 static int pci_i82557b_init(PCIDevice *pci_dev)
1876 {
1877 return nic_init(pci_dev, i82557B);
1878 }
1879
1880 static int pci_i82557c_init(PCIDevice *pci_dev)
1881 {
1882 return nic_init(pci_dev, i82557C);
1883 }
1884
1885 static int pci_i82558a_init(PCIDevice *pci_dev)
1886 {
1887 return nic_init(pci_dev, i82558A);
1888 }
1889
1890 static int pci_i82558b_init(PCIDevice *pci_dev)
1891 {
1892 return nic_init(pci_dev, i82558B);
1893 }
1894
1895 static int pci_i82559a_init(PCIDevice *pci_dev)
1896 {
1897 return nic_init(pci_dev, i82559A);
1898 }
1899
1900 static int pci_i82559b_init(PCIDevice *pci_dev)
1901 {
1902 return nic_init(pci_dev, i82559B);
1903 }
1904
1905 static int pci_i82559c_init(PCIDevice *pci_dev)
1906 {
1907 return nic_init(pci_dev, i82559C);
1908 }
1909
1910 static int pci_i82559er_init(PCIDevice *pci_dev)
1911 {
1912 return nic_init(pci_dev, i82559ER);
1913 }
1914
1915 static int pci_i82562_init(PCIDevice *pci_dev)
1916 {
1917 return nic_init(pci_dev, i82562);
1918 }
1919
1920 static PCIDeviceInfo eepro100_info[] = {
1921 {
1922 .qdev.name = "i82550",
1923 .qdev.size = sizeof(EEPRO100State),
1924 .init = pci_i82550_init,
1925 .exit = pci_nic_uninit,
1926 .qdev.props = (Property[]) {
1927 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1928 DEFINE_PROP_END_OF_LIST(),
1929 },
1930 },{
1931 .qdev.name = "i82551",
1932 .qdev.size = sizeof(EEPRO100State),
1933 .init = pci_i82551_init,
1934 .exit = pci_nic_uninit,
1935 .qdev.props = (Property[]) {
1936 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1937 DEFINE_PROP_END_OF_LIST(),
1938 },
1939 },{
1940 .qdev.name = "i82557a",
1941 .qdev.size = sizeof(EEPRO100State),
1942 .init = pci_i82557a_init,
1943 .exit = pci_nic_uninit,
1944 .qdev.props = (Property[]) {
1945 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1946 DEFINE_PROP_END_OF_LIST(),
1947 },
1948 },{
1949 .qdev.name = "i82557b",
1950 .qdev.size = sizeof(EEPRO100State),
1951 .init = pci_i82557b_init,
1952 .exit = pci_nic_uninit,
1953 .qdev.props = (Property[]) {
1954 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1955 DEFINE_PROP_END_OF_LIST(),
1956 },
1957 },{
1958 .qdev.name = "i82557c",
1959 .qdev.size = sizeof(EEPRO100State),
1960 .init = pci_i82557c_init,
1961 .exit = pci_nic_uninit,
1962 .qdev.props = (Property[]) {
1963 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1964 DEFINE_PROP_END_OF_LIST(),
1965 },
1966 },{
1967 .qdev.name = "i82558a",
1968 .qdev.size = sizeof(EEPRO100State),
1969 .init = pci_i82558a_init,
1970 .exit = pci_nic_uninit,
1971 .qdev.props = (Property[]) {
1972 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1973 DEFINE_PROP_END_OF_LIST(),
1974 },
1975 },{
1976 .qdev.name = "i82558b",
1977 .qdev.size = sizeof(EEPRO100State),
1978 .init = pci_i82558b_init,
1979 .exit = pci_nic_uninit,
1980 .qdev.props = (Property[]) {
1981 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1982 DEFINE_PROP_END_OF_LIST(),
1983 },
1984 },{
1985 .qdev.name = "i82559a",
1986 .qdev.size = sizeof(EEPRO100State),
1987 .init = pci_i82559a_init,
1988 .exit = pci_nic_uninit,
1989 .qdev.props = (Property[]) {
1990 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
1991 DEFINE_PROP_END_OF_LIST(),
1992 },
1993 },{
1994 .qdev.name = "i82559b",
1995 .qdev.size = sizeof(EEPRO100State),
1996 .init = pci_i82559b_init,
1997 .exit = pci_nic_uninit,
1998 .qdev.props = (Property[]) {
1999 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2000 DEFINE_PROP_END_OF_LIST(),
2001 },
2002 },{
2003 .qdev.name = "i82559c",
2004 .qdev.size = sizeof(EEPRO100State),
2005 .init = pci_i82559c_init,
2006 .exit = pci_nic_uninit,
2007 .qdev.props = (Property[]) {
2008 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2009 DEFINE_PROP_END_OF_LIST(),
2010 },
2011 },{
2012 .qdev.name = "i82559er",
2013 .qdev.size = sizeof(EEPRO100State),
2014 .init = pci_i82559er_init,
2015 .exit = pci_nic_uninit,
2016 .qdev.props = (Property[]) {
2017 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2018 DEFINE_PROP_END_OF_LIST(),
2019 },
2020 },{
2021 .qdev.name = "i82562",
2022 .qdev.size = sizeof(EEPRO100State),
2023 .init = pci_i82562_init,
2024 .exit = pci_nic_uninit,
2025 .qdev.props = (Property[]) {
2026 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2027 DEFINE_PROP_END_OF_LIST(),
2028 },
2029 },{
2030 /* end of list */
2031 }
2032 };
2033
2034 static void eepro100_register_devices(void)
2035 {
2036 pci_qdev_register_many(eepro100_info);
2037 }
2038
2039 device_init(eepro100_register_devices)
Anthony Liguori's QEMU queue