hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "pci.h"
  29 #include "vmware_vga.h"
  30 #include "usb-uhci.h"
  31 #include "usb-ohci.h"
  32 #include "prep_pci.h"
  33 #include "apb_pci.h"
  34 #include "block.h"
  35 #include "sysemu.h"
  36 #include "audio/audio.h"
  37 #include "net.h"
  38 #include "smbus.h"
  39 #include "boards.h"
  40 #include "monitor.h"
  41 #include "fw_cfg.h"
  42 #include "hpet_emul.h"
  43 #include "watchdog.h"
  44 #include "smbios.h"
  45 #include "ide.h"
  46 #include "loader.h"
  47 #include "elf.h"
  48 #include "multiboot.h"
  49 #include "kvm.h"
  50
  51 /* output Bochs bios info messages */
  52 //#define DEBUG_BIOS
  53
  54 #define BIOS_FILENAME "bios.bin"
  55
  56 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
  57
  58 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  59 #define ACPI_DATA_SIZE       0x10000
  60 #define BIOS_CFG_IOPORT 0x510
  61 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  62 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  63 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  64 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  65
  66 #define MAX_IDE_BUS 2
  67
  68 static FDCtrl *floppy_controller;
  69 static RTCState *rtc_state;
  70 static PITState *pit;
  71 static PCII440FXState *i440fx_state;
  72
  73 #define E820_NR_ENTRIES         16
  74
  75 struct e820_entry {
  76     uint64_t address;
  77     uint64_t length;
  78     uint32_t type;
  79 };
  80
  81 struct e820_table {
  82     uint32_t count;
  83     struct e820_entry entry[E820_NR_ENTRIES];
  84 };
  85
  86 static struct e820_table e820_table;
  87
  88 typedef struct isa_irq_state {
  89     qemu_irq *i8259;
  90     qemu_irq *ioapic;
  91 } IsaIrqState;
  92
  93 static void isa_irq_handler(void *opaque, int n, int level)
  94 {
  95     IsaIrqState *isa = (IsaIrqState *)opaque;
  96
  97     if (n < 16) {
  98         qemu_set_irq(isa->i8259[n], level);
  99     }
 100     if (isa->ioapic)
 101         qemu_set_irq(isa->ioapic[n], level);
 102 };
 103
 104 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 105 {
 106 }
 107
 108 /* MSDOS compatibility mode FPU exception support */
 109 static qemu_irq ferr_irq;
 110 /* XXX: add IGNNE support */
 111 void cpu_set_ferr(CPUX86State *s)
 112 {
 113     qemu_irq_raise(ferr_irq);
 114 }
 115
 116 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 117 {
 118     qemu_irq_lower(ferr_irq);
 119 }
 120
 121 /* TSC handling */
 122 uint64_t cpu_get_tsc(CPUX86State *env)
 123 {
 124     return cpu_get_ticks();
 125 }
 126
 127 /* SMM support */
 128 void cpu_smm_update(CPUState *env)
 129 {
 130     if (i440fx_state && env == first_cpu)
 131         i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
 132 }
 133
 134
 135 /* IRQ handling */
 136 int cpu_get_pic_interrupt(CPUState *env)
 137 {
 138     int intno;
 139
 140     intno = apic_get_interrupt(env);
 141     if (intno >= 0) {
 142         /* set irq request if a PIC irq is still pending */
 143         /* XXX: improve that */
 144         pic_update_irq(isa_pic);
 145         return intno;
 146     }
 147     /* read the irq from the PIC */
 148     if (!apic_accept_pic_intr(env))
 149         return -1;
 150
 151     intno = pic_read_irq(isa_pic);
 152     return intno;
 153 }
 154
 155 static void pic_irq_request(void *opaque, int irq, int level)
 156 {
 157     CPUState *env = first_cpu;
 158
 159     if (env->apic_state) {
 160         while (env) {
 161             if (apic_accept_pic_intr(env))
 162                 apic_deliver_pic_intr(env, level);
 163             env = env->next_cpu;
 164         }
 165     } else {
 166         if (level)
 167             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 168         else
 169             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 170     }
 171 }
 172
 173 /* PC cmos mappings */
 174
 175 #define REG_EQUIPMENT_BYTE          0x14
 176
 177 static int cmos_get_fd_drive_type(int fd0)
 178 {
 179     int val;
 180
 181     switch (fd0) {
 182     case 0:
 183         /* 1.44 Mb 3"5 drive */
 184         val = 4;
 185         break;
 186     case 1:
 187         /* 2.88 Mb 3"5 drive */
 188         val = 5;
 189         break;
 190     case 2:
 191         /* 1.2 Mb 5"5 drive */
 192         val = 2;
 193         break;
 194     default:
 195         val = 0;
 196         break;
 197     }
 198     return val;
 199 }
 200
 201 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 202 {
 203     RTCState *s = rtc_state;
 204     int cylinders, heads, sectors;
 205     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 206     rtc_set_memory(s, type_ofs, 47);
 207     rtc_set_memory(s, info_ofs, cylinders);
 208     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 209     rtc_set_memory(s, info_ofs + 2, heads);
 210     rtc_set_memory(s, info_ofs + 3, 0xff);
 211     rtc_set_memory(s, info_ofs + 4, 0xff);
 212     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 213     rtc_set_memory(s, info_ofs + 6, cylinders);
 214     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 215     rtc_set_memory(s, info_ofs + 8, sectors);
 216 }
 217
 218 /* convert boot_device letter to something recognizable by the bios */
 219 static int boot_device2nibble(char boot_device)
 220 {
 221     switch(boot_device) {
 222     case 'a':
 223     case 'b':
 224         return 0x01; /* floppy boot */
 225     case 'c':
 226         return 0x02; /* hard drive boot */
 227     case 'd':
 228         return 0x03; /* CD-ROM boot */
 229     case 'n':
 230         return 0x04; /* Network boot */
 231     }
 232     return 0;
 233 }
 234
 235 static int set_boot_dev(RTCState *s, const char *boot_device, int fd_bootchk)
 236 {
 237 #define PC_MAX_BOOT_DEVICES 3
 238     int nbds, bds[3] = { 0, };
 239     int i;
 240
 241     nbds = strlen(boot_device);
 242     if (nbds > PC_MAX_BOOT_DEVICES) {
 243         error_report("Too many boot devices for PC");
 244         return(1);
 245     }
 246     for (i = 0; i < nbds; i++) {
 247         bds[i] = boot_device2nibble(boot_device[i]);
 248         if (bds[i] == 0) {
 249             error_report("Invalid boot device for PC: '%c'",
 250                          boot_device[i]);
 251             return(1);
 252         }
 253     }
 254     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 255     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 256     return(0);
 257 }
 258
 259 static int pc_boot_set(void *opaque, const char *boot_device)
 260 {
 261     return set_boot_dev(opaque, boot_device, 0);
 262 }
 263
 264 /* hd_table must contain 4 block drivers */
 265 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 266                       const char *boot_device, DriveInfo **hd_table)
 267 {
 268     RTCState *s = rtc_state;
 269     int val;
 270     int fd0, fd1, nb;
 271     int i;
 272
 273     /* various important CMOS locations needed by PC/Bochs bios */
 274
 275     /* memory size */
 276     val = 640; /* base memory in K */
 277     rtc_set_memory(s, 0x15, val);
 278     rtc_set_memory(s, 0x16, val >> 8);
 279
 280     val = (ram_size / 1024) - 1024;
 281     if (val > 65535)
 282         val = 65535;
 283     rtc_set_memory(s, 0x17, val);
 284     rtc_set_memory(s, 0x18, val >> 8);
 285     rtc_set_memory(s, 0x30, val);
 286     rtc_set_memory(s, 0x31, val >> 8);
 287
 288     if (above_4g_mem_size) {
 289         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 290         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 291         rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
 292     }
 293
 294     if (ram_size > (16 * 1024 * 1024))
 295         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 296     else
 297         val = 0;
 298     if (val > 65535)
 299         val = 65535;
 300     rtc_set_memory(s, 0x34, val);
 301     rtc_set_memory(s, 0x35, val >> 8);
 302
 303     /* set the number of CPU */
 304     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 305
 306     /* set boot devices, and disable floppy signature check if requested */
 307     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 308         exit(1);
 309     }
 310
 311     /* floppy type */
 312
 313     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 314     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 315
 316     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 317     rtc_set_memory(s, 0x10, val);
 318
 319     val = 0;
 320     nb = 0;
 321     if (fd0 < 3)
 322         nb++;
 323     if (fd1 < 3)
 324         nb++;
 325     switch (nb) {
 326     case 0:
 327         break;
 328     case 1:
 329         val |= 0x01; /* 1 drive, ready for boot */
 330         break;
 331     case 2:
 332         val |= 0x41; /* 2 drives, ready for boot */
 333         break;
 334     }
 335     val |= 0x02; /* FPU is there */
 336     val |= 0x04; /* PS/2 mouse installed */
 337     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 338
 339     /* hard drives */
 340
 341     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 342     if (hd_table[0])
 343         cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
 344     if (hd_table[1])
 345         cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
 346
 347     val = 0;
 348     for (i = 0; i < 4; i++) {
 349         if (hd_table[i]) {
 350             int cylinders, heads, sectors, translation;
 351             /* NOTE: bdrv_get_geometry_hint() returns the physical
 352                 geometry.  It is always such that: 1 <= sects <= 63, 1
 353                 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 354                 geometry can be different if a translation is done. */
 355             translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
 356             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 357                 bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
 358                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 359                     /* No translation. */
 360                     translation = 0;
 361                 } else {
 362                     /* LBA translation. */
 363                     translation = 1;
 364                 }
 365             } else {
 366                 translation--;
 367             }
 368             val |= translation << (i * 2);
 369         }
 370     }
 371     rtc_set_memory(s, 0x39, val);
 372 }
 373
 374 void ioport_set_a20(int enable)
 375 {
 376     /* XXX: send to all CPUs ? */
 377     cpu_x86_set_a20(first_cpu, enable);
 378 }
 379
 380 int ioport_get_a20(void)
 381 {
 382     return ((first_cpu->a20_mask >> 20) & 1);
 383 }
 384
 385 static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
 386 {
 387     ioport_set_a20((val >> 1) & 1);
 388     /* XXX: bit 0 is fast reset */
 389 }
 390
 391 static uint32_t ioport92_read(void *opaque, uint32_t addr)
 392 {
 393     return ioport_get_a20() << 1;
 394 }
 395
 396 /***********************************************************/
 397 /* Bochs BIOS debug ports */
 398
 399 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 400 {
 401     static const char shutdown_str[8] = "Shutdown";
 402     static int shutdown_index = 0;
 403
 404     switch(addr) {
 405         /* Bochs BIOS messages */
 406     case 0x400:
 407     case 0x401:
 408         fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
 409         exit(1);
 410     case 0x402:
 411     case 0x403:
 412 #ifdef DEBUG_BIOS
 413         fprintf(stderr, "%c", val);
 414 #endif
 415         break;
 416     case 0x8900:
 417         /* same as Bochs power off */
 418         if (val == shutdown_str[shutdown_index]) {
 419             shutdown_index++;
 420             if (shutdown_index == 8) {
 421                 shutdown_index = 0;
 422                 qemu_system_shutdown_request();
 423             }
 424         } else {
 425             shutdown_index = 0;
 426         }
 427         break;
 428
 429         /* LGPL'ed VGA BIOS messages */
 430     case 0x501:
 431     case 0x502:
 432         fprintf(stderr, "VGA BIOS panic, line %d\n", val);
 433         exit(1);
 434     case 0x500:
 435     case 0x503:
 436 #ifdef DEBUG_BIOS
 437         fprintf(stderr, "%c", val);
 438 #endif
 439         break;
 440     }
 441 }
 442
 443 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 444 {
 445     int index = e820_table.count;
 446     struct e820_entry *entry;
 447
 448     if (index >= E820_NR_ENTRIES)
 449         return -EBUSY;
 450     entry = &e820_table.entry[index];
 451
 452     entry->address = address;
 453     entry->length = length;
 454     entry->type = type;
 455
 456     e820_table.count++;
 457     return e820_table.count;
 458 }
 459
 460 static void *bochs_bios_init(void)
 461 {
 462     void *fw_cfg;
 463     uint8_t *smbios_table;
 464     size_t smbios_len;
 465     uint64_t *numa_fw_cfg;
 466     int i, j;
 467
 468     register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
 469     register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
 470     register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
 471     register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
 472     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 473
 474     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 475     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 476     register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
 477     register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
 478
 479     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 480
 481     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 482     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 483     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 484                      acpi_tables_len);
 485     fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
 486
 487     smbios_table = smbios_get_table(&smbios_len);
 488     if (smbios_table)
 489         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 490                          smbios_table, smbios_len);
 491     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 492                      sizeof(struct e820_table));
 493
 494     /* allocate memory for the NUMA channel: one (64bit) word for the number
 495      * of nodes, one word for each VCPU->node and one word for each node to
 496      * hold the amount of memory.
 497      */
 498     numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
 499     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 500     for (i = 0; i < smp_cpus; i++) {
 501         for (j = 0; j < nb_numa_nodes; j++) {
 502             if (node_cpumask[j] & (1 << i)) {
 503                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 504                 break;
 505             }
 506         }
 507     }
 508     for (i = 0; i < nb_numa_nodes; i++) {
 509         numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 510     }
 511     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 512                      (1 + smp_cpus + nb_numa_nodes) * 8);
 513
 514     return fw_cfg;
 515 }
 516
 517 static long get_file_size(FILE *f)
 518 {
 519     long where, size;
 520
 521     /* XXX: on Unix systems, using fstat() probably makes more sense */
 522
 523     where = ftell(f);
 524     fseek(f, 0, SEEK_END);
 525     size = ftell(f);
 526     fseek(f, where, SEEK_SET);
 527
 528     return size;
 529 }
 530
 531 static void load_linux(void *fw_cfg,
 532                        const char *kernel_filename,
 533                        const char *initrd_filename,
 534                        const char *kernel_cmdline,
 535                        target_phys_addr_t max_ram_size)
 536 {
 537     uint16_t protocol;
 538     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 539     uint32_t initrd_max;
 540     uint8_t header[8192], *setup, *kernel, *initrd_data;
 541     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 542     FILE *f;
 543     char *vmode;
 544
 545     /* Align to 16 bytes as a paranoia measure */
 546     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 547
 548     /* load the kernel header */
 549     f = fopen(kernel_filename, "rb");
 550     if (!f || !(kernel_size = get_file_size(f)) ||
 551         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 552         MIN(ARRAY_SIZE(header), kernel_size)) {
 553         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 554                 kernel_filename, strerror(errno));
 555         exit(1);
 556     }
 557
 558     /* kernel protocol version */
 559 #if 0
 560     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 561 #endif
 562     if (ldl_p(header+0x202) == 0x53726448)
 563         protocol = lduw_p(header+0x206);
 564     else {
 565         /* This looks like a multiboot kernel. If it is, let's stop
 566            treating it like a Linux kernel. */
 567         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 568                            kernel_cmdline, kernel_size, header))
 569             return;
 570         protocol = 0;
 571     }
 572
 573     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 574         /* Low kernel */
 575         real_addr    = 0x90000;
 576         cmdline_addr = 0x9a000 - cmdline_size;
 577         prot_addr    = 0x10000;
 578     } else if (protocol < 0x202) {
 579         /* High but ancient kernel */
 580         real_addr    = 0x90000;
 581         cmdline_addr = 0x9a000 - cmdline_size;
 582         prot_addr    = 0x100000;
 583     } else {
 584         /* High and recent kernel */
 585         real_addr    = 0x10000;
 586         cmdline_addr = 0x20000;
 587         prot_addr    = 0x100000;
 588     }
 589
 590 #if 0
 591     fprintf(stderr,
 592             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 593             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 594             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 595             real_addr,
 596             cmdline_addr,
 597             prot_addr);
 598 #endif
 599
 600     /* highest address for loading the initrd */
 601     if (protocol >= 0x203)
 602         initrd_max = ldl_p(header+0x22c);
 603     else
 604         initrd_max = 0x37ffffff;
 605
 606     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 607         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 608
 609     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 610     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 611     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 612                      (uint8_t*)strdup(kernel_cmdline),
 613                      strlen(kernel_cmdline)+1);
 614
 615     if (protocol >= 0x202) {
 616         stl_p(header+0x228, cmdline_addr);
 617     } else {
 618         stw_p(header+0x20, 0xA33F);
 619         stw_p(header+0x22, cmdline_addr-real_addr);
 620     }
 621
 622     /* handle vga= parameter */
 623     vmode = strstr(kernel_cmdline, "vga=");
 624     if (vmode) {
 625         unsigned int video_mode;
 626         /* skip "vga=" */
 627         vmode += 4;
 628         if (!strncmp(vmode, "normal", 6)) {
 629             video_mode = 0xffff;
 630         } else if (!strncmp(vmode, "ext", 3)) {
 631             video_mode = 0xfffe;
 632         } else if (!strncmp(vmode, "ask", 3)) {
 633             video_mode = 0xfffd;
 634         } else {
 635             video_mode = strtol(vmode, NULL, 0);
 636         }
 637         stw_p(header+0x1fa, video_mode);
 638     }
 639
 640     /* loader type */
 641     /* High nybble = B reserved for Qemu; low nybble is revision number.
 642        If this code is substantially changed, you may want to consider
 643        incrementing the revision. */
 644     if (protocol >= 0x200)
 645         header[0x210] = 0xB0;
 646
 647     /* heap */
 648     if (protocol >= 0x201) {
 649         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 650         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 651     }
 652
 653     /* load initrd */
 654     if (initrd_filename) {
 655         if (protocol < 0x200) {
 656             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 657             exit(1);
 658         }
 659
 660         initrd_size = get_image_size(initrd_filename);
 661         if (initrd_size < 0) {
 662             fprintf(stderr, "qemu: error reading initrd %s\n",
 663                     initrd_filename);
 664             exit(1);
 665         }
 666
 667         initrd_addr = (initrd_max-initrd_size) & ~4095;
 668
 669         initrd_data = qemu_malloc(initrd_size);
 670         load_image(initrd_filename, initrd_data);
 671
 672         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 673         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 674         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 675
 676         stl_p(header+0x218, initrd_addr);
 677         stl_p(header+0x21c, initrd_size);
 678     }
 679
 680     /* load kernel and setup */
 681     setup_size = header[0x1f1];
 682     if (setup_size == 0)
 683         setup_size = 4;
 684     setup_size = (setup_size+1)*512;
 685     kernel_size -= setup_size;
 686
 687     setup  = qemu_malloc(setup_size);
 688     kernel = qemu_malloc(kernel_size);
 689     fseek(f, 0, SEEK_SET);
 690     if (fread(setup, 1, setup_size, f) != setup_size) {
 691         fprintf(stderr, "fread() failed\n");
 692         exit(1);
 693     }
 694     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 695         fprintf(stderr, "fread() failed\n");
 696         exit(1);
 697     }
 698     fclose(f);
 699     memcpy(setup, header, MIN(sizeof(header), setup_size));
 700
 701     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 702     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 703     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 704
 705     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 706     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 707     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 708
 709     option_rom[nb_option_roms] = "linuxboot.bin";
 710     nb_option_roms++;
 711 }
 712
 713 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 714 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 715 static const int ide_irq[2] = { 14, 15 };
 716
 717 #define NE2000_NB_MAX 6
 718
 719 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 720                                               0x280, 0x380 };
 721 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 722
 723 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 724 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 725
 726 #ifdef HAS_AUDIO
 727 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 728 {
 729     struct soundhw *c;
 730
 731     for (c = soundhw; c->name; ++c) {
 732         if (c->enabled) {
 733             if (c->isa) {
 734                 c->init.init_isa(pic);
 735             } else {
 736                 if (pci_bus) {
 737                     c->init.init_pci(pci_bus);
 738                 }
 739             }
 740         }
 741     }
 742 }
 743 #endif
 744
 745 static void pc_init_ne2k_isa(NICInfo *nd)
 746 {
 747     static int nb_ne2k = 0;
 748
 749     if (nb_ne2k == NE2000_NB_MAX)
 750         return;
 751     isa_ne2000_init(ne2000_io[nb_ne2k],
 752                     ne2000_irq[nb_ne2k], nd);
 753     nb_ne2k++;
 754 }
 755
 756 int cpu_is_bsp(CPUState *env)
 757 {
 758     /* We hard-wire the BSP to the first CPU. */
 759     return env->cpu_index == 0;
 760 }
 761
 762 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 763    BIOS will read it and start S3 resume at POST Entry */
 764 static void cmos_set_s3_resume(void *opaque, int irq, int level)
 765 {
 766     RTCState *s = opaque;
 767
 768     if (level) {
 769         rtc_set_memory(s, 0xF, 0xFE);
 770     }
 771 }
 772
 773 static void acpi_smi_interrupt(void *opaque, int irq, int level)
 774 {
 775     CPUState *s = opaque;
 776
 777     if (level) {
 778         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 779     }
 780 }
 781
 782 static CPUState *pc_new_cpu(const char *cpu_model)
 783 {
 784     CPUState *env;
 785
 786     env = cpu_init(cpu_model);
 787     if (!env) {
 788         fprintf(stderr, "Unable to find x86 CPU definition\n");
 789         exit(1);
 790     }
 791     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 792         env->cpuid_apic_id = env->cpu_index;
 793         /* APIC reset callback resets cpu */
 794         apic_init(env);
 795     } else {
 796         qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
 797     }
 798     return env;
 799 }
 800
 801 /* PC hardware initialisation */
 802 static void pc_init1(ram_addr_t ram_size,
 803                      const char *boot_device,
 804                      const char *kernel_filename,
 805                      const char *kernel_cmdline,
 806                      const char *initrd_filename,
 807                      const char *cpu_model,
 808                      int pci_enabled)
 809 {
 810     char *filename;
 811     int ret, linux_boot, i;
 812     ram_addr_t ram_addr, bios_offset, option_rom_offset;
 813     ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
 814     int bios_size, isa_bios_size;
 815     PCIBus *pci_bus;
 816     int piix3_devfn = -1;
 817     qemu_irq *cpu_irq;
 818     qemu_irq *isa_irq;
 819     qemu_irq *i8259;
 820     qemu_irq *cmos_s3;
 821     qemu_irq *smi_irq;
 822     IsaIrqState *isa_irq_state;
 823     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 824     DriveInfo *fd[MAX_FD];
 825     void *fw_cfg;
 826
 827     if (ram_size >= 0xe0000000 ) {
 828         above_4g_mem_size = ram_size - 0xe0000000;
 829         below_4g_mem_size = 0xe0000000;
 830     } else {
 831         below_4g_mem_size = ram_size;
 832     }
 833
 834     linux_boot = (kernel_filename != NULL);
 835
 836     /* init CPUs */
 837     if (cpu_model == NULL) {
 838 #ifdef TARGET_X86_64
 839         cpu_model = "qemu64";
 840 #else
 841         cpu_model = "qemu32";
 842 #endif
 843     }
 844
 845     for (i = 0; i < smp_cpus; i++) {
 846         pc_new_cpu(cpu_model);
 847     }
 848
 849     vmport_init();
 850
 851     /* allocate RAM */
 852     ram_addr = qemu_ram_alloc(below_4g_mem_size);
 853     cpu_register_physical_memory(0, 0xa0000, ram_addr);
 854     cpu_register_physical_memory(0x100000,
 855                  below_4g_mem_size - 0x100000,
 856                  ram_addr + 0x100000);
 857
 858     /* above 4giga memory allocation */
 859     if (above_4g_mem_size > 0) {
 860 #if TARGET_PHYS_ADDR_BITS == 32
 861         hw_error("To much RAM for 32-bit physical address");
 862 #else
 863         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 864         cpu_register_physical_memory(0x100000000ULL,
 865                                      above_4g_mem_size,
 866                                      ram_addr);
 867 #endif
 868     }
 869
 870
 871     /* BIOS load */
 872     if (bios_name == NULL)
 873         bios_name = BIOS_FILENAME;
 874     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 875     if (filename) {
 876         bios_size = get_image_size(filename);
 877     } else {
 878         bios_size = -1;
 879     }
 880     if (bios_size <= 0 ||
 881         (bios_size % 65536) != 0) {
 882         goto bios_error;
 883     }
 884     bios_offset = qemu_ram_alloc(bios_size);
 885     ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
 886     if (ret != 0) {
 887     bios_error:
 888         fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
 889         exit(1);
 890     }
 891     if (filename) {
 892         qemu_free(filename);
 893     }
 894     /* map the last 128KB of the BIOS in ISA space */
 895     isa_bios_size = bios_size;
 896     if (isa_bios_size > (128 * 1024))
 897         isa_bios_size = 128 * 1024;
 898     cpu_register_physical_memory(0x100000 - isa_bios_size,
 899                                  isa_bios_size,
 900                                  (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
 901
 902     option_rom_offset = qemu_ram_alloc(PC_ROM_SIZE);
 903     cpu_register_physical_memory(PC_ROM_MIN_VGA, PC_ROM_SIZE, option_rom_offset);
 904
 905     /* map all the bios at the top of memory */
 906     cpu_register_physical_memory((uint32_t)(-bios_size),
 907                                  bios_size, bios_offset | IO_MEM_ROM);
 908
 909     fw_cfg = bochs_bios_init();
 910     rom_set_fw(fw_cfg);
 911
 912     if (linux_boot) {
 913         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 914     }
 915
 916     for (i = 0; i < nb_option_roms; i++) {
 917         rom_add_option(option_rom[i]);
 918     }
 919
 920     cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
 921     i8259 = i8259_init(cpu_irq[0]);
 922     isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
 923     isa_irq_state->i8259 = i8259;
 924     isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
 925
 926     if (pci_enabled) {
 927         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
 928     } else {
 929         pci_bus = NULL;
 930         isa_bus_new(NULL);
 931     }
 932     isa_bus_irqs(isa_irq);
 933
 934     ferr_irq = isa_reserve_irq(13);
 935
 936     /* init basic PC hardware */
 937     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
 938
 939     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
 940
 941     if (cirrus_vga_enabled) {
 942         if (pci_enabled) {
 943             pci_cirrus_vga_init(pci_bus);
 944         } else {
 945             isa_cirrus_vga_init();
 946         }
 947     } else if (vmsvga_enabled) {
 948         if (pci_enabled)
 949             pci_vmsvga_init(pci_bus);
 950         else
 951             fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
 952     } else if (std_vga_enabled) {
 953         if (pci_enabled) {
 954             pci_vga_init(pci_bus, 0, 0);
 955         } else {
 956             isa_vga_init();
 957         }
 958     }
 959
 960     rtc_state = rtc_init(2000);
 961
 962     qemu_register_boot_set(pc_boot_set, rtc_state);
 963
 964     register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
 965     register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
 966
 967     if (pci_enabled) {
 968         isa_irq_state->ioapic = ioapic_init();
 969     }
 970     pit = pit_init(0x40, isa_reserve_irq(0));
 971     pcspk_init(pit);
 972     if (!no_hpet) {
 973         hpet_init(isa_irq);
 974     }
 975
 976     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 977         if (serial_hds[i]) {
 978             serial_isa_init(i, serial_hds[i]);
 979         }
 980     }
 981
 982     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 983         if (parallel_hds[i]) {
 984             parallel_init(i, parallel_hds[i]);
 985         }
 986     }
 987
 988     for(i = 0; i < nb_nics; i++) {
 989         NICInfo *nd = &nd_table[i];
 990
 991         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
 992             pc_init_ne2k_isa(nd);
 993         else
 994             pci_nic_init_nofail(nd, "e1000", NULL);
 995     }
 996
 997     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 998         fprintf(stderr, "qemu: too many IDE bus\n");
 999         exit(1);
1000     }
1001
1002     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1003         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1004     }
1005
1006     if (pci_enabled) {
1007         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
1008     } else {
1009         for(i = 0; i < MAX_IDE_BUS; i++) {
1010             isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
1011                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1012         }
1013     }
1014
1015     isa_create_simple("i8042");
1016     DMA_init(0);
1017 #ifdef HAS_AUDIO
1018     audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
1019 #endif
1020
1021     for(i = 0; i < MAX_FD; i++) {
1022         fd[i] = drive_get(IF_FLOPPY, 0, i);
1023     }
1024     floppy_controller = fdctrl_init_isa(fd);
1025
1026     cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1027
1028     if (pci_enabled && usb_enabled) {
1029         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1030     }
1031
1032     if (pci_enabled && acpi_enabled) {
1033         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1034         i2c_bus *smbus;
1035
1036         cmos_s3 = qemu_allocate_irqs(cmos_set_s3_resume, rtc_state, 1);
1037         smi_irq = qemu_allocate_irqs(acpi_smi_interrupt, first_cpu, 1);
1038         /* TODO: Populate SPD eeprom data.  */
1039         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1040                               isa_reserve_irq(9), *cmos_s3, *smi_irq,
1041                               kvm_enabled());
1042         for (i = 0; i < 8; i++) {
1043             DeviceState *eeprom;
1044             eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1045             qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
1046             qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1047             qdev_init_nofail(eeprom);
1048         }
1049         piix4_acpi_system_hot_add_init(pci_bus);
1050     }
1051
1052     if (i440fx_state) {
1053         i440fx_init_memory_mappings(i440fx_state);
1054     }
1055
1056     if (pci_enabled) {
1057         int max_bus;
1058         int bus;
1059
1060         max_bus = drive_get_max_bus(IF_SCSI);
1061         for (bus = 0; bus <= max_bus; bus++) {
1062             pci_create_simple(pci_bus, -1, "lsi53c895a");
1063         }
1064     }
1065 }
1066
1067 static void pc_init_pci(ram_addr_t ram_size,
1068                         const char *boot_device,
1069                         const char *kernel_filename,
1070                         const char *kernel_cmdline,
1071                         const char *initrd_filename,
1072                         const char *cpu_model)
1073 {
1074     pc_init1(ram_size, boot_device,
1075              kernel_filename, kernel_cmdline,
1076              initrd_filename, cpu_model, 1);
1077 }
1078
1079 static void pc_init_isa(ram_addr_t ram_size,
1080                         const char *boot_device,
1081                         const char *kernel_filename,
1082                         const char *kernel_cmdline,
1083                         const char *initrd_filename,
1084                         const char *cpu_model)
1085 {
1086     if (cpu_model == NULL)
1087         cpu_model = "486";
1088     pc_init1(ram_size, boot_device,
1089              kernel_filename, kernel_cmdline,
1090              initrd_filename, cpu_model, 0);
1091 }
1092
1093 static QEMUMachine pc_machine = {
1094     .name = "pc-0.13",
1095     .alias = "pc",
1096     .desc = "Standard PC",
1097     .init = pc_init_pci,
1098     .max_cpus = 255,
1099     .is_default = 1,
1100 };
1101
1102 static QEMUMachine pc_machine_v0_12 = {
1103     .name = "pc-0.12",
1104     .desc = "Standard PC",
1105     .init = pc_init_pci,
1106     .max_cpus = 255,
1107     .compat_props = (GlobalProperty[]) {
1108         {
1109             .driver   = "virtio-serial-pci",
1110             .property = "max_nr_ports",
1111             .value    = stringify(1),
1112         },{
1113             .driver   = "virtio-serial-pci",
1114             .property = "vectors",
1115             .value    = stringify(0),
1116         },
1117         { /* end of list */ }
1118     }
1119 };
1120
1121 static QEMUMachine pc_machine_v0_11 = {
1122     .name = "pc-0.11",
1123     .desc = "Standard PC, qemu 0.11",
1124     .init = pc_init_pci,
1125     .max_cpus = 255,
1126     .compat_props = (GlobalProperty[]) {
1127         {
1128             .driver   = "virtio-blk-pci",
1129             .property = "vectors",
1130             .value    = stringify(0),
1131         },{
1132             .driver   = "virtio-serial-pci",
1133             .property = "max_nr_ports",
1134             .value    = stringify(1),
1135         },{
1136             .driver   = "virtio-serial-pci",
1137             .property = "vectors",
1138             .value    = stringify(0),
1139         },{
1140             .driver   = "ide-drive",
1141             .property = "ver",
1142             .value    = "0.11",
1143         },{
1144             .driver   = "scsi-disk",
1145             .property = "ver",
1146             .value    = "0.11",
1147         },{
1148             .driver   = "PCI",
1149             .property = "rombar",
1150             .value    = stringify(0),
1151         },
1152         { /* end of list */ }
1153     }
1154 };
1155
1156 static QEMUMachine pc_machine_v0_10 = {
1157     .name = "pc-0.10",
1158     .desc = "Standard PC, qemu 0.10",
1159     .init = pc_init_pci,
1160     .max_cpus = 255,
1161     .compat_props = (GlobalProperty[]) {
1162         {
1163             .driver   = "virtio-blk-pci",
1164             .property = "class",
1165             .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1166         },{
1167             .driver   = "virtio-serial-pci",
1168             .property = "class",
1169             .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1170         },{
1171             .driver   = "virtio-serial-pci",
1172             .property = "max_nr_ports",
1173             .value    = stringify(1),
1174         },{
1175             .driver   = "virtio-serial-pci",
1176             .property = "vectors",
1177             .value    = stringify(0),
1178         },{
1179             .driver   = "virtio-net-pci",
1180             .property = "vectors",
1181             .value    = stringify(0),
1182         },{
1183             .driver   = "virtio-blk-pci",
1184             .property = "vectors",
1185             .value    = stringify(0),
1186         },{
1187             .driver   = "ide-drive",
1188             .property = "ver",
1189             .value    = "0.10",
1190         },{
1191             .driver   = "scsi-disk",
1192             .property = "ver",
1193             .value    = "0.10",
1194         },{
1195             .driver   = "PCI",
1196             .property = "rombar",
1197             .value    = stringify(0),
1198         },
1199         { /* end of list */ }
1200     },
1201 };
1202
1203 static QEMUMachine isapc_machine = {
1204     .name = "isapc",
1205     .desc = "ISA-only PC",
1206     .init = pc_init_isa,
1207     .max_cpus = 1,
1208 };
1209
1210 static void pc_machine_init(void)
1211 {
1212     qemu_register_machine(&pc_machine);
1213     qemu_register_machine(&pc_machine_v0_12);
1214     qemu_register_machine(&pc_machine_v0_11);
1215     qemu_register_machine(&pc_machine_v0_10);
1216     qemu_register_machine(&isapc_machine);
1217 }
1218
1219 machine_init(pc_machine_init);