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machine: pass all init options as a single QemuOpts
[qemu/aliguori-queue.git] / hw / sun4m.c
blob0856ecb452e4a865971a387228ff309cd0f6712e
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43
44 //#define DEBUG_IRQ
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #ifdef DEBUG_IRQ
75 #define DPRINTF(fmt, ...) \
76 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
77 #else
78 #define DPRINTF(fmt, ...)
79 #endif
80
81 #define KERNEL_LOAD_ADDR 0x00004000
82 #define CMDLINE_ADDR 0x007ff000
83 #define INITRD_LOAD_ADDR 0x00800000
84 #define PROM_SIZE_MAX (1024 * 1024)
85 #define PROM_VADDR 0xffd00000
86 #define PROM_FILENAME "openbios-sparc32"
87 #define CFG_ADDR 0xd00000510ULL
88 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
89
90 #define MAX_CPUS 16
91 #define MAX_PILS 16
92
93 #define ESCC_CLOCK 4915200
94
95 struct sun4m_hwdef {
96 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
97 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
98 target_phys_addr_t serial_base, fd_base;
99 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
100 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
101 target_phys_addr_t ecc_base;
102 uint32_t ecc_version;
103 uint8_t nvram_machine_id;
104 uint16_t machine_id;
105 uint32_t iommu_version;
106 uint64_t max_mem;
107 const char * const default_cpu_model;
108 };
109
110 #define MAX_IOUNITS 5
111
112 struct sun4d_hwdef {
113 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
114 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
115 target_phys_addr_t serial_base;
116 target_phys_addr_t espdma_base, esp_base;
117 target_phys_addr_t ledma_base, le_base;
118 target_phys_addr_t tcx_base;
119 target_phys_addr_t sbi_base;
120 uint8_t nvram_machine_id;
121 uint16_t machine_id;
122 uint32_t iounit_version;
123 uint64_t max_mem;
124 const char * const default_cpu_model;
125 };
126
127 struct sun4c_hwdef {
128 target_phys_addr_t iommu_base, slavio_base;
129 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
130 target_phys_addr_t serial_base, fd_base;
131 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
132 target_phys_addr_t tcx_base, aux1_base;
133 uint8_t nvram_machine_id;
134 uint16_t machine_id;
135 uint32_t iommu_version;
136 uint64_t max_mem;
137 const char * const default_cpu_model;
138 };
139
140 int DMA_get_channel_mode (int nchan)
141 {
142 return 0;
143 }
144 int DMA_read_memory (int nchan, void *buf, int pos, int size)
145 {
146 return 0;
147 }
148 int DMA_write_memory (int nchan, void *buf, int pos, int size)
149 {
150 return 0;
151 }
152 void DMA_hold_DREQ (int nchan) {}
153 void DMA_release_DREQ (int nchan) {}
154 void DMA_schedule(int nchan) {}
155
156 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
157 {
158 }
159
160 void DMA_register_channel (int nchan,
161 DMA_transfer_handler transfer_handler,
162 void *opaque)
163 {
164 }
165
166 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
167 {
168 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
169 return 0;
170 }
171
172 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
173 const char *cmdline, const char *boot_devices,
174 ram_addr_t RAM_size, uint32_t kernel_size,
175 int width, int height, int depth,
176 int nvram_machine_id, const char *arch)
177 {
178 unsigned int i;
179 uint32_t start, end;
180 uint8_t image[0x1ff0];
181 struct OpenBIOS_nvpart_v1 *part_header;
182
183 memset(image, '\0', sizeof(image));
184
185 start = 0;
186
187 // OpenBIOS nvram variables
188 // Variable partition
189 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
190 part_header->signature = OPENBIOS_PART_SYSTEM;
191 pstrcpy(part_header->name, sizeof(part_header->name), "system");
192
193 end = start + sizeof(struct OpenBIOS_nvpart_v1);
194 for (i = 0; i < nb_prom_envs; i++)
195 end = OpenBIOS_set_var(image, end, prom_envs[i]);
196
197 // End marker
198 image[end++] = '\0';
199
200 end = start + ((end - start + 15) & ~15);
201 OpenBIOS_finish_partition(part_header, end - start);
202
203 // free partition
204 start = end;
205 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
206 part_header->signature = OPENBIOS_PART_FREE;
207 pstrcpy(part_header->name, sizeof(part_header->name), "free");
208
209 end = 0x1fd0;
210 OpenBIOS_finish_partition(part_header, end - start);
211
212 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
213 nvram_machine_id);
214
215 for (i = 0; i < sizeof(image); i++)
216 m48t59_write(nvram, i, image[i]);
217 }
218
219 static DeviceState *slavio_intctl;
220
221 void pic_info(Monitor *mon)
222 {
223 if (slavio_intctl)
224 slavio_pic_info(mon, slavio_intctl);
225 }
226
227 void irq_info(Monitor *mon)
228 {
229 if (slavio_intctl)
230 slavio_irq_info(mon, slavio_intctl);
231 }
232
233 void cpu_check_irqs(CPUState *env)
234 {
235 if (env->pil_in && (env->interrupt_index == 0 ||
236 (env->interrupt_index & ~15) == TT_EXTINT)) {
237 unsigned int i;
238
239 for (i = 15; i > 0; i--) {
240 if (env->pil_in & (1 << i)) {
241 int old_interrupt = env->interrupt_index;
242
243 env->interrupt_index = TT_EXTINT | i;
244 if (old_interrupt != env->interrupt_index) {
245 DPRINTF("Set CPU IRQ %d\n", i);
246 cpu_interrupt(env, CPU_INTERRUPT_HARD);
247 }
248 break;
249 }
250 }
251 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
252 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
253 env->interrupt_index = 0;
254 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 }
257
258 static void cpu_set_irq(void *opaque, int irq, int level)
259 {
260 CPUState *env = opaque;
261
262 if (level) {
263 DPRINTF("Raise CPU IRQ %d\n", irq);
264 env->halted = 0;
265 env->pil_in |= 1 << irq;
266 cpu_check_irqs(env);
267 } else {
268 DPRINTF("Lower CPU IRQ %d\n", irq);
269 env->pil_in &= ~(1 << irq);
270 cpu_check_irqs(env);
271 }
272 }
273
274 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
275 {
276 }
277
278 static void main_cpu_reset(void *opaque)
279 {
280 CPUState *env = opaque;
281
282 cpu_reset(env);
283 env->halted = 0;
284 }
285
286 static void secondary_cpu_reset(void *opaque)
287 {
288 CPUState *env = opaque;
289
290 cpu_reset(env);
291 env->halted = 1;
292 }
293
294 static void cpu_halt_signal(void *opaque, int irq, int level)
295 {
296 if (level && cpu_single_env)
297 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
298 }
299
300 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
301 {
302 return addr - 0xf0000000ULL;
303 }
304
305 static unsigned long sun4m_load_kernel(const char *kernel_filename,
306 const char *initrd_filename,
307 ram_addr_t RAM_size)
308 {
309 int linux_boot;
310 unsigned int i;
311 long initrd_size, kernel_size;
312 uint8_t *ptr;
313
314 linux_boot = (kernel_filename != NULL);
315
316 kernel_size = 0;
317 if (linux_boot) {
318 int bswap_needed;
319
320 #ifdef BSWAP_NEEDED
321 bswap_needed = 1;
322 #else
323 bswap_needed = 0;
324 #endif
325 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
326 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
327 if (kernel_size < 0)
328 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
329 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
330 TARGET_PAGE_SIZE);
331 if (kernel_size < 0)
332 kernel_size = load_image_targphys(kernel_filename,
333 KERNEL_LOAD_ADDR,
334 RAM_size - KERNEL_LOAD_ADDR);
335 if (kernel_size < 0) {
336 fprintf(stderr, "qemu: could not load kernel '%s'\n",
337 kernel_filename);
338 exit(1);
339 }
340
341 /* load initrd */
342 initrd_size = 0;
343 if (initrd_filename) {
344 initrd_size = load_image_targphys(initrd_filename,
345 INITRD_LOAD_ADDR,
346 RAM_size - INITRD_LOAD_ADDR);
347 if (initrd_size < 0) {
348 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
349 initrd_filename);
350 exit(1);
351 }
352 }
353 if (initrd_size > 0) {
354 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
355 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
356 if (ldl_p(ptr) == 0x48647253) { // HdrS
357 stl_p(ptr + 16, INITRD_LOAD_ADDR);
358 stl_p(ptr + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
368 {
369 DeviceState *dev;
370 SysBusDevice *s;
371
372 dev = qdev_create(NULL, "iommu");
373 qdev_prop_set_uint32(dev, "version", version);
374 qdev_init_nofail(dev);
375 s = sysbus_from_qdev(dev);
376 sysbus_connect_irq(s, 0, irq);
377 sysbus_mmio_map(s, 0, addr);
378
379 return s;
380 }
381
382 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
383 void *iommu, qemu_irq *dev_irq)
384 {
385 DeviceState *dev;
386 SysBusDevice *s;
387
388 dev = qdev_create(NULL, "sparc32_dma");
389 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
390 qdev_init_nofail(dev);
391 s = sysbus_from_qdev(dev);
392 sysbus_connect_irq(s, 0, parent_irq);
393 *dev_irq = qdev_get_gpio_in(dev, 0);
394 sysbus_mmio_map(s, 0, daddr);
395
396 return s;
397 }
398
399 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
400 void *dma_opaque, qemu_irq irq)
401 {
402 DeviceState *dev;
403 SysBusDevice *s;
404 qemu_irq reset;
405
406 qemu_check_nic_model(&nd_table[0], "lance");
407
408 dev = qdev_create(NULL, "lance");
409 qdev_set_nic_properties(dev, nd);
410 qdev_prop_set_ptr(dev, "dma", dma_opaque);
411 qdev_init_nofail(dev);
412 s = sysbus_from_qdev(dev);
413 sysbus_mmio_map(s, 0, leaddr);
414 sysbus_connect_irq(s, 0, irq);
415 reset = qdev_get_gpio_in(dev, 0);
416 qdev_connect_gpio_out(dma_opaque, 0, reset);
417 }
418
419 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
420 target_phys_addr_t addrg,
421 qemu_irq **parent_irq)
422 {
423 DeviceState *dev;
424 SysBusDevice *s;
425 unsigned int i, j;
426
427 dev = qdev_create(NULL, "slavio_intctl");
428 qdev_init_nofail(dev);
429
430 s = sysbus_from_qdev(dev);
431
432 for (i = 0; i < MAX_CPUS; i++) {
433 for (j = 0; j < MAX_PILS; j++) {
434 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
435 }
436 }
437 sysbus_mmio_map(s, 0, addrg);
438 for (i = 0; i < MAX_CPUS; i++) {
439 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
440 }
441
442 return dev;
443 }
444
445 #define SYS_TIMER_OFFSET 0x10000ULL
446 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
447
448 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
449 qemu_irq *cpu_irqs, unsigned int num_cpus)
450 {
451 DeviceState *dev;
452 SysBusDevice *s;
453 unsigned int i;
454
455 dev = qdev_create(NULL, "slavio_timer");
456 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
457 qdev_init_nofail(dev);
458 s = sysbus_from_qdev(dev);
459 sysbus_connect_irq(s, 0, master_irq);
460 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
461
462 for (i = 0; i < MAX_CPUS; i++) {
463 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
464 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
465 }
466 }
467
468 #define MISC_LEDS 0x01600000
469 #define MISC_CFG 0x01800000
470 #define MISC_DIAG 0x01a00000
471 #define MISC_MDM 0x01b00000
472 #define MISC_SYS 0x01f00000
473
474 static void slavio_misc_init(target_phys_addr_t base,
475 target_phys_addr_t aux1_base,
476 target_phys_addr_t aux2_base, qemu_irq irq,
477 qemu_irq fdc_tc)
478 {
479 DeviceState *dev;
480 SysBusDevice *s;
481
482 dev = qdev_create(NULL, "slavio_misc");
483 qdev_init_nofail(dev);
484 s = sysbus_from_qdev(dev);
485 if (base) {
486 /* 8 bit registers */
487 /* Slavio control */
488 sysbus_mmio_map(s, 0, base + MISC_CFG);
489 /* Diagnostics */
490 sysbus_mmio_map(s, 1, base + MISC_DIAG);
491 /* Modem control */
492 sysbus_mmio_map(s, 2, base + MISC_MDM);
493 /* 16 bit registers */
494 /* ss600mp diag LEDs */
495 sysbus_mmio_map(s, 3, base + MISC_LEDS);
496 /* 32 bit registers */
497 /* System control */
498 sysbus_mmio_map(s, 4, base + MISC_SYS);
499 }
500 if (aux1_base) {
501 /* AUX 1 (Misc System Functions) */
502 sysbus_mmio_map(s, 5, aux1_base);
503 }
504 if (aux2_base) {
505 /* AUX 2 (Software Powerdown Control) */
506 sysbus_mmio_map(s, 6, aux2_base);
507 }
508 sysbus_connect_irq(s, 0, irq);
509 sysbus_connect_irq(s, 1, fdc_tc);
510 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
511 }
512
513 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
514 {
515 DeviceState *dev;
516 SysBusDevice *s;
517
518 dev = qdev_create(NULL, "eccmemctl");
519 qdev_prop_set_uint32(dev, "version", version);
520 qdev_init_nofail(dev);
521 s = sysbus_from_qdev(dev);
522 sysbus_connect_irq(s, 0, irq);
523 sysbus_mmio_map(s, 0, base);
524 if (version == 0) { // SS-600MP only
525 sysbus_mmio_map(s, 1, base + 0x1000);
526 }
527 }
528
529 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
530 {
531 DeviceState *dev;
532 SysBusDevice *s;
533
534 dev = qdev_create(NULL, "apc");
535 qdev_init_nofail(dev);
536 s = sysbus_from_qdev(dev);
537 /* Power management (APC) XXX: not a Slavio device */
538 sysbus_mmio_map(s, 0, power_base);
539 sysbus_connect_irq(s, 0, cpu_halt);
540 }
541
542 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
543 int height, int depth)
544 {
545 DeviceState *dev;
546 SysBusDevice *s;
547
548 dev = qdev_create(NULL, "SUNW,tcx");
549 qdev_prop_set_taddr(dev, "addr", addr);
550 qdev_prop_set_uint32(dev, "vram_size", vram_size);
551 qdev_prop_set_uint16(dev, "width", width);
552 qdev_prop_set_uint16(dev, "height", height);
553 qdev_prop_set_uint16(dev, "depth", depth);
554 qdev_init_nofail(dev);
555 s = sysbus_from_qdev(dev);
556 /* 8-bit plane */
557 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
558 /* DAC */
559 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
560 /* TEC (dummy) */
561 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
562 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
563 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
564 if (depth == 24) {
565 /* 24-bit plane */
566 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
567 /* Control plane */
568 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
569 } else {
570 /* THC 8 bit (dummy) */
571 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
572 }
573 }
574
575 /* NCR89C100/MACIO Internal ID register */
576 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
577
578 static void idreg_init(target_phys_addr_t addr)
579 {
580 DeviceState *dev;
581 SysBusDevice *s;
582
583 dev = qdev_create(NULL, "macio_idreg");
584 qdev_init_nofail(dev);
585 s = sysbus_from_qdev(dev);
586
587 sysbus_mmio_map(s, 0, addr);
588 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
589 }
590
591 static int idreg_init1(SysBusDevice *dev)
592 {
593 ram_addr_t idreg_offset;
594
595 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
596 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
597 return 0;
598 }
599
600 static SysBusDeviceInfo idreg_info = {
601 .init = idreg_init1,
602 .qdev.name = "macio_idreg",
603 .qdev.size = sizeof(SysBusDevice),
604 };
605
606 static void idreg_register_devices(void)
607 {
608 sysbus_register_withprop(&idreg_info);
609 }
610
611 device_init(idreg_register_devices);
612
613 /* SS-5 TCX AFX register */
614 static void afx_init(target_phys_addr_t addr)
615 {
616 DeviceState *dev;
617 SysBusDevice *s;
618
619 dev = qdev_create(NULL, "tcx_afx");
620 qdev_init_nofail(dev);
621 s = sysbus_from_qdev(dev);
622
623 sysbus_mmio_map(s, 0, addr);
624 }
625
626 static int afx_init1(SysBusDevice *dev)
627 {
628 ram_addr_t afx_offset;
629
630 afx_offset = qemu_ram_alloc(4);
631 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
632 return 0;
633 }
634
635 static SysBusDeviceInfo afx_info = {
636 .init = afx_init1,
637 .qdev.name = "tcx_afx",
638 .qdev.size = sizeof(SysBusDevice),
639 };
640
641 static void afx_register_devices(void)
642 {
643 sysbus_register_withprop(&afx_info);
644 }
645
646 device_init(afx_register_devices);
647
648 /* Boot PROM (OpenBIOS) */
649 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
650 {
651 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
652 return addr + *base_addr - PROM_VADDR;
653 }
654
655 static void prom_init(target_phys_addr_t addr, const char *bios_name)
656 {
657 DeviceState *dev;
658 SysBusDevice *s;
659 char *filename;
660 int ret;
661
662 dev = qdev_create(NULL, "openprom");
663 qdev_init_nofail(dev);
664 s = sysbus_from_qdev(dev);
665
666 sysbus_mmio_map(s, 0, addr);
667
668 /* load boot prom */
669 if (bios_name == NULL) {
670 bios_name = PROM_FILENAME;
671 }
672 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
673 if (filename) {
674 ret = load_elf(filename, translate_prom_address, &addr, NULL,
675 NULL, NULL, 1, ELF_MACHINE, 0);
676 if (ret < 0 || ret > PROM_SIZE_MAX) {
677 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
678 }
679 qemu_free(filename);
680 } else {
681 ret = -1;
682 }
683 if (ret < 0 || ret > PROM_SIZE_MAX) {
684 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
685 exit(1);
686 }
687 }
688
689 static int prom_init1(SysBusDevice *dev)
690 {
691 ram_addr_t prom_offset;
692
693 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
694 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
695 return 0;
696 }
697
698 static SysBusDeviceInfo prom_info = {
699 .init = prom_init1,
700 .qdev.name = "openprom",
701 .qdev.size = sizeof(SysBusDevice),
702 .qdev.props = (Property[]) {
703 {/* end of property list */}
704 }
705 };
706
707 static void prom_register_devices(void)
708 {
709 sysbus_register_withprop(&prom_info);
710 }
711
712 device_init(prom_register_devices);
713
714 typedef struct RamDevice
715 {
716 SysBusDevice busdev;
717 uint64_t size;
718 } RamDevice;
719
720 /* System RAM */
721 static int ram_init1(SysBusDevice *dev)
722 {
723 ram_addr_t RAM_size, ram_offset;
724 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
725
726 RAM_size = d->size;
727
728 ram_offset = qemu_ram_alloc(RAM_size);
729 sysbus_init_mmio(dev, RAM_size, ram_offset);
730 return 0;
731 }
732
733 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
734 uint64_t max_mem)
735 {
736 DeviceState *dev;
737 SysBusDevice *s;
738 RamDevice *d;
739
740 /* allocate RAM */
741 if ((uint64_t)RAM_size > max_mem) {
742 fprintf(stderr,
743 "qemu: Too much memory for this machine: %d, maximum %d\n",
744 (unsigned int)(RAM_size / (1024 * 1024)),
745 (unsigned int)(max_mem / (1024 * 1024)));
746 exit(1);
747 }
748 dev = qdev_create(NULL, "memory");
749 s = sysbus_from_qdev(dev);
750
751 d = FROM_SYSBUS(RamDevice, s);
752 d->size = RAM_size;
753 qdev_init_nofail(dev);
754
755 sysbus_mmio_map(s, 0, addr);
756 }
757
758 static SysBusDeviceInfo ram_info = {
759 .init = ram_init1,
760 .qdev.name = "memory",
761 .qdev.size = sizeof(RamDevice),
762 .qdev.props = (Property[]) {
763 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
764 DEFINE_PROP_END_OF_LIST(),
765 }
766 };
767
768 static void ram_register_devices(void)
769 {
770 sysbus_register_withprop(&ram_info);
771 }
772
773 device_init(ram_register_devices);
774
775 static void cpu_devinit(const char *cpu_model, unsigned int id,
776 uint64_t prom_addr, qemu_irq **cpu_irqs)
777 {
778 CPUState *env;
779
780 env = cpu_init(cpu_model);
781 if (!env) {
782 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
783 exit(1);
784 }
785
786 cpu_sparc_set_id(env, id);
787 if (id == 0) {
788 qemu_register_reset(main_cpu_reset, env);
789 } else {
790 qemu_register_reset(secondary_cpu_reset, env);
791 env->halted = 1;
792 }
793 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
794 env->prom_addr = prom_addr;
795 }
796
797 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
798 const char *boot_device,
799 const char *kernel_filename,
800 const char *kernel_cmdline,
801 const char *initrd_filename, const char *cpu_model)
802 {
803 unsigned int i;
804 void *iommu, *espdma, *ledma, *nvram;
805 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
806 espdma_irq, ledma_irq;
807 qemu_irq esp_reset;
808 qemu_irq fdc_tc;
809 qemu_irq *cpu_halt;
810 unsigned long kernel_size;
811 DriveInfo *fd[MAX_FD];
812 void *fw_cfg;
813
814 /* init CPUs */
815 if (!cpu_model)
816 cpu_model = hwdef->default_cpu_model;
817
818 for(i = 0; i < smp_cpus; i++) {
819 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
820 }
821
822 for (i = smp_cpus; i < MAX_CPUS; i++)
823 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
824
825
826 /* set up devices */
827 ram_init(0, RAM_size, hwdef->max_mem);
828 /* models without ECC don't trap when missing ram is accessed */
829 if (!hwdef->ecc_base) {
830 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
831 }
832
833 prom_init(hwdef->slavio_base, bios_name);
834
835 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
836 hwdef->intctl_base + 0x10000ULL,
837 cpu_irqs);
838
839 for (i = 0; i < 32; i++) {
840 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
841 }
842 for (i = 0; i < MAX_CPUS; i++) {
843 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
844 }
845
846 if (hwdef->idreg_base) {
847 idreg_init(hwdef->idreg_base);
848 }
849
850 if (hwdef->afx_base) {
851 afx_init(hwdef->afx_base);
852 }
853
854 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
855 slavio_irq[30]);
856
857 if (hwdef->iommu_pad_base) {
858 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
859 Software shouldn't use aliased addresses, neither should it crash
860 when does. Using empty_slot instead of aliasing can help with
861 debugging such accesses */
862 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
863 }
864
865 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
866 iommu, &espdma_irq);
867
868 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
869 slavio_irq[16], iommu, &ledma_irq);
870
871 if (graphic_depth != 8 && graphic_depth != 24) {
872 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
873 exit (1);
874 }
875 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
876 graphic_depth);
877
878 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
879
880 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
881
882 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
883
884 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
885 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
886 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
887 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
888 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
889 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
890
891 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
892 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
893 slavio_irq[30], fdc_tc);
894
895 if (hwdef->apc_base) {
896 apc_init(hwdef->apc_base, cpu_halt[0]);
897 }
898
899 if (hwdef->fd_base) {
900 /* there is zero or one floppy drive */
901 memset(fd, 0, sizeof(fd));
902 fd[0] = drive_get(IF_FLOPPY, 0, 0);
903 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
904 &fdc_tc);
905 }
906
907 if (drive_get_max_bus(IF_SCSI) > 0) {
908 fprintf(stderr, "qemu: too many SCSI bus\n");
909 exit(1);
910 }
911
912 esp_reset = qdev_get_gpio_in(espdma, 0);
913 esp_init(hwdef->esp_base, 2,
914 espdma_memory_read, espdma_memory_write,
915 espdma, espdma_irq, &esp_reset);
916
917
918 if (hwdef->cs_base) {
919 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
920 slavio_irq[5]);
921 }
922
923 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
924 RAM_size);
925
926 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
927 boot_device, RAM_size, kernel_size, graphic_width,
928 graphic_height, graphic_depth, hwdef->nvram_machine_id,
929 "Sun4m");
930
931 if (hwdef->ecc_base)
932 ecc_init(hwdef->ecc_base, slavio_irq[28],
933 hwdef->ecc_version);
934
935 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
936 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
937 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
938 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
939 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
940 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
941 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
942 if (kernel_cmdline) {
943 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
944 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
945 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
946 (uint8_t*)strdup(kernel_cmdline),
947 strlen(kernel_cmdline) + 1);
948 } else {
949 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
950 }
951 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
952 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
953 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
954 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
955 }
956
957 enum {
958 ss2_id = 0,
959 ss5_id = 32,
960 vger_id,
961 lx_id,
962 ss4_id,
963 scls_id,
964 sbook_id,
965 ss10_id = 64,
966 ss20_id,
967 ss600mp_id,
968 ss1000_id = 96,
969 ss2000_id,
970 };
971
972 static const struct sun4m_hwdef sun4m_hwdefs[] = {
973 /* SS-5 */
974 {
975 .iommu_base = 0x10000000,
976 .iommu_pad_base = 0x10004000,
977 .iommu_pad_len = 0x0fffb000,
978 .tcx_base = 0x50000000,
979 .cs_base = 0x6c000000,
980 .slavio_base = 0x70000000,
981 .ms_kb_base = 0x71000000,
982 .serial_base = 0x71100000,
983 .nvram_base = 0x71200000,
984 .fd_base = 0x71400000,
985 .counter_base = 0x71d00000,
986 .intctl_base = 0x71e00000,
987 .idreg_base = 0x78000000,
988 .dma_base = 0x78400000,
989 .esp_base = 0x78800000,
990 .le_base = 0x78c00000,
991 .apc_base = 0x6a000000,
992 .afx_base = 0x6e000000,
993 .aux1_base = 0x71900000,
994 .aux2_base = 0x71910000,
995 .nvram_machine_id = 0x80,
996 .machine_id = ss5_id,
997 .iommu_version = 0x05000000,
998 .max_mem = 0x10000000,
999 .default_cpu_model = "Fujitsu MB86904",
1000 },
1001 /* SS-10 */
1002 {
1003 .iommu_base = 0xfe0000000ULL,
1004 .tcx_base = 0xe20000000ULL,
1005 .slavio_base = 0xff0000000ULL,
1006 .ms_kb_base = 0xff1000000ULL,
1007 .serial_base = 0xff1100000ULL,
1008 .nvram_base = 0xff1200000ULL,
1009 .fd_base = 0xff1700000ULL,
1010 .counter_base = 0xff1300000ULL,
1011 .intctl_base = 0xff1400000ULL,
1012 .idreg_base = 0xef0000000ULL,
1013 .dma_base = 0xef0400000ULL,
1014 .esp_base = 0xef0800000ULL,
1015 .le_base = 0xef0c00000ULL,
1016 .apc_base = 0xefa000000ULL, // XXX should not exist
1017 .aux1_base = 0xff1800000ULL,
1018 .aux2_base = 0xff1a01000ULL,
1019 .ecc_base = 0xf00000000ULL,
1020 .ecc_version = 0x10000000, // version 0, implementation 1
1021 .nvram_machine_id = 0x72,
1022 .machine_id = ss10_id,
1023 .iommu_version = 0x03000000,
1024 .max_mem = 0xf00000000ULL,
1025 .default_cpu_model = "TI SuperSparc II",
1026 },
1027 /* SS-600MP */
1028 {
1029 .iommu_base = 0xfe0000000ULL,
1030 .tcx_base = 0xe20000000ULL,
1031 .slavio_base = 0xff0000000ULL,
1032 .ms_kb_base = 0xff1000000ULL,
1033 .serial_base = 0xff1100000ULL,
1034 .nvram_base = 0xff1200000ULL,
1035 .counter_base = 0xff1300000ULL,
1036 .intctl_base = 0xff1400000ULL,
1037 .dma_base = 0xef0081000ULL,
1038 .esp_base = 0xef0080000ULL,
1039 .le_base = 0xef0060000ULL,
1040 .apc_base = 0xefa000000ULL, // XXX should not exist
1041 .aux1_base = 0xff1800000ULL,
1042 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1043 .ecc_base = 0xf00000000ULL,
1044 .ecc_version = 0x00000000, // version 0, implementation 0
1045 .nvram_machine_id = 0x71,
1046 .machine_id = ss600mp_id,
1047 .iommu_version = 0x01000000,
1048 .max_mem = 0xf00000000ULL,
1049 .default_cpu_model = "TI SuperSparc II",
1050 },
1051 /* SS-20 */
1052 {
1053 .iommu_base = 0xfe0000000ULL,
1054 .tcx_base = 0xe20000000ULL,
1055 .slavio_base = 0xff0000000ULL,
1056 .ms_kb_base = 0xff1000000ULL,
1057 .serial_base = 0xff1100000ULL,
1058 .nvram_base = 0xff1200000ULL,
1059 .fd_base = 0xff1700000ULL,
1060 .counter_base = 0xff1300000ULL,
1061 .intctl_base = 0xff1400000ULL,
1062 .idreg_base = 0xef0000000ULL,
1063 .dma_base = 0xef0400000ULL,
1064 .esp_base = 0xef0800000ULL,
1065 .le_base = 0xef0c00000ULL,
1066 .apc_base = 0xefa000000ULL, // XXX should not exist
1067 .aux1_base = 0xff1800000ULL,
1068 .aux2_base = 0xff1a01000ULL,
1069 .ecc_base = 0xf00000000ULL,
1070 .ecc_version = 0x20000000, // version 0, implementation 2
1071 .nvram_machine_id = 0x72,
1072 .machine_id = ss20_id,
1073 .iommu_version = 0x13000000,
1074 .max_mem = 0xf00000000ULL,
1075 .default_cpu_model = "TI SuperSparc II",
1076 },
1077 /* Voyager */
1078 {
1079 .iommu_base = 0x10000000,
1080 .tcx_base = 0x50000000,
1081 .slavio_base = 0x70000000,
1082 .ms_kb_base = 0x71000000,
1083 .serial_base = 0x71100000,
1084 .nvram_base = 0x71200000,
1085 .fd_base = 0x71400000,
1086 .counter_base = 0x71d00000,
1087 .intctl_base = 0x71e00000,
1088 .idreg_base = 0x78000000,
1089 .dma_base = 0x78400000,
1090 .esp_base = 0x78800000,
1091 .le_base = 0x78c00000,
1092 .apc_base = 0x71300000, // pmc
1093 .aux1_base = 0x71900000,
1094 .aux2_base = 0x71910000,
1095 .nvram_machine_id = 0x80,
1096 .machine_id = vger_id,
1097 .iommu_version = 0x05000000,
1098 .max_mem = 0x10000000,
1099 .default_cpu_model = "Fujitsu MB86904",
1100 },
1101 /* LX */
1102 {
1103 .iommu_base = 0x10000000,
1104 .iommu_pad_base = 0x10004000,
1105 .iommu_pad_len = 0x0fffb000,
1106 .tcx_base = 0x50000000,
1107 .slavio_base = 0x70000000,
1108 .ms_kb_base = 0x71000000,
1109 .serial_base = 0x71100000,
1110 .nvram_base = 0x71200000,
1111 .fd_base = 0x71400000,
1112 .counter_base = 0x71d00000,
1113 .intctl_base = 0x71e00000,
1114 .idreg_base = 0x78000000,
1115 .dma_base = 0x78400000,
1116 .esp_base = 0x78800000,
1117 .le_base = 0x78c00000,
1118 .aux1_base = 0x71900000,
1119 .aux2_base = 0x71910000,
1120 .nvram_machine_id = 0x80,
1121 .machine_id = lx_id,
1122 .iommu_version = 0x04000000,
1123 .max_mem = 0x10000000,
1124 .default_cpu_model = "TI MicroSparc I",
1125 },
1126 /* SS-4 */
1127 {
1128 .iommu_base = 0x10000000,
1129 .tcx_base = 0x50000000,
1130 .cs_base = 0x6c000000,
1131 .slavio_base = 0x70000000,
1132 .ms_kb_base = 0x71000000,
1133 .serial_base = 0x71100000,
1134 .nvram_base = 0x71200000,
1135 .fd_base = 0x71400000,
1136 .counter_base = 0x71d00000,
1137 .intctl_base = 0x71e00000,
1138 .idreg_base = 0x78000000,
1139 .dma_base = 0x78400000,
1140 .esp_base = 0x78800000,
1141 .le_base = 0x78c00000,
1142 .apc_base = 0x6a000000,
1143 .aux1_base = 0x71900000,
1144 .aux2_base = 0x71910000,
1145 .nvram_machine_id = 0x80,
1146 .machine_id = ss4_id,
1147 .iommu_version = 0x05000000,
1148 .max_mem = 0x10000000,
1149 .default_cpu_model = "Fujitsu MB86904",
1150 },
1151 /* SPARCClassic */
1152 {
1153 .iommu_base = 0x10000000,
1154 .tcx_base = 0x50000000,
1155 .slavio_base = 0x70000000,
1156 .ms_kb_base = 0x71000000,
1157 .serial_base = 0x71100000,
1158 .nvram_base = 0x71200000,
1159 .fd_base = 0x71400000,
1160 .counter_base = 0x71d00000,
1161 .intctl_base = 0x71e00000,
1162 .idreg_base = 0x78000000,
1163 .dma_base = 0x78400000,
1164 .esp_base = 0x78800000,
1165 .le_base = 0x78c00000,
1166 .apc_base = 0x6a000000,
1167 .aux1_base = 0x71900000,
1168 .aux2_base = 0x71910000,
1169 .nvram_machine_id = 0x80,
1170 .machine_id = scls_id,
1171 .iommu_version = 0x05000000,
1172 .max_mem = 0x10000000,
1173 .default_cpu_model = "TI MicroSparc I",
1174 },
1175 /* SPARCbook */
1176 {
1177 .iommu_base = 0x10000000,
1178 .tcx_base = 0x50000000, // XXX
1179 .slavio_base = 0x70000000,
1180 .ms_kb_base = 0x71000000,
1181 .serial_base = 0x71100000,
1182 .nvram_base = 0x71200000,
1183 .fd_base = 0x71400000,
1184 .counter_base = 0x71d00000,
1185 .intctl_base = 0x71e00000,
1186 .idreg_base = 0x78000000,
1187 .dma_base = 0x78400000,
1188 .esp_base = 0x78800000,
1189 .le_base = 0x78c00000,
1190 .apc_base = 0x6a000000,
1191 .aux1_base = 0x71900000,
1192 .aux2_base = 0x71910000,
1193 .nvram_machine_id = 0x80,
1194 .machine_id = sbook_id,
1195 .iommu_version = 0x05000000,
1196 .max_mem = 0x10000000,
1197 .default_cpu_model = "TI MicroSparc I",
1198 },
1199 };
1200
1201 /* SPARCstation 5 hardware initialisation */
1202 static void ss5_init(QEMUMachine *machine, QemuOpts *opts)
1203 {
1204 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1205 const char *boot_device = qemu_opt_get(opts, "boot_device");
1206 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1207 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1208 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1209 const char *cpu_model = qemu_opt_get(opts, "cpu");
1210 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1211 kernel_cmdline, initrd_filename, cpu_model);
1212 }
1213
1214 /* SPARCstation 10 hardware initialisation */
1215 static void ss10_init(QEMUMachine *machine, QemuOpts *opts)
1216 {
1217 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1218 const char *boot_device = qemu_opt_get(opts, "boot_device");
1219 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1220 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1221 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1222 const char *cpu_model = qemu_opt_get(opts, "cpu");
1223 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1224 kernel_cmdline, initrd_filename, cpu_model);
1225 }
1226
1227 /* SPARCserver 600MP hardware initialisation */
1228 static void ss600mp_init(QEMUMachine *machine, QemuOpts *opts)
1229 {
1230 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1231 const char *boot_device = qemu_opt_get(opts, "boot_device");
1232 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1233 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1234 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1235 const char *cpu_model = qemu_opt_get(opts, "cpu");
1236 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1237 kernel_cmdline, initrd_filename, cpu_model);
1238 }
1239
1240 /* SPARCstation 20 hardware initialisation */
1241 static void ss20_init(QEMUMachine *machine, QemuOpts *opts)
1242 {
1243 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1244 const char *boot_device = qemu_opt_get(opts, "boot_device");
1245 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1246 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1247 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1248 const char *cpu_model = qemu_opt_get(opts, "cpu");
1249 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1250 kernel_cmdline, initrd_filename, cpu_model);
1251 }
1252
1253 /* SPARCstation Voyager hardware initialisation */
1254 static void vger_init(QEMUMachine *machine, QemuOpts *opts)
1255 {
1256 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1257 const char *boot_device = qemu_opt_get(opts, "boot_device");
1258 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1259 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1260 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1261 const char *cpu_model = qemu_opt_get(opts, "cpu");
1262 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1263 kernel_cmdline, initrd_filename, cpu_model);
1264 }
1265
1266 /* SPARCstation LX hardware initialisation */
1267 static void ss_lx_init(QEMUMachine *machine, QemuOpts *opts)
1268 {
1269 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1270 const char *boot_device = qemu_opt_get(opts, "boot_device");
1271 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1272 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1273 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1274 const char *cpu_model = qemu_opt_get(opts, "cpu");
1275 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1276 kernel_cmdline, initrd_filename, cpu_model);
1277 }
1278
1279 /* SPARCstation 4 hardware initialisation */
1280 static void ss4_init(QEMUMachine *machine, QemuOpts *opts)
1281 {
1282 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1283 const char *boot_device = qemu_opt_get(opts, "boot_device");
1284 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1285 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1286 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1287 const char *cpu_model = qemu_opt_get(opts, "cpu");
1288 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1289 kernel_cmdline, initrd_filename, cpu_model);
1290 }
1291
1292 /* SPARCClassic hardware initialisation */
1293 static void scls_init(QEMUMachine *machine, QemuOpts *opts)
1294 {
1295 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1296 const char *boot_device = qemu_opt_get(opts, "boot_device");
1297 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1298 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1299 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1300 const char *cpu_model = qemu_opt_get(opts, "cpu");
1301 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1302 kernel_cmdline, initrd_filename, cpu_model);
1303 }
1304
1305 /* SPARCbook hardware initialisation */
1306 static void sbook_init(QEMUMachine *machine, QemuOpts *opts)
1307 {
1308 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1309 const char *boot_device = qemu_opt_get(opts, "boot_device");
1310 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1311 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1312 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1313 const char *cpu_model = qemu_opt_get(opts, "cpu");
1314 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1315 kernel_cmdline, initrd_filename, cpu_model);
1316 }
1317
1318 static QEMUMachine ss5_machine = {
1319 .name = "SS-5",
1320 .desc = "Sun4m platform, SPARCstation 5",
1321 .init = ss5_init,
1322 .use_scsi = 1,
1323 .is_default = 1,
1324 };
1325
1326 static QEMUMachine ss10_machine = {
1327 .name = "SS-10",
1328 .desc = "Sun4m platform, SPARCstation 10",
1329 .init = ss10_init,
1330 .use_scsi = 1,
1331 .max_cpus = 4,
1332 };
1333
1334 static QEMUMachine ss600mp_machine = {
1335 .name = "SS-600MP",
1336 .desc = "Sun4m platform, SPARCserver 600MP",
1337 .init = ss600mp_init,
1338 .use_scsi = 1,
1339 .max_cpus = 4,
1340 };
1341
1342 static QEMUMachine ss20_machine = {
1343 .name = "SS-20",
1344 .desc = "Sun4m platform, SPARCstation 20",
1345 .init = ss20_init,
1346 .use_scsi = 1,
1347 .max_cpus = 4,
1348 };
1349
1350 static QEMUMachine voyager_machine = {
1351 .name = "Voyager",
1352 .desc = "Sun4m platform, SPARCstation Voyager",
1353 .init = vger_init,
1354 .use_scsi = 1,
1355 };
1356
1357 static QEMUMachine ss_lx_machine = {
1358 .name = "LX",
1359 .desc = "Sun4m platform, SPARCstation LX",
1360 .init = ss_lx_init,
1361 .use_scsi = 1,
1362 };
1363
1364 static QEMUMachine ss4_machine = {
1365 .name = "SS-4",
1366 .desc = "Sun4m platform, SPARCstation 4",
1367 .init = ss4_init,
1368 .use_scsi = 1,
1369 };
1370
1371 static QEMUMachine scls_machine = {
1372 .name = "SPARCClassic",
1373 .desc = "Sun4m platform, SPARCClassic",
1374 .init = scls_init,
1375 .use_scsi = 1,
1376 };
1377
1378 static QEMUMachine sbook_machine = {
1379 .name = "SPARCbook",
1380 .desc = "Sun4m platform, SPARCbook",
1381 .init = sbook_init,
1382 .use_scsi = 1,
1383 };
1384
1385 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1386 /* SS-1000 */
1387 {
1388 .iounit_bases = {
1389 0xfe0200000ULL,
1390 0xfe1200000ULL,
1391 0xfe2200000ULL,
1392 0xfe3200000ULL,
1393 -1,
1394 },
1395 .tcx_base = 0x820000000ULL,
1396 .slavio_base = 0xf00000000ULL,
1397 .ms_kb_base = 0xf00240000ULL,
1398 .serial_base = 0xf00200000ULL,
1399 .nvram_base = 0xf00280000ULL,
1400 .counter_base = 0xf00300000ULL,
1401 .espdma_base = 0x800081000ULL,
1402 .esp_base = 0x800080000ULL,
1403 .ledma_base = 0x800040000ULL,
1404 .le_base = 0x800060000ULL,
1405 .sbi_base = 0xf02800000ULL,
1406 .nvram_machine_id = 0x80,
1407 .machine_id = ss1000_id,
1408 .iounit_version = 0x03000000,
1409 .max_mem = 0xf00000000ULL,
1410 .default_cpu_model = "TI SuperSparc II",
1411 },
1412 /* SS-2000 */
1413 {
1414 .iounit_bases = {
1415 0xfe0200000ULL,
1416 0xfe1200000ULL,
1417 0xfe2200000ULL,
1418 0xfe3200000ULL,
1419 0xfe4200000ULL,
1420 },
1421 .tcx_base = 0x820000000ULL,
1422 .slavio_base = 0xf00000000ULL,
1423 .ms_kb_base = 0xf00240000ULL,
1424 .serial_base = 0xf00200000ULL,
1425 .nvram_base = 0xf00280000ULL,
1426 .counter_base = 0xf00300000ULL,
1427 .espdma_base = 0x800081000ULL,
1428 .esp_base = 0x800080000ULL,
1429 .ledma_base = 0x800040000ULL,
1430 .le_base = 0x800060000ULL,
1431 .sbi_base = 0xf02800000ULL,
1432 .nvram_machine_id = 0x80,
1433 .machine_id = ss2000_id,
1434 .iounit_version = 0x03000000,
1435 .max_mem = 0xf00000000ULL,
1436 .default_cpu_model = "TI SuperSparc II",
1437 },
1438 };
1439
1440 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1441 {
1442 DeviceState *dev;
1443 SysBusDevice *s;
1444 unsigned int i;
1445
1446 dev = qdev_create(NULL, "sbi");
1447 qdev_init_nofail(dev);
1448
1449 s = sysbus_from_qdev(dev);
1450
1451 for (i = 0; i < MAX_CPUS; i++) {
1452 sysbus_connect_irq(s, i, *parent_irq[i]);
1453 }
1454
1455 sysbus_mmio_map(s, 0, addr);
1456
1457 return dev;
1458 }
1459
1460 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1461 const char *boot_device,
1462 const char *kernel_filename,
1463 const char *kernel_cmdline,
1464 const char *initrd_filename, const char *cpu_model)
1465 {
1466 unsigned int i;
1467 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1468 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1469 espdma_irq, ledma_irq;
1470 qemu_irq esp_reset;
1471 unsigned long kernel_size;
1472 void *fw_cfg;
1473 DeviceState *dev;
1474
1475 /* init CPUs */
1476 if (!cpu_model)
1477 cpu_model = hwdef->default_cpu_model;
1478
1479 for(i = 0; i < smp_cpus; i++) {
1480 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1481 }
1482
1483 for (i = smp_cpus; i < MAX_CPUS; i++)
1484 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1485
1486 /* set up devices */
1487 ram_init(0, RAM_size, hwdef->max_mem);
1488
1489 prom_init(hwdef->slavio_base, bios_name);
1490
1491 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1492
1493 for (i = 0; i < 32; i++) {
1494 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1495 }
1496 for (i = 0; i < MAX_CPUS; i++) {
1497 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1498 }
1499
1500 for (i = 0; i < MAX_IOUNITS; i++)
1501 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1502 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1503 hwdef->iounit_version,
1504 sbi_irq[0]);
1505
1506 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1507 iounits[0], &espdma_irq);
1508
1509 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1510 iounits[0], &ledma_irq);
1511
1512 if (graphic_depth != 8 && graphic_depth != 24) {
1513 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1514 exit (1);
1515 }
1516 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1517 graphic_depth);
1518
1519 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1520
1521 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1522
1523 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1524
1525 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1526 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1527 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1528 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1529 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1530 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1531
1532 if (drive_get_max_bus(IF_SCSI) > 0) {
1533 fprintf(stderr, "qemu: too many SCSI bus\n");
1534 exit(1);
1535 }
1536
1537 esp_reset = qdev_get_gpio_in(espdma, 0);
1538 esp_init(hwdef->esp_base, 2,
1539 espdma_memory_read, espdma_memory_write,
1540 espdma, espdma_irq, &esp_reset);
1541
1542 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1543 RAM_size);
1544
1545 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1546 boot_device, RAM_size, kernel_size, graphic_width,
1547 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1548 "Sun4d");
1549
1550 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1551 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1552 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1553 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1554 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1555 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1556 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1557 if (kernel_cmdline) {
1558 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1559 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1560 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1561 (uint8_t*)strdup(kernel_cmdline),
1562 strlen(kernel_cmdline) + 1);
1563 } else {
1564 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1565 }
1566 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1567 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1568 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1569 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1570 }
1571
1572 /* SPARCserver 1000 hardware initialisation */
1573 static void ss1000_init(QEMUMachine *machine, QemuOpts *opts)
1574 {
1575 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1576 const char *boot_device = qemu_opt_get(opts, "boot_device");
1577 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1578 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1579 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1580 const char *cpu_model = qemu_opt_get(opts, "cpu");
1581 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1582 kernel_cmdline, initrd_filename, cpu_model);
1583 }
1584
1585 /* SPARCcenter 2000 hardware initialisation */
1586 static void ss2000_init(QEMUMachine *machine, QemuOpts *opts)
1587 {
1588 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1589 const char *boot_device = qemu_opt_get(opts, "boot_device");
1590 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1591 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1592 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1593 const char *cpu_model = qemu_opt_get(opts, "cpu");
1594 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1595 kernel_cmdline, initrd_filename, cpu_model);
1596 }
1597
1598 static QEMUMachine ss1000_machine = {
1599 .name = "SS-1000",
1600 .desc = "Sun4d platform, SPARCserver 1000",
1601 .init = ss1000_init,
1602 .use_scsi = 1,
1603 .max_cpus = 8,
1604 };
1605
1606 static QEMUMachine ss2000_machine = {
1607 .name = "SS-2000",
1608 .desc = "Sun4d platform, SPARCcenter 2000",
1609 .init = ss2000_init,
1610 .use_scsi = 1,
1611 .max_cpus = 20,
1612 };
1613
1614 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1615 /* SS-2 */
1616 {
1617 .iommu_base = 0xf8000000,
1618 .tcx_base = 0xfe000000,
1619 .slavio_base = 0xf6000000,
1620 .intctl_base = 0xf5000000,
1621 .counter_base = 0xf3000000,
1622 .ms_kb_base = 0xf0000000,
1623 .serial_base = 0xf1000000,
1624 .nvram_base = 0xf2000000,
1625 .fd_base = 0xf7200000,
1626 .dma_base = 0xf8400000,
1627 .esp_base = 0xf8800000,
1628 .le_base = 0xf8c00000,
1629 .aux1_base = 0xf7400003,
1630 .nvram_machine_id = 0x55,
1631 .machine_id = ss2_id,
1632 .max_mem = 0x10000000,
1633 .default_cpu_model = "Cypress CY7C601",
1634 },
1635 };
1636
1637 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1638 qemu_irq *parent_irq)
1639 {
1640 DeviceState *dev;
1641 SysBusDevice *s;
1642 unsigned int i;
1643
1644 dev = qdev_create(NULL, "sun4c_intctl");
1645 qdev_init_nofail(dev);
1646
1647 s = sysbus_from_qdev(dev);
1648
1649 for (i = 0; i < MAX_PILS; i++) {
1650 sysbus_connect_irq(s, i, parent_irq[i]);
1651 }
1652 sysbus_mmio_map(s, 0, addr);
1653
1654 return dev;
1655 }
1656
1657 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1658 const char *boot_device,
1659 const char *kernel_filename,
1660 const char *kernel_cmdline,
1661 const char *initrd_filename, const char *cpu_model)
1662 {
1663 void *iommu, *espdma, *ledma, *nvram;
1664 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1665 qemu_irq esp_reset;
1666 qemu_irq fdc_tc;
1667 unsigned long kernel_size;
1668 DriveInfo *fd[MAX_FD];
1669 void *fw_cfg;
1670 DeviceState *dev;
1671 unsigned int i;
1672
1673 /* init CPU */
1674 if (!cpu_model)
1675 cpu_model = hwdef->default_cpu_model;
1676
1677 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1678
1679 /* set up devices */
1680 ram_init(0, RAM_size, hwdef->max_mem);
1681
1682 prom_init(hwdef->slavio_base, bios_name);
1683
1684 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1685
1686 for (i = 0; i < 8; i++) {
1687 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1688 }
1689
1690 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1691 slavio_irq[1]);
1692
1693 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1694 iommu, &espdma_irq);
1695
1696 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1697 slavio_irq[3], iommu, &ledma_irq);
1698
1699 if (graphic_depth != 8 && graphic_depth != 24) {
1700 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1701 exit (1);
1702 }
1703 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1704 graphic_depth);
1705
1706 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1707
1708 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1709
1710 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1711 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1712 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1713 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1714 escc_init(hwdef->serial_base, slavio_irq[1],
1715 slavio_irq[1], serial_hds[0], serial_hds[1],
1716 ESCC_CLOCK, 1);
1717
1718 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1719
1720 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1721 /* there is zero or one floppy drive */
1722 memset(fd, 0, sizeof(fd));
1723 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1724 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1725 &fdc_tc);
1726 }
1727
1728 if (drive_get_max_bus(IF_SCSI) > 0) {
1729 fprintf(stderr, "qemu: too many SCSI bus\n");
1730 exit(1);
1731 }
1732
1733 esp_reset = qdev_get_gpio_in(espdma, 0);
1734 esp_init(hwdef->esp_base, 2,
1735 espdma_memory_read, espdma_memory_write,
1736 espdma, espdma_irq, &esp_reset);
1737
1738 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1739 RAM_size);
1740
1741 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1742 boot_device, RAM_size, kernel_size, graphic_width,
1743 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1744 "Sun4c");
1745
1746 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1747 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1748 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1749 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1750 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1751 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1752 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1753 if (kernel_cmdline) {
1754 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1755 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1756 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1757 (uint8_t*)strdup(kernel_cmdline),
1758 strlen(kernel_cmdline) + 1);
1759 } else {
1760 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1761 }
1762 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1763 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1764 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1765 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1766 }
1767
1768 /* SPARCstation 2 hardware initialisation */
1769 static void ss2_init(QEMUMachine *machine, QemuOpts *opts)
1770 {
1771 ram_addr_t RAM_size = qemu_opt_get_number(opts, "ram_size", 0);
1772 const char *boot_device = qemu_opt_get(opts, "boot_device");
1773 const char *kernel_filename = qemu_opt_get(opts, "kernel");
1774 const char *kernel_cmdline = qemu_opt_get(opts, "cmdline");
1775 const char *initrd_filename = qemu_opt_get(opts, "initrd");
1776 const char *cpu_model = qemu_opt_get(opts, "cpu");
1777 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1778 kernel_cmdline, initrd_filename, cpu_model);
1779 }
1780
1781 static QEMUMachine ss2_machine = {
1782 .name = "SS-2",
1783 .desc = "Sun4c platform, SPARCstation 2",
1784 .init = ss2_init,
1785 .use_scsi = 1,
1786 };
1787
1788 static void ss2_machine_init(void)
1789 {
1790 qemu_register_machine(&ss5_machine);
1791 qemu_register_machine(&ss10_machine);
1792 qemu_register_machine(&ss600mp_machine);
1793 qemu_register_machine(&ss20_machine);
1794 qemu_register_machine(&voyager_machine);
1795 qemu_register_machine(&ss_lx_machine);
1796 qemu_register_machine(&ss4_machine);
1797 qemu_register_machine(&scls_machine);
1798 qemu_register_machine(&sbook_machine);
1799 qemu_register_machine(&ss1000_machine);
1800 qemu_register_machine(&ss2000_machine);
1801 qemu_register_machine(&ss2_machine);
1802 }
1803
1804 machine_init(ss2_machine_init);
Anthony Liguori's QEMU queue