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Revert "block: prevent multiwrite_merge from creating too large iovecs"
[qemu/aliguori-queue.git] / target-ppc / helper.c
bloba4fae31e3823ecee8f7090e03635db69f556e445
1 /*
2 * PowerPC emulation helpers for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "exec-all.h"
28 #include "helper_regs.h"
29 #include "qemu-common.h"
30 #include "kvm.h"
31
32 //#define DEBUG_MMU
33 //#define DEBUG_BATS
34 //#define DEBUG_SLB
35 //#define DEBUG_SOFTWARE_TLB
36 //#define DUMP_PAGE_TABLES
37 //#define DEBUG_EXCEPTIONS
38 //#define FLUSH_ALL_TLBS
39
40 #ifdef DEBUG_MMU
41 # define LOG_MMU(...) qemu_log(__VA_ARGS__)
42 # define LOG_MMU_STATE(env) log_cpu_state((env), 0)
43 #else
44 # define LOG_MMU(...) do { } while (0)
45 # define LOG_MMU_STATE(...) do { } while (0)
46 #endif
47
48
49 #ifdef DEBUG_SOFTWARE_TLB
50 # define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
51 #else
52 # define LOG_SWTLB(...) do { } while (0)
53 #endif
54
55 #ifdef DEBUG_BATS
56 # define LOG_BATS(...) qemu_log(__VA_ARGS__)
57 #else
58 # define LOG_BATS(...) do { } while (0)
59 #endif
60
61 #ifdef DEBUG_SLB
62 # define LOG_SLB(...) qemu_log(__VA_ARGS__)
63 #else
64 # define LOG_SLB(...) do { } while (0)
65 #endif
66
67 #ifdef DEBUG_EXCEPTIONS
68 # define LOG_EXCP(...) qemu_log(__VA_ARGS__)
69 #else
70 # define LOG_EXCP(...) do { } while (0)
71 #endif
72
73
74 /*****************************************************************************/
75 /* PowerPC MMU emulation */
76
77 #if defined(CONFIG_USER_ONLY)
78 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
79 int mmu_idx, int is_softmmu)
80 {
81 int exception, error_code;
82
83 if (rw == 2) {
84 exception = POWERPC_EXCP_ISI;
85 error_code = 0x40000000;
86 } else {
87 exception = POWERPC_EXCP_DSI;
88 error_code = 0x40000000;
89 if (rw)
90 error_code |= 0x02000000;
91 env->spr[SPR_DAR] = address;
92 env->spr[SPR_DSISR] = error_code;
93 }
94 env->exception_index = exception;
95 env->error_code = error_code;
96
97 return 1;
98 }
99
100 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
101 {
102 return addr;
103 }
104
105 #else
106 /* Common routines used by software and hardware TLBs emulation */
107 static inline int pte_is_valid(target_ulong pte0)
108 {
109 return pte0 & 0x80000000 ? 1 : 0;
110 }
111
112 static inline void pte_invalidate(target_ulong *pte0)
113 {
114 *pte0 &= ~0x80000000;
115 }
116
117 #if defined(TARGET_PPC64)
118 static inline int pte64_is_valid(target_ulong pte0)
119 {
120 return pte0 & 0x0000000000000001ULL ? 1 : 0;
121 }
122
123 static inline void pte64_invalidate(target_ulong *pte0)
124 {
125 *pte0 &= ~0x0000000000000001ULL;
126 }
127 #endif
128
129 #define PTE_PTEM_MASK 0x7FFFFFBF
130 #define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
131 #if defined(TARGET_PPC64)
132 #define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
133 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
134 #endif
135
136 static inline int pp_check(int key, int pp, int nx)
137 {
138 int access;
139
140 /* Compute access rights */
141 /* When pp is 3/7, the result is undefined. Set it to noaccess */
142 access = 0;
143 if (key == 0) {
144 switch (pp) {
145 case 0x0:
146 case 0x1:
147 case 0x2:
148 access |= PAGE_WRITE;
149 /* No break here */
150 case 0x3:
151 case 0x6:
152 access |= PAGE_READ;
153 break;
154 }
155 } else {
156 switch (pp) {
157 case 0x0:
158 case 0x6:
159 access = 0;
160 break;
161 case 0x1:
162 case 0x3:
163 access = PAGE_READ;
164 break;
165 case 0x2:
166 access = PAGE_READ | PAGE_WRITE;
167 break;
168 }
169 }
170 if (nx == 0)
171 access |= PAGE_EXEC;
172
173 return access;
174 }
175
176 static inline int check_prot(int prot, int rw, int access_type)
177 {
178 int ret;
179
180 if (access_type == ACCESS_CODE) {
181 if (prot & PAGE_EXEC)
182 ret = 0;
183 else
184 ret = -2;
185 } else if (rw) {
186 if (prot & PAGE_WRITE)
187 ret = 0;
188 else
189 ret = -2;
190 } else {
191 if (prot & PAGE_READ)
192 ret = 0;
193 else
194 ret = -2;
195 }
196
197 return ret;
198 }
199
200 static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
201 target_ulong pte1, int h, int rw, int type)
202 {
203 target_ulong ptem, mmask;
204 int access, ret, pteh, ptev, pp;
205
206 access = 0;
207 ret = -1;
208 /* Check validity and table match */
209 #if defined(TARGET_PPC64)
210 if (is_64b) {
211 ptev = pte64_is_valid(pte0);
212 pteh = (pte0 >> 1) & 1;
213 } else
214 #endif
215 {
216 ptev = pte_is_valid(pte0);
217 pteh = (pte0 >> 6) & 1;
218 }
219 if (ptev && h == pteh) {
220 /* Check vsid & api */
221 #if defined(TARGET_PPC64)
222 if (is_64b) {
223 ptem = pte0 & PTE64_PTEM_MASK;
224 mmask = PTE64_CHECK_MASK;
225 pp = (pte1 & 0x00000003) | ((pte1 >> 61) & 0x00000004);
226 ctx->nx = (pte1 >> 2) & 1; /* No execute bit */
227 ctx->nx |= (pte1 >> 3) & 1; /* Guarded bit */
228 } else
229 #endif
230 {
231 ptem = pte0 & PTE_PTEM_MASK;
232 mmask = PTE_CHECK_MASK;
233 pp = pte1 & 0x00000003;
234 }
235 if (ptem == ctx->ptem) {
236 if (ctx->raddr != (target_phys_addr_t)-1ULL) {
237 /* all matches should have equal RPN, WIMG & PP */
238 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
239 qemu_log("Bad RPN/WIMG/PP\n");
240 return -3;
241 }
242 }
243 /* Compute access rights */
244 access = pp_check(ctx->key, pp, ctx->nx);
245 /* Keep the matching PTE informations */
246 ctx->raddr = pte1;
247 ctx->prot = access;
248 ret = check_prot(ctx->prot, rw, type);
249 if (ret == 0) {
250 /* Access granted */
251 LOG_MMU("PTE access granted !\n");
252 } else {
253 /* Access right violation */
254 LOG_MMU("PTE access rejected\n");
255 }
256 }
257 }
258
259 return ret;
260 }
261
262 static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
263 target_ulong pte1, int h, int rw, int type)
264 {
265 return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
266 }
267
268 #if defined(TARGET_PPC64)
269 static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
270 target_ulong pte1, int h, int rw, int type)
271 {
272 return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
273 }
274 #endif
275
276 static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
277 int ret, int rw)
278 {
279 int store = 0;
280
281 /* Update page flags */
282 if (!(*pte1p & 0x00000100)) {
283 /* Update accessed flag */
284 *pte1p |= 0x00000100;
285 store = 1;
286 }
287 if (!(*pte1p & 0x00000080)) {
288 if (rw == 1 && ret == 0) {
289 /* Update changed flag */
290 *pte1p |= 0x00000080;
291 store = 1;
292 } else {
293 /* Force page fault for first write access */
294 ctx->prot &= ~PAGE_WRITE;
295 }
296 }
297
298 return store;
299 }
300
301 /* Software driven TLB helpers */
302 static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
303 int is_code)
304 {
305 int nr;
306
307 /* Select TLB num in a way from address */
308 nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
309 /* Select TLB way */
310 nr += env->tlb_per_way * way;
311 /* 6xx have separate TLBs for instructions and data */
312 if (is_code && env->id_tlbs == 1)
313 nr += env->nb_tlb;
314
315 return nr;
316 }
317
318 static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
319 {
320 ppc6xx_tlb_t *tlb;
321 int nr, max;
322
323 //LOG_SWTLB("Invalidate all TLBs\n");
324 /* Invalidate all defined software TLB */
325 max = env->nb_tlb;
326 if (env->id_tlbs == 1)
327 max *= 2;
328 for (nr = 0; nr < max; nr++) {
329 tlb = &env->tlb[nr].tlb6;
330 pte_invalidate(&tlb->pte0);
331 }
332 tlb_flush(env, 1);
333 }
334
335 static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
336 target_ulong eaddr,
337 int is_code, int match_epn)
338 {
339 #if !defined(FLUSH_ALL_TLBS)
340 ppc6xx_tlb_t *tlb;
341 int way, nr;
342
343 /* Invalidate ITLB + DTLB, all ways */
344 for (way = 0; way < env->nb_ways; way++) {
345 nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
346 tlb = &env->tlb[nr].tlb6;
347 if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
348 LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
349 env->nb_tlb, eaddr);
350 pte_invalidate(&tlb->pte0);
351 tlb_flush_page(env, tlb->EPN);
352 }
353 }
354 #else
355 /* XXX: PowerPC specification say this is valid as well */
356 ppc6xx_tlb_invalidate_all(env);
357 #endif
358 }
359
360 static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,
361 target_ulong eaddr, int is_code)
362 {
363 __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
364 }
365
366 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
367 target_ulong pte0, target_ulong pte1)
368 {
369 ppc6xx_tlb_t *tlb;
370 int nr;
371
372 nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
373 tlb = &env->tlb[nr].tlb6;
374 LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx
375 " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);
376 /* Invalidate any pending reference in Qemu for this virtual address */
377 __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
378 tlb->pte0 = pte0;
379 tlb->pte1 = pte1;
380 tlb->EPN = EPN;
381 /* Store last way for LRU mechanism */
382 env->last_way = way;
383 }
384
385 static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
386 target_ulong eaddr, int rw, int access_type)
387 {
388 ppc6xx_tlb_t *tlb;
389 int nr, best, way;
390 int ret;
391
392 best = -1;
393 ret = -1; /* No TLB found */
394 for (way = 0; way < env->nb_ways; way++) {
395 nr = ppc6xx_tlb_getnum(env, eaddr, way,
396 access_type == ACCESS_CODE ? 1 : 0);
397 tlb = &env->tlb[nr].tlb6;
398 /* This test "emulates" the PTE index match for hardware TLBs */
399 if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
400 LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
401 "] <> " TARGET_FMT_lx "\n", nr, env->nb_tlb,
402 pte_is_valid(tlb->pte0) ? "valid" : "inval",
403 tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
404 continue;
405 }
406 LOG_SWTLB("TLB %d/%d %s " TARGET_FMT_lx " <> " TARGET_FMT_lx " "
407 TARGET_FMT_lx " %c %c\n", nr, env->nb_tlb,
408 pte_is_valid(tlb->pte0) ? "valid" : "inval",
409 tlb->EPN, eaddr, tlb->pte1,
410 rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
411 switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
412 case -3:
413 /* TLB inconsistency */
414 return -1;
415 case -2:
416 /* Access violation */
417 ret = -2;
418 best = nr;
419 break;
420 case -1:
421 default:
422 /* No match */
423 break;
424 case 0:
425 /* access granted */
426 /* XXX: we should go on looping to check all TLBs consistency
427 * but we can speed-up the whole thing as the
428 * result would be undefined if TLBs are not consistent.
429 */
430 ret = 0;
431 best = nr;
432 goto done;
433 }
434 }
435 if (best != -1) {
436 done:
437 LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",
438 ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
439 /* Update page flags */
440 pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
441 }
442
443 return ret;
444 }
445
446 /* Perform BAT hit & translation */
447 static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
448 int *protp, target_ulong *BATu,
449 target_ulong *BATl)
450 {
451 target_ulong bl;
452 int pp, valid, prot;
453
454 bl = (*BATu & 0x00001FFC) << 15;
455 valid = 0;
456 prot = 0;
457 if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
458 ((msr_pr != 0) && (*BATu & 0x00000001))) {
459 valid = 1;
460 pp = *BATl & 0x00000003;
461 if (pp != 0) {
462 prot = PAGE_READ | PAGE_EXEC;
463 if (pp == 0x2)
464 prot |= PAGE_WRITE;
465 }
466 }
467 *blp = bl;
468 *validp = valid;
469 *protp = prot;
470 }
471
472 static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
473 int *validp, int *protp,
474 target_ulong *BATu, target_ulong *BATl)
475 {
476 target_ulong bl;
477 int key, pp, valid, prot;
478
479 bl = (*BATl & 0x0000003F) << 17;
480 LOG_BATS("b %02x ==> bl " TARGET_FMT_lx " msk " TARGET_FMT_lx "\n",
481 (uint8_t)(*BATl & 0x0000003F), bl, ~bl);
482 prot = 0;
483 valid = (*BATl >> 6) & 1;
484 if (valid) {
485 pp = *BATu & 0x00000003;
486 if (msr_pr == 0)
487 key = (*BATu >> 3) & 1;
488 else
489 key = (*BATu >> 2) & 1;
490 prot = pp_check(key, pp, 0);
491 }
492 *blp = bl;
493 *validp = valid;
494 *protp = prot;
495 }
496
497 static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
498 int rw, int type)
499 {
500 target_ulong *BATlt, *BATut, *BATu, *BATl;
501 target_ulong base, BEPIl, BEPIu, bl;
502 int i, valid, prot;
503 int ret = -1;
504
505 LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
506 type == ACCESS_CODE ? 'I' : 'D', virtual);
507 switch (type) {
508 case ACCESS_CODE:
509 BATlt = env->IBAT[1];
510 BATut = env->IBAT[0];
511 break;
512 default:
513 BATlt = env->DBAT[1];
514 BATut = env->DBAT[0];
515 break;
516 }
517 base = virtual & 0xFFFC0000;
518 for (i = 0; i < env->nb_BATs; i++) {
519 BATu = &BATut[i];
520 BATl = &BATlt[i];
521 BEPIu = *BATu & 0xF0000000;
522 BEPIl = *BATu & 0x0FFE0000;
523 if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
524 bat_601_size_prot(env, &bl, &valid, &prot, BATu, BATl);
525 } else {
526 bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
527 }
528 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
529 " BATl " TARGET_FMT_lx "\n", __func__,
530 type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
531 if ((virtual & 0xF0000000) == BEPIu &&
532 ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
533 /* BAT matches */
534 if (valid != 0) {
535 /* Get physical address */
536 ctx->raddr = (*BATl & 0xF0000000) |
537 ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
538 (virtual & 0x0001F000);
539 /* Compute access rights */
540 ctx->prot = prot;
541 ret = check_prot(ctx->prot, rw, type);
542 if (ret == 0)
543 LOG_BATS("BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n",
544 i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
545 ctx->prot & PAGE_WRITE ? 'W' : '-');
546 break;
547 }
548 }
549 }
550 if (ret < 0) {
551 #if defined(DEBUG_BATS)
552 if (qemu_log_enabled()) {
553 LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", virtual);
554 for (i = 0; i < 4; i++) {
555 BATu = &BATut[i];
556 BATl = &BATlt[i];
557 BEPIu = *BATu & 0xF0000000;
558 BEPIl = *BATu & 0x0FFE0000;
559 bl = (*BATu & 0x00001FFC) << 15;
560 LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
561 " BATl " TARGET_FMT_lx " \n\t" TARGET_FMT_lx " "
562 TARGET_FMT_lx " " TARGET_FMT_lx "\n",
563 __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
564 *BATu, *BATl, BEPIu, BEPIl, bl);
565 }
566 }
567 #endif
568 }
569 /* No hit */
570 return ret;
571 }
572
573 /* PTE table lookup */
574 static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
575 int type, int target_page_bits)
576 {
577 target_ulong base, pte0, pte1;
578 int i, good = -1;
579 int ret, r;
580
581 ret = -1; /* No entry found */
582 base = ctx->pg_addr[h];
583 for (i = 0; i < 8; i++) {
584 #if defined(TARGET_PPC64)
585 if (is_64b) {
586 pte0 = ldq_phys(base + (i * 16));
587 pte1 = ldq_phys(base + (i * 16) + 8);
588
589 /* We have a TLB that saves 4K pages, so let's
590 * split a huge page to 4k chunks */
591 if (target_page_bits != TARGET_PAGE_BITS)
592 pte1 |= (ctx->eaddr & (( 1 << target_page_bits ) - 1))
593 & TARGET_PAGE_MASK;
594
595 r = pte64_check(ctx, pte0, pte1, h, rw, type);
596 LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
597 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
598 base + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
599 (int)((pte0 >> 1) & 1), ctx->ptem);
600 } else
601 #endif
602 {
603 pte0 = ldl_phys(base + (i * 8));
604 pte1 = ldl_phys(base + (i * 8) + 4);
605 r = pte32_check(ctx, pte0, pte1, h, rw, type);
606 LOG_MMU("Load pte from " TARGET_FMT_lx " => " TARGET_FMT_lx " "
607 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
608 base + (i * 8), pte0, pte1, (int)(pte0 >> 31), h,
609 (int)((pte0 >> 6) & 1), ctx->ptem);
610 }
611 switch (r) {
612 case -3:
613 /* PTE inconsistency */
614 return -1;
615 case -2:
616 /* Access violation */
617 ret = -2;
618 good = i;
619 break;
620 case -1:
621 default:
622 /* No PTE match */
623 break;
624 case 0:
625 /* access granted */
626 /* XXX: we should go on looping to check all PTEs consistency
627 * but if we can speed-up the whole thing as the
628 * result would be undefined if PTEs are not consistent.
629 */
630 ret = 0;
631 good = i;
632 goto done;
633 }
634 }
635 if (good != -1) {
636 done:
637 LOG_MMU("found PTE at addr " TARGET_FMT_lx " prot=%01x ret=%d\n",
638 ctx->raddr, ctx->prot, ret);
639 /* Update page flags */
640 pte1 = ctx->raddr;
641 if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
642 #if defined(TARGET_PPC64)
643 if (is_64b) {
644 stq_phys_notdirty(base + (good * 16) + 8, pte1);
645 } else
646 #endif
647 {
648 stl_phys_notdirty(base + (good * 8) + 4, pte1);
649 }
650 }
651 }
652
653 return ret;
654 }
655
656 static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
657 int target_page_bits)
658 {
659 return _find_pte(ctx, 0, h, rw, type, target_page_bits);
660 }
661
662 #if defined(TARGET_PPC64)
663 static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
664 int target_page_bits)
665 {
666 return _find_pte(ctx, 1, h, rw, type, target_page_bits);
667 }
668 #endif
669
670 static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
671 int type, int target_page_bits)
672 {
673 #if defined(TARGET_PPC64)
674 if (env->mmu_model & POWERPC_MMU_64)
675 return find_pte64(ctx, h, rw, type, target_page_bits);
676 #endif
677
678 return find_pte32(ctx, h, rw, type, target_page_bits);
679 }
680
681 #if defined(TARGET_PPC64)
682 static ppc_slb_t *slb_get_entry(CPUPPCState *env, int nr)
683 {
684 ppc_slb_t *retval = &env->slb[nr];
685
686 #if 0 // XXX implement bridge mode?
687 if (env->spr[SPR_ASR] & 1) {
688 target_phys_addr_t sr_base;
689
690 sr_base = env->spr[SPR_ASR] & 0xfffffffffffff000;
691 sr_base += (12 * nr);
692
693 retval->tmp64 = ldq_phys(sr_base);
694 retval->tmp = ldl_phys(sr_base + 8);
695 }
696 #endif
697
698 return retval;
699 }
700
701 static void slb_set_entry(CPUPPCState *env, int nr, ppc_slb_t *slb)
702 {
703 ppc_slb_t *entry = &env->slb[nr];
704
705 if (slb == entry)
706 return;
707
708 entry->tmp64 = slb->tmp64;
709 entry->tmp = slb->tmp;
710 }
711
712 static inline int slb_is_valid(ppc_slb_t *slb)
713 {
714 return (int)(slb->tmp64 & 0x0000000008000000ULL);
715 }
716
717 static inline void slb_invalidate(ppc_slb_t *slb)
718 {
719 slb->tmp64 &= ~0x0000000008000000ULL;
720 }
721
722 static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
723 target_ulong *vsid, target_ulong *page_mask,
724 int *attr, int *target_page_bits)
725 {
726 target_ulong mask;
727 int n, ret;
728
729 ret = -5;
730 LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
731 mask = 0x0000000000000000ULL; /* Avoid gcc warning */
732 for (n = 0; n < env->slb_nr; n++) {
733 ppc_slb_t *slb = slb_get_entry(env, n);
734
735 LOG_SLB("%s: seg %d %016" PRIx64 " %08"
736 PRIx32 "\n", __func__, n, slb->tmp64, slb->tmp);
737 if (slb_is_valid(slb)) {
738 /* SLB entry is valid */
739 if (slb->tmp & 0x8) {
740 /* 1 TB Segment */
741 mask = 0xFFFF000000000000ULL;
742 if (target_page_bits)
743 *target_page_bits = 24; // XXX 16M pages?
744 } else {
745 /* 256MB Segment */
746 mask = 0xFFFFFFFFF0000000ULL;
747 if (target_page_bits)
748 *target_page_bits = TARGET_PAGE_BITS;
749 }
750 if ((eaddr & mask) == (slb->tmp64 & mask)) {
751 /* SLB match */
752 *vsid = ((slb->tmp64 << 24) | (slb->tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
753 *page_mask = ~mask;
754 *attr = slb->tmp & 0xFF;
755 ret = n;
756 break;
757 }
758 }
759 }
760
761 return ret;
762 }
763
764 void ppc_slb_invalidate_all (CPUPPCState *env)
765 {
766 int n, do_invalidate;
767
768 do_invalidate = 0;
769 /* XXX: Warning: slbia never invalidates the first segment */
770 for (n = 1; n < env->slb_nr; n++) {
771 ppc_slb_t *slb = slb_get_entry(env, n);
772
773 if (slb_is_valid(slb)) {
774 slb_invalidate(slb);
775 slb_set_entry(env, n, slb);
776 /* XXX: given the fact that segment size is 256 MB or 1TB,
777 * and we still don't have a tlb_flush_mask(env, n, mask)
778 * in Qemu, we just invalidate all TLBs
779 */
780 do_invalidate = 1;
781 }
782 }
783 if (do_invalidate)
784 tlb_flush(env, 1);
785 }
786
787 void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
788 {
789 target_ulong vsid, page_mask;
790 int attr;
791 int n;
792
793 n = slb_lookup(env, T0, &vsid, &page_mask, &attr, NULL);
794 if (n >= 0) {
795 ppc_slb_t *slb = slb_get_entry(env, n);
796
797 if (slb_is_valid(slb)) {
798 slb_invalidate(slb);
799 slb_set_entry(env, n, slb);
800 /* XXX: given the fact that segment size is 256 MB or 1TB,
801 * and we still don't have a tlb_flush_mask(env, n, mask)
802 * in Qemu, we just invalidate all TLBs
803 */
804 tlb_flush(env, 1);
805 }
806 }
807 }
808
809 target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
810 {
811 target_ulong rt;
812 ppc_slb_t *slb = slb_get_entry(env, slb_nr);
813
814 if (slb_is_valid(slb)) {
815 /* SLB entry is valid */
816 /* Copy SLB bits 62:88 to Rt 37:63 (VSID 23:49) */
817 rt = slb->tmp >> 8; /* 65:88 => 40:63 */
818 rt |= (slb->tmp64 & 0x7) << 24; /* 62:64 => 37:39 */
819 /* Copy SLB bits 89:92 to Rt 33:36 (KsKpNL) */
820 rt |= ((slb->tmp >> 4) & 0xF) << 27;
821 } else {
822 rt = 0;
823 }
824 LOG_SLB("%s: %016" PRIx64 " %08" PRIx32 " => %d "
825 TARGET_FMT_lx "\n", __func__, slb->tmp64, slb->tmp, slb_nr, rt);
826
827 return rt;
828 }
829
830 void ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs)
831 {
832 ppc_slb_t *slb;
833
834 uint64_t vsid;
835 uint64_t esid;
836 int flags, valid, slb_nr;
837
838 vsid = rs >> 12;
839 flags = ((rs >> 8) & 0xf);
840
841 esid = rb >> 28;
842 valid = (rb & (1 << 27));
843 slb_nr = rb & 0xfff;
844
845 slb = slb_get_entry(env, slb_nr);
846 slb->tmp64 = (esid << 28) | valid | (vsid >> 24);
847 slb->tmp = (vsid << 8) | (flags << 3);
848
849 LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
850 " %08" PRIx32 "\n", __func__, slb_nr, rb, rs, slb->tmp64,
851 slb->tmp);
852
853 slb_set_entry(env, slb_nr, slb);
854 }
855 #endif /* defined(TARGET_PPC64) */
856
857 /* Perform segment based translation */
858 static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
859 int sdr_sh,
860 target_phys_addr_t hash,
861 target_phys_addr_t mask)
862 {
863 return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
864 }
865
866 static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
867 target_ulong eaddr, int rw, int type)
868 {
869 target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
870 target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
871 #if defined(TARGET_PPC64)
872 int attr;
873 #endif
874 int ds, vsid_sh, sdr_sh, pr, target_page_bits;
875 int ret, ret2;
876
877 pr = msr_pr;
878 #if defined(TARGET_PPC64)
879 if (env->mmu_model & POWERPC_MMU_64) {
880 LOG_MMU("Check SLBs\n");
881 ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr,
882 &target_page_bits);
883 if (ret < 0)
884 return ret;
885 ctx->key = ((attr & 0x40) && (pr != 0)) ||
886 ((attr & 0x80) && (pr == 0)) ? 1 : 0;
887 ds = 0;
888 ctx->nx = attr & 0x10 ? 1 : 0;
889 ctx->eaddr = eaddr;
890 vsid_mask = 0x00003FFFFFFFFF80ULL;
891 vsid_sh = 7;
892 sdr_sh = 18;
893 sdr_mask = 0x3FF80;
894 } else
895 #endif /* defined(TARGET_PPC64) */
896 {
897 sr = env->sr[eaddr >> 28];
898 page_mask = 0x0FFFFFFF;
899 ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
900 ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
901 ds = sr & 0x80000000 ? 1 : 0;
902 ctx->nx = sr & 0x10000000 ? 1 : 0;
903 vsid = sr & 0x00FFFFFF;
904 vsid_mask = 0x01FFFFC0;
905 vsid_sh = 6;
906 sdr_sh = 16;
907 sdr_mask = 0xFFC0;
908 target_page_bits = TARGET_PAGE_BITS;
909 LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip="
910 TARGET_FMT_lx " lr=" TARGET_FMT_lx
911 " ir=%d dr=%d pr=%d %d t=%d\n",
912 eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
913 (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
914 }
915 LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
916 ctx->key, ds, ctx->nx, vsid);
917 ret = -1;
918 if (!ds) {
919 /* Check if instruction fetch is allowed, if needed */
920 if (type != ACCESS_CODE || ctx->nx == 0) {
921 /* Page address translation */
922 /* Primary table address */
923 sdr = env->sdr1;
924 pgidx = (eaddr & page_mask) >> target_page_bits;
925 #if defined(TARGET_PPC64)
926 if (env->mmu_model & POWERPC_MMU_64) {
927 htab_mask = 0x0FFFFFFF >> (28 - (sdr & 0x1F));
928 /* XXX: this is false for 1 TB segments */
929 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
930 } else
931 #endif
932 {
933 htab_mask = sdr & 0x000001FF;
934 hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
935 }
936 mask = (htab_mask << sdr_sh) | sdr_mask;
937 LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
938 " mask " TARGET_FMT_plx " " TARGET_FMT_lx "\n",
939 sdr, sdr_sh, hash, mask, page_mask);
940 ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
941 /* Secondary table address */
942 hash = (~hash) & vsid_mask;
943 LOG_MMU("sdr " TARGET_FMT_plx " sh %d hash " TARGET_FMT_plx
944 " mask " TARGET_FMT_plx "\n", sdr, sdr_sh, hash, mask);
945 ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
946 #if defined(TARGET_PPC64)
947 if (env->mmu_model & POWERPC_MMU_64) {
948 /* Only 5 bits of the page index are used in the AVPN */
949 if (target_page_bits > 23) {
950 ctx->ptem = (vsid << 12) |
951 ((pgidx << (target_page_bits - 16)) & 0xF80);
952 } else {
953 ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
954 }
955 } else
956 #endif
957 {
958 ctx->ptem = (vsid << 7) | (pgidx >> 10);
959 }
960 /* Initialize real address with an invalid value */
961 ctx->raddr = (target_phys_addr_t)-1ULL;
962 if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
963 env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
964 /* Software TLB search */
965 ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
966 } else {
967 LOG_MMU("0 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
968 "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
969 " pg_addr=" TARGET_FMT_plx "\n",
970 sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
971 /* Primary table lookup */
972 ret = find_pte(env, ctx, 0, rw, type, target_page_bits);
973 if (ret < 0) {
974 /* Secondary table lookup */
975 if (eaddr != 0xEFFFFFFF)
976 LOG_MMU("1 sdr1=" TARGET_FMT_plx " vsid=" TARGET_FMT_lx " "
977 "api=" TARGET_FMT_lx " hash=" TARGET_FMT_plx
978 " pg_addr=" TARGET_FMT_plx "\n", sdr, vsid,
979 pgidx, hash, ctx->pg_addr[1]);
980 ret2 = find_pte(env, ctx, 1, rw, type,
981 target_page_bits);
982 if (ret2 != -1)
983 ret = ret2;
984 }
985 }
986 #if defined (DUMP_PAGE_TABLES)
987 if (qemu_log_enabled()) {
988 target_phys_addr_t curaddr;
989 uint32_t a0, a1, a2, a3;
990 qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
991 "\n", sdr, mask + 0x80);
992 for (curaddr = sdr; curaddr < (sdr + mask + 0x80);
993 curaddr += 16) {
994 a0 = ldl_phys(curaddr);
995 a1 = ldl_phys(curaddr + 4);
996 a2 = ldl_phys(curaddr + 8);
997 a3 = ldl_phys(curaddr + 12);
998 if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) {
999 qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n",
1000 curaddr, a0, a1, a2, a3);
1001 }
1002 }
1003 }
1004 #endif
1005 } else {
1006 LOG_MMU("No access allowed\n");
1007 ret = -3;
1008 }
1009 } else {
1010 LOG_MMU("direct store...\n");
1011 /* Direct-store segment : absolutely *BUGGY* for now */
1012 switch (type) {
1013 case ACCESS_INT:
1014 /* Integer load/store : only access allowed */
1015 break;
1016 case ACCESS_CODE:
1017 /* No code fetch is allowed in direct-store areas */
1018 return -4;
1019 case ACCESS_FLOAT:
1020 /* Floating point load/store */
1021 return -4;
1022 case ACCESS_RES:
1023 /* lwarx, ldarx or srwcx. */
1024 return -4;
1025 case ACCESS_CACHE:
1026 /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
1027 /* Should make the instruction do no-op.
1028 * As it already do no-op, it's quite easy :-)
1029 */
1030 ctx->raddr = eaddr;
1031 return 0;
1032 case ACCESS_EXT:
1033 /* eciwx or ecowx */
1034 return -4;
1035 default:
1036 qemu_log("ERROR: instruction should not need "
1037 "address translation\n");
1038 return -4;
1039 }
1040 if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
1041 ctx->raddr = eaddr;
1042 ret = 2;
1043 } else {
1044 ret = -2;
1045 }
1046 }
1047
1048 return ret;
1049 }
1050
1051 /* Generic TLB check function for embedded PowerPC implementations */
1052 static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
1053 target_phys_addr_t *raddrp,
1054 target_ulong address, uint32_t pid, int ext,
1055 int i)
1056 {
1057 target_ulong mask;
1058
1059 /* Check valid flag */
1060 if (!(tlb->prot & PAGE_VALID)) {
1061 qemu_log("%s: TLB %d not valid\n", __func__, i);
1062 return -1;
1063 }
1064 mask = ~(tlb->size - 1);
1065 LOG_SWTLB("%s: TLB %d address " TARGET_FMT_lx " PID %u <=> " TARGET_FMT_lx
1066 " " TARGET_FMT_lx " %u\n", __func__, i, address, pid, tlb->EPN,
1067 mask, (uint32_t)tlb->PID);
1068 /* Check PID */
1069 if (tlb->PID != 0 && tlb->PID != pid)
1070 return -1;
1071 /* Check effective address */
1072 if ((address & mask) != tlb->EPN)
1073 return -1;
1074 *raddrp = (tlb->RPN & mask) | (address & ~mask);
1075 #if (TARGET_PHYS_ADDR_BITS >= 36)
1076 if (ext) {
1077 /* Extend the physical address to 36 bits */
1078 *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
1079 }
1080 #endif
1081
1082 return 0;
1083 }
1084
1085 /* Generic TLB search function for PowerPC embedded implementations */
1086 int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
1087 {
1088 ppcemb_tlb_t *tlb;
1089 target_phys_addr_t raddr;
1090 int i, ret;
1091
1092 /* Default return value is no match */
1093 ret = -1;
1094 for (i = 0; i < env->nb_tlb; i++) {
1095 tlb = &env->tlb[i].tlbe;
1096 if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
1097 ret = i;
1098 break;
1099 }
1100 }
1101
1102 return ret;
1103 }
1104
1105 /* Helpers specific to PowerPC 40x implementations */
1106 static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
1107 {
1108 ppcemb_tlb_t *tlb;
1109 int i;
1110
1111 for (i = 0; i < env->nb_tlb; i++) {
1112 tlb = &env->tlb[i].tlbe;
1113 tlb->prot &= ~PAGE_VALID;
1114 }
1115 tlb_flush(env, 1);
1116 }
1117
1118 static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
1119 target_ulong eaddr, uint32_t pid)
1120 {
1121 #if !defined(FLUSH_ALL_TLBS)
1122 ppcemb_tlb_t *tlb;
1123 target_phys_addr_t raddr;
1124 target_ulong page, end;
1125 int i;
1126
1127 for (i = 0; i < env->nb_tlb; i++) {
1128 tlb = &env->tlb[i].tlbe;
1129 if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
1130 end = tlb->EPN + tlb->size;
1131 for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
1132 tlb_flush_page(env, page);
1133 tlb->prot &= ~PAGE_VALID;
1134 break;
1135 }
1136 }
1137 #else
1138 ppc4xx_tlb_invalidate_all(env);
1139 #endif
1140 }
1141
1142 static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1143 target_ulong address, int rw, int access_type)
1144 {
1145 ppcemb_tlb_t *tlb;
1146 target_phys_addr_t raddr;
1147 int i, ret, zsel, zpr, pr;
1148
1149 ret = -1;
1150 raddr = (target_phys_addr_t)-1ULL;
1151 pr = msr_pr;
1152 for (i = 0; i < env->nb_tlb; i++) {
1153 tlb = &env->tlb[i].tlbe;
1154 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1155 env->spr[SPR_40x_PID], 0, i) < 0)
1156 continue;
1157 zsel = (tlb->attr >> 4) & 0xF;
1158 zpr = (env->spr[SPR_40x_ZPR] >> (30 - (2 * zsel))) & 0x3;
1159 LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
1160 __func__, i, zsel, zpr, rw, tlb->attr);
1161 /* Check execute enable bit */
1162 switch (zpr) {
1163 case 0x2:
1164 if (pr != 0)
1165 goto check_perms;
1166 /* No break here */
1167 case 0x3:
1168 /* All accesses granted */
1169 ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1170 ret = 0;
1171 break;
1172 case 0x0:
1173 if (pr != 0) {
1174 /* Raise Zone protection fault. */
1175 env->spr[SPR_40x_ESR] = 1 << 22;
1176 ctx->prot = 0;
1177 ret = -2;
1178 break;
1179 }
1180 /* No break here */
1181 case 0x1:
1182 check_perms:
1183 /* Check from TLB entry */
1184 /* XXX: there is a problem here or in the TLB fill code... */
1185 ctx->prot = tlb->prot;
1186 ctx->prot |= PAGE_EXEC;
1187 ret = check_prot(ctx->prot, rw, access_type);
1188 if (ret == -2)
1189 env->spr[SPR_40x_ESR] = 0;
1190 break;
1191 }
1192 if (ret >= 0) {
1193 ctx->raddr = raddr;
1194 LOG_SWTLB("%s: access granted " TARGET_FMT_lx " => " TARGET_FMT_plx
1195 " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1196 ret);
1197 return 0;
1198 }
1199 }
1200 LOG_SWTLB("%s: access refused " TARGET_FMT_lx " => " TARGET_FMT_plx
1201 " %d %d\n", __func__, address, raddr, ctx->prot, ret);
1202
1203 return ret;
1204 }
1205
1206 void store_40x_sler (CPUPPCState *env, uint32_t val)
1207 {
1208 /* XXX: TO BE FIXED */
1209 if (val != 0x00000000) {
1210 cpu_abort(env, "Little-endian regions are not supported by now\n");
1211 }
1212 env->spr[SPR_405_SLER] = val;
1213 }
1214
1215 static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1216 target_ulong address, int rw,
1217 int access_type)
1218 {
1219 ppcemb_tlb_t *tlb;
1220 target_phys_addr_t raddr;
1221 int i, prot, ret;
1222
1223 ret = -1;
1224 raddr = (target_phys_addr_t)-1ULL;
1225 for (i = 0; i < env->nb_tlb; i++) {
1226 tlb = &env->tlb[i].tlbe;
1227 if (ppcemb_tlb_check(env, tlb, &raddr, address,
1228 env->spr[SPR_BOOKE_PID], 1, i) < 0)
1229 continue;
1230 if (msr_pr != 0)
1231 prot = tlb->prot & 0xF;
1232 else
1233 prot = (tlb->prot >> 4) & 0xF;
1234 /* Check the address space */
1235 if (access_type == ACCESS_CODE) {
1236 if (msr_ir != (tlb->attr & 1))
1237 continue;
1238 ctx->prot = prot;
1239 if (prot & PAGE_EXEC) {
1240 ret = 0;
1241 break;
1242 }
1243 ret = -3;
1244 } else {
1245 if (msr_dr != (tlb->attr & 1))
1246 continue;
1247 ctx->prot = prot;
1248 if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1249 ret = 0;
1250 break;
1251 }
1252 ret = -2;
1253 }
1254 }
1255 if (ret >= 0)
1256 ctx->raddr = raddr;
1257
1258 return ret;
1259 }
1260
1261 static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
1262 target_ulong eaddr, int rw)
1263 {
1264 int in_plb, ret;
1265
1266 ctx->raddr = eaddr;
1267 ctx->prot = PAGE_READ | PAGE_EXEC;
1268 ret = 0;
1269 switch (env->mmu_model) {
1270 case POWERPC_MMU_32B:
1271 case POWERPC_MMU_601:
1272 case POWERPC_MMU_SOFT_6xx:
1273 case POWERPC_MMU_SOFT_74xx:
1274 case POWERPC_MMU_SOFT_4xx:
1275 case POWERPC_MMU_REAL:
1276 case POWERPC_MMU_BOOKE:
1277 ctx->prot |= PAGE_WRITE;
1278 break;
1279 #if defined(TARGET_PPC64)
1280 case POWERPC_MMU_620:
1281 case POWERPC_MMU_64B:
1282 /* Real address are 60 bits long */
1283 ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1284 ctx->prot |= PAGE_WRITE;
1285 break;
1286 #endif
1287 case POWERPC_MMU_SOFT_4xx_Z:
1288 if (unlikely(msr_pe != 0)) {
1289 /* 403 family add some particular protections,
1290 * using PBL/PBU registers for accesses with no translation.
1291 */
1292 in_plb =
1293 /* Check PLB validity */
1294 (env->pb[0] < env->pb[1] &&
1295 /* and address in plb area */
1296 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1297 (env->pb[2] < env->pb[3] &&
1298 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1299 if (in_plb ^ msr_px) {
1300 /* Access in protected area */
1301 if (rw == 1) {
1302 /* Access is not allowed */
1303 ret = -2;
1304 }
1305 } else {
1306 /* Read-write access is allowed */
1307 ctx->prot |= PAGE_WRITE;
1308 }
1309 }
1310 break;
1311 case POWERPC_MMU_MPC8xx:
1312 /* XXX: TODO */
1313 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1314 break;
1315 case POWERPC_MMU_BOOKE_FSL:
1316 /* XXX: TODO */
1317 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1318 break;
1319 default:
1320 cpu_abort(env, "Unknown or invalid MMU model\n");
1321 return -1;
1322 }
1323
1324 return ret;
1325 }
1326
1327 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1328 int rw, int access_type)
1329 {
1330 int ret;
1331
1332 #if 0
1333 qemu_log("%s\n", __func__);
1334 #endif
1335 if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1336 (access_type != ACCESS_CODE && msr_dr == 0)) {
1337 /* No address translation */
1338 ret = check_physical(env, ctx, eaddr, rw);
1339 } else {
1340 ret = -1;
1341 switch (env->mmu_model) {
1342 case POWERPC_MMU_32B:
1343 case POWERPC_MMU_601:
1344 case POWERPC_MMU_SOFT_6xx:
1345 case POWERPC_MMU_SOFT_74xx:
1346 /* Try to find a BAT */
1347 if (env->nb_BATs != 0)
1348 ret = get_bat(env, ctx, eaddr, rw, access_type);
1349 #if defined(TARGET_PPC64)
1350 case POWERPC_MMU_620:
1351 case POWERPC_MMU_64B:
1352 #endif
1353 if (ret < 0) {
1354 /* We didn't match any BAT entry or don't have BATs */
1355 ret = get_segment(env, ctx, eaddr, rw, access_type);
1356 }
1357 break;
1358 case POWERPC_MMU_SOFT_4xx:
1359 case POWERPC_MMU_SOFT_4xx_Z:
1360 ret = mmu40x_get_physical_address(env, ctx, eaddr,
1361 rw, access_type);
1362 break;
1363 case POWERPC_MMU_BOOKE:
1364 ret = mmubooke_get_physical_address(env, ctx, eaddr,
1365 rw, access_type);
1366 break;
1367 case POWERPC_MMU_MPC8xx:
1368 /* XXX: TODO */
1369 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1370 break;
1371 case POWERPC_MMU_BOOKE_FSL:
1372 /* XXX: TODO */
1373 cpu_abort(env, "BookE FSL MMU model not implemented\n");
1374 return -1;
1375 case POWERPC_MMU_REAL:
1376 cpu_abort(env, "PowerPC in real mode do not do any translation\n");
1377 return -1;
1378 default:
1379 cpu_abort(env, "Unknown or invalid MMU model\n");
1380 return -1;
1381 }
1382 }
1383 #if 0
1384 qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
1385 __func__, eaddr, ret, ctx->raddr);
1386 #endif
1387
1388 return ret;
1389 }
1390
1391 target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1392 {
1393 mmu_ctx_t ctx;
1394
1395 if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT) != 0))
1396 return -1;
1397
1398 return ctx.raddr & TARGET_PAGE_MASK;
1399 }
1400
1401 /* Perform address translation */
1402 int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1403 int mmu_idx, int is_softmmu)
1404 {
1405 mmu_ctx_t ctx;
1406 int access_type;
1407 int ret = 0;
1408
1409 if (rw == 2) {
1410 /* code access */
1411 rw = 0;
1412 access_type = ACCESS_CODE;
1413 } else {
1414 /* data access */
1415 access_type = env->access_type;
1416 }
1417 ret = get_physical_address(env, &ctx, address, rw, access_type);
1418 if (ret == 0) {
1419 ret = tlb_set_page_exec(env, address & TARGET_PAGE_MASK,
1420 ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1421 mmu_idx, is_softmmu);
1422 } else if (ret < 0) {
1423 LOG_MMU_STATE(env);
1424 if (access_type == ACCESS_CODE) {
1425 switch (ret) {
1426 case -1:
1427 /* No matches in page tables or TLB */
1428 switch (env->mmu_model) {
1429 case POWERPC_MMU_SOFT_6xx:
1430 env->exception_index = POWERPC_EXCP_IFTLB;
1431 env->error_code = 1 << 18;
1432 env->spr[SPR_IMISS] = address;
1433 env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1434 goto tlb_miss;
1435 case POWERPC_MMU_SOFT_74xx:
1436 env->exception_index = POWERPC_EXCP_IFTLB;
1437 goto tlb_miss_74xx;
1438 case POWERPC_MMU_SOFT_4xx:
1439 case POWERPC_MMU_SOFT_4xx_Z:
1440 env->exception_index = POWERPC_EXCP_ITLB;
1441 env->error_code = 0;
1442 env->spr[SPR_40x_DEAR] = address;
1443 env->spr[SPR_40x_ESR] = 0x00000000;
1444 break;
1445 case POWERPC_MMU_32B:
1446 case POWERPC_MMU_601:
1447 #if defined(TARGET_PPC64)
1448 case POWERPC_MMU_620:
1449 case POWERPC_MMU_64B:
1450 #endif
1451 env->exception_index = POWERPC_EXCP_ISI;
1452 env->error_code = 0x40000000;
1453 break;
1454 case POWERPC_MMU_BOOKE:
1455 /* XXX: TODO */
1456 cpu_abort(env, "BookE MMU model is not implemented\n");
1457 return -1;
1458 case POWERPC_MMU_BOOKE_FSL:
1459 /* XXX: TODO */
1460 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1461 return -1;
1462 case POWERPC_MMU_MPC8xx:
1463 /* XXX: TODO */
1464 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1465 break;
1466 case POWERPC_MMU_REAL:
1467 cpu_abort(env, "PowerPC in real mode should never raise "
1468 "any MMU exceptions\n");
1469 return -1;
1470 default:
1471 cpu_abort(env, "Unknown or invalid MMU model\n");
1472 return -1;
1473 }
1474 break;
1475 case -2:
1476 /* Access rights violation */
1477 env->exception_index = POWERPC_EXCP_ISI;
1478 env->error_code = 0x08000000;
1479 break;
1480 case -3:
1481 /* No execute protection violation */
1482 env->exception_index = POWERPC_EXCP_ISI;
1483 env->error_code = 0x10000000;
1484 break;
1485 case -4:
1486 /* Direct store exception */
1487 /* No code fetch is allowed in direct-store areas */
1488 env->exception_index = POWERPC_EXCP_ISI;
1489 env->error_code = 0x10000000;
1490 break;
1491 #if defined(TARGET_PPC64)
1492 case -5:
1493 /* No match in segment table */
1494 if (env->mmu_model == POWERPC_MMU_620) {
1495 env->exception_index = POWERPC_EXCP_ISI;
1496 /* XXX: this might be incorrect */
1497 env->error_code = 0x40000000;
1498 } else {
1499 env->exception_index = POWERPC_EXCP_ISEG;
1500 env->error_code = 0;
1501 }
1502 break;
1503 #endif
1504 }
1505 } else {
1506 switch (ret) {
1507 case -1:
1508 /* No matches in page tables or TLB */
1509 switch (env->mmu_model) {
1510 case POWERPC_MMU_SOFT_6xx:
1511 if (rw == 1) {
1512 env->exception_index = POWERPC_EXCP_DSTLB;
1513 env->error_code = 1 << 16;
1514 } else {
1515 env->exception_index = POWERPC_EXCP_DLTLB;
1516 env->error_code = 0;
1517 }
1518 env->spr[SPR_DMISS] = address;
1519 env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1520 tlb_miss:
1521 env->error_code |= ctx.key << 19;
1522 env->spr[SPR_HASH1] = ctx.pg_addr[0];
1523 env->spr[SPR_HASH2] = ctx.pg_addr[1];
1524 break;
1525 case POWERPC_MMU_SOFT_74xx:
1526 if (rw == 1) {
1527 env->exception_index = POWERPC_EXCP_DSTLB;
1528 } else {
1529 env->exception_index = POWERPC_EXCP_DLTLB;
1530 }
1531 tlb_miss_74xx:
1532 /* Implement LRU algorithm */
1533 env->error_code = ctx.key << 19;
1534 env->spr[SPR_TLBMISS] = (address & ~((target_ulong)0x3)) |
1535 ((env->last_way + 1) & (env->nb_ways - 1));
1536 env->spr[SPR_PTEHI] = 0x80000000 | ctx.ptem;
1537 break;
1538 case POWERPC_MMU_SOFT_4xx:
1539 case POWERPC_MMU_SOFT_4xx_Z:
1540 env->exception_index = POWERPC_EXCP_DTLB;
1541 env->error_code = 0;
1542 env->spr[SPR_40x_DEAR] = address;
1543 if (rw)
1544 env->spr[SPR_40x_ESR] = 0x00800000;
1545 else
1546 env->spr[SPR_40x_ESR] = 0x00000000;
1547 break;
1548 case POWERPC_MMU_32B:
1549 case POWERPC_MMU_601:
1550 #if defined(TARGET_PPC64)
1551 case POWERPC_MMU_620:
1552 case POWERPC_MMU_64B:
1553 #endif
1554 env->exception_index = POWERPC_EXCP_DSI;
1555 env->error_code = 0;
1556 env->spr[SPR_DAR] = address;
1557 if (rw == 1)
1558 env->spr[SPR_DSISR] = 0x42000000;
1559 else
1560 env->spr[SPR_DSISR] = 0x40000000;
1561 break;
1562 case POWERPC_MMU_MPC8xx:
1563 /* XXX: TODO */
1564 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1565 break;
1566 case POWERPC_MMU_BOOKE:
1567 /* XXX: TODO */
1568 cpu_abort(env, "BookE MMU model is not implemented\n");
1569 return -1;
1570 case POWERPC_MMU_BOOKE_FSL:
1571 /* XXX: TODO */
1572 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1573 return -1;
1574 case POWERPC_MMU_REAL:
1575 cpu_abort(env, "PowerPC in real mode should never raise "
1576 "any MMU exceptions\n");
1577 return -1;
1578 default:
1579 cpu_abort(env, "Unknown or invalid MMU model\n");
1580 return -1;
1581 }
1582 break;
1583 case -2:
1584 /* Access rights violation */
1585 env->exception_index = POWERPC_EXCP_DSI;
1586 env->error_code = 0;
1587 if (env->mmu_model == POWERPC_MMU_SOFT_4xx
1588 || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
1589 env->spr[SPR_40x_DEAR] = address;
1590 if (rw) {
1591 env->spr[SPR_40x_ESR] |= 0x00800000;
1592 }
1593 } else {
1594 env->spr[SPR_DAR] = address;
1595 if (rw == 1) {
1596 env->spr[SPR_DSISR] = 0x0A000000;
1597 } else {
1598 env->spr[SPR_DSISR] = 0x08000000;
1599 }
1600 }
1601 break;
1602 case -4:
1603 /* Direct store exception */
1604 switch (access_type) {
1605 case ACCESS_FLOAT:
1606 /* Floating point load/store */
1607 env->exception_index = POWERPC_EXCP_ALIGN;
1608 env->error_code = POWERPC_EXCP_ALIGN_FP;
1609 env->spr[SPR_DAR] = address;
1610 break;
1611 case ACCESS_RES:
1612 /* lwarx, ldarx or stwcx. */
1613 env->exception_index = POWERPC_EXCP_DSI;
1614 env->error_code = 0;
1615 env->spr[SPR_DAR] = address;
1616 if (rw == 1)
1617 env->spr[SPR_DSISR] = 0x06000000;
1618 else
1619 env->spr[SPR_DSISR] = 0x04000000;
1620 break;
1621 case ACCESS_EXT:
1622 /* eciwx or ecowx */
1623 env->exception_index = POWERPC_EXCP_DSI;
1624 env->error_code = 0;
1625 env->spr[SPR_DAR] = address;
1626 if (rw == 1)
1627 env->spr[SPR_DSISR] = 0x06100000;
1628 else
1629 env->spr[SPR_DSISR] = 0x04100000;
1630 break;
1631 default:
1632 printf("DSI: invalid exception (%d)\n", ret);
1633 env->exception_index = POWERPC_EXCP_PROGRAM;
1634 env->error_code =
1635 POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1636 env->spr[SPR_DAR] = address;
1637 break;
1638 }
1639 break;
1640 #if defined(TARGET_PPC64)
1641 case -5:
1642 /* No match in segment table */
1643 if (env->mmu_model == POWERPC_MMU_620) {
1644 env->exception_index = POWERPC_EXCP_DSI;
1645 env->error_code = 0;
1646 env->spr[SPR_DAR] = address;
1647 /* XXX: this might be incorrect */
1648 if (rw == 1)
1649 env->spr[SPR_DSISR] = 0x42000000;
1650 else
1651 env->spr[SPR_DSISR] = 0x40000000;
1652 } else {
1653 env->exception_index = POWERPC_EXCP_DSEG;
1654 env->error_code = 0;
1655 env->spr[SPR_DAR] = address;
1656 }
1657 break;
1658 #endif
1659 }
1660 }
1661 #if 0
1662 printf("%s: set exception to %d %02x\n", __func__,
1663 env->exception, env->error_code);
1664 #endif
1665 ret = 1;
1666 }
1667
1668 return ret;
1669 }
1670
1671 /*****************************************************************************/
1672 /* BATs management */
1673 #if !defined(FLUSH_ALL_TLBS)
1674 static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
1675 target_ulong mask)
1676 {
1677 target_ulong base, end, page;
1678
1679 base = BATu & ~0x0001FFFF;
1680 end = base + mask + 0x00020000;
1681 LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
1682 TARGET_FMT_lx ")\n", base, end, mask);
1683 for (page = base; page != end; page += TARGET_PAGE_SIZE)
1684 tlb_flush_page(env, page);
1685 LOG_BATS("Flush done\n");
1686 }
1687 #endif
1688
1689 static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
1690 target_ulong value)
1691 {
1692 LOG_BATS("Set %cBAT%d%c to " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", ID,
1693 nr, ul == 0 ? 'u' : 'l', value, env->nip);
1694 }
1695
1696 void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1697 {
1698 target_ulong mask;
1699
1700 dump_store_bat(env, 'I', 0, nr, value);
1701 if (env->IBAT[0][nr] != value) {
1702 mask = (value << 15) & 0x0FFE0000UL;
1703 #if !defined(FLUSH_ALL_TLBS)
1704 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1705 #endif
1706 /* When storing valid upper BAT, mask BEPI and BRPN
1707 * and invalidate all TLBs covered by this BAT
1708 */
1709 mask = (value << 15) & 0x0FFE0000UL;
1710 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1711 (value & ~0x0001FFFFUL & ~mask);
1712 env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1713 (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1714 #if !defined(FLUSH_ALL_TLBS)
1715 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1716 #else
1717 tlb_flush(env, 1);
1718 #endif
1719 }
1720 }
1721
1722 void ppc_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1723 {
1724 dump_store_bat(env, 'I', 1, nr, value);
1725 env->IBAT[1][nr] = value;
1726 }
1727
1728 void ppc_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1729 {
1730 target_ulong mask;
1731
1732 dump_store_bat(env, 'D', 0, nr, value);
1733 if (env->DBAT[0][nr] != value) {
1734 /* When storing valid upper BAT, mask BEPI and BRPN
1735 * and invalidate all TLBs covered by this BAT
1736 */
1737 mask = (value << 15) & 0x0FFE0000UL;
1738 #if !defined(FLUSH_ALL_TLBS)
1739 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1740 #endif
1741 mask = (value << 15) & 0x0FFE0000UL;
1742 env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1743 (value & ~0x0001FFFFUL & ~mask);
1744 env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1745 (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1746 #if !defined(FLUSH_ALL_TLBS)
1747 do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1748 #else
1749 tlb_flush(env, 1);
1750 #endif
1751 }
1752 }
1753
1754 void ppc_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1755 {
1756 dump_store_bat(env, 'D', 1, nr, value);
1757 env->DBAT[1][nr] = value;
1758 }
1759
1760 void ppc_store_ibatu_601 (CPUPPCState *env, int nr, target_ulong value)
1761 {
1762 target_ulong mask;
1763 int do_inval;
1764
1765 dump_store_bat(env, 'I', 0, nr, value);
1766 if (env->IBAT[0][nr] != value) {
1767 do_inval = 0;
1768 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1769 if (env->IBAT[1][nr] & 0x40) {
1770 /* Invalidate BAT only if it is valid */
1771 #if !defined(FLUSH_ALL_TLBS)
1772 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1773 #else
1774 do_inval = 1;
1775 #endif
1776 }
1777 /* When storing valid upper BAT, mask BEPI and BRPN
1778 * and invalidate all TLBs covered by this BAT
1779 */
1780 env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1781 (value & ~0x0001FFFFUL & ~mask);
1782 env->DBAT[0][nr] = env->IBAT[0][nr];
1783 if (env->IBAT[1][nr] & 0x40) {
1784 #if !defined(FLUSH_ALL_TLBS)
1785 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1786 #else
1787 do_inval = 1;
1788 #endif
1789 }
1790 #if defined(FLUSH_ALL_TLBS)
1791 if (do_inval)
1792 tlb_flush(env, 1);
1793 #endif
1794 }
1795 }
1796
1797 void ppc_store_ibatl_601 (CPUPPCState *env, int nr, target_ulong value)
1798 {
1799 target_ulong mask;
1800 int do_inval;
1801
1802 dump_store_bat(env, 'I', 1, nr, value);
1803 if (env->IBAT[1][nr] != value) {
1804 do_inval = 0;
1805 if (env->IBAT[1][nr] & 0x40) {
1806 #if !defined(FLUSH_ALL_TLBS)
1807 mask = (env->IBAT[1][nr] << 17) & 0x0FFE0000UL;
1808 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1809 #else
1810 do_inval = 1;
1811 #endif
1812 }
1813 if (value & 0x40) {
1814 #if !defined(FLUSH_ALL_TLBS)
1815 mask = (value << 17) & 0x0FFE0000UL;
1816 do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1817 #else
1818 do_inval = 1;
1819 #endif
1820 }
1821 env->IBAT[1][nr] = value;
1822 env->DBAT[1][nr] = value;
1823 #if defined(FLUSH_ALL_TLBS)
1824 if (do_inval)
1825 tlb_flush(env, 1);
1826 #endif
1827 }
1828 }
1829
1830 /*****************************************************************************/
1831 /* TLB management */
1832 void ppc_tlb_invalidate_all (CPUPPCState *env)
1833 {
1834 switch (env->mmu_model) {
1835 case POWERPC_MMU_SOFT_6xx:
1836 case POWERPC_MMU_SOFT_74xx:
1837 ppc6xx_tlb_invalidate_all(env);
1838 break;
1839 case POWERPC_MMU_SOFT_4xx:
1840 case POWERPC_MMU_SOFT_4xx_Z:
1841 ppc4xx_tlb_invalidate_all(env);
1842 break;
1843 case POWERPC_MMU_REAL:
1844 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1845 break;
1846 case POWERPC_MMU_MPC8xx:
1847 /* XXX: TODO */
1848 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1849 break;
1850 case POWERPC_MMU_BOOKE:
1851 /* XXX: TODO */
1852 cpu_abort(env, "BookE MMU model is not implemented\n");
1853 break;
1854 case POWERPC_MMU_BOOKE_FSL:
1855 /* XXX: TODO */
1856 if (!kvm_enabled())
1857 cpu_abort(env, "BookE MMU model is not implemented\n");
1858 break;
1859 case POWERPC_MMU_32B:
1860 case POWERPC_MMU_601:
1861 #if defined(TARGET_PPC64)
1862 case POWERPC_MMU_620:
1863 case POWERPC_MMU_64B:
1864 #endif /* defined(TARGET_PPC64) */
1865 tlb_flush(env, 1);
1866 break;
1867 default:
1868 /* XXX: TODO */
1869 cpu_abort(env, "Unknown MMU model\n");
1870 break;
1871 }
1872 }
1873
1874 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1875 {
1876 #if !defined(FLUSH_ALL_TLBS)
1877 addr &= TARGET_PAGE_MASK;
1878 switch (env->mmu_model) {
1879 case POWERPC_MMU_SOFT_6xx:
1880 case POWERPC_MMU_SOFT_74xx:
1881 ppc6xx_tlb_invalidate_virt(env, addr, 0);
1882 if (env->id_tlbs == 1)
1883 ppc6xx_tlb_invalidate_virt(env, addr, 1);
1884 break;
1885 case POWERPC_MMU_SOFT_4xx:
1886 case POWERPC_MMU_SOFT_4xx_Z:
1887 ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1888 break;
1889 case POWERPC_MMU_REAL:
1890 cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
1891 break;
1892 case POWERPC_MMU_MPC8xx:
1893 /* XXX: TODO */
1894 cpu_abort(env, "MPC8xx MMU model is not implemented\n");
1895 break;
1896 case POWERPC_MMU_BOOKE:
1897 /* XXX: TODO */
1898 cpu_abort(env, "BookE MMU model is not implemented\n");
1899 break;
1900 case POWERPC_MMU_BOOKE_FSL:
1901 /* XXX: TODO */
1902 cpu_abort(env, "BookE FSL MMU model is not implemented\n");
1903 break;
1904 case POWERPC_MMU_32B:
1905 case POWERPC_MMU_601:
1906 /* tlbie invalidate TLBs for all segments */
1907 addr &= ~((target_ulong)-1ULL << 28);
1908 /* XXX: this case should be optimized,
1909 * giving a mask to tlb_flush_page
1910 */
1911 tlb_flush_page(env, addr | (0x0 << 28));
1912 tlb_flush_page(env, addr | (0x1 << 28));
1913 tlb_flush_page(env, addr | (0x2 << 28));
1914 tlb_flush_page(env, addr | (0x3 << 28));
1915 tlb_flush_page(env, addr | (0x4 << 28));
1916 tlb_flush_page(env, addr | (0x5 << 28));
1917 tlb_flush_page(env, addr | (0x6 << 28));
1918 tlb_flush_page(env, addr | (0x7 << 28));
1919 tlb_flush_page(env, addr | (0x8 << 28));
1920 tlb_flush_page(env, addr | (0x9 << 28));
1921 tlb_flush_page(env, addr | (0xA << 28));
1922 tlb_flush_page(env, addr | (0xB << 28));
1923 tlb_flush_page(env, addr | (0xC << 28));
1924 tlb_flush_page(env, addr | (0xD << 28));
1925 tlb_flush_page(env, addr | (0xE << 28));
1926 tlb_flush_page(env, addr | (0xF << 28));
1927 break;
1928 #if defined(TARGET_PPC64)
1929 case POWERPC_MMU_620:
1930 case POWERPC_MMU_64B:
1931 /* tlbie invalidate TLBs for all segments */
1932 /* XXX: given the fact that there are too many segments to invalidate,
1933 * and we still don't have a tlb_flush_mask(env, n, mask) in Qemu,
1934 * we just invalidate all TLBs
1935 */
1936 tlb_flush(env, 1);
1937 break;
1938 #endif /* defined(TARGET_PPC64) */
1939 default:
1940 /* XXX: TODO */
1941 cpu_abort(env, "Unknown MMU model\n");
1942 break;
1943 }
1944 #else
1945 ppc_tlb_invalidate_all(env);
1946 #endif
1947 }
1948
1949 /*****************************************************************************/
1950 /* Special registers manipulation */
1951 #if defined(TARGET_PPC64)
1952 void ppc_store_asr (CPUPPCState *env, target_ulong value)
1953 {
1954 if (env->asr != value) {
1955 env->asr = value;
1956 tlb_flush(env, 1);
1957 }
1958 }
1959 #endif
1960
1961 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
1962 {
1963 LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
1964 if (env->sdr1 != value) {
1965 /* XXX: for PowerPC 64, should check that the HTABSIZE value
1966 * is <= 28
1967 */
1968 env->sdr1 = value;
1969 tlb_flush(env, 1);
1970 }
1971 }
1972
1973 #if defined(TARGET_PPC64)
1974 target_ulong ppc_load_sr (CPUPPCState *env, int slb_nr)
1975 {
1976 // XXX
1977 return 0;
1978 }
1979 #endif
1980
1981 void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1982 {
1983 LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
1984 srnum, value, env->sr[srnum]);
1985 #if defined(TARGET_PPC64)
1986 if (env->mmu_model & POWERPC_MMU_64) {
1987 uint64_t rb = 0, rs = 0;
1988
1989 /* ESID = srnum */
1990 rb |= ((uint32_t)srnum & 0xf) << 28;
1991 /* Set the valid bit */
1992 rb |= 1 << 27;
1993 /* Index = ESID */
1994 rb |= (uint32_t)srnum;
1995
1996 /* VSID = VSID */
1997 rs |= (value & 0xfffffff) << 12;
1998 /* flags = flags */
1999 rs |= ((value >> 27) & 0xf) << 9;
2000
2001 ppc_store_slb(env, rb, rs);
2002 } else
2003 #endif
2004 if (env->sr[srnum] != value) {
2005 env->sr[srnum] = value;
2006 /* Invalidating 256MB of virtual memory in 4kB pages is way longer than
2007 flusing the whole TLB. */
2008 #if !defined(FLUSH_ALL_TLBS) && 0
2009 {
2010 target_ulong page, end;
2011 /* Invalidate 256 MB of virtual memory */
2012 page = (16 << 20) * srnum;
2013 end = page + (16 << 20);
2014 for (; page != end; page += TARGET_PAGE_SIZE)
2015 tlb_flush_page(env, page);
2016 }
2017 #else
2018 tlb_flush(env, 1);
2019 #endif
2020 }
2021 }
2022 #endif /* !defined (CONFIG_USER_ONLY) */
2023
2024 /* GDBstub can read and write MSR... */
2025 void ppc_store_msr (CPUPPCState *env, target_ulong value)
2026 {
2027 hreg_store_msr(env, value, 0);
2028 }
2029
2030 /*****************************************************************************/
2031 /* Exception processing */
2032 #if defined (CONFIG_USER_ONLY)
2033 void do_interrupt (CPUState *env)
2034 {
2035 env->exception_index = POWERPC_EXCP_NONE;
2036 env->error_code = 0;
2037 }
2038
2039 void ppc_hw_interrupt (CPUState *env)
2040 {
2041 env->exception_index = POWERPC_EXCP_NONE;
2042 env->error_code = 0;
2043 }
2044 #else /* defined (CONFIG_USER_ONLY) */
2045 static inline void dump_syscall(CPUState *env)
2046 {
2047 qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64
2048 " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64
2049 " nip=" TARGET_FMT_lx "\n",
2050 ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3),
2051 ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5),
2052 ppc_dump_gpr(env, 6), env->nip);
2053 }
2054
2055 /* Note that this function should be greatly optimized
2056 * when called with a constant excp, from ppc_hw_interrupt
2057 */
2058 static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
2059 {
2060 target_ulong msr, new_msr, vector;
2061 int srr0, srr1, asrr0, asrr1;
2062 int lpes0, lpes1, lev;
2063
2064 if (0) {
2065 /* XXX: find a suitable condition to enable the hypervisor mode */
2066 lpes0 = (env->spr[SPR_LPCR] >> 1) & 1;
2067 lpes1 = (env->spr[SPR_LPCR] >> 2) & 1;
2068 } else {
2069 /* Those values ensure we won't enter the hypervisor mode */
2070 lpes0 = 0;
2071 lpes1 = 1;
2072 }
2073
2074 qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
2075 " => %08x (%02x)\n", env->nip, excp, env->error_code);
2076 msr = env->msr;
2077 new_msr = msr;
2078 srr0 = SPR_SRR0;
2079 srr1 = SPR_SRR1;
2080 asrr0 = -1;
2081 asrr1 = -1;
2082 msr &= ~((target_ulong)0x783F0000);
2083 switch (excp) {
2084 case POWERPC_EXCP_NONE:
2085 /* Should never happen */
2086 return;
2087 case POWERPC_EXCP_CRITICAL: /* Critical input */
2088 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2089 switch (excp_model) {
2090 case POWERPC_EXCP_40x:
2091 srr0 = SPR_40x_SRR2;
2092 srr1 = SPR_40x_SRR3;
2093 break;
2094 case POWERPC_EXCP_BOOKE:
2095 srr0 = SPR_BOOKE_CSRR0;
2096 srr1 = SPR_BOOKE_CSRR1;
2097 break;
2098 case POWERPC_EXCP_G2:
2099 break;
2100 default:
2101 goto excp_invalid;
2102 }
2103 goto store_next;
2104 case POWERPC_EXCP_MCHECK: /* Machine check exception */
2105 if (msr_me == 0) {
2106 /* Machine check exception is not enabled.
2107 * Enter checkstop state.
2108 */
2109 if (qemu_log_enabled()) {
2110 qemu_log("Machine check while not allowed. "
2111 "Entering checkstop state\n");
2112 } else {
2113 fprintf(stderr, "Machine check while not allowed. "
2114 "Entering checkstop state\n");
2115 }
2116 env->halted = 1;
2117 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
2118 }
2119 new_msr &= ~((target_ulong)1 << MSR_RI);
2120 new_msr &= ~((target_ulong)1 << MSR_ME);
2121 if (0) {
2122 /* XXX: find a suitable condition to enable the hypervisor mode */
2123 new_msr |= (target_ulong)MSR_HVB;
2124 }
2125 /* XXX: should also have something loaded in DAR / DSISR */
2126 switch (excp_model) {
2127 case POWERPC_EXCP_40x:
2128 srr0 = SPR_40x_SRR2;
2129 srr1 = SPR_40x_SRR3;
2130 break;
2131 case POWERPC_EXCP_BOOKE:
2132 srr0 = SPR_BOOKE_MCSRR0;
2133 srr1 = SPR_BOOKE_MCSRR1;
2134 asrr0 = SPR_BOOKE_CSRR0;
2135 asrr1 = SPR_BOOKE_CSRR1;
2136 break;
2137 default:
2138 break;
2139 }
2140 goto store_next;
2141 case POWERPC_EXCP_DSI: /* Data storage exception */
2142 LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx
2143 "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
2144 new_msr &= ~((target_ulong)1 << MSR_RI);
2145 if (lpes1 == 0)
2146 new_msr |= (target_ulong)MSR_HVB;
2147 goto store_next;
2148 case POWERPC_EXCP_ISI: /* Instruction storage exception */
2149 LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx
2150 "\n", msr, env->nip);
2151 new_msr &= ~((target_ulong)1 << MSR_RI);
2152 if (lpes1 == 0)
2153 new_msr |= (target_ulong)MSR_HVB;
2154 msr |= env->error_code;
2155 goto store_next;
2156 case POWERPC_EXCP_EXTERNAL: /* External input */
2157 new_msr &= ~((target_ulong)1 << MSR_RI);
2158 if (lpes0 == 1)
2159 new_msr |= (target_ulong)MSR_HVB;
2160 goto store_next;
2161 case POWERPC_EXCP_ALIGN: /* Alignment exception */
2162 new_msr &= ~((target_ulong)1 << MSR_RI);
2163 if (lpes1 == 0)
2164 new_msr |= (target_ulong)MSR_HVB;
2165 /* XXX: this is false */
2166 /* Get rS/rD and rA from faulting opcode */
2167 env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2168 goto store_current;
2169 case POWERPC_EXCP_PROGRAM: /* Program exception */
2170 switch (env->error_code & ~0xF) {
2171 case POWERPC_EXCP_FP:
2172 if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2173 LOG_EXCP("Ignore floating point exception\n");
2174 env->exception_index = POWERPC_EXCP_NONE;
2175 env->error_code = 0;
2176 return;
2177 }
2178 new_msr &= ~((target_ulong)1 << MSR_RI);
2179 if (lpes1 == 0)
2180 new_msr |= (target_ulong)MSR_HVB;
2181 msr |= 0x00100000;
2182 if (msr_fe0 == msr_fe1)
2183 goto store_next;
2184 msr |= 0x00010000;
2185 break;
2186 case POWERPC_EXCP_INVAL:
2187 LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
2188 new_msr &= ~((target_ulong)1 << MSR_RI);
2189 if (lpes1 == 0)
2190 new_msr |= (target_ulong)MSR_HVB;
2191 msr |= 0x00080000;
2192 break;
2193 case POWERPC_EXCP_PRIV:
2194 new_msr &= ~((target_ulong)1 << MSR_RI);
2195 if (lpes1 == 0)
2196 new_msr |= (target_ulong)MSR_HVB;
2197 msr |= 0x00040000;
2198 break;
2199 case POWERPC_EXCP_TRAP:
2200 new_msr &= ~((target_ulong)1 << MSR_RI);
2201 if (lpes1 == 0)
2202 new_msr |= (target_ulong)MSR_HVB;
2203 msr |= 0x00020000;
2204 break;
2205 default:
2206 /* Should never occur */
2207 cpu_abort(env, "Invalid program exception %d. Aborting\n",
2208 env->error_code);
2209 break;
2210 }
2211 goto store_current;
2212 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
2213 new_msr &= ~((target_ulong)1 << MSR_RI);
2214 if (lpes1 == 0)
2215 new_msr |= (target_ulong)MSR_HVB;
2216 goto store_current;
2217 case POWERPC_EXCP_SYSCALL: /* System call exception */
2218 /* NOTE: this is a temporary hack to support graphics OSI
2219 calls from the MOL driver */
2220 /* XXX: To be removed */
2221 if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2222 env->osi_call) {
2223 if (env->osi_call(env) != 0) {
2224 env->exception_index = POWERPC_EXCP_NONE;
2225 env->error_code = 0;
2226 return;
2227 }
2228 }
2229 dump_syscall(env);
2230 new_msr &= ~((target_ulong)1 << MSR_RI);
2231 lev = env->error_code;
2232 if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2233 new_msr |= (target_ulong)MSR_HVB;
2234 goto store_next;
2235 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
2236 new_msr &= ~((target_ulong)1 << MSR_RI);
2237 goto store_current;
2238 case POWERPC_EXCP_DECR: /* Decrementer exception */
2239 new_msr &= ~((target_ulong)1 << MSR_RI);
2240 if (lpes1 == 0)
2241 new_msr |= (target_ulong)MSR_HVB;
2242 goto store_next;
2243 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
2244 /* FIT on 4xx */
2245 LOG_EXCP("FIT exception\n");
2246 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2247 goto store_next;
2248 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
2249 LOG_EXCP("WDT exception\n");
2250 switch (excp_model) {
2251 case POWERPC_EXCP_BOOKE:
2252 srr0 = SPR_BOOKE_CSRR0;
2253 srr1 = SPR_BOOKE_CSRR1;
2254 break;
2255 default:
2256 break;
2257 }
2258 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2259 goto store_next;
2260 case POWERPC_EXCP_DTLB: /* Data TLB error */
2261 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2262 goto store_next;
2263 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
2264 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2265 goto store_next;
2266 case POWERPC_EXCP_DEBUG: /* Debug interrupt */
2267 switch (excp_model) {
2268 case POWERPC_EXCP_BOOKE:
2269 srr0 = SPR_BOOKE_DSRR0;
2270 srr1 = SPR_BOOKE_DSRR1;
2271 asrr0 = SPR_BOOKE_CSRR0;
2272 asrr1 = SPR_BOOKE_CSRR1;
2273 break;
2274 default:
2275 break;
2276 }
2277 /* XXX: TODO */
2278 cpu_abort(env, "Debug exception is not implemented yet !\n");
2279 goto store_next;
2280 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
2281 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2282 goto store_current;
2283 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
2284 /* XXX: TODO */
2285 cpu_abort(env, "Embedded floating point data exception "
2286 "is not implemented yet !\n");
2287 goto store_next;
2288 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
2289 /* XXX: TODO */
2290 cpu_abort(env, "Embedded floating point round exception "
2291 "is not implemented yet !\n");
2292 goto store_next;
2293 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
2294 new_msr &= ~((target_ulong)1 << MSR_RI);
2295 /* XXX: TODO */
2296 cpu_abort(env,
2297 "Performance counter exception is not implemented yet !\n");
2298 goto store_next;
2299 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
2300 /* XXX: TODO */
2301 cpu_abort(env,
2302 "Embedded doorbell interrupt is not implemented yet !\n");
2303 goto store_next;
2304 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
2305 switch (excp_model) {
2306 case POWERPC_EXCP_BOOKE:
2307 srr0 = SPR_BOOKE_CSRR0;
2308 srr1 = SPR_BOOKE_CSRR1;
2309 break;
2310 default:
2311 break;
2312 }
2313 /* XXX: TODO */
2314 cpu_abort(env, "Embedded doorbell critical interrupt "
2315 "is not implemented yet !\n");
2316 goto store_next;
2317 case POWERPC_EXCP_RESET: /* System reset exception */
2318 new_msr &= ~((target_ulong)1 << MSR_RI);
2319 if (0) {
2320 /* XXX: find a suitable condition to enable the hypervisor mode */
2321 new_msr |= (target_ulong)MSR_HVB;
2322 }
2323 goto store_next;
2324 case POWERPC_EXCP_DSEG: /* Data segment exception */
2325 new_msr &= ~((target_ulong)1 << MSR_RI);
2326 if (lpes1 == 0)
2327 new_msr |= (target_ulong)MSR_HVB;
2328 goto store_next;
2329 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
2330 new_msr &= ~((target_ulong)1 << MSR_RI);
2331 if (lpes1 == 0)
2332 new_msr |= (target_ulong)MSR_HVB;
2333 goto store_next;
2334 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
2335 srr0 = SPR_HSRR0;
2336 srr1 = SPR_HSRR1;
2337 new_msr |= (target_ulong)MSR_HVB;
2338 goto store_next;
2339 case POWERPC_EXCP_TRACE: /* Trace exception */
2340 new_msr &= ~((target_ulong)1 << MSR_RI);
2341 if (lpes1 == 0)
2342 new_msr |= (target_ulong)MSR_HVB;
2343 goto store_next;
2344 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
2345 srr0 = SPR_HSRR0;
2346 srr1 = SPR_HSRR1;
2347 new_msr |= (target_ulong)MSR_HVB;
2348 goto store_next;
2349 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
2350 srr0 = SPR_HSRR0;
2351 srr1 = SPR_HSRR1;
2352 new_msr |= (target_ulong)MSR_HVB;
2353 goto store_next;
2354 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
2355 srr0 = SPR_HSRR0;
2356 srr1 = SPR_HSRR1;
2357 new_msr |= (target_ulong)MSR_HVB;
2358 goto store_next;
2359 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
2360 srr0 = SPR_HSRR0;
2361 srr1 = SPR_HSRR1;
2362 new_msr |= (target_ulong)MSR_HVB;
2363 goto store_next;
2364 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
2365 new_msr &= ~((target_ulong)1 << MSR_RI);
2366 if (lpes1 == 0)
2367 new_msr |= (target_ulong)MSR_HVB;
2368 goto store_current;
2369 case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
2370 LOG_EXCP("PIT exception\n");
2371 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2372 goto store_next;
2373 case POWERPC_EXCP_IO: /* IO error exception */
2374 /* XXX: TODO */
2375 cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2376 goto store_next;
2377 case POWERPC_EXCP_RUNM: /* Run mode exception */
2378 /* XXX: TODO */
2379 cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2380 goto store_next;
2381 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
2382 /* XXX: TODO */
2383 cpu_abort(env, "602 emulation trap exception "
2384 "is not implemented yet !\n");
2385 goto store_next;
2386 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
2387 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2388 if (lpes1 == 0) /* XXX: check this */
2389 new_msr |= (target_ulong)MSR_HVB;
2390 switch (excp_model) {
2391 case POWERPC_EXCP_602:
2392 case POWERPC_EXCP_603:
2393 case POWERPC_EXCP_603E:
2394 case POWERPC_EXCP_G2:
2395 goto tlb_miss_tgpr;
2396 case POWERPC_EXCP_7x5:
2397 goto tlb_miss;
2398 case POWERPC_EXCP_74xx:
2399 goto tlb_miss_74xx;
2400 default:
2401 cpu_abort(env, "Invalid instruction TLB miss exception\n");
2402 break;
2403 }
2404 break;
2405 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
2406 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2407 if (lpes1 == 0) /* XXX: check this */
2408 new_msr |= (target_ulong)MSR_HVB;
2409 switch (excp_model) {
2410 case POWERPC_EXCP_602:
2411 case POWERPC_EXCP_603:
2412 case POWERPC_EXCP_603E:
2413 case POWERPC_EXCP_G2:
2414 goto tlb_miss_tgpr;
2415 case POWERPC_EXCP_7x5:
2416 goto tlb_miss;
2417 case POWERPC_EXCP_74xx:
2418 goto tlb_miss_74xx;
2419 default:
2420 cpu_abort(env, "Invalid data load TLB miss exception\n");
2421 break;
2422 }
2423 break;
2424 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
2425 new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
2426 if (lpes1 == 0) /* XXX: check this */
2427 new_msr |= (target_ulong)MSR_HVB;
2428 switch (excp_model) {
2429 case POWERPC_EXCP_602:
2430 case POWERPC_EXCP_603:
2431 case POWERPC_EXCP_603E:
2432 case POWERPC_EXCP_G2:
2433 tlb_miss_tgpr:
2434 /* Swap temporary saved registers with GPRs */
2435 if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
2436 new_msr |= (target_ulong)1 << MSR_TGPR;
2437 hreg_swap_gpr_tgpr(env);
2438 }
2439 goto tlb_miss;
2440 case POWERPC_EXCP_7x5:
2441 tlb_miss:
2442 #if defined (DEBUG_SOFTWARE_TLB)
2443 if (qemu_log_enabled()) {
2444 const char *es;
2445 target_ulong *miss, *cmp;
2446 int en;
2447 if (excp == POWERPC_EXCP_IFTLB) {
2448 es = "I";
2449 en = 'I';
2450 miss = &env->spr[SPR_IMISS];
2451 cmp = &env->spr[SPR_ICMP];
2452 } else {
2453 if (excp == POWERPC_EXCP_DLTLB)
2454 es = "DL";
2455 else
2456 es = "DS";
2457 en = 'D';
2458 miss = &env->spr[SPR_DMISS];
2459 cmp = &env->spr[SPR_DCMP];
2460 }
2461 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
2462 TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 "
2463 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
2464 env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2465 env->error_code);
2466 }
2467 #endif
2468 msr |= env->crf[0] << 28;
2469 msr |= env->error_code; /* key, D/I, S/L bits */
2470 /* Set way using a LRU mechanism */
2471 msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2472 break;
2473 case POWERPC_EXCP_74xx:
2474 tlb_miss_74xx:
2475 #if defined (DEBUG_SOFTWARE_TLB)
2476 if (qemu_log_enabled()) {
2477 const char *es;
2478 target_ulong *miss, *cmp;
2479 int en;
2480 if (excp == POWERPC_EXCP_IFTLB) {
2481 es = "I";
2482 en = 'I';
2483 miss = &env->spr[SPR_TLBMISS];
2484 cmp = &env->spr[SPR_PTEHI];
2485 } else {
2486 if (excp == POWERPC_EXCP_DLTLB)
2487 es = "DL";
2488 else
2489 es = "DS";
2490 en = 'D';
2491 miss = &env->spr[SPR_TLBMISS];
2492 cmp = &env->spr[SPR_PTEHI];
2493 }
2494 qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC "
2495 TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp,
2496 env->error_code);
2497 }
2498 #endif
2499 msr |= env->error_code; /* key bit */
2500 break;
2501 default:
2502 cpu_abort(env, "Invalid data store TLB miss exception\n");
2503 break;
2504 }
2505 goto store_next;
2506 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
2507 /* XXX: TODO */
2508 cpu_abort(env, "Floating point assist exception "
2509 "is not implemented yet !\n");
2510 goto store_next;
2511 case POWERPC_EXCP_DABR: /* Data address breakpoint */
2512 /* XXX: TODO */
2513 cpu_abort(env, "DABR exception is not implemented yet !\n");
2514 goto store_next;
2515 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
2516 /* XXX: TODO */
2517 cpu_abort(env, "IABR exception is not implemented yet !\n");
2518 goto store_next;
2519 case POWERPC_EXCP_SMI: /* System management interrupt */
2520 /* XXX: TODO */
2521 cpu_abort(env, "SMI exception is not implemented yet !\n");
2522 goto store_next;
2523 case POWERPC_EXCP_THERM: /* Thermal interrupt */
2524 /* XXX: TODO */
2525 cpu_abort(env, "Thermal management exception "
2526 "is not implemented yet !\n");
2527 goto store_next;
2528 case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
2529 new_msr &= ~((target_ulong)1 << MSR_RI);
2530 if (lpes1 == 0)
2531 new_msr |= (target_ulong)MSR_HVB;
2532 /* XXX: TODO */
2533 cpu_abort(env,
2534 "Performance counter exception is not implemented yet !\n");
2535 goto store_next;
2536 case POWERPC_EXCP_VPUA: /* Vector assist exception */
2537 /* XXX: TODO */
2538 cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2539 goto store_next;
2540 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
2541 /* XXX: TODO */
2542 cpu_abort(env,
2543 "970 soft-patch exception is not implemented yet !\n");
2544 goto store_next;
2545 case POWERPC_EXCP_MAINT: /* Maintenance exception */
2546 /* XXX: TODO */
2547 cpu_abort(env,
2548 "970 maintenance exception is not implemented yet !\n");
2549 goto store_next;
2550 case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
2551 /* XXX: TODO */
2552 cpu_abort(env, "Maskable external exception "
2553 "is not implemented yet !\n");
2554 goto store_next;
2555 case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
2556 /* XXX: TODO */
2557 cpu_abort(env, "Non maskable external exception "
2558 "is not implemented yet !\n");
2559 goto store_next;
2560 default:
2561 excp_invalid:
2562 cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2563 break;
2564 store_current:
2565 /* save current instruction location */
2566 env->spr[srr0] = env->nip - 4;
2567 break;
2568 store_next:
2569 /* save next instruction location */
2570 env->spr[srr0] = env->nip;
2571 break;
2572 }
2573 /* Save MSR */
2574 env->spr[srr1] = msr;
2575 /* If any alternate SRR register are defined, duplicate saved values */
2576 if (asrr0 != -1)
2577 env->spr[asrr0] = env->spr[srr0];
2578 if (asrr1 != -1)
2579 env->spr[asrr1] = env->spr[srr1];
2580 /* If we disactivated any translation, flush TLBs */
2581 if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
2582 tlb_flush(env, 1);
2583 /* reload MSR with correct bits */
2584 new_msr &= ~((target_ulong)1 << MSR_EE);
2585 new_msr &= ~((target_ulong)1 << MSR_PR);
2586 new_msr &= ~((target_ulong)1 << MSR_FP);
2587 new_msr &= ~((target_ulong)1 << MSR_FE0);
2588 new_msr &= ~((target_ulong)1 << MSR_SE);
2589 new_msr &= ~((target_ulong)1 << MSR_BE);
2590 new_msr &= ~((target_ulong)1 << MSR_FE1);
2591 new_msr &= ~((target_ulong)1 << MSR_IR);
2592 new_msr &= ~((target_ulong)1 << MSR_DR);
2593 #if 0 /* Fix this: not on all targets */
2594 new_msr &= ~((target_ulong)1 << MSR_PMM);
2595 #endif
2596 new_msr &= ~((target_ulong)1 << MSR_LE);
2597 if (msr_ile)
2598 new_msr |= (target_ulong)1 << MSR_LE;
2599 else
2600 new_msr &= ~((target_ulong)1 << MSR_LE);
2601 /* Jump to handler */
2602 vector = env->excp_vectors[excp];
2603 if (vector == (target_ulong)-1ULL) {
2604 cpu_abort(env, "Raised an exception without defined vector %d\n",
2605 excp);
2606 }
2607 vector |= env->excp_prefix;
2608 #if defined(TARGET_PPC64)
2609 if (excp_model == POWERPC_EXCP_BOOKE) {
2610 if (!msr_icm) {
2611 new_msr &= ~((target_ulong)1 << MSR_CM);
2612 vector = (uint32_t)vector;
2613 } else {
2614 new_msr |= (target_ulong)1 << MSR_CM;
2615 }
2616 } else {
2617 if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) {
2618 new_msr &= ~((target_ulong)1 << MSR_SF);
2619 vector = (uint32_t)vector;
2620 } else {
2621 new_msr |= (target_ulong)1 << MSR_SF;
2622 }
2623 }
2624 #endif
2625 /* XXX: we don't use hreg_store_msr here as already have treated
2626 * any special case that could occur. Just store MSR and update hflags
2627 */
2628 env->msr = new_msr & env->msr_mask;
2629 hreg_compute_hflags(env);
2630 env->nip = vector;
2631 /* Reset exception state */
2632 env->exception_index = POWERPC_EXCP_NONE;
2633 env->error_code = 0;
2634 }
2635
2636 void do_interrupt (CPUState *env)
2637 {
2638 powerpc_excp(env, env->excp_model, env->exception_index);
2639 }
2640
2641 void ppc_hw_interrupt (CPUPPCState *env)
2642 {
2643 int hdice;
2644
2645 #if 0
2646 qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n",
2647 __func__, env, env->pending_interrupts,
2648 env->interrupt_request, (int)msr_me, (int)msr_ee);
2649 #endif
2650 /* External reset */
2651 if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2652 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2653 powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2654 return;
2655 }
2656 /* Machine check exception */
2657 if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2658 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2659 powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2660 return;
2661 }
2662 #if 0 /* TODO */
2663 /* External debug exception */
2664 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2665 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2666 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2667 return;
2668 }
2669 #endif
2670 if (0) {
2671 /* XXX: find a suitable condition to enable the hypervisor mode */
2672 hdice = env->spr[SPR_LPCR] & 1;
2673 } else {
2674 hdice = 0;
2675 }
2676 if ((msr_ee != 0 || msr_hv == 0 || msr_pr != 0) && hdice != 0) {
2677 /* Hypervisor decrementer exception */
2678 if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2679 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2680 powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2681 return;
2682 }
2683 }
2684 if (msr_ce != 0) {
2685 /* External critical interrupt */
2686 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2687 /* Taking a critical external interrupt does not clear the external
2688 * critical interrupt status
2689 */
2690 #if 0
2691 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2692 #endif
2693 powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2694 return;
2695 }
2696 }
2697 if (msr_ee != 0) {
2698 /* Watchdog timer on embedded PowerPC */
2699 if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2700 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2701 powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2702 return;
2703 }
2704 if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2705 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2706 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2707 return;
2708 }
2709 /* Fixed interval timer on embedded PowerPC */
2710 if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2711 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2712 powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2713 return;
2714 }
2715 /* Programmable interval timer on embedded PowerPC */
2716 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2717 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2718 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2719 return;
2720 }
2721 /* Decrementer exception */
2722 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2723 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2724 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2725 return;
2726 }
2727 /* External interrupt */
2728 if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2729 /* Taking an external interrupt does not clear the external
2730 * interrupt status
2731 */
2732 #if 0
2733 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2734 #endif
2735 powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2736 return;
2737 }
2738 if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2739 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2740 powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2741 return;
2742 }
2743 if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2744 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2745 powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2746 return;
2747 }
2748 /* Thermal interrupt */
2749 if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2750 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2751 powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2752 return;
2753 }
2754 }
2755 }
2756 #endif /* !CONFIG_USER_ONLY */
2757
2758 void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2759 {
2760 qemu_log("Return from exception at " TARGET_FMT_lx " with flags "
2761 TARGET_FMT_lx "\n", RA, msr);
2762 }
2763
2764 void cpu_reset(CPUPPCState *env)
2765 {
2766 target_ulong msr;
2767
2768 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2769 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
2770 log_cpu_state(env, 0);
2771 }
2772
2773 msr = (target_ulong)0;
2774 if (0) {
2775 /* XXX: find a suitable condition to enable the hypervisor mode */
2776 msr |= (target_ulong)MSR_HVB;
2777 }
2778 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
2779 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
2780 msr |= (target_ulong)1 << MSR_EP;
2781 #if defined (DO_SINGLE_STEP) && 0
2782 /* Single step trace mode */
2783 msr |= (target_ulong)1 << MSR_SE;
2784 msr |= (target_ulong)1 << MSR_BE;
2785 #endif
2786 #if defined(CONFIG_USER_ONLY)
2787 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
2788 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
2789 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
2790 msr |= (target_ulong)1 << MSR_PR;
2791 #else
2792 env->excp_prefix = env->hreset_excp_prefix;
2793 env->nip = env->hreset_vector | env->excp_prefix;
2794 if (env->mmu_model != POWERPC_MMU_REAL)
2795 ppc_tlb_invalidate_all(env);
2796 #endif
2797 env->msr = msr & env->msr_mask;
2798 #if defined(TARGET_PPC64)
2799 if (env->mmu_model & POWERPC_MMU_64)
2800 env->msr |= (1ULL << MSR_SF);
2801 #endif
2802 hreg_compute_hflags(env);
2803 env->reserve_addr = (target_ulong)-1ULL;
2804 /* Be sure no exception or interrupt is pending */
2805 env->pending_interrupts = 0;
2806 env->exception_index = POWERPC_EXCP_NONE;
2807 env->error_code = 0;
2808 /* Flush all TLBs */
2809 tlb_flush(env, 1);
2810 }
2811
2812 CPUPPCState *cpu_ppc_init (const char *cpu_model)
2813 {
2814 CPUPPCState *env;
2815 const ppc_def_t *def;
2816
2817 def = cpu_ppc_find_by_name(cpu_model);
2818 if (!def)
2819 return NULL;
2820
2821 env = qemu_mallocz(sizeof(CPUPPCState));
2822 cpu_exec_init(env);
2823 ppc_translate_init();
2824 env->cpu_model_str = cpu_model;
2825 cpu_ppc_register_internal(env, def);
2826
2827 qemu_init_vcpu(env);
2828
2829 return env;
2830 }
2831
2832 void cpu_ppc_close (CPUPPCState *env)
2833 {
2834 /* Should also remove all opcode tables... */
2835 qemu_free(env);
2836 }
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