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Expose whether a mouse is an absolute device via QMP and the human monitor.
[qemu/aliguori-queue.git] / hw / eepro100.c
blob7db6fb5a706d42bf286a6df0855d484d559bb65e
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stdbool.h> /* bool */
45 #include <stddef.h> /* offsetof */
46 #include "hw.h"
47 #include "pci.h"
48 #include "net.h"
49 #include "eeprom93xx.h"
50
51 #define KiB 1024
52
53 /* Debug EEPRO100 card. */
54 #if 0
55 # define DEBUG_EEPRO100
56 #endif
57
58 #ifdef DEBUG_EEPRO100
59 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
60 #else
61 #define logout(fmt, ...) ((void)0)
62 #endif
63
64 /* Set flags to 0 to disable debug output. */
65 #define INT 1 /* interrupt related actions */
66 #define MDI 1 /* mdi related actions */
67 #define OTHER 1
68 #define RXTX 1
69 #define EEPROM 1 /* eeprom related actions */
70
71 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
72
73 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
74
75 #define MAX_ETH_FRAME_SIZE 1514
76
77 /* This driver supports several different devices which are declared here. */
78 #define i82550 0x82550
79 #define i82551 0x82551
80 #define i82557A 0x82557a
81 #define i82557B 0x82557b
82 #define i82557C 0x82557c
83 #define i82558A 0x82558a
84 #define i82558B 0x82558b
85 #define i82559A 0x82559a
86 #define i82559B 0x82559b
87 #define i82559C 0x82559c
88 #define i82559ER 0x82559e
89 #define i82562 0x82562
90
91 /* Use 64 word EEPROM. TODO: could be a runtime option. */
92 #define EEPROM_SIZE 64
93
94 #define PCI_MEM_SIZE (4 * KiB)
95 #define PCI_IO_SIZE 64
96 #define PCI_FLASH_SIZE (128 * KiB)
97
98 #define BIT(n) (1 << (n))
99 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
100
101 /* The SCB accepts the following controls for the Tx and Rx units: */
102 #define CU_NOP 0x0000 /* No operation. */
103 #define CU_START 0x0010 /* CU start. */
104 #define CU_RESUME 0x0020 /* CU resume. */
105 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
106 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
107 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
108 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
109 #define CU_SRESUME 0x00a0 /* CU static resume. */
110
111 #define RU_NOP 0x0000
112 #define RX_START 0x0001
113 #define RX_RESUME 0x0002
114 #define RU_ABORT 0x0004
115 #define RX_ADDR_LOAD 0x0006
116 #define RX_RESUMENR 0x0007
117 #define INT_MASK 0x0100
118 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
119
120 /* Offsets to the various registers.
121 All accesses need not be longword aligned. */
122 enum speedo_offsets {
123 SCBStatus = 0, /* Status Word. */
124 SCBAck = 1,
125 SCBCmd = 2, /* Rx/Command Unit command and status. */
126 SCBIntmask = 3,
127 SCBPointer = 4, /* General purpose pointer. */
128 SCBPort = 8, /* Misc. commands and operands. */
129 SCBflash = 12, /* Flash memory control. */
130 SCBeeprom = 14, /* EEPROM control. */
131 SCBCtrlMDI = 16, /* MDI interface control. */
132 SCBEarlyRx = 20, /* Early receive byte count. */
133 SCBFlow = 24, /* Flow Control. */
134 SCBpmdr = 27, /* Power Management Driver. */
135 SCBgctrl = 28, /* General Control. */
136 SCBgstat = 29, /* General Status. */
137 };
138
139 /* A speedo3 transmit buffer descriptor with two buffers... */
140 typedef struct {
141 uint16_t status;
142 uint16_t command;
143 uint32_t link; /* void * */
144 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
145 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
146 uint8_t tx_threshold; /* transmit threshold */
147 uint8_t tbd_count; /* TBD number */
148 #if 0
149 /* This constitutes two "TBD" entries: hdr and data */
150 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
151 int32_t tx_buf_size0; /* Length of Tx hdr. */
152 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
153 int32_t tx_buf_size1; /* Length of Tx data. */
154 #endif
155 } eepro100_tx_t;
156
157 /* Receive frame descriptor. */
158 typedef struct {
159 int16_t status;
160 uint16_t command;
161 uint32_t link; /* struct RxFD * */
162 uint32_t rx_buf_addr; /* void * */
163 uint16_t count;
164 uint16_t size;
165 char packet[MAX_ETH_FRAME_SIZE + 4];
166 } eepro100_rx_t;
167
168 typedef enum {
169 COMMAND_EL = BIT(15),
170 COMMAND_S = BIT(14),
171 COMMAND_I = BIT(13),
172 COMMAND_NC = BIT(4),
173 COMMAND_SF = BIT(3),
174 COMMAND_CMD = BITS(2, 0),
175 } scb_command_bit;
176
177 typedef enum {
178 STATUS_C = BIT(15),
179 STATUS_OK = BIT(13),
180 } scb_status_bit;
181
182 typedef struct {
183 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
184 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
185 tx_multiple_collisions, tx_total_collisions;
186 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
187 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
188 rx_short_frame_errors;
189 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
190 uint16_t xmt_tco_frames, rcv_tco_frames;
191 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
192 uint32_t reserved[4];
193 } eepro100_stats_t;
194
195 typedef enum {
196 cu_idle = 0,
197 cu_suspended = 1,
198 cu_active = 2,
199 cu_lpq_active = 2,
200 cu_hqp_active = 3
201 } cu_state_t;
202
203 typedef enum {
204 ru_idle = 0,
205 ru_suspended = 1,
206 ru_no_resources = 2,
207 ru_ready = 4
208 } ru_state_t;
209
210 typedef struct {
211 PCIDevice dev;
212 uint8_t mult[8]; /* multicast mask array */
213 int mmio_index;
214 NICState *nic;
215 NICConf conf;
216 uint8_t scb_stat; /* SCB stat/ack byte */
217 uint8_t int_stat; /* PCI interrupt status */
218 /* region must not be saved by nic_save. */
219 uint32_t region[3]; /* PCI region addresses */
220 uint16_t mdimem[32];
221 eeprom_t *eeprom;
222 uint32_t device; /* device variant */
223 uint32_t pointer;
224 /* (cu_base + cu_offset) address the next command block in the command block list. */
225 uint32_t cu_base; /* CU base address */
226 uint32_t cu_offset; /* CU address offset */
227 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
228 uint32_t ru_base; /* RU base address */
229 uint32_t ru_offset; /* RU address offset */
230 uint32_t statsaddr; /* pointer to eepro100_stats_t */
231
232 /* Temporary status information (no need to save these values),
233 * used while processing CU commands. */
234 eepro100_tx_t tx; /* transmit buffer descriptor */
235 uint32_t cb_address; /* = cu_base + cu_offset */
236
237 /* Statistical counters. Also used for wake-up packet (i82559). */
238 eepro100_stats_t statistics;
239
240 #if 0
241 uint16_t status;
242 #endif
243
244 /* Configuration bytes. */
245 uint8_t configuration[22];
246
247 /* Data in mem is always in the byte order of the controller (le). */
248 uint8_t mem[PCI_MEM_SIZE];
249 /* vmstate for each particular nic */
250 VMStateDescription *vmstate;
251
252 /* Quasi static device properties (no need to save them). */
253 uint16_t stats_size;
254 bool has_extended_tcb_support;
255 } EEPRO100State;
256
257 /* Word indices in EEPROM. */
258 typedef enum {
259 EEPROM_CNFG_MDIX = 0x03,
260 EEPROM_ID = 0x05,
261 EEPROM_PHY_ID = 0x06,
262 EEPROM_VENDOR_ID = 0x0c,
263 EEPROM_CONFIG_ASF = 0x0d,
264 EEPROM_DEVICE_ID = 0x23,
265 EEPROM_SMBUS_ADDR = 0x90,
266 } EEPROMOffset;
267
268 /* Bit values for EEPROM ID word. */
269 typedef enum {
270 EEPROM_ID_MDM = BIT(0), /* Modem */
271 EEPROM_ID_STB = BIT(1), /* Standby Enable */
272 EEPROM_ID_WMR = BIT(2), /* ??? */
273 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
274 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
275 EEPROM_ID_ALT = BIT(7), /* */
276 /* BITS(10, 8) device revision */
277 EEPROM_ID_BD = BIT(11), /* boot disable */
278 EEPROM_ID_ID = BIT(13), /* id bit */
279 /* BITS(15, 14) signature */
280 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
281 } eeprom_id_bit;
282
283 /* Default values for MDI (PHY) registers */
284 static const uint16_t eepro100_mdi_default[] = {
285 /* MDI Registers 0 - 6, 7 */
286 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
287 /* MDI Registers 8 - 15 */
288 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
289 /* MDI Registers 16 - 31 */
290 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
291 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
292 };
293
294 /* Readonly mask for MDI (PHY) registers */
295 static const uint16_t eepro100_mdi_mask[] = {
296 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
297 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
298 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
299 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
300 };
301
302 /* XXX: optimize */
303 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
304 {
305 val = cpu_to_le32(val);
306 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
307 }
308
309 #define POLYNOMIAL 0x04c11db6
310
311 /* From FreeBSD */
312 /* XXX: optimize */
313 static unsigned compute_mcast_idx(const uint8_t * ep)
314 {
315 uint32_t crc;
316 int carry, i, j;
317 uint8_t b;
318
319 crc = 0xffffffff;
320 for (i = 0; i < 6; i++) {
321 b = *ep++;
322 for (j = 0; j < 8; j++) {
323 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
324 crc <<= 1;
325 b >>= 1;
326 if (carry) {
327 crc = ((crc ^ POLYNOMIAL) | carry);
328 }
329 }
330 }
331 return (crc & BITS(7, 2)) >> 2;
332 }
333
334 #if defined(DEBUG_EEPRO100)
335 static const char *nic_dump(const uint8_t * buf, unsigned size)
336 {
337 static char dump[3 * 16 + 1];
338 char *p = &dump[0];
339 if (size > 16) {
340 size = 16;
341 }
342 while (size-- > 0) {
343 p += sprintf(p, " %02x", *buf++);
344 }
345 return dump;
346 }
347 #endif /* DEBUG_EEPRO100 */
348
349 enum scb_stat_ack {
350 stat_ack_not_ours = 0x00,
351 stat_ack_sw_gen = 0x04,
352 stat_ack_rnr = 0x10,
353 stat_ack_cu_idle = 0x20,
354 stat_ack_frame_rx = 0x40,
355 stat_ack_cu_cmd_done = 0x80,
356 stat_ack_not_present = 0xFF,
357 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
358 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
359 };
360
361 static void disable_interrupt(EEPRO100State * s)
362 {
363 if (s->int_stat) {
364 TRACE(INT, logout("interrupt disabled\n"));
365 qemu_irq_lower(s->dev.irq[0]);
366 s->int_stat = 0;
367 }
368 }
369
370 static void enable_interrupt(EEPRO100State * s)
371 {
372 if (!s->int_stat) {
373 TRACE(INT, logout("interrupt enabled\n"));
374 qemu_irq_raise(s->dev.irq[0]);
375 s->int_stat = 1;
376 }
377 }
378
379 static void eepro100_acknowledge(EEPRO100State * s)
380 {
381 s->scb_stat &= ~s->mem[SCBAck];
382 s->mem[SCBAck] = s->scb_stat;
383 if (s->scb_stat == 0) {
384 disable_interrupt(s);
385 }
386 }
387
388 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
389 {
390 uint8_t mask = ~s->mem[SCBIntmask];
391 s->mem[SCBAck] |= status;
392 status = s->scb_stat = s->mem[SCBAck];
393 status &= (mask | 0x0f);
394 #if 0
395 status &= (~s->mem[SCBIntmask] | 0x0xf);
396 #endif
397 if (status && (mask & 0x01)) {
398 /* SCB mask and SCB Bit M do not disable interrupt. */
399 enable_interrupt(s);
400 } else if (s->int_stat) {
401 disable_interrupt(s);
402 }
403 }
404
405 static void eepro100_cx_interrupt(EEPRO100State * s)
406 {
407 /* CU completed action command. */
408 /* Transmit not ok (82557 only, not in emulation). */
409 eepro100_interrupt(s, 0x80);
410 }
411
412 static void eepro100_cna_interrupt(EEPRO100State * s)
413 {
414 /* CU left the active state. */
415 eepro100_interrupt(s, 0x20);
416 }
417
418 static void eepro100_fr_interrupt(EEPRO100State * s)
419 {
420 /* RU received a complete frame. */
421 eepro100_interrupt(s, 0x40);
422 }
423
424 static void eepro100_rnr_interrupt(EEPRO100State * s)
425 {
426 /* RU is not ready. */
427 eepro100_interrupt(s, 0x10);
428 }
429
430 static void eepro100_mdi_interrupt(EEPRO100State * s)
431 {
432 /* MDI completed read or write cycle. */
433 eepro100_interrupt(s, 0x08);
434 }
435
436 static void eepro100_swi_interrupt(EEPRO100State * s)
437 {
438 /* Software has requested an interrupt. */
439 eepro100_interrupt(s, 0x04);
440 }
441
442 #if 0
443 static void eepro100_fcp_interrupt(EEPRO100State * s)
444 {
445 /* Flow control pause interrupt (82558 and later). */
446 eepro100_interrupt(s, 0x01);
447 }
448 #endif
449
450 static void pci_reset(EEPRO100State * s)
451 {
452 uint32_t device = s->device;
453 uint8_t *pci_conf = s->dev.config;
454 bool power_management = 1;
455
456 TRACE(OTHER, logout("%p\n", s));
457
458 /* PCI Vendor ID */
459 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
460 /* PCI Device ID depends on device and is set below. */
461 /* PCI Status */
462 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
463 /* PCI Revision ID */
464 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x08);
465 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
466 /* PCI Latency Timer */
467 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
468 /* Capability Pointer */
469 /* TODO: revisions with power_management 1 use this but
470 * do not set new capability list bit in status register. */
471 pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0xdc);
472 /* Minimum Grant */
473 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
474 /* Maximum Latency */
475 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
476
477 switch (device) {
478 case i82550:
479 /* TODO: check device id. */
480 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
481 /* Revision ID: 0x0c, 0x0d, 0x0e. */
482 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0e);
483 /* TODO: check size of statistical counters. */
484 s->stats_size = 80;
485 /* TODO: check extended tcb support. */
486 s->has_extended_tcb_support = 1;
487 break;
488 case i82551:
489 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
490 /* Revision ID: 0x0f, 0x10. */
491 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0f);
492 /* TODO: check size of statistical counters. */
493 s->stats_size = 80;
494 s->has_extended_tcb_support = 1;
495 break;
496 case i82557A:
497 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
498 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x01);
499 pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
500 power_management = 0;
501 break;
502 case i82557B:
503 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
504 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x02);
505 pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
506 power_management = 0;
507 break;
508 case i82557C:
509 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
510 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x03);
511 pci_set_byte(pci_conf + PCI_CAPABILITY_LIST, 0x00);
512 power_management = 0;
513 break;
514 case i82558A:
515 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
516 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
517 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
518 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x04);
519 s->stats_size = 76;
520 s->has_extended_tcb_support = 1;
521 break;
522 case i82558B:
523 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
524 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
525 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
526 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x05);
527 s->stats_size = 76;
528 s->has_extended_tcb_support = 1;
529 break;
530 case i82559A:
531 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
532 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
533 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
534 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x06);
535 s->stats_size = 80;
536 s->has_extended_tcb_support = 1;
537 break;
538 case i82559B:
539 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
540 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
541 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
542 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x07);
543 s->stats_size = 80;
544 s->has_extended_tcb_support = 1;
545 break;
546 case i82559C:
547 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
548 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
549 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
550 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x08);
551 /* TODO: Windows wants revision id 0x0c. */
552 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0c);
553 #if EEPROM_SIZE > 0
554 pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
555 pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, 0x0040);
556 #endif
557 s->stats_size = 80;
558 s->has_extended_tcb_support = 1;
559 break;
560 case i82559ER:
561 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
562 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
563 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
564 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x09);
565 s->stats_size = 80;
566 s->has_extended_tcb_support = 1;
567 break;
568 case i82562:
569 /* TODO: check device id. */
570 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
571 /* TODO: wrong revision id. */
572 pci_set_byte(pci_conf + PCI_REVISION_ID, 0x0e);
573 s->stats_size = 80;
574 s->has_extended_tcb_support = 1;
575 break;
576 default:
577 logout("Device %X is undefined!\n", device);
578 }
579
580 s->configuration[6] |= BIT(5);
581
582 if (s->stats_size == 80) {
583 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
584 if (s->configuration[6] & BIT(2)) {
585 /* TCO statistical counters. */
586 assert(s->configuration[6] & BIT(5));
587 } else {
588 if (s->configuration[6] & BIT(5)) {
589 /* No extended statistical counters, i82557 compatible. */
590 s->stats_size = 64;
591 } else {
592 /* i82558 compatible. */
593 s->stats_size = 76;
594 }
595 }
596 } else {
597 if (s->configuration[6] & BIT(5)) {
598 /* No extended statistical counters. */
599 s->stats_size = 64;
600 }
601 }
602 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
603
604 if (power_management) {
605 /* Power Management Capabilities */
606 pci_set_byte(pci_conf + 0xdc, 0x01);
607 /* Next Item Pointer */
608 /* Capability ID */
609 pci_set_word(pci_conf + 0xde, 0x7e21);
610 /* TODO: Power Management Control / Status. */
611 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
612 }
613
614 #if EEPROM_SIZE > 0
615 if (device == i82557C || device == i82558B || device == i82559C) {
616 /*
617 TODO: get vendor id from EEPROM for i82557C or later.
618 TODO: get device id from EEPROM for i82557C or later.
619 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
620 TODO: header type is determined by EEPROM for i82559.
621 TODO: get subsystem id from EEPROM for i82557C or later.
622 TODO: get subsystem vendor id from EEPROM for i82557C or later.
623 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
624 TODO: capability pointer depends on EEPROM for i82558.
625 */
626 logout("Get device id and revision from EEPROM!!!\n");
627 }
628 #endif /* EEPROM_SIZE > 0 */
629 }
630
631 static void nic_selective_reset(EEPRO100State * s)
632 {
633 size_t i;
634 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
635 #if 0
636 eeprom93xx_reset(s->eeprom);
637 #endif
638 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
639 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
640 if (s->device == i82557B || s->device == i82557C)
641 eeprom_contents[5] = 0x0100;
642 eeprom_contents[EEPROM_PHY_ID] = 1;
643 uint16_t sum = 0;
644 for (i = 0; i < EEPROM_SIZE - 1; i++) {
645 sum += eeprom_contents[i];
646 }
647 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
648 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
649
650 memset(s->mem, 0, sizeof(s->mem));
651 uint32_t val = BIT(21);
652 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
653
654 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
655 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
656 }
657
658 static void nic_reset(void *opaque)
659 {
660 EEPRO100State *s = opaque;
661 TRACE(OTHER, logout("%p\n", s));
662 /* TODO: Clearing of multicast table for selective reset, too? */
663 memset(&s->mult[0], 0, sizeof(s->mult));
664 nic_selective_reset(s);
665 }
666
667 #if defined(DEBUG_EEPRO100)
668 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
669 "Command/Status",
670 "General Pointer",
671 "Port",
672 "EEPROM/Flash Control",
673 "MDI Control",
674 "Receive DMA Byte Count",
675 "Flow Control",
676 "General Status/Control"
677 };
678
679 static char *regname(uint32_t addr)
680 {
681 static char buf[32];
682 if (addr < PCI_IO_SIZE) {
683 const char *r = e100_reg[addr / 4];
684 if (r != 0) {
685 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
686 } else {
687 snprintf(buf, sizeof(buf), "0x%02x", addr);
688 }
689 } else {
690 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
691 }
692 return buf;
693 }
694 #endif /* DEBUG_EEPRO100 */
695
696 #if 0
697 static uint16_t eepro100_read_status(EEPRO100State * s)
698 {
699 uint16_t val = s->status;
700 TRACE(OTHER, logout("val=0x%04x\n", val));
701 return val;
702 }
703
704 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
705 {
706 TRACE(OTHER, logout("val=0x%04x\n", val));
707 s->status = val;
708 }
709 #endif
710
711 /*****************************************************************************
712 *
713 * Command emulation.
714 *
715 ****************************************************************************/
716
717 #if 0
718 static uint16_t eepro100_read_command(EEPRO100State * s)
719 {
720 uint16_t val = 0xffff;
721 TRACE(OTHER, logout("val=0x%04x\n", val));
722 return val;
723 }
724 #endif
725
726 /* Commands that can be put in a command list entry. */
727 enum commands {
728 CmdNOp = 0,
729 CmdIASetup = 1,
730 CmdConfigure = 2,
731 CmdMulticastList = 3,
732 CmdTx = 4,
733 CmdTDR = 5, /* load microcode */
734 CmdDump = 6,
735 CmdDiagnose = 7,
736
737 /* And some extra flags: */
738 CmdSuspend = 0x4000, /* Suspend after completion. */
739 CmdIntr = 0x2000, /* Interrupt after completion. */
740 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
741 };
742
743 static cu_state_t get_cu_state(EEPRO100State * s)
744 {
745 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
746 }
747
748 static void set_cu_state(EEPRO100State * s, cu_state_t state)
749 {
750 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
751 }
752
753 static ru_state_t get_ru_state(EEPRO100State * s)
754 {
755 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
756 }
757
758 static void set_ru_state(EEPRO100State * s, ru_state_t state)
759 {
760 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
761 }
762
763 static void dump_statistics(EEPRO100State * s)
764 {
765 /* Dump statistical data. Most data is never changed by the emulation
766 * and always 0, so we first just copy the whole block and then those
767 * values which really matter.
768 * Number of data should check configuration!!!
769 */
770 cpu_physical_memory_write(s->statsaddr,
771 (uint8_t *) & s->statistics, s->stats_size);
772 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
773 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
774 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
775 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
776 #if 0
777 stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
778 stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
779 missing("CU dump statistical counters");
780 #endif
781 }
782
783 static void read_cb(EEPRO100State *s)
784 {
785 cpu_physical_memory_read(s->cb_address, (uint8_t *) &s->tx, sizeof(s->tx));
786 s->tx.status = le16_to_cpu(s->tx.status);
787 s->tx.command = le16_to_cpu(s->tx.command);
788 s->tx.link = le32_to_cpu(s->tx.link);
789 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
790 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
791 }
792
793 static void tx_command(EEPRO100State *s)
794 {
795 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
796 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
797 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
798 uint8_t buf[2600];
799 uint16_t size = 0;
800 uint32_t tbd_address = s->cb_address + 0x10;
801 TRACE(RXTX, logout
802 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
803 tbd_array, tcb_bytes, s->tx.tbd_count));
804
805 if (tcb_bytes > 2600) {
806 logout("TCB byte count too large, using 2600\n");
807 tcb_bytes = 2600;
808 }
809 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
810 logout
811 ("illegal values of TBD array address and TCB byte count!\n");
812 }
813 assert(tcb_bytes <= sizeof(buf));
814 while (size < tcb_bytes) {
815 uint32_t tx_buffer_address = ldl_phys(tbd_address);
816 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
817 #if 0
818 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
819 #endif
820 tbd_address += 8;
821 TRACE(RXTX, logout
822 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
823 tx_buffer_address, tx_buffer_size));
824 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
825 cpu_physical_memory_read(tx_buffer_address, &buf[size],
826 tx_buffer_size);
827 size += tx_buffer_size;
828 }
829 if (tbd_array == 0xffffffff) {
830 /* Simplified mode. Was already handled by code above. */
831 } else {
832 /* Flexible mode. */
833 uint8_t tbd_count = 0;
834 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
835 /* Extended Flexible TCB. */
836 for (; tbd_count < 2; tbd_count++) {
837 uint32_t tx_buffer_address = ldl_phys(tbd_address);
838 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
839 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
840 tbd_address += 8;
841 TRACE(RXTX, logout
842 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
843 tx_buffer_address, tx_buffer_size));
844 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
845 cpu_physical_memory_read(tx_buffer_address, &buf[size],
846 tx_buffer_size);
847 size += tx_buffer_size;
848 if (tx_buffer_el & 1) {
849 break;
850 }
851 }
852 }
853 tbd_address = tbd_array;
854 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
855 uint32_t tx_buffer_address = ldl_phys(tbd_address);
856 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
857 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
858 tbd_address += 8;
859 TRACE(RXTX, logout
860 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
861 tx_buffer_address, tx_buffer_size));
862 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
863 cpu_physical_memory_read(tx_buffer_address, &buf[size],
864 tx_buffer_size);
865 size += tx_buffer_size;
866 if (tx_buffer_el & 1) {
867 break;
868 }
869 }
870 }
871 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
872 qemu_send_packet(&s->nic->nc, buf, size);
873 s->statistics.tx_good_frames++;
874 /* Transmit with bad status would raise an CX/TNO interrupt.
875 * (82557 only). Emulation never has bad status. */
876 #if 0
877 eepro100_cx_interrupt(s);
878 #endif
879 }
880
881 static void set_multicast_list(EEPRO100State *s)
882 {
883 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
884 uint16_t i;
885 memset(&s->mult[0], 0, sizeof(s->mult));
886 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
887 for (i = 0; i < multicast_count; i += 6) {
888 uint8_t multicast_addr[6];
889 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
890 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
891 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
892 assert(mcast_idx < 64);
893 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
894 }
895 }
896
897 static void action_command(EEPRO100State *s)
898 {
899 for (;;) {
900 bool bit_el;
901 bool bit_s;
902 bool bit_i;
903 bool bit_nc;
904 bool success = true;
905 s->cb_address = s->cu_base + s->cu_offset;
906 read_cb(s);
907 bit_el = ((s->tx.command & COMMAND_EL) != 0);
908 bit_s = ((s->tx.command & COMMAND_S) != 0);
909 bit_i = ((s->tx.command & COMMAND_I) != 0);
910 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
911 #if 0
912 bool bit_sf = ((s->tx.command & COMMAND_SF) != 0);
913 #endif
914 s->cu_offset = s->tx.link;
915 TRACE(OTHER,
916 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
917 s->tx.status, s->tx.command, s->tx.link));
918 switch (s->tx.command & COMMAND_CMD) {
919 case CmdNOp:
920 /* Do nothing. */
921 break;
922 case CmdIASetup:
923 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
924 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
925 break;
926 case CmdConfigure:
927 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
928 sizeof(s->configuration));
929 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
930 break;
931 case CmdMulticastList:
932 set_multicast_list(s);
933 break;
934 case CmdTx:
935 if (bit_nc) {
936 missing("CmdTx: NC = 0");
937 success = false;
938 break;
939 }
940 tx_command(s);
941 break;
942 case CmdTDR:
943 TRACE(OTHER, logout("load microcode\n"));
944 /* Starting with offset 8, the command contains
945 * 64 dwords microcode which we just ignore here. */
946 break;
947 case CmdDiagnose:
948 TRACE(OTHER, logout("diagnose\n"));
949 /* Make sure error flag is not set. */
950 s->tx.status = 0;
951 break;
952 default:
953 missing("undefined command");
954 success = false;
955 break;
956 }
957 /* Write new status. */
958 stw_phys(s->cb_address, s->tx.status | STATUS_C | (success ? STATUS_OK : 0));
959 if (bit_i) {
960 /* CU completed action. */
961 eepro100_cx_interrupt(s);
962 }
963 if (bit_el) {
964 /* CU becomes idle. Terminate command loop. */
965 set_cu_state(s, cu_idle);
966 eepro100_cna_interrupt(s);
967 break;
968 } else if (bit_s) {
969 /* CU becomes suspended. Terminate command loop. */
970 set_cu_state(s, cu_suspended);
971 eepro100_cna_interrupt(s);
972 break;
973 } else {
974 /* More entries in list. */
975 TRACE(OTHER, logout("CU list with at least one more entry\n"));
976 }
977 }
978 TRACE(OTHER, logout("CU list empty\n"));
979 /* List is empty. Now CU is idle or suspended. */
980 }
981
982 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
983 {
984 cu_state_t cu_state;
985 switch (val) {
986 case CU_NOP:
987 /* No operation. */
988 break;
989 case CU_START:
990 cu_state = get_cu_state(s);
991 if (cu_state != cu_idle && cu_state != cu_suspended) {
992 /* Intel documentation says that CU must be idle or suspended
993 * for the CU start command. */
994 logout("unexpected CU state is %u\n", cu_state);
995 }
996 set_cu_state(s, cu_active);
997 s->cu_offset = s->pointer;
998 action_command(s);
999 break;
1000 case CU_RESUME:
1001 if (get_cu_state(s) != cu_suspended) {
1002 logout("bad CU resume from CU state %u\n", get_cu_state(s));
1003 /* Workaround for bad Linux eepro100 driver which resumes
1004 * from idle state. */
1005 #if 0
1006 missing("cu resume");
1007 #endif
1008 set_cu_state(s, cu_suspended);
1009 }
1010 if (get_cu_state(s) == cu_suspended) {
1011 TRACE(OTHER, logout("CU resuming\n"));
1012 set_cu_state(s, cu_active);
1013 action_command(s);
1014 }
1015 break;
1016 case CU_STATSADDR:
1017 /* Load dump counters address. */
1018 s->statsaddr = s->pointer;
1019 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1020 break;
1021 case CU_SHOWSTATS:
1022 /* Dump statistical counters. */
1023 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1024 dump_statistics(s);
1025 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1026 break;
1027 case CU_CMD_BASE:
1028 /* Load CU base. */
1029 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1030 s->cu_base = s->pointer;
1031 break;
1032 case CU_DUMPSTATS:
1033 /* Dump and reset statistical counters. */
1034 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1035 dump_statistics(s);
1036 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1037 memset(&s->statistics, 0, sizeof(s->statistics));
1038 break;
1039 case CU_SRESUME:
1040 /* CU static resume. */
1041 missing("CU static resume");
1042 break;
1043 default:
1044 missing("Undefined CU command");
1045 }
1046 }
1047
1048 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1049 {
1050 switch (val) {
1051 case RU_NOP:
1052 /* No operation. */
1053 break;
1054 case RX_START:
1055 /* RU start. */
1056 if (get_ru_state(s) != ru_idle) {
1057 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1058 #if 0
1059 assert(!"wrong RU state");
1060 #endif
1061 }
1062 set_ru_state(s, ru_ready);
1063 s->ru_offset = s->pointer;
1064 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1065 break;
1066 case RX_RESUME:
1067 /* Restart RU. */
1068 if (get_ru_state(s) != ru_suspended) {
1069 logout("RU state is %u, should be %u\n", get_ru_state(s),
1070 ru_suspended);
1071 #if 0
1072 assert(!"wrong RU state");
1073 #endif
1074 }
1075 set_ru_state(s, ru_ready);
1076 break;
1077 case RU_ABORT:
1078 /* RU abort. */
1079 if (get_ru_state(s) == ru_ready) {
1080 eepro100_rnr_interrupt(s);
1081 }
1082 set_ru_state(s, ru_idle);
1083 break;
1084 case RX_ADDR_LOAD:
1085 /* Load RU base. */
1086 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1087 s->ru_base = s->pointer;
1088 break;
1089 default:
1090 logout("val=0x%02x (undefined RU command)\n", val);
1091 missing("Undefined SU command");
1092 }
1093 }
1094
1095 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1096 {
1097 eepro100_ru_command(s, val & 0x0f);
1098 eepro100_cu_command(s, val & 0xf0);
1099 if ((val) == 0) {
1100 TRACE(OTHER, logout("val=0x%02x\n", val));
1101 }
1102 /* Clear command byte after command was accepted. */
1103 s->mem[SCBCmd] = 0;
1104 }
1105
1106 /*****************************************************************************
1107 *
1108 * EEPROM emulation.
1109 *
1110 ****************************************************************************/
1111
1112 #define EEPROM_CS 0x02
1113 #define EEPROM_SK 0x01
1114 #define EEPROM_DI 0x04
1115 #define EEPROM_DO 0x08
1116
1117 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1118 {
1119 uint16_t val;
1120 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1121 if (eeprom93xx_read(s->eeprom)) {
1122 val |= EEPROM_DO;
1123 } else {
1124 val &= ~EEPROM_DO;
1125 }
1126 TRACE(EEPROM, logout("val=0x%04x\n", val));
1127 return val;
1128 }
1129
1130 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1131 {
1132 TRACE(EEPROM, logout("val=0x%02x\n", val));
1133
1134 /* mask unwriteable bits */
1135 #if 0
1136 val = SET_MASKED(val, 0x31, eeprom->value);
1137 #endif
1138
1139 int eecs = ((val & EEPROM_CS) != 0);
1140 int eesk = ((val & EEPROM_SK) != 0);
1141 int eedi = ((val & EEPROM_DI) != 0);
1142 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1143 }
1144
1145 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1146 {
1147 s->pointer = le32_to_cpu(val);
1148 TRACE(OTHER, logout("val=0x%08x\n", val));
1149 }
1150
1151 /*****************************************************************************
1152 *
1153 * MDI emulation.
1154 *
1155 ****************************************************************************/
1156
1157 #if defined(DEBUG_EEPRO100)
1158 static const char * const mdi_op_name[] = {
1159 "opcode 0",
1160 "write",
1161 "read",
1162 "opcode 3"
1163 };
1164
1165 static const char * const mdi_reg_name[] = {
1166 "Control",
1167 "Status",
1168 "PHY Identification (Word 1)",
1169 "PHY Identification (Word 2)",
1170 "Auto-Negotiation Advertisement",
1171 "Auto-Negotiation Link Partner Ability",
1172 "Auto-Negotiation Expansion"
1173 };
1174
1175 static const char *reg2name(uint8_t reg)
1176 {
1177 static char buffer[10];
1178 const char *p = buffer;
1179 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1180 p = mdi_reg_name[reg];
1181 } else {
1182 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1183 }
1184 return p;
1185 }
1186 #endif /* DEBUG_EEPRO100 */
1187
1188 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1189 {
1190 uint32_t val;
1191 memcpy(&val, &s->mem[0x10], sizeof(val));
1192
1193 #ifdef DEBUG_EEPRO100
1194 uint8_t raiseint = (val & BIT(29)) >> 29;
1195 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1196 uint8_t phy = (val & BITS(25, 21)) >> 21;
1197 uint8_t reg = (val & BITS(20, 16)) >> 16;
1198 uint16_t data = (val & BITS(15, 0));
1199 #endif
1200 /* Emulation takes no time to finish MDI transaction. */
1201 val |= BIT(28);
1202 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1203 val, raiseint, mdi_op_name[opcode], phy,
1204 reg2name(reg), data));
1205 return val;
1206 }
1207
1208 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1209 {
1210 uint8_t raiseint = (val & BIT(29)) >> 29;
1211 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1212 uint8_t phy = (val & BITS(25, 21)) >> 21;
1213 uint8_t reg = (val & BITS(20, 16)) >> 16;
1214 uint16_t data = (val & BITS(15, 0));
1215 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1216 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1217 if (phy != 1) {
1218 /* Unsupported PHY address. */
1219 #if 0
1220 logout("phy must be 1 but is %u\n", phy);
1221 #endif
1222 data = 0;
1223 } else if (opcode != 1 && opcode != 2) {
1224 /* Unsupported opcode. */
1225 logout("opcode must be 1 or 2 but is %u\n", opcode);
1226 data = 0;
1227 } else if (reg > 6) {
1228 /* Unsupported register. */
1229 logout("register must be 0...6 but is %u\n", reg);
1230 data = 0;
1231 } else {
1232 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1233 val, raiseint, mdi_op_name[opcode], phy,
1234 reg2name(reg), data));
1235 if (opcode == 1) {
1236 /* MDI write */
1237 switch (reg) {
1238 case 0: /* Control Register */
1239 if (data & 0x8000) {
1240 /* Reset status and control registers to default. */
1241 s->mdimem[0] = eepro100_mdi_default[0];
1242 s->mdimem[1] = eepro100_mdi_default[1];
1243 data = s->mdimem[reg];
1244 } else {
1245 /* Restart Auto Configuration = Normal Operation */
1246 data &= ~0x0200;
1247 }
1248 break;
1249 case 1: /* Status Register */
1250 missing("not writable");
1251 data = s->mdimem[reg];
1252 break;
1253 case 2: /* PHY Identification Register (Word 1) */
1254 case 3: /* PHY Identification Register (Word 2) */
1255 missing("not implemented");
1256 break;
1257 case 4: /* Auto-Negotiation Advertisement Register */
1258 case 5: /* Auto-Negotiation Link Partner Ability Register */
1259 break;
1260 case 6: /* Auto-Negotiation Expansion Register */
1261 default:
1262 missing("not implemented");
1263 }
1264 s->mdimem[reg] = data;
1265 } else if (opcode == 2) {
1266 /* MDI read */
1267 switch (reg) {
1268 case 0: /* Control Register */
1269 if (data & 0x8000) {
1270 /* Reset status and control registers to default. */
1271 s->mdimem[0] = eepro100_mdi_default[0];
1272 s->mdimem[1] = eepro100_mdi_default[1];
1273 }
1274 break;
1275 case 1: /* Status Register */
1276 s->mdimem[reg] |= 0x0020;
1277 break;
1278 case 2: /* PHY Identification Register (Word 1) */
1279 case 3: /* PHY Identification Register (Word 2) */
1280 case 4: /* Auto-Negotiation Advertisement Register */
1281 break;
1282 case 5: /* Auto-Negotiation Link Partner Ability Register */
1283 s->mdimem[reg] = 0x41fe;
1284 break;
1285 case 6: /* Auto-Negotiation Expansion Register */
1286 s->mdimem[reg] = 0x0001;
1287 break;
1288 }
1289 data = s->mdimem[reg];
1290 }
1291 /* Emulation takes no time to finish MDI transaction.
1292 * Set MDI bit in SCB status register. */
1293 s->mem[SCBAck] |= 0x08;
1294 val |= BIT(28);
1295 if (raiseint) {
1296 eepro100_mdi_interrupt(s);
1297 }
1298 }
1299 val = (val & 0xffff0000) + data;
1300 memcpy(&s->mem[0x10], &val, sizeof(val));
1301 }
1302
1303 /*****************************************************************************
1304 *
1305 * Port emulation.
1306 *
1307 ****************************************************************************/
1308
1309 #define PORT_SOFTWARE_RESET 0
1310 #define PORT_SELFTEST 1
1311 #define PORT_SELECTIVE_RESET 2
1312 #define PORT_DUMP 3
1313 #define PORT_SELECTION_MASK 3
1314
1315 typedef struct {
1316 uint32_t st_sign; /* Self Test Signature */
1317 uint32_t st_result; /* Self Test Results */
1318 } eepro100_selftest_t;
1319
1320 static uint32_t eepro100_read_port(EEPRO100State * s)
1321 {
1322 return 0;
1323 }
1324
1325 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1326 {
1327 val = le32_to_cpu(val);
1328 uint32_t address = (val & ~PORT_SELECTION_MASK);
1329 uint8_t selection = (val & PORT_SELECTION_MASK);
1330 switch (selection) {
1331 case PORT_SOFTWARE_RESET:
1332 nic_reset(s);
1333 break;
1334 case PORT_SELFTEST:
1335 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1336 eepro100_selftest_t data;
1337 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1338 data.st_sign = 0xffffffff;
1339 data.st_result = 0;
1340 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1341 break;
1342 case PORT_SELECTIVE_RESET:
1343 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1344 nic_selective_reset(s);
1345 break;
1346 default:
1347 logout("val=0x%08x\n", val);
1348 missing("unknown port selection");
1349 }
1350 }
1351
1352 /*****************************************************************************
1353 *
1354 * General hardware emulation.
1355 *
1356 ****************************************************************************/
1357
1358 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1359 {
1360 uint8_t val;
1361 if (addr <= sizeof(s->mem) - sizeof(val)) {
1362 memcpy(&val, &s->mem[addr], sizeof(val));
1363 }
1364
1365 switch (addr) {
1366 case SCBStatus:
1367 #if 0
1368 val = eepro100_read_status(s);
1369 #endif
1370 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1371 break;
1372 case SCBAck:
1373 #if 0
1374 val = eepro100_read_status(s);
1375 #endif
1376 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1377 break;
1378 case SCBCmd:
1379 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1380 #if 0
1381 val = eepro100_read_command(s);
1382 #endif
1383 break;
1384 case SCBIntmask:
1385 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1386 break;
1387 case SCBPort + 3:
1388 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1389 break;
1390 case SCBeeprom:
1391 val = eepro100_read_eeprom(s);
1392 break;
1393 case SCBpmdr: /* Power Management Driver Register */
1394 val = 0;
1395 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1396 break;
1397 case SCBgstat: /* General Status Register */
1398 /* 100 Mbps full duplex, valid link */
1399 val = 0x07;
1400 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1401 break;
1402 default:
1403 logout("addr=%s val=0x%02x\n", regname(addr), val);
1404 missing("unknown byte read");
1405 }
1406 return val;
1407 }
1408
1409 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1410 {
1411 uint16_t val;
1412 if (addr <= sizeof(s->mem) - sizeof(val)) {
1413 memcpy(&val, &s->mem[addr], sizeof(val));
1414 }
1415
1416 switch (addr) {
1417 case SCBStatus:
1418 #if 0
1419 val = eepro100_read_status(s);
1420 #endif
1421 case SCBCmd:
1422 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1423 break;
1424 case SCBeeprom:
1425 val = eepro100_read_eeprom(s);
1426 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1427 break;
1428 default:
1429 logout("addr=%s val=0x%04x\n", regname(addr), val);
1430 missing("unknown word read");
1431 }
1432 return val;
1433 }
1434
1435 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1436 {
1437 uint32_t val;
1438 if (addr <= sizeof(s->mem) - sizeof(val)) {
1439 memcpy(&val, &s->mem[addr], sizeof(val));
1440 }
1441
1442 switch (addr) {
1443 case SCBStatus:
1444 #if 0
1445 val = eepro100_read_status(s);
1446 #endif
1447 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1448 break;
1449 case SCBPointer:
1450 #if 0
1451 val = eepro100_read_pointer(s);
1452 #endif
1453 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1454 break;
1455 case SCBPort:
1456 val = eepro100_read_port(s);
1457 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1458 break;
1459 case SCBCtrlMDI:
1460 val = eepro100_read_mdi(s);
1461 break;
1462 default:
1463 logout("addr=%s val=0x%08x\n", regname(addr), val);
1464 missing("unknown longword read");
1465 }
1466 return val;
1467 }
1468
1469 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1470 {
1471 if (addr <= sizeof(s->mem) - sizeof(val)) {
1472 memcpy(&s->mem[addr], &val, sizeof(val));
1473 }
1474
1475 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1476
1477 switch (addr) {
1478 case SCBStatus:
1479 #if 0
1480 eepro100_write_status(s, val);
1481 #endif
1482 break;
1483 case SCBAck:
1484 eepro100_acknowledge(s);
1485 break;
1486 case SCBCmd:
1487 eepro100_write_command(s, val);
1488 break;
1489 case SCBIntmask:
1490 if (val & BIT(1)) {
1491 eepro100_swi_interrupt(s);
1492 }
1493 eepro100_interrupt(s, 0);
1494 break;
1495 case SCBPort + 3:
1496 case SCBFlow: /* does not exist on 82557 */
1497 case SCBFlow + 1:
1498 case SCBFlow + 2:
1499 case SCBpmdr: /* does not exist on 82557 */
1500 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1501 break;
1502 case SCBeeprom:
1503 eepro100_write_eeprom(s->eeprom, val);
1504 break;
1505 default:
1506 logout("addr=%s val=0x%02x\n", regname(addr), val);
1507 missing("unknown byte write");
1508 }
1509 }
1510
1511 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1512 {
1513 if (addr <= sizeof(s->mem) - sizeof(val)) {
1514 memcpy(&s->mem[addr], &val, sizeof(val));
1515 }
1516
1517 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1518
1519 switch (addr) {
1520 case SCBStatus:
1521 #if 0
1522 eepro100_write_status(s, val);
1523 #endif
1524 eepro100_acknowledge(s);
1525 break;
1526 case SCBCmd:
1527 eepro100_write_command(s, val);
1528 eepro100_write1(s, SCBIntmask, val >> 8);
1529 break;
1530 case SCBeeprom:
1531 eepro100_write_eeprom(s->eeprom, val);
1532 break;
1533 default:
1534 logout("addr=%s val=0x%04x\n", regname(addr), val);
1535 missing("unknown word write");
1536 }
1537 }
1538
1539 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1540 {
1541 if (addr <= sizeof(s->mem) - sizeof(val)) {
1542 memcpy(&s->mem[addr], &val, sizeof(val));
1543 }
1544
1545 switch (addr) {
1546 case SCBPointer:
1547 eepro100_write_pointer(s, val);
1548 break;
1549 case SCBPort:
1550 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1551 eepro100_write_port(s, val);
1552 break;
1553 case SCBCtrlMDI:
1554 eepro100_write_mdi(s, val);
1555 break;
1556 default:
1557 logout("addr=%s val=0x%08x\n", regname(addr), val);
1558 missing("unknown longword write");
1559 }
1560 }
1561
1562 /*****************************************************************************
1563 *
1564 * Port mapped I/O.
1565 *
1566 ****************************************************************************/
1567
1568 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1569 {
1570 EEPRO100State *s = opaque;
1571 #if 0
1572 logout("addr=%s\n", regname(addr));
1573 #endif
1574 return eepro100_read1(s, addr - s->region[1]);
1575 }
1576
1577 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1578 {
1579 EEPRO100State *s = opaque;
1580 return eepro100_read2(s, addr - s->region[1]);
1581 }
1582
1583 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1584 {
1585 EEPRO100State *s = opaque;
1586 return eepro100_read4(s, addr - s->region[1]);
1587 }
1588
1589 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1590 {
1591 EEPRO100State *s = opaque;
1592 #if 0
1593 logout("addr=%s val=0x%02x\n", regname(addr), val);
1594 #endif
1595 eepro100_write1(s, addr - s->region[1], val);
1596 }
1597
1598 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1599 {
1600 EEPRO100State *s = opaque;
1601 eepro100_write2(s, addr - s->region[1], val);
1602 }
1603
1604 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1605 {
1606 EEPRO100State *s = opaque;
1607 eepro100_write4(s, addr - s->region[1], val);
1608 }
1609
1610 /***********************************************************/
1611 /* PCI EEPRO100 definitions */
1612
1613 static void pci_map(PCIDevice * pci_dev, int region_num,
1614 pcibus_t addr, pcibus_t size, int type)
1615 {
1616 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1617
1618 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1619 "size=0x%08"FMT_PCIBUS", type=%d\n",
1620 region_num, addr, size, type));
1621
1622 assert(region_num == 1);
1623 register_ioport_write(addr, size, 1, ioport_write1, s);
1624 register_ioport_read(addr, size, 1, ioport_read1, s);
1625 register_ioport_write(addr, size, 2, ioport_write2, s);
1626 register_ioport_read(addr, size, 2, ioport_read2, s);
1627 register_ioport_write(addr, size, 4, ioport_write4, s);
1628 register_ioport_read(addr, size, 4, ioport_read4, s);
1629
1630 s->region[region_num] = addr;
1631 }
1632
1633 /*****************************************************************************
1634 *
1635 * Memory mapped I/O.
1636 *
1637 ****************************************************************************/
1638
1639 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1640 {
1641 EEPRO100State *s = opaque;
1642 #if 0
1643 logout("addr=%s val=0x%02x\n", regname(addr), val);
1644 #endif
1645 eepro100_write1(s, addr, val);
1646 }
1647
1648 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1649 {
1650 EEPRO100State *s = opaque;
1651 #if 0
1652 logout("addr=%s val=0x%02x\n", regname(addr), val);
1653 #endif
1654 eepro100_write2(s, addr, val);
1655 }
1656
1657 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1658 {
1659 EEPRO100State *s = opaque;
1660 #if 0
1661 logout("addr=%s val=0x%02x\n", regname(addr), val);
1662 #endif
1663 eepro100_write4(s, addr, val);
1664 }
1665
1666 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1667 {
1668 EEPRO100State *s = opaque;
1669 #if 0
1670 logout("addr=%s\n", regname(addr));
1671 #endif
1672 return eepro100_read1(s, addr);
1673 }
1674
1675 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1676 {
1677 EEPRO100State *s = opaque;
1678 #if 0
1679 logout("addr=%s\n", regname(addr));
1680 #endif
1681 return eepro100_read2(s, addr);
1682 }
1683
1684 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1685 {
1686 EEPRO100State *s = opaque;
1687 #if 0
1688 logout("addr=%s\n", regname(addr));
1689 #endif
1690 return eepro100_read4(s, addr);
1691 }
1692
1693 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1694 pci_mmio_writeb,
1695 pci_mmio_writew,
1696 pci_mmio_writel
1697 };
1698
1699 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1700 pci_mmio_readb,
1701 pci_mmio_readw,
1702 pci_mmio_readl
1703 };
1704
1705 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1706 pcibus_t addr, pcibus_t size, int type)
1707 {
1708 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1709
1710 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1711 "size=0x%08"FMT_PCIBUS", type=%d\n",
1712 region_num, addr, size, type));
1713
1714 if (region_num == 0) {
1715 /* Map control / status registers. */
1716 cpu_register_physical_memory(addr, size, s->mmio_index);
1717 s->region[region_num] = addr;
1718 }
1719 }
1720
1721 static int nic_can_receive(VLANClientState *nc)
1722 {
1723 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1724 TRACE(RXTX, logout("%p\n", s));
1725 return get_ru_state(s) == ru_ready;
1726 #if 0
1727 return !eepro100_buffer_full(s);
1728 #endif
1729 }
1730
1731 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1732 {
1733 /* TODO:
1734 * - Magic packets should set bit 30 in power management driver register.
1735 * - Interesting packets should set bit 29 in power management driver register.
1736 */
1737 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1738 uint16_t rfd_status = 0xa000;
1739 static const uint8_t broadcast_macaddr[6] =
1740 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1741
1742 /* TODO: check multiple IA bit. */
1743 if (s->configuration[20] & BIT(6)) {
1744 missing("Multiple IA bit");
1745 return -1;
1746 }
1747
1748 if (s->configuration[8] & 0x80) {
1749 /* CSMA is disabled. */
1750 logout("%p received while CSMA is disabled\n", s);
1751 return -1;
1752 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1753 /* Short frame and configuration byte 7/0 (discard short receive) set:
1754 * Short frame is discarded */
1755 logout("%p received short frame (%zu byte)\n", s, size);
1756 s->statistics.rx_short_frame_errors++;
1757 #if 0
1758 return -1;
1759 #endif
1760 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1761 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1762 * Long frames are discarded. */
1763 logout("%p received long frame (%zu byte), ignored\n", s, size);
1764 return -1;
1765 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1766 /* Frame matches individual address. */
1767 /* TODO: check configuration byte 15/4 (ignore U/L). */
1768 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1769 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1770 /* Broadcast frame. */
1771 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1772 rfd_status |= 0x0002;
1773 } else if (buf[0] & 0x01) {
1774 /* Multicast frame. */
1775 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1776 if (s->configuration[21] & BIT(3)) {
1777 /* Multicast all bit is set, receive all multicast frames. */
1778 } else {
1779 unsigned mcast_idx = compute_mcast_idx(buf);
1780 assert(mcast_idx < 64);
1781 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1782 /* Multicast frame is allowed in hash table. */
1783 } else if (s->configuration[15] & BIT(0)) {
1784 /* Promiscuous: receive all. */
1785 rfd_status |= 0x0004;
1786 } else {
1787 TRACE(RXTX, logout("%p multicast ignored\n", s));
1788 return -1;
1789 }
1790 }
1791 /* TODO: Next not for promiscuous mode? */
1792 rfd_status |= 0x0002;
1793 } else if (s->configuration[15] & BIT(0)) {
1794 /* Promiscuous: receive all. */
1795 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1796 rfd_status |= 0x0004;
1797 } else {
1798 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1799 nic_dump(buf, size)));
1800 return size;
1801 }
1802
1803 if (get_ru_state(s) != ru_ready) {
1804 /* No resources available. */
1805 logout("no resources, state=%u\n", get_ru_state(s));
1806 /* TODO: RNR interrupt only at first failed frame? */
1807 eepro100_rnr_interrupt(s);
1808 s->statistics.rx_resource_errors++;
1809 #if 0
1810 assert(!"no resources");
1811 #endif
1812 return -1;
1813 }
1814 /* !!! */
1815 eepro100_rx_t rx;
1816 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1817 offsetof(eepro100_rx_t, packet));
1818 uint16_t rfd_command = le16_to_cpu(rx.command);
1819 uint16_t rfd_size = le16_to_cpu(rx.size);
1820
1821 if (size > rfd_size) {
1822 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1823 "(%zu bytes); data truncated\n", rfd_size, size);
1824 size = rfd_size;
1825 }
1826 if (size < 64) {
1827 rfd_status |= 0x0080;
1828 }
1829 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1830 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1831 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1832 rfd_status);
1833 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1834 /* Early receive interrupt not supported. */
1835 #if 0
1836 eepro100_er_interrupt(s);
1837 #endif
1838 /* Receive CRC Transfer not supported. */
1839 if (s->configuration[18] & BIT(2)) {
1840 missing("Receive CRC Transfer");
1841 return -1;
1842 }
1843 /* TODO: check stripping enable bit. */
1844 #if 0
1845 assert(!(s->configuration[17] & BIT(0)));
1846 #endif
1847 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1848 offsetof(eepro100_rx_t, packet), buf, size);
1849 s->statistics.rx_good_frames++;
1850 eepro100_fr_interrupt(s);
1851 s->ru_offset = le32_to_cpu(rx.link);
1852 if (rfd_command & COMMAND_EL) {
1853 /* EL bit is set, so this was the last frame. */
1854 logout("receive: Running out of frames\n");
1855 set_ru_state(s, ru_suspended);
1856 }
1857 if (rfd_command & COMMAND_S) {
1858 /* S bit is set. */
1859 set_ru_state(s, ru_suspended);
1860 }
1861 return size;
1862 }
1863
1864 static const VMStateDescription vmstate_eepro100 = {
1865 .version_id = 3,
1866 .minimum_version_id = 2,
1867 .minimum_version_id_old = 2,
1868 .fields = (VMStateField []) {
1869 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1870 VMSTATE_UNUSED(32),
1871 VMSTATE_BUFFER(mult, EEPRO100State),
1872 VMSTATE_BUFFER(mem, EEPRO100State),
1873 /* Save all members of struct between scb_stat and mem. */
1874 VMSTATE_UINT8(scb_stat, EEPRO100State),
1875 VMSTATE_UINT8(int_stat, EEPRO100State),
1876 VMSTATE_UNUSED(3*4),
1877 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1878 VMSTATE_UNUSED(19*4),
1879 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1880 /* The eeprom should be saved and restored by its own routines. */
1881 VMSTATE_UINT32(device, EEPRO100State),
1882 /* TODO check device. */
1883 VMSTATE_UINT32(pointer, EEPRO100State),
1884 VMSTATE_UINT32(cu_base, EEPRO100State),
1885 VMSTATE_UINT32(cu_offset, EEPRO100State),
1886 VMSTATE_UINT32(ru_base, EEPRO100State),
1887 VMSTATE_UINT32(ru_offset, EEPRO100State),
1888 VMSTATE_UINT32(statsaddr, EEPRO100State),
1889 /* Save eepro100_stats_t statistics. */
1890 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1891 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1892 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1893 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1894 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1895 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1896 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1897 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1898 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1899 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1900 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1901 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1902 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1903 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1904 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1905 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1906 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1907 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1908 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1909 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1910 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1911 #if 0
1912 VMSTATE_UINT16(status, EEPRO100State),
1913 #endif
1914 /* Configuration bytes. */
1915 VMSTATE_BUFFER(configuration, EEPRO100State),
1916 VMSTATE_END_OF_LIST()
1917 }
1918 };
1919
1920 static void nic_cleanup(VLANClientState *nc)
1921 {
1922 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1923
1924 s->nic = NULL;
1925 }
1926
1927 static int pci_nic_uninit(PCIDevice *pci_dev)
1928 {
1929 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1930
1931 cpu_unregister_io_memory(s->mmio_index);
1932 vmstate_unregister(s->vmstate, s);
1933 eeprom93xx_free(s->eeprom);
1934 qemu_del_vlan_client(&s->nic->nc);
1935 return 0;
1936 }
1937
1938 static NetClientInfo net_eepro100_info = {
1939 .type = NET_CLIENT_TYPE_NIC,
1940 .size = sizeof(NICState),
1941 .can_receive = nic_can_receive,
1942 .receive = nic_receive,
1943 .cleanup = nic_cleanup,
1944 };
1945
1946 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1947 {
1948 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1949
1950 TRACE(OTHER, logout("\n"));
1951
1952 s->device = device;
1953
1954 pci_reset(s);
1955
1956 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1957 * i82559 and later support 64 or 256 word EEPROM. */
1958 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1959
1960 /* Handler for memory-mapped I/O */
1961 s->mmio_index =
1962 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1963
1964 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1965 PCI_BASE_ADDRESS_SPACE_MEMORY |
1966 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1967 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1968 pci_map);
1969 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1970 pci_mmio_map);
1971
1972 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1973 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1974 assert(s->region[1] == 0);
1975
1976 nic_reset(s);
1977
1978 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1979 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1980
1981 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1982 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1983
1984 qemu_register_reset(nic_reset, s);
1985
1986 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1987 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1988 s->vmstate->name = s->nic->nc.model;
1989 vmstate_register(-1, s->vmstate, s);
1990
1991 return 0;
1992 }
1993
1994 static int pci_i82550_init(PCIDevice *pci_dev)
1995 {
1996 return nic_init(pci_dev, i82550);
1997 }
1998
1999 static int pci_i82551_init(PCIDevice *pci_dev)
2000 {
2001 return nic_init(pci_dev, i82551);
2002 }
2003
2004 static int pci_i82557a_init(PCIDevice *pci_dev)
2005 {
2006 return nic_init(pci_dev, i82557A);
2007 }
2008
2009 static int pci_i82557b_init(PCIDevice *pci_dev)
2010 {
2011 return nic_init(pci_dev, i82557B);
2012 }
2013
2014 static int pci_i82557c_init(PCIDevice *pci_dev)
2015 {
2016 return nic_init(pci_dev, i82557C);
2017 }
2018
2019 static int pci_i82558a_init(PCIDevice *pci_dev)
2020 {
2021 return nic_init(pci_dev, i82558A);
2022 }
2023
2024 static int pci_i82558b_init(PCIDevice *pci_dev)
2025 {
2026 return nic_init(pci_dev, i82558B);
2027 }
2028
2029 static int pci_i82559a_init(PCIDevice *pci_dev)
2030 {
2031 return nic_init(pci_dev, i82559A);
2032 }
2033
2034 static int pci_i82559b_init(PCIDevice *pci_dev)
2035 {
2036 return nic_init(pci_dev, i82559B);
2037 }
2038
2039 static int pci_i82559c_init(PCIDevice *pci_dev)
2040 {
2041 return nic_init(pci_dev, i82559C);
2042 }
2043
2044 static int pci_i82559er_init(PCIDevice *pci_dev)
2045 {
2046 return nic_init(pci_dev, i82559ER);
2047 }
2048
2049 static int pci_i82562_init(PCIDevice *pci_dev)
2050 {
2051 return nic_init(pci_dev, i82562);
2052 }
2053
2054 static PCIDeviceInfo eepro100_info[] = {
2055 {
2056 .qdev.name = "i82550",
2057 .qdev.desc = "Intel i82550 Ethernet",
2058 .qdev.size = sizeof(EEPRO100State),
2059 .init = pci_i82550_init,
2060 .exit = pci_nic_uninit,
2061 .romfile = "gpxe-eepro100-80861209.rom",
2062 .qdev.props = (Property[]) {
2063 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2064 DEFINE_PROP_END_OF_LIST(),
2065 },
2066 },{
2067 .qdev.name = "i82551",
2068 .qdev.desc = "Intel i82551 Ethernet",
2069 .qdev.size = sizeof(EEPRO100State),
2070 .init = pci_i82551_init,
2071 .exit = pci_nic_uninit,
2072 .romfile = "gpxe-eepro100-80861209.rom",
2073 .qdev.props = (Property[]) {
2074 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2075 DEFINE_PROP_END_OF_LIST(),
2076 },
2077 },{
2078 .qdev.name = "i82557a",
2079 .qdev.desc = "Intel i82557A Ethernet",
2080 .qdev.size = sizeof(EEPRO100State),
2081 .init = pci_i82557a_init,
2082 .exit = pci_nic_uninit,
2083 .romfile = "gpxe-eepro100-80861229.rom",
2084 .qdev.props = (Property[]) {
2085 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2086 DEFINE_PROP_END_OF_LIST(),
2087 },
2088 },{
2089 .qdev.name = "i82557b",
2090 .qdev.desc = "Intel i82557B Ethernet",
2091 .qdev.size = sizeof(EEPRO100State),
2092 .init = pci_i82557b_init,
2093 .exit = pci_nic_uninit,
2094 .romfile = "gpxe-eepro100-80861229.rom",
2095 .qdev.props = (Property[]) {
2096 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2097 DEFINE_PROP_END_OF_LIST(),
2098 },
2099 },{
2100 .qdev.name = "i82557c",
2101 .qdev.desc = "Intel i82557C Ethernet",
2102 .qdev.size = sizeof(EEPRO100State),
2103 .init = pci_i82557c_init,
2104 .exit = pci_nic_uninit,
2105 .romfile = "gpxe-eepro100-80861229.rom",
2106 .qdev.props = (Property[]) {
2107 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2108 DEFINE_PROP_END_OF_LIST(),
2109 },
2110 },{
2111 .qdev.name = "i82558a",
2112 .qdev.desc = "Intel i82558A Ethernet",
2113 .qdev.size = sizeof(EEPRO100State),
2114 .init = pci_i82558a_init,
2115 .exit = pci_nic_uninit,
2116 .romfile = "gpxe-eepro100-80861229.rom",
2117 .qdev.props = (Property[]) {
2118 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2119 DEFINE_PROP_END_OF_LIST(),
2120 },
2121 },{
2122 .qdev.name = "i82558b",
2123 .qdev.desc = "Intel i82558B Ethernet",
2124 .qdev.size = sizeof(EEPRO100State),
2125 .init = pci_i82558b_init,
2126 .exit = pci_nic_uninit,
2127 .romfile = "gpxe-eepro100-80861229.rom",
2128 .qdev.props = (Property[]) {
2129 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2130 DEFINE_PROP_END_OF_LIST(),
2131 },
2132 },{
2133 .qdev.name = "i82559a",
2134 .qdev.desc = "Intel i82559A Ethernet",
2135 .qdev.size = sizeof(EEPRO100State),
2136 .init = pci_i82559a_init,
2137 .exit = pci_nic_uninit,
2138 .romfile = "gpxe-eepro100-80861229.rom",
2139 .qdev.props = (Property[]) {
2140 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2141 DEFINE_PROP_END_OF_LIST(),
2142 },
2143 },{
2144 .qdev.name = "i82559b",
2145 .qdev.desc = "Intel i82559B Ethernet",
2146 .qdev.size = sizeof(EEPRO100State),
2147 .init = pci_i82559b_init,
2148 .exit = pci_nic_uninit,
2149 .romfile = "gpxe-eepro100-80861229.rom",
2150 .qdev.props = (Property[]) {
2151 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2152 DEFINE_PROP_END_OF_LIST(),
2153 },
2154 },{
2155 .qdev.name = "i82559c",
2156 .qdev.desc = "Intel i82559C Ethernet",
2157 .qdev.size = sizeof(EEPRO100State),
2158 .init = pci_i82559c_init,
2159 .exit = pci_nic_uninit,
2160 .romfile = "gpxe-eepro100-80861229.rom",
2161 .qdev.props = (Property[]) {
2162 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2163 DEFINE_PROP_END_OF_LIST(),
2164 },
2165 },{
2166 .qdev.name = "i82559er",
2167 .qdev.desc = "Intel i82559ER Ethernet",
2168 .qdev.size = sizeof(EEPRO100State),
2169 .init = pci_i82559er_init,
2170 .exit = pci_nic_uninit,
2171 .romfile = "gpxe-eepro100-80861209.rom",
2172 .qdev.props = (Property[]) {
2173 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2174 DEFINE_PROP_END_OF_LIST(),
2175 },
2176 },{
2177 .qdev.name = "i82562",
2178 .qdev.desc = "Intel i82562 Ethernet",
2179 .qdev.size = sizeof(EEPRO100State),
2180 .init = pci_i82562_init,
2181 .exit = pci_nic_uninit,
2182 .romfile = "gpxe-eepro100-80861209.rom",
2183 .qdev.props = (Property[]) {
2184 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2185 DEFINE_PROP_END_OF_LIST(),
2186 },
2187 },{
2188 /* end of list */
2189 }
2190 };
2191
2192 static void eepro100_register_devices(void)
2193 {
2194 pci_qdev_register_many(eepro100_info);
2195 }
2196
2197 device_init(eepro100_register_devices)
Anthony Liguori's QEMU queue