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Update version and changelog to sync with stable branch
[qemu/aliguori-queue.git] / hw / sun4m.c
blob7db00b8222f65f616b2eadb04dfb4fe6e8fffdd6
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "qdev-addr.h"
40 #include "loader.h"
41 #include "elf.h"
42
43 //#define DEBUG_IRQ
44
45 /*
46 * Sun4m architecture was used in the following machines:
47 *
48 * SPARCserver 6xxMP/xx
49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
50 * SPARCclassic X (4/10)
51 * SPARCstation LX/ZX (4/30)
52 * SPARCstation Voyager
53 * SPARCstation 10/xx, SPARCserver 10/xx
54 * SPARCstation 5, SPARCserver 5
55 * SPARCstation 20/xx, SPARCserver 20
56 * SPARCstation 4
57 *
58 * Sun4d architecture was used in the following machines:
59 *
60 * SPARCcenter 2000
61 * SPARCserver 1000
62 *
63 * Sun4c architecture was used in the following machines:
64 * SPARCstation 1/1+, SPARCserver 1/1+
65 * SPARCstation SLC
66 * SPARCstation IPC
67 * SPARCstation ELC
68 * SPARCstation IPX
69 *
70 * See for example: http://www.sunhelp.org/faq/sunref1.html
71 */
72
73 #ifdef DEBUG_IRQ
74 #define DPRINTF(fmt, ...) \
75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
76 #else
77 #define DPRINTF(fmt, ...)
78 #endif
79
80 #define KERNEL_LOAD_ADDR 0x00004000
81 #define CMDLINE_ADDR 0x007ff000
82 #define INITRD_LOAD_ADDR 0x00800000
83 #define PROM_SIZE_MAX (1024 * 1024)
84 #define PROM_VADDR 0xffd00000
85 #define PROM_FILENAME "openbios-sparc32"
86 #define CFG_ADDR 0xd00000510ULL
87 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
88
89 #define MAX_CPUS 16
90 #define MAX_PILS 16
91
92 #define ESCC_CLOCK 4915200
93
94 struct sun4m_hwdef {
95 target_phys_addr_t iommu_base, slavio_base;
96 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
97 target_phys_addr_t serial_base, fd_base;
98 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
99 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
100 target_phys_addr_t ecc_base;
101 uint32_t ecc_version;
102 uint8_t nvram_machine_id;
103 uint16_t machine_id;
104 uint32_t iommu_version;
105 uint64_t max_mem;
106 const char * const default_cpu_model;
107 };
108
109 #define MAX_IOUNITS 5
110
111 struct sun4d_hwdef {
112 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
113 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
114 target_phys_addr_t serial_base;
115 target_phys_addr_t espdma_base, esp_base;
116 target_phys_addr_t ledma_base, le_base;
117 target_phys_addr_t tcx_base;
118 target_phys_addr_t sbi_base;
119 uint8_t nvram_machine_id;
120 uint16_t machine_id;
121 uint32_t iounit_version;
122 uint64_t max_mem;
123 const char * const default_cpu_model;
124 };
125
126 struct sun4c_hwdef {
127 target_phys_addr_t iommu_base, slavio_base;
128 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
129 target_phys_addr_t serial_base, fd_base;
130 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
131 target_phys_addr_t tcx_base, aux1_base;
132 uint8_t nvram_machine_id;
133 uint16_t machine_id;
134 uint32_t iommu_version;
135 uint64_t max_mem;
136 const char * const default_cpu_model;
137 };
138
139 int DMA_get_channel_mode (int nchan)
140 {
141 return 0;
142 }
143 int DMA_read_memory (int nchan, void *buf, int pos, int size)
144 {
145 return 0;
146 }
147 int DMA_write_memory (int nchan, void *buf, int pos, int size)
148 {
149 return 0;
150 }
151 void DMA_hold_DREQ (int nchan) {}
152 void DMA_release_DREQ (int nchan) {}
153 void DMA_schedule(int nchan) {}
154 void DMA_init (int high_page_enable) {}
155 void DMA_register_channel (int nchan,
156 DMA_transfer_handler transfer_handler,
157 void *opaque)
158 {
159 }
160
161 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
162 {
163 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
164 return 0;
165 }
166
167 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
168 const char *boot_devices, ram_addr_t RAM_size,
169 uint32_t kernel_size,
170 int width, int height, int depth,
171 int nvram_machine_id, const char *arch)
172 {
173 unsigned int i;
174 uint32_t start, end;
175 uint8_t image[0x1ff0];
176 struct OpenBIOS_nvpart_v1 *part_header;
177
178 memset(image, '\0', sizeof(image));
179
180 start = 0;
181
182 // OpenBIOS nvram variables
183 // Variable partition
184 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
185 part_header->signature = OPENBIOS_PART_SYSTEM;
186 pstrcpy(part_header->name, sizeof(part_header->name), "system");
187
188 end = start + sizeof(struct OpenBIOS_nvpart_v1);
189 for (i = 0; i < nb_prom_envs; i++)
190 end = OpenBIOS_set_var(image, end, prom_envs[i]);
191
192 // End marker
193 image[end++] = '\0';
194
195 end = start + ((end - start + 15) & ~15);
196 OpenBIOS_finish_partition(part_header, end - start);
197
198 // free partition
199 start = end;
200 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
201 part_header->signature = OPENBIOS_PART_FREE;
202 pstrcpy(part_header->name, sizeof(part_header->name), "free");
203
204 end = 0x1fd0;
205 OpenBIOS_finish_partition(part_header, end - start);
206
207 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
208 nvram_machine_id);
209
210 for (i = 0; i < sizeof(image); i++)
211 m48t59_write(nvram, i, image[i]);
212 }
213
214 static DeviceState *slavio_intctl;
215
216 void pic_info(Monitor *mon)
217 {
218 if (slavio_intctl)
219 slavio_pic_info(mon, slavio_intctl);
220 }
221
222 void irq_info(Monitor *mon)
223 {
224 if (slavio_intctl)
225 slavio_irq_info(mon, slavio_intctl);
226 }
227
228 void cpu_check_irqs(CPUState *env)
229 {
230 if (env->pil_in && (env->interrupt_index == 0 ||
231 (env->interrupt_index & ~15) == TT_EXTINT)) {
232 unsigned int i;
233
234 for (i = 15; i > 0; i--) {
235 if (env->pil_in & (1 << i)) {
236 int old_interrupt = env->interrupt_index;
237
238 env->interrupt_index = TT_EXTINT | i;
239 if (old_interrupt != env->interrupt_index) {
240 DPRINTF("Set CPU IRQ %d\n", i);
241 cpu_interrupt(env, CPU_INTERRUPT_HARD);
242 }
243 break;
244 }
245 }
246 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
247 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
248 env->interrupt_index = 0;
249 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
250 }
251 }
252
253 static void cpu_set_irq(void *opaque, int irq, int level)
254 {
255 CPUState *env = opaque;
256
257 if (level) {
258 DPRINTF("Raise CPU IRQ %d\n", irq);
259 env->halted = 0;
260 env->pil_in |= 1 << irq;
261 cpu_check_irqs(env);
262 } else {
263 DPRINTF("Lower CPU IRQ %d\n", irq);
264 env->pil_in &= ~(1 << irq);
265 cpu_check_irqs(env);
266 }
267 }
268
269 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
270 {
271 }
272
273 static void main_cpu_reset(void *opaque)
274 {
275 CPUState *env = opaque;
276
277 cpu_reset(env);
278 env->halted = 0;
279 }
280
281 static void secondary_cpu_reset(void *opaque)
282 {
283 CPUState *env = opaque;
284
285 cpu_reset(env);
286 env->halted = 1;
287 }
288
289 static void cpu_halt_signal(void *opaque, int irq, int level)
290 {
291 if (level && cpu_single_env)
292 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
293 }
294
295 static unsigned long sun4m_load_kernel(const char *kernel_filename,
296 const char *initrd_filename,
297 ram_addr_t RAM_size)
298 {
299 int linux_boot;
300 unsigned int i;
301 long initrd_size, kernel_size;
302 uint8_t *ptr;
303
304 linux_boot = (kernel_filename != NULL);
305
306 kernel_size = 0;
307 if (linux_boot) {
308 int bswap_needed;
309
310 #ifdef BSWAP_NEEDED
311 bswap_needed = 1;
312 #else
313 bswap_needed = 0;
314 #endif
315 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
316 NULL, 1, ELF_MACHINE, 0);
317 if (kernel_size < 0)
318 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
319 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
320 TARGET_PAGE_SIZE);
321 if (kernel_size < 0)
322 kernel_size = load_image_targphys(kernel_filename,
323 KERNEL_LOAD_ADDR,
324 RAM_size - KERNEL_LOAD_ADDR);
325 if (kernel_size < 0) {
326 fprintf(stderr, "qemu: could not load kernel '%s'\n",
327 kernel_filename);
328 exit(1);
329 }
330
331 /* load initrd */
332 initrd_size = 0;
333 if (initrd_filename) {
334 initrd_size = load_image_targphys(initrd_filename,
335 INITRD_LOAD_ADDR,
336 RAM_size - INITRD_LOAD_ADDR);
337 if (initrd_size < 0) {
338 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
339 initrd_filename);
340 exit(1);
341 }
342 }
343 if (initrd_size > 0) {
344 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
345 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
346 if (ldl_p(ptr) == 0x48647253) { // HdrS
347 stl_p(ptr + 16, INITRD_LOAD_ADDR);
348 stl_p(ptr + 20, initrd_size);
349 break;
350 }
351 }
352 }
353 }
354 return kernel_size;
355 }
356
357 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
358 {
359 DeviceState *dev;
360 SysBusDevice *s;
361
362 dev = qdev_create(NULL, "iommu");
363 qdev_prop_set_uint32(dev, "version", version);
364 qdev_init_nofail(dev);
365 s = sysbus_from_qdev(dev);
366 sysbus_connect_irq(s, 0, irq);
367 sysbus_mmio_map(s, 0, addr);
368
369 return s;
370 }
371
372 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
373 void *iommu, qemu_irq *dev_irq)
374 {
375 DeviceState *dev;
376 SysBusDevice *s;
377
378 dev = qdev_create(NULL, "sparc32_dma");
379 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
380 qdev_init_nofail(dev);
381 s = sysbus_from_qdev(dev);
382 sysbus_connect_irq(s, 0, parent_irq);
383 *dev_irq = qdev_get_gpio_in(dev, 0);
384 sysbus_mmio_map(s, 0, daddr);
385
386 return s;
387 }
388
389 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
390 void *dma_opaque, qemu_irq irq)
391 {
392 DeviceState *dev;
393 SysBusDevice *s;
394 qemu_irq reset;
395
396 qemu_check_nic_model(&nd_table[0], "lance");
397
398 dev = qdev_create(NULL, "lance");
399 qdev_set_nic_properties(dev, nd);
400 qdev_prop_set_ptr(dev, "dma", dma_opaque);
401 qdev_init_nofail(dev);
402 s = sysbus_from_qdev(dev);
403 sysbus_mmio_map(s, 0, leaddr);
404 sysbus_connect_irq(s, 0, irq);
405 reset = qdev_get_gpio_in(dev, 0);
406 qdev_connect_gpio_out(dma_opaque, 0, reset);
407 }
408
409 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
410 target_phys_addr_t addrg,
411 qemu_irq **parent_irq)
412 {
413 DeviceState *dev;
414 SysBusDevice *s;
415 unsigned int i, j;
416
417 dev = qdev_create(NULL, "slavio_intctl");
418 qdev_init_nofail(dev);
419
420 s = sysbus_from_qdev(dev);
421
422 for (i = 0; i < MAX_CPUS; i++) {
423 for (j = 0; j < MAX_PILS; j++) {
424 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
425 }
426 }
427 sysbus_mmio_map(s, 0, addrg);
428 for (i = 0; i < MAX_CPUS; i++) {
429 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
430 }
431
432 return dev;
433 }
434
435 #define SYS_TIMER_OFFSET 0x10000ULL
436 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
437
438 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
439 qemu_irq *cpu_irqs, unsigned int num_cpus)
440 {
441 DeviceState *dev;
442 SysBusDevice *s;
443 unsigned int i;
444
445 dev = qdev_create(NULL, "slavio_timer");
446 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
447 qdev_init_nofail(dev);
448 s = sysbus_from_qdev(dev);
449 sysbus_connect_irq(s, 0, master_irq);
450 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
451
452 for (i = 0; i < MAX_CPUS; i++) {
453 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
454 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
455 }
456 }
457
458 #define MISC_LEDS 0x01600000
459 #define MISC_CFG 0x01800000
460 #define MISC_DIAG 0x01a00000
461 #define MISC_MDM 0x01b00000
462 #define MISC_SYS 0x01f00000
463
464 static void slavio_misc_init(target_phys_addr_t base,
465 target_phys_addr_t aux1_base,
466 target_phys_addr_t aux2_base, qemu_irq irq,
467 qemu_irq fdc_tc)
468 {
469 DeviceState *dev;
470 SysBusDevice *s;
471
472 dev = qdev_create(NULL, "slavio_misc");
473 qdev_init_nofail(dev);
474 s = sysbus_from_qdev(dev);
475 if (base) {
476 /* 8 bit registers */
477 /* Slavio control */
478 sysbus_mmio_map(s, 0, base + MISC_CFG);
479 /* Diagnostics */
480 sysbus_mmio_map(s, 1, base + MISC_DIAG);
481 /* Modem control */
482 sysbus_mmio_map(s, 2, base + MISC_MDM);
483 /* 16 bit registers */
484 /* ss600mp diag LEDs */
485 sysbus_mmio_map(s, 3, base + MISC_LEDS);
486 /* 32 bit registers */
487 /* System control */
488 sysbus_mmio_map(s, 4, base + MISC_SYS);
489 }
490 if (aux1_base) {
491 /* AUX 1 (Misc System Functions) */
492 sysbus_mmio_map(s, 5, aux1_base);
493 }
494 if (aux2_base) {
495 /* AUX 2 (Software Powerdown Control) */
496 sysbus_mmio_map(s, 6, aux2_base);
497 }
498 sysbus_connect_irq(s, 0, irq);
499 sysbus_connect_irq(s, 1, fdc_tc);
500 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
501 }
502
503 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
504 {
505 DeviceState *dev;
506 SysBusDevice *s;
507
508 dev = qdev_create(NULL, "eccmemctl");
509 qdev_prop_set_uint32(dev, "version", version);
510 qdev_init_nofail(dev);
511 s = sysbus_from_qdev(dev);
512 sysbus_connect_irq(s, 0, irq);
513 sysbus_mmio_map(s, 0, base);
514 if (version == 0) { // SS-600MP only
515 sysbus_mmio_map(s, 1, base + 0x1000);
516 }
517 }
518
519 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
520 {
521 DeviceState *dev;
522 SysBusDevice *s;
523
524 dev = qdev_create(NULL, "apc");
525 qdev_init_nofail(dev);
526 s = sysbus_from_qdev(dev);
527 /* Power management (APC) XXX: not a Slavio device */
528 sysbus_mmio_map(s, 0, power_base);
529 sysbus_connect_irq(s, 0, cpu_halt);
530 }
531
532 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
533 int height, int depth)
534 {
535 DeviceState *dev;
536 SysBusDevice *s;
537
538 dev = qdev_create(NULL, "SUNW,tcx");
539 qdev_prop_set_taddr(dev, "addr", addr);
540 qdev_prop_set_uint32(dev, "vram_size", vram_size);
541 qdev_prop_set_uint16(dev, "width", width);
542 qdev_prop_set_uint16(dev, "height", height);
543 qdev_prop_set_uint16(dev, "depth", depth);
544 qdev_init_nofail(dev);
545 s = sysbus_from_qdev(dev);
546 /* 8-bit plane */
547 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
548 /* DAC */
549 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
550 /* TEC (dummy) */
551 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
552 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
553 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
554 if (depth == 24) {
555 /* 24-bit plane */
556 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
557 /* Control plane */
558 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
559 } else {
560 /* THC 8 bit (dummy) */
561 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
562 }
563 }
564
565 /* NCR89C100/MACIO Internal ID register */
566 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
567
568 static void idreg_init(target_phys_addr_t addr)
569 {
570 DeviceState *dev;
571 SysBusDevice *s;
572
573 dev = qdev_create(NULL, "macio_idreg");
574 qdev_init_nofail(dev);
575 s = sysbus_from_qdev(dev);
576
577 sysbus_mmio_map(s, 0, addr);
578 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
579 }
580
581 static int idreg_init1(SysBusDevice *dev)
582 {
583 ram_addr_t idreg_offset;
584
585 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
586 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
587 return 0;
588 }
589
590 static SysBusDeviceInfo idreg_info = {
591 .init = idreg_init1,
592 .qdev.name = "macio_idreg",
593 .qdev.size = sizeof(SysBusDevice),
594 };
595
596 static void idreg_register_devices(void)
597 {
598 sysbus_register_withprop(&idreg_info);
599 }
600
601 device_init(idreg_register_devices);
602
603 /* SS-5 TCX AFX register */
604 static void afx_init(target_phys_addr_t addr)
605 {
606 DeviceState *dev;
607 SysBusDevice *s;
608
609 dev = qdev_create(NULL, "tcx_afx");
610 qdev_init_nofail(dev);
611 s = sysbus_from_qdev(dev);
612
613 sysbus_mmio_map(s, 0, addr);
614 }
615
616 static int afx_init1(SysBusDevice *dev)
617 {
618 ram_addr_t afx_offset;
619
620 afx_offset = qemu_ram_alloc(4);
621 sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM);
622 return 0;
623 }
624
625 static SysBusDeviceInfo afx_info = {
626 .init = afx_init1,
627 .qdev.name = "tcx_afx",
628 .qdev.size = sizeof(SysBusDevice),
629 };
630
631 static void afx_register_devices(void)
632 {
633 sysbus_register_withprop(&afx_info);
634 }
635
636 device_init(afx_register_devices);
637
638 /* Boot PROM (OpenBIOS) */
639 static void prom_init(target_phys_addr_t addr, const char *bios_name)
640 {
641 DeviceState *dev;
642 SysBusDevice *s;
643 char *filename;
644 int ret;
645
646 dev = qdev_create(NULL, "openprom");
647 qdev_init_nofail(dev);
648 s = sysbus_from_qdev(dev);
649
650 sysbus_mmio_map(s, 0, addr);
651
652 /* load boot prom */
653 if (bios_name == NULL) {
654 bios_name = PROM_FILENAME;
655 }
656 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
657 if (filename) {
658 ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
659 1, ELF_MACHINE, 0);
660 if (ret < 0 || ret > PROM_SIZE_MAX) {
661 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
662 }
663 qemu_free(filename);
664 } else {
665 ret = -1;
666 }
667 if (ret < 0 || ret > PROM_SIZE_MAX) {
668 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
669 exit(1);
670 }
671 }
672
673 static int prom_init1(SysBusDevice *dev)
674 {
675 ram_addr_t prom_offset;
676
677 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
678 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
679 return 0;
680 }
681
682 static SysBusDeviceInfo prom_info = {
683 .init = prom_init1,
684 .qdev.name = "openprom",
685 .qdev.size = sizeof(SysBusDevice),
686 .qdev.props = (Property[]) {
687 {/* end of property list */}
688 }
689 };
690
691 static void prom_register_devices(void)
692 {
693 sysbus_register_withprop(&prom_info);
694 }
695
696 device_init(prom_register_devices);
697
698 typedef struct RamDevice
699 {
700 SysBusDevice busdev;
701 uint64_t size;
702 } RamDevice;
703
704 /* System RAM */
705 static int ram_init1(SysBusDevice *dev)
706 {
707 ram_addr_t RAM_size, ram_offset;
708 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
709
710 RAM_size = d->size;
711
712 ram_offset = qemu_ram_alloc(RAM_size);
713 sysbus_init_mmio(dev, RAM_size, ram_offset);
714 return 0;
715 }
716
717 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
718 uint64_t max_mem)
719 {
720 DeviceState *dev;
721 SysBusDevice *s;
722 RamDevice *d;
723
724 /* allocate RAM */
725 if ((uint64_t)RAM_size > max_mem) {
726 fprintf(stderr,
727 "qemu: Too much memory for this machine: %d, maximum %d\n",
728 (unsigned int)(RAM_size / (1024 * 1024)),
729 (unsigned int)(max_mem / (1024 * 1024)));
730 exit(1);
731 }
732 dev = qdev_create(NULL, "memory");
733 s = sysbus_from_qdev(dev);
734
735 d = FROM_SYSBUS(RamDevice, s);
736 d->size = RAM_size;
737 qdev_init_nofail(dev);
738
739 sysbus_mmio_map(s, 0, addr);
740 }
741
742 static SysBusDeviceInfo ram_info = {
743 .init = ram_init1,
744 .qdev.name = "memory",
745 .qdev.size = sizeof(RamDevice),
746 .qdev.props = (Property[]) {
747 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
748 DEFINE_PROP_END_OF_LIST(),
749 }
750 };
751
752 static void ram_register_devices(void)
753 {
754 sysbus_register_withprop(&ram_info);
755 }
756
757 device_init(ram_register_devices);
758
759 static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
760 uint64_t prom_addr, qemu_irq **cpu_irqs)
761 {
762 CPUState *env;
763
764 env = cpu_init(cpu_model);
765 if (!env) {
766 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
767 exit(1);
768 }
769
770 cpu_sparc_set_id(env, id);
771 if (id == 0) {
772 qemu_register_reset(main_cpu_reset, env);
773 } else {
774 qemu_register_reset(secondary_cpu_reset, env);
775 env->halted = 1;
776 }
777 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
778 env->prom_addr = prom_addr;
779
780 return env;
781 }
782
783 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
784 const char *boot_device,
785 const char *kernel_filename,
786 const char *kernel_cmdline,
787 const char *initrd_filename, const char *cpu_model)
788 {
789 CPUState *envs[MAX_CPUS];
790 unsigned int i;
791 void *iommu, *espdma, *ledma, *nvram;
792 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
793 espdma_irq, ledma_irq;
794 qemu_irq esp_reset;
795 qemu_irq fdc_tc;
796 qemu_irq *cpu_halt;
797 unsigned long kernel_size;
798 DriveInfo *fd[MAX_FD];
799 void *fw_cfg;
800
801 /* init CPUs */
802 if (!cpu_model)
803 cpu_model = hwdef->default_cpu_model;
804
805 for(i = 0; i < smp_cpus; i++) {
806 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
807 }
808
809 for (i = smp_cpus; i < MAX_CPUS; i++)
810 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
811
812
813 /* set up devices */
814 ram_init(0, RAM_size, hwdef->max_mem);
815
816 prom_init(hwdef->slavio_base, bios_name);
817
818 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
819 hwdef->intctl_base + 0x10000ULL,
820 cpu_irqs);
821
822 for (i = 0; i < 32; i++) {
823 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
824 }
825 for (i = 0; i < MAX_CPUS; i++) {
826 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
827 }
828
829 if (hwdef->idreg_base) {
830 idreg_init(hwdef->idreg_base);
831 }
832
833 if (hwdef->afx_base) {
834 afx_init(hwdef->afx_base);
835 }
836
837 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
838 slavio_irq[30]);
839
840 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
841 iommu, &espdma_irq);
842
843 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
844 slavio_irq[16], iommu, &ledma_irq);
845
846 if (graphic_depth != 8 && graphic_depth != 24) {
847 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
848 exit (1);
849 }
850 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
851 graphic_depth);
852
853 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
854
855 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
856
857 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
858
859 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
860 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
861 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
862 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
863 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
864 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
865
866 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
867 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
868 slavio_irq[30], fdc_tc);
869
870 if (hwdef->apc_base) {
871 apc_init(hwdef->apc_base, cpu_halt[0]);
872 }
873
874 if (hwdef->fd_base) {
875 /* there is zero or one floppy drive */
876 memset(fd, 0, sizeof(fd));
877 fd[0] = drive_get(IF_FLOPPY, 0, 0);
878 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
879 &fdc_tc);
880 }
881
882 if (drive_get_max_bus(IF_SCSI) > 0) {
883 fprintf(stderr, "qemu: too many SCSI bus\n");
884 exit(1);
885 }
886
887 esp_reset = qdev_get_gpio_in(espdma, 0);
888 esp_init(hwdef->esp_base, 2,
889 espdma_memory_read, espdma_memory_write,
890 espdma, espdma_irq, &esp_reset);
891
892
893 if (hwdef->cs_base) {
894 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
895 slavio_irq[5]);
896 }
897
898 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
899 RAM_size);
900
901 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
902 boot_device, RAM_size, kernel_size, graphic_width,
903 graphic_height, graphic_depth, hwdef->nvram_machine_id,
904 "Sun4m");
905
906 if (hwdef->ecc_base)
907 ecc_init(hwdef->ecc_base, slavio_irq[28],
908 hwdef->ecc_version);
909
910 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
911 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
912 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
913 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
914 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
915 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
916 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
917 if (kernel_cmdline) {
918 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
919 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
920 } else {
921 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
922 }
923 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
924 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
925 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
926 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
927 }
928
929 enum {
930 ss2_id = 0,
931 ss5_id = 32,
932 vger_id,
933 lx_id,
934 ss4_id,
935 scls_id,
936 sbook_id,
937 ss10_id = 64,
938 ss20_id,
939 ss600mp_id,
940 ss1000_id = 96,
941 ss2000_id,
942 };
943
944 static const struct sun4m_hwdef sun4m_hwdefs[] = {
945 /* SS-5 */
946 {
947 .iommu_base = 0x10000000,
948 .tcx_base = 0x50000000,
949 .cs_base = 0x6c000000,
950 .slavio_base = 0x70000000,
951 .ms_kb_base = 0x71000000,
952 .serial_base = 0x71100000,
953 .nvram_base = 0x71200000,
954 .fd_base = 0x71400000,
955 .counter_base = 0x71d00000,
956 .intctl_base = 0x71e00000,
957 .idreg_base = 0x78000000,
958 .dma_base = 0x78400000,
959 .esp_base = 0x78800000,
960 .le_base = 0x78c00000,
961 .apc_base = 0x6a000000,
962 .afx_base = 0x6e000000,
963 .aux1_base = 0x71900000,
964 .aux2_base = 0x71910000,
965 .nvram_machine_id = 0x80,
966 .machine_id = ss5_id,
967 .iommu_version = 0x05000000,
968 .max_mem = 0x10000000,
969 .default_cpu_model = "Fujitsu MB86904",
970 },
971 /* SS-10 */
972 {
973 .iommu_base = 0xfe0000000ULL,
974 .tcx_base = 0xe20000000ULL,
975 .slavio_base = 0xff0000000ULL,
976 .ms_kb_base = 0xff1000000ULL,
977 .serial_base = 0xff1100000ULL,
978 .nvram_base = 0xff1200000ULL,
979 .fd_base = 0xff1700000ULL,
980 .counter_base = 0xff1300000ULL,
981 .intctl_base = 0xff1400000ULL,
982 .idreg_base = 0xef0000000ULL,
983 .dma_base = 0xef0400000ULL,
984 .esp_base = 0xef0800000ULL,
985 .le_base = 0xef0c00000ULL,
986 .apc_base = 0xefa000000ULL, // XXX should not exist
987 .aux1_base = 0xff1800000ULL,
988 .aux2_base = 0xff1a01000ULL,
989 .ecc_base = 0xf00000000ULL,
990 .ecc_version = 0x10000000, // version 0, implementation 1
991 .nvram_machine_id = 0x72,
992 .machine_id = ss10_id,
993 .iommu_version = 0x03000000,
994 .max_mem = 0xf00000000ULL,
995 .default_cpu_model = "TI SuperSparc II",
996 },
997 /* SS-600MP */
998 {
999 .iommu_base = 0xfe0000000ULL,
1000 .tcx_base = 0xe20000000ULL,
1001 .slavio_base = 0xff0000000ULL,
1002 .ms_kb_base = 0xff1000000ULL,
1003 .serial_base = 0xff1100000ULL,
1004 .nvram_base = 0xff1200000ULL,
1005 .counter_base = 0xff1300000ULL,
1006 .intctl_base = 0xff1400000ULL,
1007 .dma_base = 0xef0081000ULL,
1008 .esp_base = 0xef0080000ULL,
1009 .le_base = 0xef0060000ULL,
1010 .apc_base = 0xefa000000ULL, // XXX should not exist
1011 .aux1_base = 0xff1800000ULL,
1012 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1013 .ecc_base = 0xf00000000ULL,
1014 .ecc_version = 0x00000000, // version 0, implementation 0
1015 .nvram_machine_id = 0x71,
1016 .machine_id = ss600mp_id,
1017 .iommu_version = 0x01000000,
1018 .max_mem = 0xf00000000ULL,
1019 .default_cpu_model = "TI SuperSparc II",
1020 },
1021 /* SS-20 */
1022 {
1023 .iommu_base = 0xfe0000000ULL,
1024 .tcx_base = 0xe20000000ULL,
1025 .slavio_base = 0xff0000000ULL,
1026 .ms_kb_base = 0xff1000000ULL,
1027 .serial_base = 0xff1100000ULL,
1028 .nvram_base = 0xff1200000ULL,
1029 .fd_base = 0xff1700000ULL,
1030 .counter_base = 0xff1300000ULL,
1031 .intctl_base = 0xff1400000ULL,
1032 .idreg_base = 0xef0000000ULL,
1033 .dma_base = 0xef0400000ULL,
1034 .esp_base = 0xef0800000ULL,
1035 .le_base = 0xef0c00000ULL,
1036 .apc_base = 0xefa000000ULL, // XXX should not exist
1037 .aux1_base = 0xff1800000ULL,
1038 .aux2_base = 0xff1a01000ULL,
1039 .ecc_base = 0xf00000000ULL,
1040 .ecc_version = 0x20000000, // version 0, implementation 2
1041 .nvram_machine_id = 0x72,
1042 .machine_id = ss20_id,
1043 .iommu_version = 0x13000000,
1044 .max_mem = 0xf00000000ULL,
1045 .default_cpu_model = "TI SuperSparc II",
1046 },
1047 /* Voyager */
1048 {
1049 .iommu_base = 0x10000000,
1050 .tcx_base = 0x50000000,
1051 .slavio_base = 0x70000000,
1052 .ms_kb_base = 0x71000000,
1053 .serial_base = 0x71100000,
1054 .nvram_base = 0x71200000,
1055 .fd_base = 0x71400000,
1056 .counter_base = 0x71d00000,
1057 .intctl_base = 0x71e00000,
1058 .idreg_base = 0x78000000,
1059 .dma_base = 0x78400000,
1060 .esp_base = 0x78800000,
1061 .le_base = 0x78c00000,
1062 .apc_base = 0x71300000, // pmc
1063 .aux1_base = 0x71900000,
1064 .aux2_base = 0x71910000,
1065 .nvram_machine_id = 0x80,
1066 .machine_id = vger_id,
1067 .iommu_version = 0x05000000,
1068 .max_mem = 0x10000000,
1069 .default_cpu_model = "Fujitsu MB86904",
1070 },
1071 /* LX */
1072 {
1073 .iommu_base = 0x10000000,
1074 .tcx_base = 0x50000000,
1075 .slavio_base = 0x70000000,
1076 .ms_kb_base = 0x71000000,
1077 .serial_base = 0x71100000,
1078 .nvram_base = 0x71200000,
1079 .fd_base = 0x71400000,
1080 .counter_base = 0x71d00000,
1081 .intctl_base = 0x71e00000,
1082 .idreg_base = 0x78000000,
1083 .dma_base = 0x78400000,
1084 .esp_base = 0x78800000,
1085 .le_base = 0x78c00000,
1086 .aux1_base = 0x71900000,
1087 .aux2_base = 0x71910000,
1088 .nvram_machine_id = 0x80,
1089 .machine_id = lx_id,
1090 .iommu_version = 0x04000000,
1091 .max_mem = 0x10000000,
1092 .default_cpu_model = "TI MicroSparc I",
1093 },
1094 /* SS-4 */
1095 {
1096 .iommu_base = 0x10000000,
1097 .tcx_base = 0x50000000,
1098 .cs_base = 0x6c000000,
1099 .slavio_base = 0x70000000,
1100 .ms_kb_base = 0x71000000,
1101 .serial_base = 0x71100000,
1102 .nvram_base = 0x71200000,
1103 .fd_base = 0x71400000,
1104 .counter_base = 0x71d00000,
1105 .intctl_base = 0x71e00000,
1106 .idreg_base = 0x78000000,
1107 .dma_base = 0x78400000,
1108 .esp_base = 0x78800000,
1109 .le_base = 0x78c00000,
1110 .apc_base = 0x6a000000,
1111 .aux1_base = 0x71900000,
1112 .aux2_base = 0x71910000,
1113 .nvram_machine_id = 0x80,
1114 .machine_id = ss4_id,
1115 .iommu_version = 0x05000000,
1116 .max_mem = 0x10000000,
1117 .default_cpu_model = "Fujitsu MB86904",
1118 },
1119 /* SPARCClassic */
1120 {
1121 .iommu_base = 0x10000000,
1122 .tcx_base = 0x50000000,
1123 .slavio_base = 0x70000000,
1124 .ms_kb_base = 0x71000000,
1125 .serial_base = 0x71100000,
1126 .nvram_base = 0x71200000,
1127 .fd_base = 0x71400000,
1128 .counter_base = 0x71d00000,
1129 .intctl_base = 0x71e00000,
1130 .idreg_base = 0x78000000,
1131 .dma_base = 0x78400000,
1132 .esp_base = 0x78800000,
1133 .le_base = 0x78c00000,
1134 .apc_base = 0x6a000000,
1135 .aux1_base = 0x71900000,
1136 .aux2_base = 0x71910000,
1137 .nvram_machine_id = 0x80,
1138 .machine_id = scls_id,
1139 .iommu_version = 0x05000000,
1140 .max_mem = 0x10000000,
1141 .default_cpu_model = "TI MicroSparc I",
1142 },
1143 /* SPARCbook */
1144 {
1145 .iommu_base = 0x10000000,
1146 .tcx_base = 0x50000000, // XXX
1147 .slavio_base = 0x70000000,
1148 .ms_kb_base = 0x71000000,
1149 .serial_base = 0x71100000,
1150 .nvram_base = 0x71200000,
1151 .fd_base = 0x71400000,
1152 .counter_base = 0x71d00000,
1153 .intctl_base = 0x71e00000,
1154 .idreg_base = 0x78000000,
1155 .dma_base = 0x78400000,
1156 .esp_base = 0x78800000,
1157 .le_base = 0x78c00000,
1158 .apc_base = 0x6a000000,
1159 .aux1_base = 0x71900000,
1160 .aux2_base = 0x71910000,
1161 .nvram_machine_id = 0x80,
1162 .machine_id = sbook_id,
1163 .iommu_version = 0x05000000,
1164 .max_mem = 0x10000000,
1165 .default_cpu_model = "TI MicroSparc I",
1166 },
1167 };
1168
1169 /* SPARCstation 5 hardware initialisation */
1170 static void ss5_init(ram_addr_t RAM_size,
1171 const char *boot_device,
1172 const char *kernel_filename, const char *kernel_cmdline,
1173 const char *initrd_filename, const char *cpu_model)
1174 {
1175 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1176 kernel_cmdline, initrd_filename, cpu_model);
1177 }
1178
1179 /* SPARCstation 10 hardware initialisation */
1180 static void ss10_init(ram_addr_t RAM_size,
1181 const char *boot_device,
1182 const char *kernel_filename, const char *kernel_cmdline,
1183 const char *initrd_filename, const char *cpu_model)
1184 {
1185 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1186 kernel_cmdline, initrd_filename, cpu_model);
1187 }
1188
1189 /* SPARCserver 600MP hardware initialisation */
1190 static void ss600mp_init(ram_addr_t RAM_size,
1191 const char *boot_device,
1192 const char *kernel_filename,
1193 const char *kernel_cmdline,
1194 const char *initrd_filename, const char *cpu_model)
1195 {
1196 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1197 kernel_cmdline, initrd_filename, cpu_model);
1198 }
1199
1200 /* SPARCstation 20 hardware initialisation */
1201 static void ss20_init(ram_addr_t RAM_size,
1202 const char *boot_device,
1203 const char *kernel_filename, const char *kernel_cmdline,
1204 const char *initrd_filename, const char *cpu_model)
1205 {
1206 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1207 kernel_cmdline, initrd_filename, cpu_model);
1208 }
1209
1210 /* SPARCstation Voyager hardware initialisation */
1211 static void vger_init(ram_addr_t RAM_size,
1212 const char *boot_device,
1213 const char *kernel_filename, const char *kernel_cmdline,
1214 const char *initrd_filename, const char *cpu_model)
1215 {
1216 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1217 kernel_cmdline, initrd_filename, cpu_model);
1218 }
1219
1220 /* SPARCstation LX hardware initialisation */
1221 static void ss_lx_init(ram_addr_t RAM_size,
1222 const char *boot_device,
1223 const char *kernel_filename, const char *kernel_cmdline,
1224 const char *initrd_filename, const char *cpu_model)
1225 {
1226 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1227 kernel_cmdline, initrd_filename, cpu_model);
1228 }
1229
1230 /* SPARCstation 4 hardware initialisation */
1231 static void ss4_init(ram_addr_t RAM_size,
1232 const char *boot_device,
1233 const char *kernel_filename, const char *kernel_cmdline,
1234 const char *initrd_filename, const char *cpu_model)
1235 {
1236 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1237 kernel_cmdline, initrd_filename, cpu_model);
1238 }
1239
1240 /* SPARCClassic hardware initialisation */
1241 static void scls_init(ram_addr_t RAM_size,
1242 const char *boot_device,
1243 const char *kernel_filename, const char *kernel_cmdline,
1244 const char *initrd_filename, const char *cpu_model)
1245 {
1246 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1247 kernel_cmdline, initrd_filename, cpu_model);
1248 }
1249
1250 /* SPARCbook hardware initialisation */
1251 static void sbook_init(ram_addr_t RAM_size,
1252 const char *boot_device,
1253 const char *kernel_filename, const char *kernel_cmdline,
1254 const char *initrd_filename, const char *cpu_model)
1255 {
1256 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1257 kernel_cmdline, initrd_filename, cpu_model);
1258 }
1259
1260 static QEMUMachine ss5_machine = {
1261 .name = "SS-5",
1262 .desc = "Sun4m platform, SPARCstation 5",
1263 .init = ss5_init,
1264 .use_scsi = 1,
1265 .is_default = 1,
1266 };
1267
1268 static QEMUMachine ss10_machine = {
1269 .name = "SS-10",
1270 .desc = "Sun4m platform, SPARCstation 10",
1271 .init = ss10_init,
1272 .use_scsi = 1,
1273 .max_cpus = 4,
1274 };
1275
1276 static QEMUMachine ss600mp_machine = {
1277 .name = "SS-600MP",
1278 .desc = "Sun4m platform, SPARCserver 600MP",
1279 .init = ss600mp_init,
1280 .use_scsi = 1,
1281 .max_cpus = 4,
1282 };
1283
1284 static QEMUMachine ss20_machine = {
1285 .name = "SS-20",
1286 .desc = "Sun4m platform, SPARCstation 20",
1287 .init = ss20_init,
1288 .use_scsi = 1,
1289 .max_cpus = 4,
1290 };
1291
1292 static QEMUMachine voyager_machine = {
1293 .name = "Voyager",
1294 .desc = "Sun4m platform, SPARCstation Voyager",
1295 .init = vger_init,
1296 .use_scsi = 1,
1297 };
1298
1299 static QEMUMachine ss_lx_machine = {
1300 .name = "LX",
1301 .desc = "Sun4m platform, SPARCstation LX",
1302 .init = ss_lx_init,
1303 .use_scsi = 1,
1304 };
1305
1306 static QEMUMachine ss4_machine = {
1307 .name = "SS-4",
1308 .desc = "Sun4m platform, SPARCstation 4",
1309 .init = ss4_init,
1310 .use_scsi = 1,
1311 };
1312
1313 static QEMUMachine scls_machine = {
1314 .name = "SPARCClassic",
1315 .desc = "Sun4m platform, SPARCClassic",
1316 .init = scls_init,
1317 .use_scsi = 1,
1318 };
1319
1320 static QEMUMachine sbook_machine = {
1321 .name = "SPARCbook",
1322 .desc = "Sun4m platform, SPARCbook",
1323 .init = sbook_init,
1324 .use_scsi = 1,
1325 };
1326
1327 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1328 /* SS-1000 */
1329 {
1330 .iounit_bases = {
1331 0xfe0200000ULL,
1332 0xfe1200000ULL,
1333 0xfe2200000ULL,
1334 0xfe3200000ULL,
1335 -1,
1336 },
1337 .tcx_base = 0x820000000ULL,
1338 .slavio_base = 0xf00000000ULL,
1339 .ms_kb_base = 0xf00240000ULL,
1340 .serial_base = 0xf00200000ULL,
1341 .nvram_base = 0xf00280000ULL,
1342 .counter_base = 0xf00300000ULL,
1343 .espdma_base = 0x800081000ULL,
1344 .esp_base = 0x800080000ULL,
1345 .ledma_base = 0x800040000ULL,
1346 .le_base = 0x800060000ULL,
1347 .sbi_base = 0xf02800000ULL,
1348 .nvram_machine_id = 0x80,
1349 .machine_id = ss1000_id,
1350 .iounit_version = 0x03000000,
1351 .max_mem = 0xf00000000ULL,
1352 .default_cpu_model = "TI SuperSparc II",
1353 },
1354 /* SS-2000 */
1355 {
1356 .iounit_bases = {
1357 0xfe0200000ULL,
1358 0xfe1200000ULL,
1359 0xfe2200000ULL,
1360 0xfe3200000ULL,
1361 0xfe4200000ULL,
1362 },
1363 .tcx_base = 0x820000000ULL,
1364 .slavio_base = 0xf00000000ULL,
1365 .ms_kb_base = 0xf00240000ULL,
1366 .serial_base = 0xf00200000ULL,
1367 .nvram_base = 0xf00280000ULL,
1368 .counter_base = 0xf00300000ULL,
1369 .espdma_base = 0x800081000ULL,
1370 .esp_base = 0x800080000ULL,
1371 .ledma_base = 0x800040000ULL,
1372 .le_base = 0x800060000ULL,
1373 .sbi_base = 0xf02800000ULL,
1374 .nvram_machine_id = 0x80,
1375 .machine_id = ss2000_id,
1376 .iounit_version = 0x03000000,
1377 .max_mem = 0xf00000000ULL,
1378 .default_cpu_model = "TI SuperSparc II",
1379 },
1380 };
1381
1382 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1383 {
1384 DeviceState *dev;
1385 SysBusDevice *s;
1386 unsigned int i;
1387
1388 dev = qdev_create(NULL, "sbi");
1389 qdev_init_nofail(dev);
1390
1391 s = sysbus_from_qdev(dev);
1392
1393 for (i = 0; i < MAX_CPUS; i++) {
1394 sysbus_connect_irq(s, i, *parent_irq[i]);
1395 }
1396
1397 sysbus_mmio_map(s, 0, addr);
1398
1399 return dev;
1400 }
1401
1402 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1403 const char *boot_device,
1404 const char *kernel_filename,
1405 const char *kernel_cmdline,
1406 const char *initrd_filename, const char *cpu_model)
1407 {
1408 CPUState *envs[MAX_CPUS];
1409 unsigned int i;
1410 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1411 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1412 espdma_irq, ledma_irq;
1413 qemu_irq esp_reset;
1414 unsigned long kernel_size;
1415 void *fw_cfg;
1416 DeviceState *dev;
1417
1418 /* init CPUs */
1419 if (!cpu_model)
1420 cpu_model = hwdef->default_cpu_model;
1421
1422 for(i = 0; i < smp_cpus; i++) {
1423 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1424 }
1425
1426 for (i = smp_cpus; i < MAX_CPUS; i++)
1427 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1428
1429 /* set up devices */
1430 ram_init(0, RAM_size, hwdef->max_mem);
1431
1432 prom_init(hwdef->slavio_base, bios_name);
1433
1434 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1435
1436 for (i = 0; i < 32; i++) {
1437 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1438 }
1439 for (i = 0; i < MAX_CPUS; i++) {
1440 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1441 }
1442
1443 for (i = 0; i < MAX_IOUNITS; i++)
1444 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1445 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1446 hwdef->iounit_version,
1447 sbi_irq[0]);
1448
1449 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1450 iounits[0], &espdma_irq);
1451
1452 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1453 iounits[0], &ledma_irq);
1454
1455 if (graphic_depth != 8 && graphic_depth != 24) {
1456 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1457 exit (1);
1458 }
1459 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1460 graphic_depth);
1461
1462 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1463
1464 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1465
1466 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1467
1468 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1469 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1470 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1471 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1472 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1473 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1474
1475 if (drive_get_max_bus(IF_SCSI) > 0) {
1476 fprintf(stderr, "qemu: too many SCSI bus\n");
1477 exit(1);
1478 }
1479
1480 esp_reset = qdev_get_gpio_in(espdma, 0);
1481 esp_init(hwdef->esp_base, 2,
1482 espdma_memory_read, espdma_memory_write,
1483 espdma, espdma_irq, &esp_reset);
1484
1485 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1486 RAM_size);
1487
1488 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1489 boot_device, RAM_size, kernel_size, graphic_width,
1490 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1491 "Sun4d");
1492
1493 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1494 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1495 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1496 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1497 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1498 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1499 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1500 if (kernel_cmdline) {
1501 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1502 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1503 } else {
1504 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1505 }
1506 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1507 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1508 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1509 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1510 }
1511
1512 /* SPARCserver 1000 hardware initialisation */
1513 static void ss1000_init(ram_addr_t RAM_size,
1514 const char *boot_device,
1515 const char *kernel_filename, const char *kernel_cmdline,
1516 const char *initrd_filename, const char *cpu_model)
1517 {
1518 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1519 kernel_cmdline, initrd_filename, cpu_model);
1520 }
1521
1522 /* SPARCcenter 2000 hardware initialisation */
1523 static void ss2000_init(ram_addr_t RAM_size,
1524 const char *boot_device,
1525 const char *kernel_filename, const char *kernel_cmdline,
1526 const char *initrd_filename, const char *cpu_model)
1527 {
1528 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1529 kernel_cmdline, initrd_filename, cpu_model);
1530 }
1531
1532 static QEMUMachine ss1000_machine = {
1533 .name = "SS-1000",
1534 .desc = "Sun4d platform, SPARCserver 1000",
1535 .init = ss1000_init,
1536 .use_scsi = 1,
1537 .max_cpus = 8,
1538 };
1539
1540 static QEMUMachine ss2000_machine = {
1541 .name = "SS-2000",
1542 .desc = "Sun4d platform, SPARCcenter 2000",
1543 .init = ss2000_init,
1544 .use_scsi = 1,
1545 .max_cpus = 20,
1546 };
1547
1548 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1549 /* SS-2 */
1550 {
1551 .iommu_base = 0xf8000000,
1552 .tcx_base = 0xfe000000,
1553 .slavio_base = 0xf6000000,
1554 .intctl_base = 0xf5000000,
1555 .counter_base = 0xf3000000,
1556 .ms_kb_base = 0xf0000000,
1557 .serial_base = 0xf1000000,
1558 .nvram_base = 0xf2000000,
1559 .fd_base = 0xf7200000,
1560 .dma_base = 0xf8400000,
1561 .esp_base = 0xf8800000,
1562 .le_base = 0xf8c00000,
1563 .aux1_base = 0xf7400003,
1564 .nvram_machine_id = 0x55,
1565 .machine_id = ss2_id,
1566 .max_mem = 0x10000000,
1567 .default_cpu_model = "Cypress CY7C601",
1568 },
1569 };
1570
1571 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1572 qemu_irq *parent_irq)
1573 {
1574 DeviceState *dev;
1575 SysBusDevice *s;
1576 unsigned int i;
1577
1578 dev = qdev_create(NULL, "sun4c_intctl");
1579 qdev_init_nofail(dev);
1580
1581 s = sysbus_from_qdev(dev);
1582
1583 for (i = 0; i < MAX_PILS; i++) {
1584 sysbus_connect_irq(s, i, parent_irq[i]);
1585 }
1586 sysbus_mmio_map(s, 0, addr);
1587
1588 return dev;
1589 }
1590
1591 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1592 const char *boot_device,
1593 const char *kernel_filename,
1594 const char *kernel_cmdline,
1595 const char *initrd_filename, const char *cpu_model)
1596 {
1597 CPUState *env;
1598 void *iommu, *espdma, *ledma, *nvram;
1599 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1600 qemu_irq esp_reset;
1601 qemu_irq fdc_tc;
1602 unsigned long kernel_size;
1603 DriveInfo *fd[MAX_FD];
1604 void *fw_cfg;
1605 DeviceState *dev;
1606 unsigned int i;
1607
1608 /* init CPU */
1609 if (!cpu_model)
1610 cpu_model = hwdef->default_cpu_model;
1611
1612 env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1613
1614 /* set up devices */
1615 ram_init(0, RAM_size, hwdef->max_mem);
1616
1617 prom_init(hwdef->slavio_base, bios_name);
1618
1619 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1620
1621 for (i = 0; i < 8; i++) {
1622 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1623 }
1624
1625 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1626 slavio_irq[1]);
1627
1628 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1629 iommu, &espdma_irq);
1630
1631 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1632 slavio_irq[3], iommu, &ledma_irq);
1633
1634 if (graphic_depth != 8 && graphic_depth != 24) {
1635 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1636 exit (1);
1637 }
1638 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1639 graphic_depth);
1640
1641 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1642
1643 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1644
1645 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1646 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1647 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1648 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1649 escc_init(hwdef->serial_base, slavio_irq[1],
1650 slavio_irq[1], serial_hds[0], serial_hds[1],
1651 ESCC_CLOCK, 1);
1652
1653 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1654
1655 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1656 /* there is zero or one floppy drive */
1657 memset(fd, 0, sizeof(fd));
1658 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1659 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1660 &fdc_tc);
1661 }
1662
1663 if (drive_get_max_bus(IF_SCSI) > 0) {
1664 fprintf(stderr, "qemu: too many SCSI bus\n");
1665 exit(1);
1666 }
1667
1668 esp_reset = qdev_get_gpio_in(espdma, 0);
1669 esp_init(hwdef->esp_base, 2,
1670 espdma_memory_read, espdma_memory_write,
1671 espdma, espdma_irq, &esp_reset);
1672
1673 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1674 RAM_size);
1675
1676 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1677 boot_device, RAM_size, kernel_size, graphic_width,
1678 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1679 "Sun4c");
1680
1681 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1682 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1683 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1684 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1685 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1686 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1687 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1688 if (kernel_cmdline) {
1689 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1690 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1691 } else {
1692 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1693 }
1694 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1695 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1696 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1697 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1698 }
1699
1700 /* SPARCstation 2 hardware initialisation */
1701 static void ss2_init(ram_addr_t RAM_size,
1702 const char *boot_device,
1703 const char *kernel_filename, const char *kernel_cmdline,
1704 const char *initrd_filename, const char *cpu_model)
1705 {
1706 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1707 kernel_cmdline, initrd_filename, cpu_model);
1708 }
1709
1710 static QEMUMachine ss2_machine = {
1711 .name = "SS-2",
1712 .desc = "Sun4c platform, SPARCstation 2",
1713 .init = ss2_init,
1714 .use_scsi = 1,
1715 };
1716
1717 static void ss2_machine_init(void)
1718 {
1719 qemu_register_machine(&ss5_machine);
1720 qemu_register_machine(&ss10_machine);
1721 qemu_register_machine(&ss600mp_machine);
1722 qemu_register_machine(&ss20_machine);
1723 qemu_register_machine(&voyager_machine);
1724 qemu_register_machine(&ss_lx_machine);
1725 qemu_register_machine(&ss4_machine);
1726 qemu_register_machine(&scls_machine);
1727 qemu_register_machine(&sbook_machine);
1728 qemu_register_machine(&ss1000_machine);
1729 qemu_register_machine(&ss2000_machine);
1730 qemu_register_machine(&ss2_machine);
1731 }
1732
1733 machine_init(ss2_machine_init);
Anthony Liguori's QEMU queue